Unified Coverage Report :: Group :: cip_base_pkg::intr_pins_cg::SHAPE{(num_interrupts - 1)=14}

Group : cip_base_pkg::intr_pins_cg::SHAPE{(num_interrupts - 1)=14}

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
100.00	1	100	1	64	64

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_dv_cip_lib_0/cip_base_env_cov.sv

---

Summary for Group cip_base_pkg::intr_pins_cg::SHAPE{(num_interrupts - 1)=14}

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	19	0	19	100.00
Crosses	60	0	60	100.00

Variables for Group cip_base_pkg::intr_pins_cg::SHAPE{(num_interrupts - 1)=14}

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
cp_intr_pin	15	0	15	100.00	100	1	1	0
cp_intr_pin_value	4	0	4	100.00	100	1	1	0

Crosses for Group cip_base_pkg::intr_pins_cg::SHAPE{(num_interrupts - 1)=14}

CROSS	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	PRINT MISSING	COMMENT
cp_intr_pins_all_values	60	0	60	100.00	100	1	1	0

Summary for Variable cp_intr_pin

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	15	0	15	100.00

User Defined Bins for cp_intr_pin

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
all_pins[0]	636898	1			T2	2		T3	144		T4	2
all_pins[1]	636898	1			T2	2		T3	144		T4	2
all_pins[2]	636898	1			T2	2		T3	144		T4	2
all_pins[3]	636898	1			T2	2		T3	144		T4	2
all_pins[4]	636898	1			T2	2		T3	144		T4	2
all_pins[5]	636898	1			T2	2		T3	144		T4	2
all_pins[6]	636898	1			T2	2		T3	144		T4	2
all_pins[7]	636898	1			T2	2		T3	144		T4	2
all_pins[8]	636898	1			T2	2		T3	144		T4	2
all_pins[9]	636898	1			T2	2		T3	144		T4	2
all_pins[10]	636898	1			T2	2		T3	144		T4	2
all_pins[11]	636898	1			T2	2		T3	144		T4	2
all_pins[12]	636898	1			T2	2		T3	144		T4	2
all_pins[13]	636898	1			T2	2		T3	144		T4	2
all_pins[14]	636898	1			T2	2		T3	144		T4	2

---

Summary for Variable cp_intr_pin_value

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	4	0	4	100.00

User Defined Bins for cp_intr_pin_value

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
values[0x0]	7885999	1			T2	26		T3	1944		T4	26
values[0x1]	1667471	1			T2	4		T3	216		T4	4
transitions[0x0=>0x1]	1666476	1			T2	4		T3	216		T4	4
transitions[0x1=>0x0]	1665171	1			T2	3		T3	215		T4	3

---

Summary for Cross cp_intr_pins_all_values

Samples crossed: cp_intr_pin cp_intr_pin_value

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	60	0	60	100.00

Automatically Generated Cross Bins for cp_intr_pins_all_values

Bins

cp_intr_pin	cp_intr_pin_value	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
all_pins[0]	values[0x0]	111393	1			T3	129		T10	1		T14	1309
all_pins[0]	values[0x1]	525505	1			T2	2		T3	15		T4	2
all_pins[0]	transitions[0x0=>0x1]	524846	1			T2	2		T3	15		T4	2
all_pins[0]	transitions[0x1=>0x0]	72	1			T21	1		T292	4		T189	2
all_pins[1]	values[0x0]	636167	1			T2	2		T3	144		T4	2
all_pins[1]	values[0x1]	731	1			T41	6		T105	5		T21	1
all_pins[1]	transitions[0x0=>0x1]	718	1			T41	6		T105	5		T21	1
all_pins[1]	transitions[0x1=>0x0]	117	1			T293	1		T94	1		T96	1
all_pins[2]	values[0x0]	636768	1			T2	2		T3	144		T4	2
all_pins[2]	values[0x1]	130	1			T293	1		T94	1		T96	1
all_pins[2]	transitions[0x0=>0x1]	113	1			T293	1		T94	1		T96	1
all_pins[2]	transitions[0x1=>0x0]	61	1			T21	3		T242	3		T275	1
all_pins[3]	values[0x0]	636820	1			T2	2		T3	144		T4	2
all_pins[3]	values[0x1]	78	1			T21	3		T27	1		T242	3
all_pins[3]	transitions[0x0=>0x1]	61	1			T21	3		T242	3		T275	1
all_pins[3]	transitions[0x1=>0x0]	75	1			T23	1		T259	1		T262	1
all_pins[4]	values[0x0]	636806	1			T2	2		T3	144		T4	2
all_pins[4]	values[0x1]	92	1			T23	1		T27	1		T259	1
all_pins[4]	transitions[0x0=>0x1]	71	1			T23	1		T27	1		T259	1
all_pins[4]	transitions[0x1=>0x0]	83	1			T188	1		T242	4		T136	1
all_pins[5]	values[0x0]	636794	1			T2	2		T3	144		T4	2
all_pins[5]	values[0x1]	104	1			T188	1		T189	2		T242	6
all_pins[5]	transitions[0x0=>0x1]	71	1			T189	2		T242	3		T136	2
all_pins[5]	transitions[0x1=>0x0]	76	1			T189	1		T242	4		T243	5
all_pins[6]	values[0x0]	636789	1			T2	2		T3	144		T4	2
all_pins[6]	values[0x1]	109	1			T188	1		T189	1		T242	7
all_pins[6]	transitions[0x0=>0x1]	76	1			T188	1		T189	1		T242	2
all_pins[6]	transitions[0x1=>0x0]	29231	1			T3	59		T16	279		T15	205
all_pins[7]	values[0x0]	607634	1			T2	2		T3	85		T4	2
all_pins[7]	values[0x1]	29264	1			T3	59		T16	279		T15	205
all_pins[7]	transitions[0x0=>0x1]	29239	1			T3	59		T16	279		T15	205
all_pins[7]	transitions[0x1=>0x0]	57	1			T188	2		T242	2		T137	4
all_pins[8]	values[0x0]	636816	1			T2	2		T3	144		T4	2
all_pins[8]	values[0x1]	82	1			T188	2		T189	3		T242	2
all_pins[8]	transitions[0x0=>0x1]	66	1			T188	2		T189	3		T242	2
all_pins[8]	transitions[0x1=>0x0]	480695	1			T10	1		T45	1		T14	3
all_pins[9]	values[0x0]	156187	1			T2	2		T3	144		T4	2
all_pins[9]	values[0x1]	480711	1			T10	1		T45	1		T14	3
all_pins[9]	transitions[0x0=>0x1]	480693	1			T10	1		T45	1		T14	3
all_pins[9]	transitions[0x1=>0x0]	81	1			T27	1		T188	1		T189	1
all_pins[10]	values[0x0]	636799	1			T2	2		T3	144		T4	2
all_pins[10]	values[0x1]	99	1			T27	2		T188	1		T189	2
all_pins[10]	transitions[0x0=>0x1]	75	1			T27	2		T189	2		T242	2
all_pins[10]	transitions[0x1=>0x0]	630194	1			T2	2		T3	142		T4	2
all_pins[11]	values[0x0]	6680	1			T3	2		T10	1		T14	3
all_pins[11]	values[0x1]	630218	1			T2	2		T3	142		T4	2
all_pins[11]	transitions[0x0=>0x1]	630189	1			T2	2		T3	142		T4	2
all_pins[11]	transitions[0x1=>0x0]	113	1			T53	1		T71	1		T72	1
all_pins[12]	values[0x0]	636756	1			T2	2		T3	144		T4	2
all_pins[12]	values[0x1]	142	1			T53	1		T71	1		T72	1
all_pins[12]	transitions[0x0=>0x1]	121	1			T53	1		T71	1		T72	1
all_pins[12]	transitions[0x1=>0x0]	87	1			T188	2		T242	8		T275	3
all_pins[13]	values[0x0]	636790	1			T2	2		T3	144		T4	2
all_pins[13]	values[0x1]	108	1			T188	2		T242	10		T275	3
all_pins[13]	transitions[0x0=>0x1]	74	1			T188	2		T242	6		T275	1
all_pins[13]	transitions[0x1=>0x0]	64	1			T21	1		T189	1		T242	3
all_pins[14]	values[0x0]	636800	1			T2	2		T3	144		T4	2
all_pins[14]	values[0x1]	98	1			T21	1		T189	1		T242	7
all_pins[14]	transitions[0x0=>0x1]	63	1			T242	4		T275	2		T137	6
all_pins[14]	transitions[0x1=>0x0]	524165	1			T2	1		T3	14		T4	1