Unified Coverage Report :: Group :: cip_base_pkg::intr_test_cg::SHAPE{(num_interrupts - 1)=14}

Group : cip_base_pkg::intr_test_cg::SHAPE{(num_interrupts - 1)=14}

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
100.00	1	100	1	64	64

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_dv_cip_lib_0/cip_base_env_cov.sv

---

Summary for Group cip_base_pkg::intr_test_cg::SHAPE{(num_interrupts - 1)=14}

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	21	0	21	100.00
Crosses	90	0	90	100.00

Variables for Group cip_base_pkg::intr_test_cg::SHAPE{(num_interrupts - 1)=14}

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
cp_intr	15	0	15	100.00	100	1	1	0
cp_intr_en	2	0	2	100.00	100	1	1	2
cp_intr_state	2	0	2	100.00	100	1	1	2
cp_intr_test	2	0	2	100.00	100	1	1	2

Crosses for Group cip_base_pkg::intr_test_cg::SHAPE{(num_interrupts - 1)=14}

CROSS	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	PRINT MISSING	COMMENT
intr_test_cg_cc	90	0	90	100.00	100	1	1	0

Summary for Variable cp_intr

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	15	0	15	100.00

User Defined Bins for cp_intr

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
all_values[0]	389	1			T21	4		T27	4		T188	4
all_values[1]	389	1			T21	4		T27	4		T188	4
all_values[2]	389	1			T21	4		T27	4		T188	4
all_values[3]	389	1			T21	4		T27	4		T188	4
all_values[4]	389	1			T21	4		T27	4		T188	4
all_values[5]	389	1			T21	4		T27	4		T188	4
all_values[6]	389	1			T21	4		T27	4		T188	4
all_values[7]	389	1			T21	4		T27	4		T188	4
all_values[8]	389	1			T21	4		T27	4		T188	4
all_values[9]	389	1			T21	4		T27	4		T188	4
all_values[10]	389	1			T21	4		T27	4		T188	4
all_values[11]	389	1			T21	4		T27	4		T188	4
all_values[12]	389	1			T21	4		T27	4		T188	4
all_values[13]	389	1			T21	4		T27	4		T188	4
all_values[14]	389	1			T21	4		T27	4		T188	4

---

Summary for Variable cp_intr_en

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cp_intr_en

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

3147

1

T21

36

T27

43

T188

38

auto[1]

2688

1

T21

24

T27

17

T188

22

---

Summary for Variable cp_intr_state

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cp_intr_state

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

844

1

T21

21

T27

13

T188

10

auto[1]

4991

1

T21

39

T27

47

T188

50

---

Summary for Variable cp_intr_test

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cp_intr_test

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

3356

1

T21

43

T27

31

T188

34

auto[1]

2479

1

T21

17

T27

29

T188

26

---

Summary for Cross intr_test_cg_cc

Samples crossed: cp_intr cp_intr_test cp_intr_en cp_intr_state

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
TOTAL	90	0	90	100.00
Automatically Generated Cross Bins	90	0	90	100.00
User Defined Cross Bins	0	0	0

Automatically Generated Cross Bins for intr_test_cg_cc

Bins

cp_intr	cp_intr_test	cp_intr_en	cp_intr_state	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
all_values[0]	auto[0]	auto[0]	auto[0]	48	1			T21	1		T275	4		T136	3
all_values[0]	auto[0]	auto[0]	auto[1]	74	1			T189	1		T242	3		T275	1
all_values[0]	auto[0]	auto[1]	auto[0]	19	1			T138	1		T294	1		T295	1
all_values[0]	auto[0]	auto[1]	auto[1]	87	1			T21	1		T27	1		T188	1
all_values[0]	auto[1]	auto[0]	auto[1]	98	1			T27	3		T188	1		T189	5
all_values[0]	auto[1]	auto[1]	auto[1]	63	1			T21	2		T188	2		T242	4
all_values[1]	auto[0]	auto[0]	auto[0]	34	1			T27	2		T242	1		T296	1
all_values[1]	auto[0]	auto[0]	auto[1]	86	1			T21	1		T189	2		T242	1
all_values[1]	auto[0]	auto[1]	auto[0]	17	1			T294	4		T297	2		T298	2
all_values[1]	auto[0]	auto[1]	auto[1]	85	1			T27	1		T188	1		T189	2
all_values[1]	auto[1]	auto[0]	auto[1]	89	1			T21	3		T27	1		T188	3
all_values[1]	auto[1]	auto[1]	auto[1]	78	1			T189	1		T242	5		T275	4
all_values[2]	auto[0]	auto[0]	auto[0]	23	1			T189	1		T275	2		T299	1
all_values[2]	auto[0]	auto[0]	auto[1]	105	1			T21	2		T27	1		T188	1
all_values[2]	auto[0]	auto[1]	auto[0]	21	1			T242	1		T275	1		T296	2
all_values[2]	auto[0]	auto[1]	auto[1]	85	1			T21	1		T188	1		T242	5
all_values[2]	auto[1]	auto[0]	auto[1]	93	1			T21	1		T27	3		T188	2
all_values[2]	auto[1]	auto[1]	auto[1]	62	1			T243	2		T136	2		T137	2
all_values[3]	auto[0]	auto[0]	auto[0]	32	1			T189	1		T242	1		T136	1
all_values[3]	auto[0]	auto[0]	auto[1]	88	1			T188	2		T189	1		T242	3
all_values[3]	auto[0]	auto[1]	auto[0]	19	1			T189	2		T243	1		T296	2
all_values[3]	auto[0]	auto[1]	auto[1]	82	1			T21	2		T27	3		T188	1
all_values[3]	auto[1]	auto[0]	auto[1]	91	1			T21	1		T27	1		T188	1
all_values[3]	auto[1]	auto[1]	auto[1]	77	1			T21	1		T189	2		T242	3
all_values[4]	auto[0]	auto[0]	auto[0]	31	1			T21	1		T242	3		T275	1
all_values[4]	auto[0]	auto[0]	auto[1]	85	1			T21	1		T27	1		T188	2
all_values[4]	auto[0]	auto[1]	auto[0]	22	1			T242	1		T275	2		T243	3
all_values[4]	auto[0]	auto[1]	auto[1]	75	1			T21	1		T188	1		T189	1
all_values[4]	auto[1]	auto[0]	auto[1]	96	1			T21	1		T27	3		T188	1
all_values[4]	auto[1]	auto[1]	auto[1]	80	1			T189	5		T242	2		T243	2
all_values[5]	auto[0]	auto[0]	auto[0]	39	1			T21	1		T27	4		T243	2
all_values[5]	auto[0]	auto[0]	auto[1]	69	1			T21	1		T188	1		T242	4
all_values[5]	auto[0]	auto[1]	auto[0]	17	1			T21	1		T188	1		T138	2
all_values[5]	auto[0]	auto[1]	auto[1]	100	1			T189	4		T242	3		T275	2
all_values[5]	auto[1]	auto[0]	auto[1]	72	1			T189	2		T242	4		T275	3
all_values[5]	auto[1]	auto[1]	auto[1]	92	1			T21	1		T188	2		T189	1
all_values[6]	auto[0]	auto[0]	auto[0]	25	1			T21	1		T27	1		T189	1
all_values[6]	auto[0]	auto[0]	auto[1]	70	1			T188	1		T189	1		T242	3
all_values[6]	auto[0]	auto[1]	auto[0]	21	1			T21	3		T189	1		T242	2
all_values[6]	auto[0]	auto[1]	auto[1]	101	1			T27	1		T188	1		T189	2
all_values[6]	auto[1]	auto[0]	auto[1]	89	1			T27	2		T188	2		T242	2
all_values[6]	auto[1]	auto[1]	auto[1]	83	1			T189	2		T242	3		T275	1
all_values[7]	auto[0]	auto[0]	auto[0]	35	1			T27	2		T188	1		T243	2
all_values[7]	auto[0]	auto[0]	auto[1]	97	1			T21	2		T188	2		T242	6
all_values[7]	auto[0]	auto[1]	auto[0]	18	1			T138	1		T139	1		T297	1
all_values[7]	auto[0]	auto[1]	auto[1]	77	1			T21	1		T27	1		T189	3
all_values[7]	auto[1]	auto[0]	auto[1]	87	1			T21	1		T27	1		T188	1
all_values[7]	auto[1]	auto[1]	auto[1]	75	1			T189	3		T242	2		T275	2
all_values[8]	auto[0]	auto[0]	auto[0]	40	1			T27	1		T189	1		T136	4
all_values[8]	auto[0]	auto[0]	auto[1]	92	1			T21	1		T27	2		T189	1
all_values[8]	auto[0]	auto[1]	auto[0]	13	1			T188	1		T242	1		T136	1
all_values[8]	auto[0]	auto[1]	auto[1]	85	1			T21	2		T188	1		T189	1
all_values[8]	auto[1]	auto[0]	auto[1]	93	1			T21	1		T27	1		T188	1
all_values[8]	auto[1]	auto[1]	auto[1]	66	1			T188	1		T189	2		T242	3
all_values[9]	auto[0]	auto[0]	auto[0]	35	1			T21	4		T188	1		T242	1
all_values[9]	auto[0]	auto[0]	auto[1]	100	1			T27	1		T188	1		T189	1
all_values[9]	auto[0]	auto[1]	auto[0]	22	1			T242	1		T137	1		T138	1
all_values[9]	auto[0]	auto[1]	auto[1]	73	1			T189	4		T242	4		T275	1
all_values[9]	auto[1]	auto[0]	auto[1]	90	1			T27	1		T188	2		T189	2
all_values[9]	auto[1]	auto[1]	auto[1]	69	1			T27	2		T242	5		T275	1
all_values[10]	auto[0]	auto[0]	auto[0]	35	1			T21	3		T27	1		T275	1
all_values[10]	auto[0]	auto[0]	auto[1]	81	1			T188	2		T189	2		T242	7
all_values[10]	auto[0]	auto[1]	auto[0]	20	1			T21	1		T243	1		T299	1
all_values[10]	auto[0]	auto[1]	auto[1]	79	1			T27	1		T188	1		T189	1
all_values[10]	auto[1]	auto[0]	auto[1]	93	1			T189	4		T242	2		T243	2
all_values[10]	auto[1]	auto[1]	auto[1]	81	1			T27	2		T188	1		T242	4
all_values[11]	auto[0]	auto[0]	auto[0]	34	1			T189	1		T275	3		T136	1
all_values[11]	auto[0]	auto[0]	auto[1]	81	1			T21	1		T27	1		T189	2
all_values[11]	auto[0]	auto[1]	auto[0]	16	1			T189	1		T243	2		T137	1
all_values[11]	auto[0]	auto[1]	auto[1]	85	1			T21	1		T188	1		T189	1
all_values[11]	auto[1]	auto[0]	auto[1]	97	1			T21	2		T27	3		T242	6
all_values[11]	auto[1]	auto[1]	auto[1]	76	1			T188	3		T189	2		T242	3
all_values[12]	auto[0]	auto[0]	auto[0]	49	1			T21	1		T188	3		T189	1
all_values[12]	auto[0]	auto[0]	auto[1]	79	1			T21	1		T189	2		T242	5
all_values[12]	auto[0]	auto[1]	auto[0]	22	1			T188	1		T189	1		T299	2
all_values[12]	auto[0]	auto[1]	auto[1]	75	1			T21	1		T27	1		T189	2
all_values[12]	auto[1]	auto[0]	auto[1]	86	1			T21	1		T27	3		T242	3
all_values[12]	auto[1]	auto[1]	auto[1]	78	1			T189	1		T242	5		T243	3
all_values[13]	auto[0]	auto[0]	auto[0]	39	1			T21	2		T27	1		T189	3
all_values[13]	auto[0]	auto[0]	auto[1]	76	1			T188	1		T189	2		T242	2
all_values[13]	auto[0]	auto[1]	auto[0]	27	1			T21	2		T27	1		T137	2
all_values[13]	auto[0]	auto[1]	auto[1]	89	1			T27	1		T188	1		T242	7
all_values[13]	auto[1]	auto[0]	auto[1]	81	1			T188	2		T189	2		T242	3
all_values[13]	auto[1]	auto[1]	auto[1]	77	1			T27	1		T242	6		T275	2
all_values[14]	auto[0]	auto[0]	auto[0]	39	1			T188	2		T275	2		T243	3
all_values[14]	auto[0]	auto[0]	auto[1]	68	1			T27	1		T188	1		T189	4
all_values[14]	auto[0]	auto[1]	auto[0]	32	1			T242	1		T275	2		T243	4
all_values[14]	auto[0]	auto[1]	auto[1]	83	1			T21	2		T27	1		T242	4
all_values[14]	auto[1]	auto[0]	auto[1]	103	1			T21	1		T27	2		T188	1
all_values[14]	auto[1]	auto[1]	auto[1]	64	1			T21	1		T189	1		T242	3

User Defined Cross Bins for intr_test_cg_cc

Excluded/Illegal bins

NAME	COUNT	STATUS
test_1_state_0	0	Illegal