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Total Coverage Summary 
SCORELINECONDTOGGLEFSMBRANCHASSERTGROUP
91.14 97.15 89.39 97.22 71.43 94.11 98.44 90.21


Total test records in report: 1849
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T113 /workspace/coverage/cover_reg_top/0.i2c_same_csr_outstanding.1727590230 Aug 12 04:32:46 PM PDT 24 Aug 12 04:32:47 PM PDT 24 104461998 ps
T114 /workspace/coverage/cover_reg_top/15.i2c_csr_rw.2026970378 Aug 12 04:32:58 PM PDT 24 Aug 12 04:32:59 PM PDT 24 36699435 ps
T115 /workspace/coverage/cover_reg_top/17.i2c_csr_rw.173850578 Aug 12 04:33:08 PM PDT 24 Aug 12 04:33:09 PM PDT 24 19870239 ps
T1769 /workspace/coverage/cover_reg_top/0.i2c_csr_bit_bash.2971616756 Aug 12 04:32:44 PM PDT 24 Aug 12 04:32:49 PM PDT 24 3480317737 ps
T220 /workspace/coverage/cover_reg_top/0.i2c_tl_intg_err.2628436058 Aug 12 04:32:44 PM PDT 24 Aug 12 04:32:46 PM PDT 24 81724086 ps
T218 /workspace/coverage/cover_reg_top/9.i2c_tl_intg_err.4175636459 Aug 12 04:32:48 PM PDT 24 Aug 12 04:32:49 PM PDT 24 123141771 ps
T1770 /workspace/coverage/cover_reg_top/4.i2c_csr_rw.672937626 Aug 12 04:33:12 PM PDT 24 Aug 12 04:33:12 PM PDT 24 70163248 ps
T1771 /workspace/coverage/cover_reg_top/13.i2c_same_csr_outstanding.2118418720 Aug 12 04:32:51 PM PDT 24 Aug 12 04:32:51 PM PDT 24 54606762 ps
T1772 /workspace/coverage/cover_reg_top/1.i2c_csr_hw_reset.1453269163 Aug 12 04:33:00 PM PDT 24 Aug 12 04:33:01 PM PDT 24 52154882 ps
T1773 /workspace/coverage/cover_reg_top/7.i2c_same_csr_outstanding.2569537093 Aug 12 04:32:57 PM PDT 24 Aug 12 04:32:58 PM PDT 24 52366251 ps
T1774 /workspace/coverage/cover_reg_top/4.i2c_tl_errors.1977840336 Aug 12 04:33:57 PM PDT 24 Aug 12 04:33:58 PM PDT 24 67709767 ps
T284 /workspace/coverage/cover_reg_top/8.i2c_tl_intg_err.2824393216 Aug 12 04:32:42 PM PDT 24 Aug 12 04:32:44 PM PDT 24 411986697 ps
T1775 /workspace/coverage/cover_reg_top/21.i2c_intr_test.957607557 Aug 12 04:32:54 PM PDT 24 Aug 12 04:32:55 PM PDT 24 20054563 ps
T1776 /workspace/coverage/cover_reg_top/12.i2c_csr_mem_rw_with_rand_reset.3430688219 Aug 12 04:34:13 PM PDT 24 Aug 12 04:34:15 PM PDT 24 135041782 ps
T1777 /workspace/coverage/cover_reg_top/34.i2c_intr_test.3952730547 Aug 12 04:33:05 PM PDT 24 Aug 12 04:33:06 PM PDT 24 39179077 ps
T1778 /workspace/coverage/cover_reg_top/3.i2c_csr_hw_reset.1780833331 Aug 12 04:32:54 PM PDT 24 Aug 12 04:32:55 PM PDT 24 57725017 ps
T1779 /workspace/coverage/cover_reg_top/19.i2c_intr_test.413084967 Aug 12 04:33:10 PM PDT 24 Aug 12 04:33:11 PM PDT 24 38724067 ps
T1780 /workspace/coverage/cover_reg_top/5.i2c_csr_rw.303080618 Aug 12 04:33:02 PM PDT 24 Aug 12 04:33:02 PM PDT 24 47027943 ps
T1781 /workspace/coverage/cover_reg_top/24.i2c_intr_test.331203978 Aug 12 04:32:52 PM PDT 24 Aug 12 04:32:53 PM PDT 24 33326213 ps
T1782 /workspace/coverage/cover_reg_top/27.i2c_intr_test.2500898555 Aug 12 04:32:50 PM PDT 24 Aug 12 04:32:51 PM PDT 24 43559056 ps
T1783 /workspace/coverage/cover_reg_top/12.i2c_tl_errors.669288296 Aug 12 04:32:56 PM PDT 24 Aug 12 04:32:57 PM PDT 24 55606071 ps
T1784 /workspace/coverage/cover_reg_top/4.i2c_csr_mem_rw_with_rand_reset.2869663341 Aug 12 04:32:49 PM PDT 24 Aug 12 04:32:51 PM PDT 24 29817123 ps
T1785 /workspace/coverage/cover_reg_top/12.i2c_intr_test.2189243255 Aug 12 04:32:44 PM PDT 24 Aug 12 04:32:45 PM PDT 24 20126535 ps
T1786 /workspace/coverage/cover_reg_top/18.i2c_same_csr_outstanding.4093320358 Aug 12 04:33:05 PM PDT 24 Aug 12 04:33:06 PM PDT 24 84872635 ps
T1787 /workspace/coverage/cover_reg_top/41.i2c_intr_test.3262113125 Aug 12 04:33:04 PM PDT 24 Aug 12 04:33:05 PM PDT 24 142998463 ps
T1788 /workspace/coverage/cover_reg_top/0.i2c_tl_errors.2344637423 Aug 12 04:32:57 PM PDT 24 Aug 12 04:33:00 PM PDT 24 194344056 ps
T1789 /workspace/coverage/cover_reg_top/35.i2c_intr_test.1989237119 Aug 12 04:32:53 PM PDT 24 Aug 12 04:32:54 PM PDT 24 59739248 ps
T217 /workspace/coverage/cover_reg_top/7.i2c_tl_intg_err.560022794 Aug 12 04:32:47 PM PDT 24 Aug 12 04:32:48 PM PDT 24 51072036 ps
T1790 /workspace/coverage/cover_reg_top/37.i2c_intr_test.3391341757 Aug 12 04:33:03 PM PDT 24 Aug 12 04:33:04 PM PDT 24 16230661 ps
T1791 /workspace/coverage/cover_reg_top/4.i2c_tl_intg_err.2914847812 Aug 12 04:33:57 PM PDT 24 Aug 12 04:33:58 PM PDT 24 141918339 ps
T221 /workspace/coverage/cover_reg_top/15.i2c_tl_intg_err.4105484373 Aug 12 04:32:44 PM PDT 24 Aug 12 04:32:46 PM PDT 24 176197281 ps
T1792 /workspace/coverage/cover_reg_top/46.i2c_intr_test.1179815386 Aug 12 04:32:57 PM PDT 24 Aug 12 04:32:58 PM PDT 24 17443791 ps
T1793 /workspace/coverage/cover_reg_top/49.i2c_intr_test.4209895137 Aug 12 04:33:15 PM PDT 24 Aug 12 04:33:16 PM PDT 24 23632372 ps
T232 /workspace/coverage/cover_reg_top/6.i2c_csr_rw.2190155159 Aug 12 04:33:57 PM PDT 24 Aug 12 04:33:58 PM PDT 24 47857572 ps
T1794 /workspace/coverage/cover_reg_top/31.i2c_intr_test.785235866 Aug 12 04:32:54 PM PDT 24 Aug 12 04:32:55 PM PDT 24 26831018 ps
T1795 /workspace/coverage/cover_reg_top/8.i2c_csr_rw.1715346434 Aug 12 04:32:51 PM PDT 24 Aug 12 04:32:52 PM PDT 24 116311851 ps
T1796 /workspace/coverage/cover_reg_top/19.i2c_csr_mem_rw_with_rand_reset.881242003 Aug 12 04:33:04 PM PDT 24 Aug 12 04:33:06 PM PDT 24 45995804 ps
T1797 /workspace/coverage/cover_reg_top/18.i2c_csr_rw.865823449 Aug 12 04:33:17 PM PDT 24 Aug 12 04:33:18 PM PDT 24 17743160 ps
T1798 /workspace/coverage/cover_reg_top/8.i2c_tl_errors.3318894869 Aug 12 04:32:44 PM PDT 24 Aug 12 04:32:46 PM PDT 24 38342766 ps
T1799 /workspace/coverage/cover_reg_top/1.i2c_csr_rw.561300208 Aug 12 04:32:50 PM PDT 24 Aug 12 04:32:51 PM PDT 24 17284703 ps
T1800 /workspace/coverage/cover_reg_top/13.i2c_csr_mem_rw_with_rand_reset.4046886833 Aug 12 04:33:04 PM PDT 24 Aug 12 04:33:05 PM PDT 24 41881085 ps
T1801 /workspace/coverage/cover_reg_top/12.i2c_same_csr_outstanding.128909236 Aug 12 04:34:11 PM PDT 24 Aug 12 04:34:12 PM PDT 24 75441284 ps
T1802 /workspace/coverage/cover_reg_top/6.i2c_csr_mem_rw_with_rand_reset.3262707912 Aug 12 04:32:57 PM PDT 24 Aug 12 04:32:58 PM PDT 24 56632472 ps
T1803 /workspace/coverage/cover_reg_top/18.i2c_csr_mem_rw_with_rand_reset.4100904510 Aug 12 04:32:53 PM PDT 24 Aug 12 04:32:54 PM PDT 24 123356162 ps
T1804 /workspace/coverage/cover_reg_top/3.i2c_tl_errors.630506704 Aug 12 04:33:01 PM PDT 24 Aug 12 04:33:02 PM PDT 24 119830998 ps
T1805 /workspace/coverage/cover_reg_top/14.i2c_tl_errors.2221758693 Aug 12 04:32:57 PM PDT 24 Aug 12 04:32:59 PM PDT 24 194358107 ps
T1806 /workspace/coverage/cover_reg_top/33.i2c_intr_test.3668156029 Aug 12 04:33:05 PM PDT 24 Aug 12 04:33:05 PM PDT 24 29941003 ps
T1807 /workspace/coverage/cover_reg_top/8.i2c_intr_test.671576801 Aug 12 04:32:53 PM PDT 24 Aug 12 04:32:53 PM PDT 24 24948790 ps
T224 /workspace/coverage/cover_reg_top/10.i2c_tl_intg_err.1379327103 Aug 12 04:33:00 PM PDT 24 Aug 12 04:33:02 PM PDT 24 107597042 ps
T1808 /workspace/coverage/cover_reg_top/19.i2c_tl_errors.3573477182 Aug 12 04:32:54 PM PDT 24 Aug 12 04:32:56 PM PDT 24 322879855 ps
T1809 /workspace/coverage/cover_reg_top/44.i2c_intr_test.747234546 Aug 12 04:33:02 PM PDT 24 Aug 12 04:33:03 PM PDT 24 31973065 ps
T1810 /workspace/coverage/cover_reg_top/9.i2c_csr_rw.4262678178 Aug 12 04:32:53 PM PDT 24 Aug 12 04:32:53 PM PDT 24 45201860 ps
T1811 /workspace/coverage/cover_reg_top/2.i2c_csr_aliasing.325672273 Aug 12 04:32:49 PM PDT 24 Aug 12 04:32:50 PM PDT 24 54143380 ps
T1812 /workspace/coverage/cover_reg_top/18.i2c_tl_errors.3990384710 Aug 12 04:32:46 PM PDT 24 Aug 12 04:32:49 PM PDT 24 119828357 ps
T1813 /workspace/coverage/cover_reg_top/9.i2c_same_csr_outstanding.3922803542 Aug 12 04:32:50 PM PDT 24 Aug 12 04:32:51 PM PDT 24 22390982 ps
T233 /workspace/coverage/cover_reg_top/3.i2c_csr_rw.3885274284 Aug 12 04:32:57 PM PDT 24 Aug 12 04:32:58 PM PDT 24 21369394 ps
T1814 /workspace/coverage/cover_reg_top/25.i2c_intr_test.1725608962 Aug 12 04:33:04 PM PDT 24 Aug 12 04:33:05 PM PDT 24 23626178 ps
T1815 /workspace/coverage/cover_reg_top/17.i2c_tl_errors.1345042665 Aug 12 04:33:55 PM PDT 24 Aug 12 04:33:57 PM PDT 24 70104551 ps
T1816 /workspace/coverage/cover_reg_top/47.i2c_intr_test.137967506 Aug 12 04:32:53 PM PDT 24 Aug 12 04:32:54 PM PDT 24 19087202 ps
T234 /workspace/coverage/cover_reg_top/12.i2c_csr_rw.1098089789 Aug 12 04:34:20 PM PDT 24 Aug 12 04:34:21 PM PDT 24 86368714 ps
T1817 /workspace/coverage/cover_reg_top/11.i2c_tl_errors.2588905782 Aug 12 04:33:15 PM PDT 24 Aug 12 04:33:17 PM PDT 24 98157913 ps
T235 /workspace/coverage/cover_reg_top/2.i2c_csr_rw.1137117504 Aug 12 04:33:39 PM PDT 24 Aug 12 04:33:41 PM PDT 24 17220671 ps
T1818 /workspace/coverage/cover_reg_top/30.i2c_intr_test.3913098248 Aug 12 04:33:00 PM PDT 24 Aug 12 04:33:00 PM PDT 24 40110931 ps
T1819 /workspace/coverage/cover_reg_top/8.i2c_csr_mem_rw_with_rand_reset.2886882457 Aug 12 04:32:47 PM PDT 24 Aug 12 04:32:48 PM PDT 24 66259087 ps
T1820 /workspace/coverage/cover_reg_top/11.i2c_csr_rw.2636905641 Aug 12 04:34:13 PM PDT 24 Aug 12 04:34:14 PM PDT 24 45556198 ps
T1821 /workspace/coverage/cover_reg_top/1.i2c_intr_test.861209745 Aug 12 04:32:47 PM PDT 24 Aug 12 04:32:48 PM PDT 24 17734508 ps
T1822 /workspace/coverage/cover_reg_top/0.i2c_intr_test.1719539623 Aug 12 04:32:41 PM PDT 24 Aug 12 04:32:42 PM PDT 24 131051178 ps
T1823 /workspace/coverage/cover_reg_top/5.i2c_same_csr_outstanding.3784517121 Aug 12 04:33:01 PM PDT 24 Aug 12 04:33:02 PM PDT 24 41419388 ps
T1824 /workspace/coverage/cover_reg_top/17.i2c_intr_test.4116476606 Aug 12 04:34:20 PM PDT 24 Aug 12 04:34:21 PM PDT 24 79166622 ps
T1825 /workspace/coverage/cover_reg_top/3.i2c_same_csr_outstanding.2024296706 Aug 12 04:32:47 PM PDT 24 Aug 12 04:32:48 PM PDT 24 48007347 ps
T1826 /workspace/coverage/cover_reg_top/36.i2c_intr_test.1198353449 Aug 12 04:32:51 PM PDT 24 Aug 12 04:32:51 PM PDT 24 51302111 ps
T1827 /workspace/coverage/cover_reg_top/32.i2c_intr_test.4272581199 Aug 12 04:33:04 PM PDT 24 Aug 12 04:33:05 PM PDT 24 18490617 ps
T1828 /workspace/coverage/cover_reg_top/2.i2c_csr_hw_reset.3739561495 Aug 12 04:33:04 PM PDT 24 Aug 12 04:33:05 PM PDT 24 16320782 ps
T236 /workspace/coverage/cover_reg_top/13.i2c_csr_rw.1020554840 Aug 12 04:32:58 PM PDT 24 Aug 12 04:32:59 PM PDT 24 17970307 ps
T1829 /workspace/coverage/cover_reg_top/4.i2c_intr_test.1211146618 Aug 12 04:32:47 PM PDT 24 Aug 12 04:32:48 PM PDT 24 18427876 ps
T1830 /workspace/coverage/cover_reg_top/19.i2c_tl_intg_err.752869527 Aug 12 04:33:05 PM PDT 24 Aug 12 04:33:07 PM PDT 24 207763450 ps
T286 /workspace/coverage/cover_reg_top/5.i2c_tl_intg_err.1058289716 Aug 12 04:32:54 PM PDT 24 Aug 12 04:32:56 PM PDT 24 82408003 ps
T1831 /workspace/coverage/cover_reg_top/1.i2c_csr_mem_rw_with_rand_reset.4080597166 Aug 12 04:33:02 PM PDT 24 Aug 12 04:33:03 PM PDT 24 64093596 ps
T1832 /workspace/coverage/cover_reg_top/18.i2c_intr_test.1162840880 Aug 12 04:32:49 PM PDT 24 Aug 12 04:32:50 PM PDT 24 41910548 ps
T1833 /workspace/coverage/cover_reg_top/17.i2c_same_csr_outstanding.1957215196 Aug 12 04:32:47 PM PDT 24 Aug 12 04:32:48 PM PDT 24 30806622 ps
T1834 /workspace/coverage/cover_reg_top/10.i2c_intr_test.1950392832 Aug 12 04:32:47 PM PDT 24 Aug 12 04:32:48 PM PDT 24 169917840 ps
T1835 /workspace/coverage/cover_reg_top/16.i2c_intr_test.4280101267 Aug 12 04:32:43 PM PDT 24 Aug 12 04:32:44 PM PDT 24 29651080 ps
T1836 /workspace/coverage/cover_reg_top/3.i2c_intr_test.3437661521 Aug 12 04:33:00 PM PDT 24 Aug 12 04:33:01 PM PDT 24 21645831 ps
T1837 /workspace/coverage/cover_reg_top/15.i2c_csr_mem_rw_with_rand_reset.647490323 Aug 12 04:33:03 PM PDT 24 Aug 12 04:33:05 PM PDT 24 142855466 ps
T1838 /workspace/coverage/cover_reg_top/14.i2c_csr_rw.2930860400 Aug 12 04:32:45 PM PDT 24 Aug 12 04:32:46 PM PDT 24 33846281 ps
T1839 /workspace/coverage/cover_reg_top/16.i2c_csr_rw.1828190643 Aug 12 04:32:57 PM PDT 24 Aug 12 04:32:57 PM PDT 24 36576016 ps
T1840 /workspace/coverage/cover_reg_top/5.i2c_intr_test.2593752126 Aug 12 04:33:57 PM PDT 24 Aug 12 04:33:58 PM PDT 24 18284242 ps
T1841 /workspace/coverage/cover_reg_top/11.i2c_csr_mem_rw_with_rand_reset.255156805 Aug 12 04:33:02 PM PDT 24 Aug 12 04:33:03 PM PDT 24 85104814 ps
T212 /workspace/coverage/cover_reg_top/1.i2c_tl_intg_err.3556770167 Aug 12 04:32:49 PM PDT 24 Aug 12 04:32:52 PM PDT 24 376696692 ps
T1842 /workspace/coverage/cover_reg_top/0.i2c_csr_hw_reset.1950977547 Aug 12 04:32:57 PM PDT 24 Aug 12 04:32:58 PM PDT 24 45334651 ps
T1843 /workspace/coverage/cover_reg_top/9.i2c_intr_test.1720793900 Aug 12 04:32:44 PM PDT 24 Aug 12 04:32:45 PM PDT 24 50257458 ps
T1844 /workspace/coverage/cover_reg_top/2.i2c_csr_bit_bash.472331112 Aug 12 04:32:46 PM PDT 24 Aug 12 04:32:50 PM PDT 24 117294348 ps
T1845 /workspace/coverage/cover_reg_top/16.i2c_csr_mem_rw_with_rand_reset.2352928861 Aug 12 04:32:52 PM PDT 24 Aug 12 04:32:53 PM PDT 24 39627440 ps
T1846 /workspace/coverage/cover_reg_top/19.i2c_same_csr_outstanding.2090979150 Aug 12 04:33:05 PM PDT 24 Aug 12 04:33:06 PM PDT 24 82067255 ps
T213 /workspace/coverage/cover_reg_top/17.i2c_tl_intg_err.1000757826 Aug 12 04:34:19 PM PDT 24 Aug 12 04:34:21 PM PDT 24 91852245 ps
T190 /workspace/coverage/cover_reg_top/16.i2c_same_csr_outstanding.912364338 Aug 12 04:32:53 PM PDT 24 Aug 12 04:32:54 PM PDT 24 130734515 ps
T1847 /workspace/coverage/cover_reg_top/6.i2c_tl_errors.3069551422 Aug 12 04:33:39 PM PDT 24 Aug 12 04:33:42 PM PDT 24 155105259 ps
T1848 /workspace/coverage/cover_reg_top/45.i2c_intr_test.3571064640 Aug 12 04:33:05 PM PDT 24 Aug 12 04:33:06 PM PDT 24 41896904 ps
T1849 /workspace/coverage/cover_reg_top/3.i2c_tl_intg_err.3991887877 Aug 12 04:32:45 PM PDT 24 Aug 12 04:32:46 PM PDT 24 70672821 ps

Test location /workspace/coverage/default/4.i2c_target_smoke.750061669
Short name T8
Test name
Test status
Simulation time 2275652361 ps
CPU time 6.96 seconds
Started Aug 12 04:41:03 PM PDT 24
Finished Aug 12 04:41:10 PM PDT 24
Peak memory 213784 kb
Host smart-fb16db5e-0c8f-44c4-b1bb-89a80b1b2f2e
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=100_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licq
ueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=750061669 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ
=i2c_target_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.i2c_targ
et_smoke.750061669
Directory /workspace/4.i2c_target_smoke/latest

Test location /workspace/coverage/default/16.i2c_host_perf.2024884199
Short name T14
Test name
Test status
Simulation time 7359786124 ps
CPU time 271.12 seconds
Started Aug 12 04:42:32 PM PDT 24
Finished Aug 12 04:47:04 PM PDT 24
Peak memory 223312 kb
Host smart-7e5a34f7-2517-4054-b2af-9823babb0688
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2024884199 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_perf_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.i2c_host_perf.2024884199
Directory /workspace/16.i2c_host_perf/latest

Test location /workspace/coverage/default/5.i2c_host_stress_all.2007208214
Short name T21
Test name
Test status
Simulation time 39038390172 ps
CPU time 344.72 seconds
Started Aug 12 04:41:12 PM PDT 24
Finished Aug 12 04:46:57 PM PDT 24
Peak memory 1875004 kb
Host smart-5a61054b-7e13-45bd-941c-bbae1f714b6c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2007208214 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_stress_all_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.i2c_host_stress_all.2007208214
Directory /workspace/5.i2c_host_stress_all/latest

Test location /workspace/coverage/default/0.i2c_target_glitch.1452936719
Short name T51
Test name
Test status
Simulation time 4765464547 ps
CPU time 11.21 seconds
Started Aug 12 04:40:41 PM PDT 24
Finished Aug 12 04:40:53 PM PDT 24
Peak memory 213904 kb
Host smart-431e6d3f-c11a-4ef8-87ed-ee6ee57e39e7
User root
Command /workspace/default/simv +i2c_agent_mode=Host +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /wor
kspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1452936719 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_glitch_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.i2c_target_glitch.1452936719
Directory /workspace/0.i2c_target_glitch/latest

Test location /workspace/coverage/default/19.i2c_target_stress_all.1727218978
Short name T58
Test name
Test status
Simulation time 79102695702 ps
CPU time 147.2 seconds
Started Aug 12 04:43:08 PM PDT 24
Finished Aug 12 04:45:36 PM PDT 24
Peak memory 1513096 kb
Host smart-a50a481c-93c6-48a6-875f-01ad06e2cf3a
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=300_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VER
BOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1727218978 -assert nopostproc +UVM_TESTNAME=i2c_ba
se_test +UVM_TEST_SEQ=i2c_target_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /de
v/null -cm_name 19.i2c_target_stress_all.1727218978
Directory /workspace/19.i2c_target_stress_all/latest

Test location /workspace/coverage/cover_reg_top/10.i2c_csr_mem_rw_with_rand_reset.3390610350
Short name T107
Test name
Test status
Simulation time 195368245 ps
CPU time 0.83 seconds
Started Aug 12 04:33:04 PM PDT 24
Finished Aug 12 04:33:05 PM PDT 24
Peak memory 204620 kb
Host smart-3ebce5fb-9765-4985-aded-2a3e4b2d162f
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3390610350 -assert nopostproc +UVM_TESTNAME
=i2c_base_test +UVM_TEST_SEQ=i2c_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /
dev/null -cm_name 10.i2c_csr_mem_rw_with_rand_reset.3390610350
Directory /workspace/10.i2c_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/default/21.i2c_host_stress_all.1790024346
Short name T242
Test name
Test status
Simulation time 8445925446 ps
CPU time 593.43 seconds
Started Aug 12 04:43:21 PM PDT 24
Finished Aug 12 04:53:15 PM PDT 24
Peak memory 747156 kb
Host smart-1067793f-7e97-4fdc-a007-13213018944d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1790024346 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_stress_all_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.i2c_host_stress_all.1790024346
Directory /workspace/21.i2c_host_stress_all/latest

Test location /workspace/coverage/default/2.i2c_target_nack_txstretch.3651971185
Short name T9
Test name
Test status
Simulation time 314187843 ps
CPU time 1.47 seconds
Started Aug 12 04:41:00 PM PDT 24
Finished Aug 12 04:41:02 PM PDT 24
Peak memory 222220 kb
Host smart-d4f520cc-8f9e-41b5-b0b9-0711cdd09061
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3651971185 -assert nopostproc +UVM_TESTNAME=i2c_bas
e_test +UVM_TEST_SEQ=i2c_target_nack_txstretch_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log
/dev/null -cm_name 2.i2c_target_nack_txstretch.3651971185
Directory /workspace/2.i2c_target_nack_txstretch/latest

Test location /workspace/coverage/default/11.i2c_host_may_nack.3678139904
Short name T22
Test name
Test status
Simulation time 1800746240 ps
CPU time 37.13 seconds
Started Aug 12 04:42:01 PM PDT 24
Finished Aug 12 04:42:38 PM PDT 24
Peak memory 205304 kb
Host smart-45dacc18-0e1f-4e56-bb5e-f8f7dfbdba54
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3678139904 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_may_nack_vseq +en_cov=1 -cm line+cond+f
sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.i2c_host_may_nack.3678139904
Directory /workspace/11.i2c_host_may_nack/latest

Test location /workspace/coverage/default/14.i2c_host_override.2930007998
Short name T101
Test name
Test status
Simulation time 150088394 ps
CPU time 0.69 seconds
Started Aug 12 04:42:16 PM PDT 24
Finished Aug 12 04:42:17 PM PDT 24
Peak memory 204952 kb
Host smart-f2aa7c34-ec11-46bc-b31f-efc7dc74b698
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2930007998 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_override_vseq +en_cov=1 -cm line+cond+f
sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.i2c_host_override.2930007998
Directory /workspace/14.i2c_host_override/latest

Test location /workspace/coverage/default/1.i2c_sec_cm.2756176819
Short name T196
Test name
Test status
Simulation time 39983569 ps
CPU time 0.9 seconds
Started Aug 12 04:40:53 PM PDT 24
Finished Aug 12 04:40:54 PM PDT 24
Peak memory 223248 kb
Host smart-8c346aac-8dd2-4ffa-a0fe-b95b058db5fc
User root
Command /workspace/default/simv +run_sec_cm_fi +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2756176819 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_common_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.i2c_sec_cm.2756176819
Directory /workspace/1.i2c_sec_cm/latest

Test location /workspace/coverage/default/13.i2c_target_nack_acqfull_addr.289051597
Short name T60
Test name
Test status
Simulation time 871132149 ps
CPU time 2.62 seconds
Started Aug 12 04:42:19 PM PDT 24
Finished Aug 12 04:42:21 PM PDT 24
Peak memory 205468 kb
Host smart-e1399c4e-fd3a-468a-ae32-fca50eb3e9e8
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=289051597 -assert nopostproc +UVM_TESTNAME=i2c_base
_test +UVM_TEST_SEQ=i2c_target_nack_acqfull_addr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_lo
g /dev/null -cm_name 13.i2c_target_nack_acqfull_addr.289051597
Directory /workspace/13.i2c_target_nack_acqfull_addr/latest

Test location /workspace/coverage/default/6.i2c_host_fifo_reset_rx.3912188192
Short name T10
Test name
Test status
Simulation time 918861697 ps
CPU time 3.63 seconds
Started Aug 12 04:41:19 PM PDT 24
Finished Aug 12 04:41:23 PM PDT 24
Peak memory 205200 kb
Host smart-d7d2f874-68e6-42c0-8aad-28f84d60e96b
User root
Command /workspace/default/simv +test_timeout_ns=10_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3912188192 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_fifo_reset_
rx_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.i2c_host_fifo_reset_rx.
3912188192
Directory /workspace/6.i2c_host_fifo_reset_rx/latest

Test location /workspace/coverage/default/25.i2c_target_nack_acqfull_addr.388211359
Short name T71
Test name
Test status
Simulation time 1014799716 ps
CPU time 2.66 seconds
Started Aug 12 04:43:45 PM PDT 24
Finished Aug 12 04:43:48 PM PDT 24
Peak memory 205436 kb
Host smart-1febd386-72c2-495d-aa29-44534f46495c
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=388211359 -assert nopostproc +UVM_TESTNAME=i2c_base
_test +UVM_TEST_SEQ=i2c_target_nack_acqfull_addr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_lo
g /dev/null -cm_name 25.i2c_target_nack_acqfull_addr.388211359
Directory /workspace/25.i2c_target_nack_acqfull_addr/latest

Test location /workspace/coverage/default/15.i2c_host_perf.2587518355
Short name T16
Test name
Test status
Simulation time 25916343400 ps
CPU time 594.97 seconds
Started Aug 12 04:42:24 PM PDT 24
Finished Aug 12 04:52:20 PM PDT 24
Peak memory 1637500 kb
Host smart-ce677188-adf9-4203-ba2d-cad32285ef46
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2587518355 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_perf_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.i2c_host_perf.2587518355
Directory /workspace/15.i2c_host_perf/latest

Test location /workspace/coverage/cover_reg_top/3.i2c_csr_aliasing.1117943285
Short name T230
Test name
Test status
Simulation time 77780959 ps
CPU time 1.28 seconds
Started Aug 12 04:32:56 PM PDT 24
Finished Aug 12 04:32:57 PM PDT 24
Peak memory 204676 kb
Host smart-e6086f92-a29c-4f9e-826d-d285d04dbe8d
User root
Command /workspace/cover_reg_top/simv +csr_aliasing +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1117943285 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_common_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.i2c_csr_aliasing.1117943285
Directory /workspace/3.i2c_csr_aliasing/latest

Test location /workspace/coverage/cover_reg_top/11.i2c_tl_intg_err.2210595802
Short name T215
Test name
Test status
Simulation time 283508110 ps
CPU time 2.08 seconds
Started Aug 12 04:32:56 PM PDT 24
Finished Aug 12 04:32:59 PM PDT 24
Peak memory 204720 kb
Host smart-952a652c-d7bf-4c33-8ebf-04cef37bba66
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2210595802 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 11.i2c_tl_intg_err.2210595802
Directory /workspace/11.i2c_tl_intg_err/latest

Test location /workspace/coverage/default/49.i2c_target_bad_addr.3110167581
Short name T64
Test name
Test status
Simulation time 1278844612 ps
CPU time 6.41 seconds
Started Aug 12 04:46:55 PM PDT 24
Finished Aug 12 04:47:02 PM PDT 24
Peak memory 217256 kb
Host smart-5648f7a3-f1a1-458a-9a26-9bf2ab676af3
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +i2c_bad_addr_pct=50 +cdc_instrumentation_enabled=1 +UVM_
NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3110167581 -assert nopostproc
+UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_target_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.
vdb -cm_log /dev/null -cm_name 49.i2c_target_bad_addr.3110167581
Directory /workspace/49.i2c_target_bad_addr/latest

Test location /workspace/coverage/cover_reg_top/29.i2c_intr_test.942819065
Short name T295
Test name
Test status
Simulation time 39073368 ps
CPU time 0.65 seconds
Started Aug 12 04:32:57 PM PDT 24
Finished Aug 12 04:32:58 PM PDT 24
Peak memory 204488 kb
Host smart-e56feb18-7039-46c1-b4e8-e31cfeba1c11
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=942819065 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_common_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 29.i2c_intr_test.942819065
Directory /workspace/29.i2c_intr_test/latest

Test location /workspace/coverage/default/20.i2c_target_nack_acqfull.1718613644
Short name T67
Test name
Test status
Simulation time 2057332971 ps
CPU time 2.89 seconds
Started Aug 12 04:43:11 PM PDT 24
Finished Aug 12 04:43:14 PM PDT 24
Peak memory 213712 kb
Host smart-14798ceb-e9c5-4ddd-ada6-8368a060154c
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1718613644 -assert nopostproc +UVM_TESTNAME=i2c_bas
e_test +UVM_TEST_SEQ=i2c_target_nack_acqfull_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /d
ev/null -cm_name 20.i2c_target_nack_acqfull.1718613644
Directory /workspace/20.i2c_target_nack_acqfull/latest

Test location /workspace/coverage/default/22.i2c_host_fifo_reset_fmt.4143678225
Short name T251
Test name
Test status
Simulation time 111830885 ps
CPU time 1 seconds
Started Aug 12 04:43:21 PM PDT 24
Finished Aug 12 04:43:22 PM PDT 24
Peak memory 204980 kb
Host smart-1d6ba38c-bccd-424f-8e98-ade2e7b951f7
User root
Command /workspace/default/simv +test_timeout_ns=10_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4143678225 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_fifo_reset_
fmt_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.i2c_host_fifo_reset_f
mt.4143678225
Directory /workspace/22.i2c_host_fifo_reset_fmt/latest

Test location /workspace/coverage/default/11.i2c_host_stress_all.4257769221
Short name T26
Test name
Test status
Simulation time 89554325789 ps
CPU time 901.07 seconds
Started Aug 12 04:42:01 PM PDT 24
Finished Aug 12 04:57:03 PM PDT 24
Peak memory 2477588 kb
Host smart-f9306e90-fe81-4703-987d-8b12aca8014b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4257769221 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_stress_all_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.i2c_host_stress_all.4257769221
Directory /workspace/11.i2c_host_stress_all/latest

Test location /workspace/coverage/cover_reg_top/1.i2c_tl_errors.4033927134
Short name T193
Test name
Test status
Simulation time 125845864 ps
CPU time 2.28 seconds
Started Aug 12 04:32:56 PM PDT 24
Finished Aug 12 04:32:58 PM PDT 24
Peak memory 204800 kb
Host smart-c1036f2f-352c-440c-8bd7-76b901d2595a
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4033927134 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_common_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.i2c_tl_errors.4033927134
Directory /workspace/1.i2c_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/8.i2c_same_csr_outstanding.1798783533
Short name T241
Test name
Test status
Simulation time 177212628 ps
CPU time 1.18 seconds
Started Aug 12 04:32:51 PM PDT 24
Finished Aug 12 04:32:52 PM PDT 24
Peak memory 204620 kb
Host smart-9cfef87f-48c7-4ec6-8df0-3ce078457450
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1798783533 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_co
mmon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 8.i2c_same_csr_ou
tstanding.1798783533
Directory /workspace/8.i2c_same_csr_outstanding/latest

Test location /workspace/coverage/default/10.i2c_alert_test.2917903729
Short name T372
Test name
Test status
Simulation time 22275634 ps
CPU time 0.67 seconds
Started Aug 12 04:41:55 PM PDT 24
Finished Aug 12 04:41:56 PM PDT 24
Peak memory 204516 kb
Host smart-8b742e01-513e-4cd5-a90c-bead7b92d64c
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2917903729 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_common_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.i2c_alert_test.2917903729
Directory /workspace/10.i2c_alert_test/latest

Test location /workspace/coverage/default/11.i2c_target_fifo_watermarks_acq.2766930457
Short name T388
Test name
Test status
Simulation time 943100546 ps
CPU time 1.57 seconds
Started Aug 12 04:42:00 PM PDT 24
Finished Aug 12 04:42:02 PM PDT 24
Peak memory 205216 kb
Host smart-e6043e56-525f-469e-b111-8e6678b4fa45
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2766930457 -assert nopostproc +UVM_TESTNAME=i2c_bas
e_test +UVM_TEST_SEQ=i2c_target_fifo_watermarks_acq_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm
_log /dev/null -cm_name 11.i2c_target_fifo_watermarks_acq.2766930457
Directory /workspace/11.i2c_target_fifo_watermarks_acq/latest

Test location /workspace/coverage/default/20.i2c_target_intr_stress_wr.2242302643
Short name T426
Test name
Test status
Simulation time 20823376075 ps
CPU time 142.19 seconds
Started Aug 12 04:43:05 PM PDT 24
Finished Aug 12 04:45:28 PM PDT 24
Peak memory 1747144 kb
Host smart-3cbbbbc7-b8a4-42dd-8093-a38289943bdd
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=600_000_000 +use_intr_handler=1 +slow_acq=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNO
TES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2242302643 -assert nopostproc +UVM_TES
TNAME=i2c_base_test +UVM_TEST_SEQ=i2c_target_stress_wr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb
-cm_log /dev/null -cm_name 20.i2c_target_intr_stress_wr.2242302643
Directory /workspace/20.i2c_target_intr_stress_wr/latest

Test location /workspace/coverage/default/17.i2c_host_stress_all.1768174277
Short name T243
Test name
Test status
Simulation time 2811307289 ps
CPU time 170.61 seconds
Started Aug 12 04:42:42 PM PDT 24
Finished Aug 12 04:45:32 PM PDT 24
Peak memory 531044 kb
Host smart-baccc458-18fb-475e-8405-80354d24be3a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1768174277 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_stress_all_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.i2c_host_stress_all.1768174277
Directory /workspace/17.i2c_host_stress_all/latest

Test location /workspace/coverage/default/4.i2c_host_may_nack.2302542320
Short name T258
Test name
Test status
Simulation time 2436895397 ps
CPU time 24.48 seconds
Started Aug 12 04:41:11 PM PDT 24
Finished Aug 12 04:41:36 PM PDT 24
Peak memory 205268 kb
Host smart-71bddc22-870d-470c-a2c8-01f7a5f7de03
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2302542320 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_may_nack_vseq +en_cov=1 -cm line+cond+f
sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.i2c_host_may_nack.2302542320
Directory /workspace/4.i2c_host_may_nack/latest

Test location /workspace/coverage/default/10.i2c_host_mode_toggle.2545417201
Short name T11
Test name
Test status
Simulation time 76491924 ps
CPU time 3.03 seconds
Started Aug 12 04:41:55 PM PDT 24
Finished Aug 12 04:41:58 PM PDT 24
Peak memory 205204 kb
Host smart-3cac8710-67a8-4ab0-bbeb-207d456dd600
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2545417201 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_mode_toggle_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.i2c_host_mode_toggle.2545417201
Directory /workspace/10.i2c_host_mode_toggle/latest

Test location /workspace/coverage/default/10.i2c_host_stress_all.3611341686
Short name T105
Test name
Test status
Simulation time 24418701799 ps
CPU time 333.37 seconds
Started Aug 12 04:42:00 PM PDT 24
Finished Aug 12 04:47:34 PM PDT 24
Peak memory 1373160 kb
Host smart-19a08a53-81ae-45d5-b264-5bb89988f3bc
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3611341686 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_stress_all_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.i2c_host_stress_all.3611341686
Directory /workspace/10.i2c_host_stress_all/latest

Test location /workspace/coverage/default/1.i2c_host_fifo_watermark.433896268
Short name T124
Test name
Test status
Simulation time 6556145729 ps
CPU time 62.13 seconds
Started Aug 12 04:40:46 PM PDT 24
Finished Aug 12 04:41:48 PM PDT 24
Peak memory 890924 kb
Host smart-09e4cbb9-d66b-498f-87a5-68ae630b1245
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=433896268 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_fifo_watermark_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.i2c_host_fifo_watermark.433896268
Directory /workspace/1.i2c_host_fifo_watermark/latest

Test location /workspace/coverage/default/11.i2c_target_fifo_reset_tx.2380229964
Short name T92
Test name
Test status
Simulation time 427585100 ps
CPU time 1.09 seconds
Started Aug 12 04:41:59 PM PDT 24
Finished Aug 12 04:42:01 PM PDT 24
Peak memory 205600 kb
Host smart-2c23d425-c3c9-4ed5-9275-99319881426f
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2380229964 -assert nopostproc +UVM_TESTNAME=i2c_bas
e_test +UVM_TEST_SEQ=i2c_target_fifo_reset_tx_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /
dev/null -cm_name 11.i2c_target_fifo_reset_tx.2380229964
Directory /workspace/11.i2c_target_fifo_reset_tx/latest

Test location /workspace/coverage/cover_reg_top/17.i2c_tl_intg_err.1000757826
Short name T213
Test name
Test status
Simulation time 91852245 ps
CPU time 2 seconds
Started Aug 12 04:34:19 PM PDT 24
Finished Aug 12 04:34:21 PM PDT 24
Peak memory 204756 kb
Host smart-4aa8c073-e4c5-4f23-93d5-dfb3a250b510
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1000757826 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 17.i2c_tl_intg_err.1000757826
Directory /workspace/17.i2c_tl_intg_err/latest

Test location /workspace/coverage/default/1.i2c_host_fifo_reset_fmt.253431989
Short name T1741
Test name
Test status
Simulation time 144182401 ps
CPU time 1.16 seconds
Started Aug 12 04:40:52 PM PDT 24
Finished Aug 12 04:40:54 PM PDT 24
Peak memory 204912 kb
Host smart-c555fcd6-2065-4328-a569-f8ac2bb822c6
User root
Command /workspace/default/simv +test_timeout_ns=10_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=253431989 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_fifo_reset_f
mt_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.i2c_host_fifo_reset_fmt
.253431989
Directory /workspace/1.i2c_host_fifo_reset_fmt/latest

Test location /workspace/coverage/default/11.i2c_host_perf_precise.3330549794
Short name T911
Test name
Test status
Simulation time 1215400186 ps
CPU time 30.81 seconds
Started Aug 12 04:41:54 PM PDT 24
Finished Aug 12 04:42:25 PM PDT 24
Peak memory 317756 kb
Host smart-aa07eee4-4cc4-48dd-bff5-db6270756387
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3330549794 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_perf_precise_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.i2c_host_perf_precise.3330549794
Directory /workspace/11.i2c_host_perf_precise/latest

Test location /workspace/coverage/default/33.i2c_host_may_nack.2256615941
Short name T267
Test name
Test status
Simulation time 931587206 ps
CPU time 11.33 seconds
Started Aug 12 04:44:42 PM PDT 24
Finished Aug 12 04:44:53 PM PDT 24
Peak memory 205280 kb
Host smart-a31c9e7e-1b3a-4d5e-815c-7c49b2da3f3a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2256615941 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_may_nack_vseq +en_cov=1 -cm line+cond+f
sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.i2c_host_may_nack.2256615941
Directory /workspace/33.i2c_host_may_nack/latest

Test location /workspace/coverage/default/45.i2c_target_fifo_reset_acq.4118743003
Short name T247
Test name
Test status
Simulation time 869464859 ps
CPU time 1.19 seconds
Started Aug 12 04:46:15 PM PDT 24
Finished Aug 12 04:46:17 PM PDT 24
Peak memory 205268 kb
Host smart-70227366-839a-437c-a8e3-fe6fd8ec0715
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4118743003 -assert nopostproc +UVM_TESTNAME=i2c_bas
e_test +UVM_TEST_SEQ=i2c_target_fifo_reset_acq_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log
/dev/null -cm_name 45.i2c_target_fifo_reset_acq.4118743003
Directory /workspace/45.i2c_target_fifo_reset_acq/latest

Test location /workspace/coverage/default/8.i2c_target_stress_rd.2475251347
Short name T288
Test name
Test status
Simulation time 8784043976 ps
CPU time 50.16 seconds
Started Aug 12 04:41:38 PM PDT 24
Finished Aug 12 04:42:28 PM PDT 24
Peak memory 216328 kb
Host smart-9f98b391-aa91-4e18-bf52-931c8afc21b8
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=100_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licq
ueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2475251347 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SE
Q=i2c_target_stress_rd_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.i2c
_target_stress_rd.2475251347
Directory /workspace/8.i2c_target_stress_rd/latest

Test location /workspace/coverage/default/21.i2c_target_tx_stretch_ctrl.1207485847
Short name T57
Test name
Test status
Simulation time 144192061 ps
CPU time 3.19 seconds
Started Aug 12 04:43:21 PM PDT 24
Finished Aug 12 04:43:24 PM PDT 24
Peak memory 205416 kb
Host smart-53e35f76-c655-4879-acd2-81dd5122d522
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1207485847 -assert nopostproc +UVM_TESTNAME=i2c_bas
e_test +UVM_TEST_SEQ=i2c_target_tx_stretch_ctrl_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log
/dev/null -cm_name 21.i2c_target_tx_stretch_ctrl.1207485847
Directory /workspace/21.i2c_target_tx_stretch_ctrl/latest

Test location /workspace/coverage/cover_reg_top/12.i2c_tl_intg_err.2090961954
Short name T219
Test name
Test status
Simulation time 247811565 ps
CPU time 2.14 seconds
Started Aug 12 04:32:46 PM PDT 24
Finished Aug 12 04:32:48 PM PDT 24
Peak memory 204872 kb
Host smart-a75c42ff-17a6-4a63-aa14-446366c80aca
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2090961954 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 12.i2c_tl_intg_err.2090961954
Directory /workspace/12.i2c_tl_intg_err/latest

Test location /workspace/coverage/default/12.i2c_host_perf.1996145079
Short name T37
Test name
Test status
Simulation time 53543317033 ps
CPU time 187.28 seconds
Started Aug 12 04:42:00 PM PDT 24
Finished Aug 12 04:45:07 PM PDT 24
Peak memory 785280 kb
Host smart-6f746750-be6b-4e77-a71c-759ff2bbf6a6
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1996145079 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_perf_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.i2c_host_perf.1996145079
Directory /workspace/12.i2c_host_perf/latest

Test location /workspace/coverage/default/1.i2c_host_may_nack.2660664493
Short name T1463
Test name
Test status
Simulation time 488378028 ps
CPU time 5.98 seconds
Started Aug 12 04:40:52 PM PDT 24
Finished Aug 12 04:40:58 PM PDT 24
Peak memory 205184 kb
Host smart-69479301-0cc5-40e8-ab17-148e58e9b576
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2660664493 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_may_nack_vseq +en_cov=1 -cm line+cond+f
sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.i2c_host_may_nack.2660664493
Directory /workspace/1.i2c_host_may_nack/latest

Test location /workspace/coverage/default/11.i2c_target_perf.1430127920
Short name T291
Test name
Test status
Simulation time 661300339 ps
CPU time 5.08 seconds
Started Aug 12 04:42:05 PM PDT 24
Finished Aug 12 04:42:11 PM PDT 24
Peak memory 214404 kb
Host smart-fcec15f9-c733-4160-8541-8aec25532a51
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1430127920 -assert nopostproc +UVM_TESTNAME=i2c_bas
e_test +UVM_TEST_SEQ=i2c_target_perf_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null
-cm_name 11.i2c_target_perf.1430127920
Directory /workspace/11.i2c_target_perf/latest

Test location /workspace/coverage/default/15.i2c_target_fifo_reset_acq.1743121815
Short name T321
Test name
Test status
Simulation time 291799208 ps
CPU time 1.59 seconds
Started Aug 12 04:42:35 PM PDT 24
Finished Aug 12 04:42:37 PM PDT 24
Peak memory 205472 kb
Host smart-9790f47c-5722-4462-b849-15529b4f81bf
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1743121815 -assert nopostproc +UVM_TESTNAME=i2c_bas
e_test +UVM_TEST_SEQ=i2c_target_fifo_reset_acq_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log
/dev/null -cm_name 15.i2c_target_fifo_reset_acq.1743121815
Directory /workspace/15.i2c_target_fifo_reset_acq/latest

Test location /workspace/coverage/default/26.i2c_host_may_nack.11884386
Short name T272
Test name
Test status
Simulation time 1901840286 ps
CPU time 7.85 seconds
Started Aug 12 04:43:52 PM PDT 24
Finished Aug 12 04:44:00 PM PDT 24
Peak memory 205288 kb
Host smart-ec3c2463-7ebe-47ad-918a-5c04b2272ca4
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=11884386 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_may_nack_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.i2c_host_may_nack.11884386
Directory /workspace/26.i2c_host_may_nack/latest

Test location /workspace/coverage/default/7.i2c_host_override.592692396
Short name T278
Test name
Test status
Simulation time 40007206 ps
CPU time 0.65 seconds
Started Aug 12 04:41:27 PM PDT 24
Finished Aug 12 04:41:27 PM PDT 24
Peak memory 204884 kb
Host smart-e167c90d-d161-4bc4-b411-fc738aebfbeb
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=592692396 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_override_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.i2c_host_override.592692396
Directory /workspace/7.i2c_host_override/latest

Test location /workspace/coverage/default/8.i2c_host_may_nack.4138845023
Short name T257
Test name
Test status
Simulation time 1902246573 ps
CPU time 7.01 seconds
Started Aug 12 04:41:37 PM PDT 24
Finished Aug 12 04:41:44 PM PDT 24
Peak memory 205176 kb
Host smart-576a6e23-cf00-4947-869e-9338cc328ffe
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4138845023 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_may_nack_vseq +en_cov=1 -cm line+cond+f
sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.i2c_host_may_nack.4138845023
Directory /workspace/8.i2c_host_may_nack/latest

Test location /workspace/coverage/cover_reg_top/0.i2c_tl_intg_err.2628436058
Short name T220
Test name
Test status
Simulation time 81724086 ps
CPU time 1.59 seconds
Started Aug 12 04:32:44 PM PDT 24
Finished Aug 12 04:32:46 PM PDT 24
Peak memory 204684 kb
Host smart-10157734-d888-4fa9-bbec-f2eedf7a4564
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2628436058 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.i2c_tl_intg_err.2628436058
Directory /workspace/0.i2c_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/13.i2c_tl_intg_err.2075657895
Short name T207
Test name
Test status
Simulation time 184115631 ps
CPU time 2.2 seconds
Started Aug 12 04:33:07 PM PDT 24
Finished Aug 12 04:33:10 PM PDT 24
Peak memory 204760 kb
Host smart-f1c7da49-ac03-449f-ba7d-0e2a3ce628d5
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2075657895 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 13.i2c_tl_intg_err.2075657895
Directory /workspace/13.i2c_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/16.i2c_same_csr_outstanding.912364338
Short name T190
Test name
Test status
Simulation time 130734515 ps
CPU time 1.06 seconds
Started Aug 12 04:32:53 PM PDT 24
Finished Aug 12 04:32:54 PM PDT 24
Peak memory 204688 kb
Host smart-87369deb-8bc0-4c2a-9ee1-60abaa8aa40f
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=912364338 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_com
mon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 16.i2c_same_csr_ou
tstanding.912364338
Directory /workspace/16.i2c_same_csr_outstanding/latest

Test location /workspace/coverage/default/14.i2c_target_hrst.1834111321
Short name T186
Test name
Test status
Simulation time 256852495 ps
CPU time 2.28 seconds
Started Aug 12 04:42:27 PM PDT 24
Finished Aug 12 04:42:29 PM PDT 24
Peak memory 215896 kb
Host smart-c4fb5768-88bb-4bdb-bc4c-5c1e1c454363
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1834111321 -assert nopostproc +UVM_TESTNAME=i2c_bas
e_test +UVM_TEST_SEQ=i2c_target_hrst_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null
-cm_name 14.i2c_target_hrst.1834111321
Directory /workspace/14.i2c_target_hrst/latest

Test location /workspace/coverage/default/22.i2c_host_mode_toggle.142713270
Short name T563
Test name
Test status
Simulation time 157068769 ps
CPU time 2.52 seconds
Started Aug 12 04:43:25 PM PDT 24
Finished Aug 12 04:43:28 PM PDT 24
Peak memory 221452 kb
Host smart-25751e18-46d8-4185-9da3-05d773c1f6b9
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=142713270 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_mode_toggle_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.i2c_host_mode_toggle.142713270
Directory /workspace/22.i2c_host_mode_toggle/latest

Test location /workspace/coverage/default/34.i2c_host_mode_toggle.3695363074
Short name T75
Test name
Test status
Simulation time 348692486 ps
CPU time 1.5 seconds
Started Aug 12 04:44:52 PM PDT 24
Finished Aug 12 04:44:53 PM PDT 24
Peak memory 221300 kb
Host smart-43e3e451-a7b1-4ae8-a199-967218e67d3b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3695363074 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_mode_toggle_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.i2c_host_mode_toggle.3695363074
Directory /workspace/34.i2c_host_mode_toggle/latest

Test location /workspace/coverage/cover_reg_top/0.i2c_csr_aliasing.855318499
Short name T1761
Test name
Test status
Simulation time 91148459 ps
CPU time 1.19 seconds
Started Aug 12 04:32:58 PM PDT 24
Finished Aug 12 04:32:59 PM PDT 24
Peak memory 204716 kb
Host smart-cc14c58b-0942-4beb-96c3-e133631c0428
User root
Command /workspace/cover_reg_top/simv +csr_aliasing +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=855318499 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_common_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.i2c_csr_aliasing.855318499
Directory /workspace/0.i2c_csr_aliasing/latest

Test location /workspace/coverage/cover_reg_top/0.i2c_csr_bit_bash.2971616756
Short name T1769
Test name
Test status
Simulation time 3480317737 ps
CPU time 5.02 seconds
Started Aug 12 04:32:44 PM PDT 24
Finished Aug 12 04:32:49 PM PDT 24
Peak memory 204724 kb
Host smart-3b0c49ac-c77e-4f42-9da0-782c3195450f
User root
Command /workspace/cover_reg_top/simv +csr_bit_bash +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2971616756 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_common_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.i2c_csr_bit_bash.2971616756
Directory /workspace/0.i2c_csr_bit_bash/latest

Test location /workspace/coverage/cover_reg_top/0.i2c_csr_hw_reset.1950977547
Short name T1842
Test name
Test status
Simulation time 45334651 ps
CPU time 0.74 seconds
Started Aug 12 04:32:57 PM PDT 24
Finished Aug 12 04:32:58 PM PDT 24
Peak memory 204460 kb
Host smart-2814ad3f-dbde-4ecf-b1c6-411e8ed7f4cc
User root
Command /workspace/cover_reg_top/simv +csr_hw_reset +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1950977547 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_common_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.i2c_csr_hw_reset.1950977547
Directory /workspace/0.i2c_csr_hw_reset/latest

Test location /workspace/coverage/cover_reg_top/0.i2c_csr_mem_rw_with_rand_reset.313981103
Short name T226
Test name
Test status
Simulation time 85626242 ps
CPU time 1.16 seconds
Started Aug 12 04:32:43 PM PDT 24
Finished Aug 12 04:32:44 PM PDT 24
Peak memory 204844 kb
Host smart-f14a9518-dbd2-49ab-881e-f412e063afd2
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=313981103 -assert nopostproc +UVM_TESTNAME=
i2c_base_test +UVM_TEST_SEQ=i2c_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /d
ev/null -cm_name 0.i2c_csr_mem_rw_with_rand_reset.313981103
Directory /workspace/0.i2c_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/0.i2c_csr_rw.80255248
Short name T163
Test name
Test status
Simulation time 81354311 ps
CPU time 0.78 seconds
Started Aug 12 04:32:54 PM PDT 24
Finished Aug 12 04:32:55 PM PDT 24
Peak memory 204620 kb
Host smart-3a8551b9-6113-4d61-8d1a-7ce8a32f407f
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=80255248 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.i2c_csr_rw.80255248
Directory /workspace/0.i2c_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/0.i2c_intr_test.1719539623
Short name T1822
Test name
Test status
Simulation time 131051178 ps
CPU time 0.66 seconds
Started Aug 12 04:32:41 PM PDT 24
Finished Aug 12 04:32:42 PM PDT 24
Peak memory 204468 kb
Host smart-107c5afd-fad3-40d5-ac90-1f776ffec7d8
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1719539623 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_common_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.i2c_intr_test.1719539623
Directory /workspace/0.i2c_intr_test/latest

Test location /workspace/coverage/cover_reg_top/0.i2c_same_csr_outstanding.1727590230
Short name T113
Test name
Test status
Simulation time 104461998 ps
CPU time 0.86 seconds
Started Aug 12 04:32:46 PM PDT 24
Finished Aug 12 04:32:47 PM PDT 24
Peak memory 204500 kb
Host smart-4f38bc3f-f358-4abf-abe5-001de902dcb6
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1727590230 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_co
mmon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.i2c_same_csr_ou
tstanding.1727590230
Directory /workspace/0.i2c_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/0.i2c_tl_errors.2344637423
Short name T1788
Test name
Test status
Simulation time 194344056 ps
CPU time 2.64 seconds
Started Aug 12 04:32:57 PM PDT 24
Finished Aug 12 04:33:00 PM PDT 24
Peak memory 204800 kb
Host smart-a0f2477f-0c8d-43f7-b759-8207282d8dbb
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2344637423 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_common_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.i2c_tl_errors.2344637423
Directory /workspace/0.i2c_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/1.i2c_csr_aliasing.2518459158
Short name T1750
Test name
Test status
Simulation time 303943323 ps
CPU time 1.88 seconds
Started Aug 12 04:32:50 PM PDT 24
Finished Aug 12 04:32:52 PM PDT 24
Peak memory 204800 kb
Host smart-12ce94a2-2361-4439-b9d2-25854ead605f
User root
Command /workspace/cover_reg_top/simv +csr_aliasing +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2518459158 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_common_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.i2c_csr_aliasing.2518459158
Directory /workspace/1.i2c_csr_aliasing/latest

Test location /workspace/coverage/cover_reg_top/1.i2c_csr_bit_bash.1235887556
Short name T1747
Test name
Test status
Simulation time 112720732 ps
CPU time 4.68 seconds
Started Aug 12 04:33:02 PM PDT 24
Finished Aug 12 04:33:06 PM PDT 24
Peak memory 204800 kb
Host smart-efccd42d-1523-4716-a5fb-c868f45523b2
User root
Command /workspace/cover_reg_top/simv +csr_bit_bash +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1235887556 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_common_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.i2c_csr_bit_bash.1235887556
Directory /workspace/1.i2c_csr_bit_bash/latest

Test location /workspace/coverage/cover_reg_top/1.i2c_csr_hw_reset.1453269163
Short name T1772
Test name
Test status
Simulation time 52154882 ps
CPU time 0.8 seconds
Started Aug 12 04:33:00 PM PDT 24
Finished Aug 12 04:33:01 PM PDT 24
Peak memory 204576 kb
Host smart-080ad93e-e858-48c9-9291-aa937c5340d9
User root
Command /workspace/cover_reg_top/simv +csr_hw_reset +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1453269163 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_common_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.i2c_csr_hw_reset.1453269163
Directory /workspace/1.i2c_csr_hw_reset/latest

Test location /workspace/coverage/cover_reg_top/1.i2c_csr_mem_rw_with_rand_reset.4080597166
Short name T1831
Test name
Test status
Simulation time 64093596 ps
CPU time 1.05 seconds
Started Aug 12 04:33:02 PM PDT 24
Finished Aug 12 04:33:03 PM PDT 24
Peak memory 204516 kb
Host smart-6dae6fcc-424f-43c8-b1b9-7b3e5d9c9217
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4080597166 -assert nopostproc +UVM_TESTNAME
=i2c_base_test +UVM_TEST_SEQ=i2c_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /
dev/null -cm_name 1.i2c_csr_mem_rw_with_rand_reset.4080597166
Directory /workspace/1.i2c_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/1.i2c_csr_rw.561300208
Short name T1799
Test name
Test status
Simulation time 17284703 ps
CPU time 0.76 seconds
Started Aug 12 04:32:50 PM PDT 24
Finished Aug 12 04:32:51 PM PDT 24
Peak memory 204564 kb
Host smart-fd0eda05-761a-448f-b5df-d65f51365ab8
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=561300208 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.i2c_csr_rw.561300208
Directory /workspace/1.i2c_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/1.i2c_intr_test.861209745
Short name T1821
Test name
Test status
Simulation time 17734508 ps
CPU time 0.74 seconds
Started Aug 12 04:32:47 PM PDT 24
Finished Aug 12 04:32:48 PM PDT 24
Peak memory 204496 kb
Host smart-e68f3c6b-70eb-442a-beb4-3110e67a1d66
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=861209745 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_common_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.i2c_intr_test.861209745
Directory /workspace/1.i2c_intr_test/latest

Test location /workspace/coverage/cover_reg_top/1.i2c_tl_intg_err.3556770167
Short name T212
Test name
Test status
Simulation time 376696692 ps
CPU time 2.23 seconds
Started Aug 12 04:32:49 PM PDT 24
Finished Aug 12 04:32:52 PM PDT 24
Peak memory 204764 kb
Host smart-9bfb038c-8590-41fb-a07f-1907961564f9
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3556770167 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.i2c_tl_intg_err.3556770167
Directory /workspace/1.i2c_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/10.i2c_csr_rw.123391176
Short name T1763
Test name
Test status
Simulation time 51262917 ps
CPU time 0.7 seconds
Started Aug 12 04:33:00 PM PDT 24
Finished Aug 12 04:33:01 PM PDT 24
Peak memory 204616 kb
Host smart-3e12a6d5-e35e-46ad-8111-fe1ca8ca63d2
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=123391176 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 10.i2c_csr_rw.123391176
Directory /workspace/10.i2c_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/10.i2c_intr_test.1950392832
Short name T1834
Test name
Test status
Simulation time 169917840 ps
CPU time 0.64 seconds
Started Aug 12 04:32:47 PM PDT 24
Finished Aug 12 04:32:48 PM PDT 24
Peak memory 204548 kb
Host smart-905d0d3a-c79e-4f79-add3-51d1831a7e41
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1950392832 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_common_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 10.i2c_intr_test.1950392832
Directory /workspace/10.i2c_intr_test/latest

Test location /workspace/coverage/cover_reg_top/10.i2c_same_csr_outstanding.2556975245
Short name T135
Test name
Test status
Simulation time 69201384 ps
CPU time 0.91 seconds
Started Aug 12 04:32:51 PM PDT 24
Finished Aug 12 04:32:52 PM PDT 24
Peak memory 204524 kb
Host smart-1aea1eac-e916-4cd8-93c9-387b554d9e02
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2556975245 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_co
mmon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 10.i2c_same_csr_o
utstanding.2556975245
Directory /workspace/10.i2c_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/10.i2c_tl_errors.2590560893
Short name T192
Test name
Test status
Simulation time 131541685 ps
CPU time 3 seconds
Started Aug 12 04:32:57 PM PDT 24
Finished Aug 12 04:33:00 PM PDT 24
Peak memory 213028 kb
Host smart-d866024c-b796-4979-80af-500d547b57d2
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2590560893 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_common_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 10.i2c_tl_errors.2590560893
Directory /workspace/10.i2c_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/10.i2c_tl_intg_err.1379327103
Short name T224
Test name
Test status
Simulation time 107597042 ps
CPU time 2.18 seconds
Started Aug 12 04:33:00 PM PDT 24
Finished Aug 12 04:33:02 PM PDT 24
Peak memory 204684 kb
Host smart-c0287245-30f1-4ddd-a385-b74837948020
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1379327103 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 10.i2c_tl_intg_err.1379327103
Directory /workspace/10.i2c_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/11.i2c_csr_mem_rw_with_rand_reset.255156805
Short name T1841
Test name
Test status
Simulation time 85104814 ps
CPU time 0.88 seconds
Started Aug 12 04:33:02 PM PDT 24
Finished Aug 12 04:33:03 PM PDT 24
Peak memory 204452 kb
Host smart-37a26831-ef1b-4764-92a4-c28789004834
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=255156805 -assert nopostproc +UVM_TESTNAME=
i2c_base_test +UVM_TEST_SEQ=i2c_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /d
ev/null -cm_name 11.i2c_csr_mem_rw_with_rand_reset.255156805
Directory /workspace/11.i2c_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/11.i2c_csr_rw.2636905641
Short name T1820
Test name
Test status
Simulation time 45556198 ps
CPU time 0.68 seconds
Started Aug 12 04:34:13 PM PDT 24
Finished Aug 12 04:34:14 PM PDT 24
Peak memory 203996 kb
Host smart-bfb79987-74fc-4dac-8ed1-1e927a97cd51
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2636905641 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_common_vseq +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 11.i2c_csr_rw.2636905641
Directory /workspace/11.i2c_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/11.i2c_intr_test.800427697
Short name T1751
Test name
Test status
Simulation time 56329818 ps
CPU time 0.65 seconds
Started Aug 12 04:34:23 PM PDT 24
Finished Aug 12 04:34:28 PM PDT 24
Peak memory 204504 kb
Host smart-d8418076-da13-475e-b7a2-e170ebf3bcf3
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=800427697 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_common_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 11.i2c_intr_test.800427697
Directory /workspace/11.i2c_intr_test/latest

Test location /workspace/coverage/cover_reg_top/11.i2c_same_csr_outstanding.3618075127
Short name T240
Test name
Test status
Simulation time 49760271 ps
CPU time 1.2 seconds
Started Aug 12 04:32:45 PM PDT 24
Finished Aug 12 04:32:47 PM PDT 24
Peak memory 204000 kb
Host smart-584c0875-e49e-4cef-b3ff-3255196cc4e3
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3618075127 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_co
mmon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 11.i2c_same_csr_o
utstanding.3618075127
Directory /workspace/11.i2c_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/11.i2c_tl_errors.2588905782
Short name T1817
Test name
Test status
Simulation time 98157913 ps
CPU time 1.44 seconds
Started Aug 12 04:33:15 PM PDT 24
Finished Aug 12 04:33:17 PM PDT 24
Peak memory 204804 kb
Host smart-41bbf816-464a-4da0-ac76-feb3e71b470d
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2588905782 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_common_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 11.i2c_tl_errors.2588905782
Directory /workspace/11.i2c_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/12.i2c_csr_mem_rw_with_rand_reset.3430688219
Short name T1776
Test name
Test status
Simulation time 135041782 ps
CPU time 0.99 seconds
Started Aug 12 04:34:13 PM PDT 24
Finished Aug 12 04:34:15 PM PDT 24
Peak memory 204572 kb
Host smart-3f00066b-5614-430d-b3f2-96b9d8c81d22
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3430688219 -assert nopostproc +UVM_TESTNAME
=i2c_base_test +UVM_TEST_SEQ=i2c_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /
dev/null -cm_name 12.i2c_csr_mem_rw_with_rand_reset.3430688219
Directory /workspace/12.i2c_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/12.i2c_csr_rw.1098089789
Short name T234
Test name
Test status
Simulation time 86368714 ps
CPU time 0.78 seconds
Started Aug 12 04:34:20 PM PDT 24
Finished Aug 12 04:34:21 PM PDT 24
Peak memory 204516 kb
Host smart-8419c1e8-46e0-4c38-bd10-9084d1402bdb
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1098089789 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_common_vseq +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 12.i2c_csr_rw.1098089789
Directory /workspace/12.i2c_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/12.i2c_intr_test.2189243255
Short name T1785
Test name
Test status
Simulation time 20126535 ps
CPU time 0.73 seconds
Started Aug 12 04:32:44 PM PDT 24
Finished Aug 12 04:32:45 PM PDT 24
Peak memory 204524 kb
Host smart-09318ae2-94fc-48ce-b5d0-a93287cd5108
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2189243255 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_common_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 12.i2c_intr_test.2189243255
Directory /workspace/12.i2c_intr_test/latest

Test location /workspace/coverage/cover_reg_top/12.i2c_same_csr_outstanding.128909236
Short name T1801
Test name
Test status
Simulation time 75441284 ps
CPU time 0.97 seconds
Started Aug 12 04:34:11 PM PDT 24
Finished Aug 12 04:34:12 PM PDT 24
Peak memory 204168 kb
Host smart-9eedcfb6-9ede-45a5-84ea-bd946fafcc10
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=128909236 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_com
mon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 12.i2c_same_csr_ou
tstanding.128909236
Directory /workspace/12.i2c_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/12.i2c_tl_errors.669288296
Short name T1783
Test name
Test status
Simulation time 55606071 ps
CPU time 1.26 seconds
Started Aug 12 04:32:56 PM PDT 24
Finished Aug 12 04:32:57 PM PDT 24
Peak memory 204932 kb
Host smart-47ec156e-010f-4c54-8209-c90ac1c22d94
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=669288296 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_common_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 12.i2c_tl_errors.669288296
Directory /workspace/12.i2c_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/13.i2c_csr_mem_rw_with_rand_reset.4046886833
Short name T1800
Test name
Test status
Simulation time 41881085 ps
CPU time 0.77 seconds
Started Aug 12 04:33:04 PM PDT 24
Finished Aug 12 04:33:05 PM PDT 24
Peak memory 204600 kb
Host smart-1a994771-5c15-4647-92fb-0207ebb1d842
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4046886833 -assert nopostproc +UVM_TESTNAME
=i2c_base_test +UVM_TEST_SEQ=i2c_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /
dev/null -cm_name 13.i2c_csr_mem_rw_with_rand_reset.4046886833
Directory /workspace/13.i2c_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/13.i2c_csr_rw.1020554840
Short name T236
Test name
Test status
Simulation time 17970307 ps
CPU time 0.69 seconds
Started Aug 12 04:32:58 PM PDT 24
Finished Aug 12 04:32:59 PM PDT 24
Peak memory 204540 kb
Host smart-3ce41835-6c17-4824-a0bd-de9e8b2e0592
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1020554840 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_common_vseq +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 13.i2c_csr_rw.1020554840
Directory /workspace/13.i2c_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/13.i2c_intr_test.4279807006
Short name T1756
Test name
Test status
Simulation time 19095144 ps
CPU time 0.67 seconds
Started Aug 12 04:32:49 PM PDT 24
Finished Aug 12 04:32:50 PM PDT 24
Peak memory 204512 kb
Host smart-d7e80bae-8fb0-4ccb-becc-f380f63db00c
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4279807006 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_common_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 13.i2c_intr_test.4279807006
Directory /workspace/13.i2c_intr_test/latest

Test location /workspace/coverage/cover_reg_top/13.i2c_same_csr_outstanding.2118418720
Short name T1771
Test name
Test status
Simulation time 54606762 ps
CPU time 0.8 seconds
Started Aug 12 04:32:51 PM PDT 24
Finished Aug 12 04:32:51 PM PDT 24
Peak memory 204456 kb
Host smart-6c137842-55ce-4338-93b0-ff3b3bf622f6
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2118418720 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_co
mmon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 13.i2c_same_csr_o
utstanding.2118418720
Directory /workspace/13.i2c_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/13.i2c_tl_errors.2933917824
Short name T210
Test name
Test status
Simulation time 106155293 ps
CPU time 1.56 seconds
Started Aug 12 04:32:58 PM PDT 24
Finished Aug 12 04:33:00 PM PDT 24
Peak memory 204752 kb
Host smart-0b7d7ee7-3114-4fc4-955e-bdff52237693
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2933917824 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_common_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 13.i2c_tl_errors.2933917824
Directory /workspace/13.i2c_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/14.i2c_csr_mem_rw_with_rand_reset.2467201981
Short name T214
Test name
Test status
Simulation time 45651830 ps
CPU time 1.26 seconds
Started Aug 12 04:32:59 PM PDT 24
Finished Aug 12 04:33:00 PM PDT 24
Peak memory 204816 kb
Host smart-55803731-04f9-4c5e-831d-09071058fbe5
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2467201981 -assert nopostproc +UVM_TESTNAME
=i2c_base_test +UVM_TEST_SEQ=i2c_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /
dev/null -cm_name 14.i2c_csr_mem_rw_with_rand_reset.2467201981
Directory /workspace/14.i2c_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/14.i2c_csr_rw.2930860400
Short name T1838
Test name
Test status
Simulation time 33846281 ps
CPU time 0.79 seconds
Started Aug 12 04:32:45 PM PDT 24
Finished Aug 12 04:32:46 PM PDT 24
Peak memory 204536 kb
Host smart-23d63b79-a7c6-4131-a427-c294cc3560fd
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2930860400 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_common_vseq +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 14.i2c_csr_rw.2930860400
Directory /workspace/14.i2c_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/14.i2c_intr_test.1949603646
Short name T296
Test name
Test status
Simulation time 23848101 ps
CPU time 0.64 seconds
Started Aug 12 04:32:58 PM PDT 24
Finished Aug 12 04:32:59 PM PDT 24
Peak memory 204520 kb
Host smart-5d72a9a0-3b94-4b70-b05a-a5c71a23440b
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1949603646 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_common_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 14.i2c_intr_test.1949603646
Directory /workspace/14.i2c_intr_test/latest

Test location /workspace/coverage/cover_reg_top/14.i2c_same_csr_outstanding.430167191
Short name T238
Test name
Test status
Simulation time 32168510 ps
CPU time 0.77 seconds
Started Aug 12 04:34:11 PM PDT 24
Finished Aug 12 04:34:12 PM PDT 24
Peak memory 203896 kb
Host smart-a0b55c3d-942c-47ab-a11a-9b29cf7168cf
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=430167191 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_com
mon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 14.i2c_same_csr_ou
tstanding.430167191
Directory /workspace/14.i2c_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/14.i2c_tl_errors.2221758693
Short name T1805
Test name
Test status
Simulation time 194358107 ps
CPU time 1.63 seconds
Started Aug 12 04:32:57 PM PDT 24
Finished Aug 12 04:32:59 PM PDT 24
Peak memory 204792 kb
Host smart-3c758e50-b6f8-4330-87a2-cca8f2bdee9d
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2221758693 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_common_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 14.i2c_tl_errors.2221758693
Directory /workspace/14.i2c_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/14.i2c_tl_intg_err.864574309
Short name T216
Test name
Test status
Simulation time 178421798 ps
CPU time 1.42 seconds
Started Aug 12 04:32:53 PM PDT 24
Finished Aug 12 04:32:54 PM PDT 24
Peak memory 204708 kb
Host smart-e728dd7a-26cd-41ce-aafb-85a2155d551f
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=864574309 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 14.i2c_tl_intg_err.864574309
Directory /workspace/14.i2c_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/15.i2c_csr_mem_rw_with_rand_reset.647490323
Short name T1837
Test name
Test status
Simulation time 142855466 ps
CPU time 1.02 seconds
Started Aug 12 04:33:03 PM PDT 24
Finished Aug 12 04:33:05 PM PDT 24
Peak memory 204604 kb
Host smart-949eb781-93f8-480e-a5d2-3d8f3378c93e
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=647490323 -assert nopostproc +UVM_TESTNAME=
i2c_base_test +UVM_TEST_SEQ=i2c_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /d
ev/null -cm_name 15.i2c_csr_mem_rw_with_rand_reset.647490323
Directory /workspace/15.i2c_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/15.i2c_csr_rw.2026970378
Short name T114
Test name
Test status
Simulation time 36699435 ps
CPU time 0.67 seconds
Started Aug 12 04:32:58 PM PDT 24
Finished Aug 12 04:32:59 PM PDT 24
Peak memory 204540 kb
Host smart-9c70a887-1d9f-466d-b7c2-45fa2aa9bd00
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2026970378 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_common_vseq +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 15.i2c_csr_rw.2026970378
Directory /workspace/15.i2c_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/15.i2c_intr_test.3430742500
Short name T139
Test name
Test status
Simulation time 19781259 ps
CPU time 0.71 seconds
Started Aug 12 04:32:58 PM PDT 24
Finished Aug 12 04:32:58 PM PDT 24
Peak memory 204516 kb
Host smart-8b6f026c-2e7d-4331-b4ce-4af212396c24
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3430742500 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_common_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 15.i2c_intr_test.3430742500
Directory /workspace/15.i2c_intr_test/latest

Test location /workspace/coverage/cover_reg_top/15.i2c_same_csr_outstanding.3337227602
Short name T222
Test name
Test status
Simulation time 30526338 ps
CPU time 0.81 seconds
Started Aug 12 04:34:13 PM PDT 24
Finished Aug 12 04:34:14 PM PDT 24
Peak memory 203932 kb
Host smart-1863acda-1522-4187-a6d4-79dacaeaddb6
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3337227602 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_co
mmon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 15.i2c_same_csr_o
utstanding.3337227602
Directory /workspace/15.i2c_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/15.i2c_tl_errors.3092110883
Short name T112
Test name
Test status
Simulation time 536585632 ps
CPU time 2.75 seconds
Started Aug 12 04:32:48 PM PDT 24
Finished Aug 12 04:32:51 PM PDT 24
Peak memory 204808 kb
Host smart-c8e45e51-146d-4a84-b5ad-712df4d9d3ea
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3092110883 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_common_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 15.i2c_tl_errors.3092110883
Directory /workspace/15.i2c_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/15.i2c_tl_intg_err.4105484373
Short name T221
Test name
Test status
Simulation time 176197281 ps
CPU time 2.31 seconds
Started Aug 12 04:32:44 PM PDT 24
Finished Aug 12 04:32:46 PM PDT 24
Peak memory 204632 kb
Host smart-03cb103e-ed8c-4525-b370-b07f6ed62dcf
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4105484373 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 15.i2c_tl_intg_err.4105484373
Directory /workspace/15.i2c_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/16.i2c_csr_mem_rw_with_rand_reset.2352928861
Short name T1845
Test name
Test status
Simulation time 39627440 ps
CPU time 0.95 seconds
Started Aug 12 04:32:52 PM PDT 24
Finished Aug 12 04:32:53 PM PDT 24
Peak memory 204608 kb
Host smart-c0a74d40-bac7-4345-b2c4-3781ac891a6f
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2352928861 -assert nopostproc +UVM_TESTNAME
=i2c_base_test +UVM_TEST_SEQ=i2c_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /
dev/null -cm_name 16.i2c_csr_mem_rw_with_rand_reset.2352928861
Directory /workspace/16.i2c_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/16.i2c_csr_rw.1828190643
Short name T1839
Test name
Test status
Simulation time 36576016 ps
CPU time 0.75 seconds
Started Aug 12 04:32:57 PM PDT 24
Finished Aug 12 04:32:57 PM PDT 24
Peak memory 204540 kb
Host smart-2e4e4cde-a017-4839-8576-01ec3d817d33
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1828190643 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_common_vseq +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 16.i2c_csr_rw.1828190643
Directory /workspace/16.i2c_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/16.i2c_intr_test.4280101267
Short name T1835
Test name
Test status
Simulation time 29651080 ps
CPU time 0.71 seconds
Started Aug 12 04:32:43 PM PDT 24
Finished Aug 12 04:32:44 PM PDT 24
Peak memory 204440 kb
Host smart-c19baf94-ea07-420b-9e42-f308c535f6b7
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4280101267 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_common_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 16.i2c_intr_test.4280101267
Directory /workspace/16.i2c_intr_test/latest

Test location /workspace/coverage/cover_reg_top/16.i2c_tl_errors.873993536
Short name T1768
Test name
Test status
Simulation time 109224278 ps
CPU time 1.28 seconds
Started Aug 12 04:32:51 PM PDT 24
Finished Aug 12 04:32:53 PM PDT 24
Peak memory 204744 kb
Host smart-6033fc61-1971-47b8-b46e-c07866f9c234
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=873993536 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_common_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 16.i2c_tl_errors.873993536
Directory /workspace/16.i2c_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/16.i2c_tl_intg_err.868029324
Short name T108
Test name
Test status
Simulation time 69198900 ps
CPU time 1.47 seconds
Started Aug 12 04:33:03 PM PDT 24
Finished Aug 12 04:33:04 PM PDT 24
Peak memory 204680 kb
Host smart-ab2ed645-66e4-465b-a068-a8fbd1c7d202
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=868029324 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 16.i2c_tl_intg_err.868029324
Directory /workspace/16.i2c_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/17.i2c_csr_mem_rw_with_rand_reset.1297146158
Short name T1752
Test name
Test status
Simulation time 30966782 ps
CPU time 0.87 seconds
Started Aug 12 04:32:45 PM PDT 24
Finished Aug 12 04:32:46 PM PDT 24
Peak memory 204604 kb
Host smart-98742b88-9076-4839-bfb0-3dd7a25463cf
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1297146158 -assert nopostproc +UVM_TESTNAME
=i2c_base_test +UVM_TEST_SEQ=i2c_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /
dev/null -cm_name 17.i2c_csr_mem_rw_with_rand_reset.1297146158
Directory /workspace/17.i2c_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/17.i2c_csr_rw.173850578
Short name T115
Test name
Test status
Simulation time 19870239 ps
CPU time 0.65 seconds
Started Aug 12 04:33:08 PM PDT 24
Finished Aug 12 04:33:09 PM PDT 24
Peak memory 204528 kb
Host smart-0b5cdfea-bdcb-49de-b980-8f60882edb59
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=173850578 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 17.i2c_csr_rw.173850578
Directory /workspace/17.i2c_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/17.i2c_intr_test.4116476606
Short name T1824
Test name
Test status
Simulation time 79166622 ps
CPU time 0.65 seconds
Started Aug 12 04:34:20 PM PDT 24
Finished Aug 12 04:34:21 PM PDT 24
Peak memory 204504 kb
Host smart-c0815afa-6a7f-474f-93f8-0b06874f2022
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4116476606 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_common_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 17.i2c_intr_test.4116476606
Directory /workspace/17.i2c_intr_test/latest

Test location /workspace/coverage/cover_reg_top/17.i2c_same_csr_outstanding.1957215196
Short name T1833
Test name
Test status
Simulation time 30806622 ps
CPU time 1.15 seconds
Started Aug 12 04:32:47 PM PDT 24
Finished Aug 12 04:32:48 PM PDT 24
Peak memory 204608 kb
Host smart-47f42901-91ca-425b-bff7-5697bdb11c2d
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1957215196 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_co
mmon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 17.i2c_same_csr_o
utstanding.1957215196
Directory /workspace/17.i2c_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/17.i2c_tl_errors.1345042665
Short name T1815
Test name
Test status
Simulation time 70104551 ps
CPU time 1.6 seconds
Started Aug 12 04:33:55 PM PDT 24
Finished Aug 12 04:33:57 PM PDT 24
Peak memory 204028 kb
Host smart-7c22d3ad-87ad-4955-8ea3-a1891167c990
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1345042665 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_common_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 17.i2c_tl_errors.1345042665
Directory /workspace/17.i2c_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/18.i2c_csr_mem_rw_with_rand_reset.4100904510
Short name T1803
Test name
Test status
Simulation time 123356162 ps
CPU time 1.06 seconds
Started Aug 12 04:32:53 PM PDT 24
Finished Aug 12 04:32:54 PM PDT 24
Peak memory 204756 kb
Host smart-191dda4b-6fe4-4c23-8a5a-0b5538bda148
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4100904510 -assert nopostproc +UVM_TESTNAME
=i2c_base_test +UVM_TEST_SEQ=i2c_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /
dev/null -cm_name 18.i2c_csr_mem_rw_with_rand_reset.4100904510
Directory /workspace/18.i2c_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/18.i2c_csr_rw.865823449
Short name T1797
Test name
Test status
Simulation time 17743160 ps
CPU time 0.74 seconds
Started Aug 12 04:33:17 PM PDT 24
Finished Aug 12 04:33:18 PM PDT 24
Peak memory 204556 kb
Host smart-51f59362-afc9-4371-94bf-41e5e6431777
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=865823449 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 18.i2c_csr_rw.865823449
Directory /workspace/18.i2c_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/18.i2c_intr_test.1162840880
Short name T1832
Test name
Test status
Simulation time 41910548 ps
CPU time 0.68 seconds
Started Aug 12 04:32:49 PM PDT 24
Finished Aug 12 04:32:50 PM PDT 24
Peak memory 204576 kb
Host smart-02ed5611-f850-479c-a8bb-92e691c9a529
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1162840880 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_common_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 18.i2c_intr_test.1162840880
Directory /workspace/18.i2c_intr_test/latest

Test location /workspace/coverage/cover_reg_top/18.i2c_same_csr_outstanding.4093320358
Short name T1786
Test name
Test status
Simulation time 84872635 ps
CPU time 0.88 seconds
Started Aug 12 04:33:05 PM PDT 24
Finished Aug 12 04:33:06 PM PDT 24
Peak memory 204492 kb
Host smart-1c8cb48e-ef9f-48e2-b91f-6fad5588c91b
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4093320358 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_co
mmon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 18.i2c_same_csr_o
utstanding.4093320358
Directory /workspace/18.i2c_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/18.i2c_tl_errors.3990384710
Short name T1812
Test name
Test status
Simulation time 119828357 ps
CPU time 2.47 seconds
Started Aug 12 04:32:46 PM PDT 24
Finished Aug 12 04:32:49 PM PDT 24
Peak memory 204796 kb
Host smart-0ecc8db6-f7fe-4784-a368-a0cc115d9684
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3990384710 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_common_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 18.i2c_tl_errors.3990384710
Directory /workspace/18.i2c_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/18.i2c_tl_intg_err.2836279825
Short name T285
Test name
Test status
Simulation time 145067853 ps
CPU time 1.32 seconds
Started Aug 12 04:34:14 PM PDT 24
Finished Aug 12 04:34:15 PM PDT 24
Peak memory 204688 kb
Host smart-65962058-f7d0-4f01-a73a-bfd737fe2454
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2836279825 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 18.i2c_tl_intg_err.2836279825
Directory /workspace/18.i2c_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/19.i2c_csr_mem_rw_with_rand_reset.881242003
Short name T1796
Test name
Test status
Simulation time 45995804 ps
CPU time 0.87 seconds
Started Aug 12 04:33:04 PM PDT 24
Finished Aug 12 04:33:06 PM PDT 24
Peak memory 203740 kb
Host smart-e1e347c5-271e-414a-9e7c-6209df9db4f9
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=881242003 -assert nopostproc +UVM_TESTNAME=
i2c_base_test +UVM_TEST_SEQ=i2c_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /d
ev/null -cm_name 19.i2c_csr_mem_rw_with_rand_reset.881242003
Directory /workspace/19.i2c_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/19.i2c_csr_rw.2161523583
Short name T231
Test name
Test status
Simulation time 19289969 ps
CPU time 0.71 seconds
Started Aug 12 04:32:53 PM PDT 24
Finished Aug 12 04:32:54 PM PDT 24
Peak memory 204524 kb
Host smart-272472c5-07c0-40bb-8bcd-9df78413fc7a
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2161523583 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_common_vseq +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 19.i2c_csr_rw.2161523583
Directory /workspace/19.i2c_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/19.i2c_intr_test.413084967
Short name T1779
Test name
Test status
Simulation time 38724067 ps
CPU time 0.64 seconds
Started Aug 12 04:33:10 PM PDT 24
Finished Aug 12 04:33:11 PM PDT 24
Peak memory 204528 kb
Host smart-a95768db-9308-4155-ae2b-ac0178813f9d
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=413084967 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_common_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 19.i2c_intr_test.413084967
Directory /workspace/19.i2c_intr_test/latest

Test location /workspace/coverage/cover_reg_top/19.i2c_same_csr_outstanding.2090979150
Short name T1846
Test name
Test status
Simulation time 82067255 ps
CPU time 1.15 seconds
Started Aug 12 04:33:05 PM PDT 24
Finished Aug 12 04:33:06 PM PDT 24
Peak memory 204104 kb
Host smart-776600b1-80a6-4763-ac13-27dd77fdac10
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2090979150 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_co
mmon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 19.i2c_same_csr_o
utstanding.2090979150
Directory /workspace/19.i2c_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/19.i2c_tl_errors.3573477182
Short name T1808
Test name
Test status
Simulation time 322879855 ps
CPU time 2 seconds
Started Aug 12 04:32:54 PM PDT 24
Finished Aug 12 04:32:56 PM PDT 24
Peak memory 204840 kb
Host smart-2863a87e-a81c-48be-b58c-1919049926ca
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3573477182 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_common_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 19.i2c_tl_errors.3573477182
Directory /workspace/19.i2c_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/19.i2c_tl_intg_err.752869527
Short name T1830
Test name
Test status
Simulation time 207763450 ps
CPU time 1.46 seconds
Started Aug 12 04:33:05 PM PDT 24
Finished Aug 12 04:33:07 PM PDT 24
Peak memory 203516 kb
Host smart-cad970a8-0792-4daa-a3bd-da521557eb75
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=752869527 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 19.i2c_tl_intg_err.752869527
Directory /workspace/19.i2c_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/2.i2c_csr_aliasing.325672273
Short name T1811
Test name
Test status
Simulation time 54143380 ps
CPU time 1.25 seconds
Started Aug 12 04:32:49 PM PDT 24
Finished Aug 12 04:32:50 PM PDT 24
Peak memory 204740 kb
Host smart-7f520e2d-efdb-41a0-abec-20c7ef93057b
User root
Command /workspace/cover_reg_top/simv +csr_aliasing +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=325672273 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_common_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.i2c_csr_aliasing.325672273
Directory /workspace/2.i2c_csr_aliasing/latest

Test location /workspace/coverage/cover_reg_top/2.i2c_csr_bit_bash.472331112
Short name T1844
Test name
Test status
Simulation time 117294348 ps
CPU time 4.51 seconds
Started Aug 12 04:32:46 PM PDT 24
Finished Aug 12 04:32:50 PM PDT 24
Peak memory 204752 kb
Host smart-f38f8606-ca1d-446a-9f13-e2516087455d
User root
Command /workspace/cover_reg_top/simv +csr_bit_bash +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=472331112 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_common_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.i2c_csr_bit_bash.472331112
Directory /workspace/2.i2c_csr_bit_bash/latest

Test location /workspace/coverage/cover_reg_top/2.i2c_csr_hw_reset.3739561495
Short name T1828
Test name
Test status
Simulation time 16320782 ps
CPU time 0.74 seconds
Started Aug 12 04:33:04 PM PDT 24
Finished Aug 12 04:33:05 PM PDT 24
Peak memory 204536 kb
Host smart-54902a1e-da06-4d1f-89e4-12a2137d47d5
User root
Command /workspace/cover_reg_top/simv +csr_hw_reset +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3739561495 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_common_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.i2c_csr_hw_reset.3739561495
Directory /workspace/2.i2c_csr_hw_reset/latest

Test location /workspace/coverage/cover_reg_top/2.i2c_csr_mem_rw_with_rand_reset.4086274965
Short name T1757
Test name
Test status
Simulation time 22478171 ps
CPU time 0.85 seconds
Started Aug 12 04:32:56 PM PDT 24
Finished Aug 12 04:32:57 PM PDT 24
Peak memory 204532 kb
Host smart-68189cfa-f6eb-42ae-aa8c-510f34bfba65
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4086274965 -assert nopostproc +UVM_TESTNAME
=i2c_base_test +UVM_TEST_SEQ=i2c_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /
dev/null -cm_name 2.i2c_csr_mem_rw_with_rand_reset.4086274965
Directory /workspace/2.i2c_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/2.i2c_csr_rw.1137117504
Short name T235
Test name
Test status
Simulation time 17220671 ps
CPU time 0.75 seconds
Started Aug 12 04:33:39 PM PDT 24
Finished Aug 12 04:33:41 PM PDT 24
Peak memory 203220 kb
Host smart-7f89c316-7a3a-4192-80a5-2bfbc59e7a87
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1137117504 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_common_vseq +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.i2c_csr_rw.1137117504
Directory /workspace/2.i2c_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/2.i2c_intr_test.2965526863
Short name T1758
Test name
Test status
Simulation time 32642148 ps
CPU time 0.69 seconds
Started Aug 12 04:32:45 PM PDT 24
Finished Aug 12 04:32:46 PM PDT 24
Peak memory 204516 kb
Host smart-5e891883-7719-4977-b72d-a89fca959578
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2965526863 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_common_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.i2c_intr_test.2965526863
Directory /workspace/2.i2c_intr_test/latest

Test location /workspace/coverage/cover_reg_top/2.i2c_same_csr_outstanding.4011104042
Short name T109
Test name
Test status
Simulation time 96227862 ps
CPU time 1.16 seconds
Started Aug 12 04:32:45 PM PDT 24
Finished Aug 12 04:32:46 PM PDT 24
Peak memory 204732 kb
Host smart-9071ded7-878c-4358-a1f2-95331f05cf76
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4011104042 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_co
mmon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.i2c_same_csr_ou
tstanding.4011104042
Directory /workspace/2.i2c_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/2.i2c_tl_errors.3574275964
Short name T134
Test name
Test status
Simulation time 119687051 ps
CPU time 1.52 seconds
Started Aug 12 04:32:44 PM PDT 24
Finished Aug 12 04:32:47 PM PDT 24
Peak memory 204076 kb
Host smart-4712828a-7978-4342-89c8-21f28210883f
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3574275964 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_common_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.i2c_tl_errors.3574275964
Directory /workspace/2.i2c_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/2.i2c_tl_intg_err.1464769027
Short name T208
Test name
Test status
Simulation time 237046271 ps
CPU time 2.05 seconds
Started Aug 12 04:32:42 PM PDT 24
Finished Aug 12 04:32:44 PM PDT 24
Peak memory 204676 kb
Host smart-03f825cb-c809-4906-aa73-7352ec30defa
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1464769027 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.i2c_tl_intg_err.1464769027
Directory /workspace/2.i2c_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/20.i2c_intr_test.411437227
Short name T294
Test name
Test status
Simulation time 17407356 ps
CPU time 0.67 seconds
Started Aug 12 04:33:05 PM PDT 24
Finished Aug 12 04:33:06 PM PDT 24
Peak memory 204544 kb
Host smart-4f59d7fc-9c49-41f2-9da2-68b48d4f40c7
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=411437227 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_common_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 20.i2c_intr_test.411437227
Directory /workspace/20.i2c_intr_test/latest

Test location /workspace/coverage/cover_reg_top/21.i2c_intr_test.957607557
Short name T1775
Test name
Test status
Simulation time 20054563 ps
CPU time 0.7 seconds
Started Aug 12 04:32:54 PM PDT 24
Finished Aug 12 04:32:55 PM PDT 24
Peak memory 204612 kb
Host smart-8e7664bf-8b9a-4763-bd71-f142cb930d23
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=957607557 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_common_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 21.i2c_intr_test.957607557
Directory /workspace/21.i2c_intr_test/latest

Test location /workspace/coverage/cover_reg_top/22.i2c_intr_test.3607925896
Short name T1749
Test name
Test status
Simulation time 18144012 ps
CPU time 0.66 seconds
Started Aug 12 04:33:10 PM PDT 24
Finished Aug 12 04:33:10 PM PDT 24
Peak memory 204524 kb
Host smart-ac49fe95-263c-4897-a02b-a59f4418dad3
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3607925896 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_common_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 22.i2c_intr_test.3607925896
Directory /workspace/22.i2c_intr_test/latest

Test location /workspace/coverage/cover_reg_top/23.i2c_intr_test.3613519499
Short name T140
Test name
Test status
Simulation time 21136703 ps
CPU time 0.7 seconds
Started Aug 12 04:32:57 PM PDT 24
Finished Aug 12 04:32:58 PM PDT 24
Peak memory 204508 kb
Host smart-4335ad90-e2b7-4d3a-9f71-d808f50b12d7
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3613519499 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_common_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 23.i2c_intr_test.3613519499
Directory /workspace/23.i2c_intr_test/latest

Test location /workspace/coverage/cover_reg_top/24.i2c_intr_test.331203978
Short name T1781
Test name
Test status
Simulation time 33326213 ps
CPU time 0.65 seconds
Started Aug 12 04:32:52 PM PDT 24
Finished Aug 12 04:32:53 PM PDT 24
Peak memory 204488 kb
Host smart-d56bfdde-73d3-414c-8ff1-fb75853b2a87
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=331203978 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_common_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 24.i2c_intr_test.331203978
Directory /workspace/24.i2c_intr_test/latest

Test location /workspace/coverage/cover_reg_top/25.i2c_intr_test.1725608962
Short name T1814
Test name
Test status
Simulation time 23626178 ps
CPU time 0.72 seconds
Started Aug 12 04:33:04 PM PDT 24
Finished Aug 12 04:33:05 PM PDT 24
Peak memory 204484 kb
Host smart-64f60d3c-685b-4711-ad7a-487a0b024d7f
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1725608962 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_common_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 25.i2c_intr_test.1725608962
Directory /workspace/25.i2c_intr_test/latest

Test location /workspace/coverage/cover_reg_top/26.i2c_intr_test.728144368
Short name T141
Test name
Test status
Simulation time 19133013 ps
CPU time 0.68 seconds
Started Aug 12 04:32:53 PM PDT 24
Finished Aug 12 04:32:54 PM PDT 24
Peak memory 204864 kb
Host smart-6ce19fa7-50cf-431a-b5e6-355bd1ff47f2
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=728144368 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_common_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 26.i2c_intr_test.728144368
Directory /workspace/26.i2c_intr_test/latest

Test location /workspace/coverage/cover_reg_top/27.i2c_intr_test.2500898555
Short name T1782
Test name
Test status
Simulation time 43559056 ps
CPU time 0.66 seconds
Started Aug 12 04:32:50 PM PDT 24
Finished Aug 12 04:32:51 PM PDT 24
Peak memory 204524 kb
Host smart-2d7345a6-51a0-4c9b-a1b9-6b4523cadbaa
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2500898555 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_common_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 27.i2c_intr_test.2500898555
Directory /workspace/27.i2c_intr_test/latest

Test location /workspace/coverage/cover_reg_top/28.i2c_intr_test.129171513
Short name T1753
Test name
Test status
Simulation time 104910170 ps
CPU time 0.73 seconds
Started Aug 12 04:33:02 PM PDT 24
Finished Aug 12 04:33:03 PM PDT 24
Peak memory 204568 kb
Host smart-00166c3a-b033-463a-a21e-66d5cb685212
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=129171513 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_common_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 28.i2c_intr_test.129171513
Directory /workspace/28.i2c_intr_test/latest

Test location /workspace/coverage/cover_reg_top/3.i2c_csr_bit_bash.3930556411
Short name T106
Test name
Test status
Simulation time 538152470 ps
CPU time 3.05 seconds
Started Aug 12 04:32:45 PM PDT 24
Finished Aug 12 04:32:48 PM PDT 24
Peak memory 204768 kb
Host smart-9c4effc4-574a-43d5-9894-5f2f8fb27ca2
User root
Command /workspace/cover_reg_top/simv +csr_bit_bash +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3930556411 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_common_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.i2c_csr_bit_bash.3930556411
Directory /workspace/3.i2c_csr_bit_bash/latest

Test location /workspace/coverage/cover_reg_top/3.i2c_csr_hw_reset.1780833331
Short name T1778
Test name
Test status
Simulation time 57725017 ps
CPU time 0.73 seconds
Started Aug 12 04:32:54 PM PDT 24
Finished Aug 12 04:32:55 PM PDT 24
Peak memory 204472 kb
Host smart-59fcd30a-90be-41d2-b02c-cbacb0a49e08
User root
Command /workspace/cover_reg_top/simv +csr_hw_reset +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1780833331 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_common_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.i2c_csr_hw_reset.1780833331
Directory /workspace/3.i2c_csr_hw_reset/latest

Test location /workspace/coverage/cover_reg_top/3.i2c_csr_mem_rw_with_rand_reset.1207413011
Short name T1766
Test name
Test status
Simulation time 151559901 ps
CPU time 1.67 seconds
Started Aug 12 04:32:43 PM PDT 24
Finished Aug 12 04:32:45 PM PDT 24
Peak memory 220728 kb
Host smart-a92a211d-81d0-40d4-b759-e0c012630c27
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1207413011 -assert nopostproc +UVM_TESTNAME
=i2c_base_test +UVM_TEST_SEQ=i2c_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /
dev/null -cm_name 3.i2c_csr_mem_rw_with_rand_reset.1207413011
Directory /workspace/3.i2c_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/3.i2c_csr_rw.3885274284
Short name T233
Test name
Test status
Simulation time 21369394 ps
CPU time 0.75 seconds
Started Aug 12 04:32:57 PM PDT 24
Finished Aug 12 04:32:58 PM PDT 24
Peak memory 204592 kb
Host smart-25b3a160-17ef-40cb-8aeb-6557ac909258
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3885274284 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_common_vseq +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.i2c_csr_rw.3885274284
Directory /workspace/3.i2c_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/3.i2c_intr_test.3437661521
Short name T1836
Test name
Test status
Simulation time 21645831 ps
CPU time 0.68 seconds
Started Aug 12 04:33:00 PM PDT 24
Finished Aug 12 04:33:01 PM PDT 24
Peak memory 204500 kb
Host smart-3fd90195-bb5c-4185-8b34-7d9fc9d76a37
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3437661521 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_common_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.i2c_intr_test.3437661521
Directory /workspace/3.i2c_intr_test/latest

Test location /workspace/coverage/cover_reg_top/3.i2c_same_csr_outstanding.2024296706
Short name T1825
Test name
Test status
Simulation time 48007347 ps
CPU time 1.13 seconds
Started Aug 12 04:32:47 PM PDT 24
Finished Aug 12 04:32:48 PM PDT 24
Peak memory 204640 kb
Host smart-c348b3c3-a887-48ac-b96f-055d022e1fac
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2024296706 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_co
mmon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.i2c_same_csr_ou
tstanding.2024296706
Directory /workspace/3.i2c_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/3.i2c_tl_errors.630506704
Short name T1804
Test name
Test status
Simulation time 119830998 ps
CPU time 1.49 seconds
Started Aug 12 04:33:01 PM PDT 24
Finished Aug 12 04:33:02 PM PDT 24
Peak memory 204808 kb
Host smart-85651b3c-1529-44f7-9b87-1c16a2b7642b
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=630506704 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_common_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.i2c_tl_errors.630506704
Directory /workspace/3.i2c_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/3.i2c_tl_intg_err.3991887877
Short name T1849
Test name
Test status
Simulation time 70672821 ps
CPU time 1.52 seconds
Started Aug 12 04:32:45 PM PDT 24
Finished Aug 12 04:32:46 PM PDT 24
Peak memory 204680 kb
Host smart-264fb6c8-645f-4456-b753-c5846a536eeb
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3991887877 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.i2c_tl_intg_err.3991887877
Directory /workspace/3.i2c_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/30.i2c_intr_test.3913098248
Short name T1818
Test name
Test status
Simulation time 40110931 ps
CPU time 0.64 seconds
Started Aug 12 04:33:00 PM PDT 24
Finished Aug 12 04:33:00 PM PDT 24
Peak memory 204500 kb
Host smart-ee9bedac-58ef-4bb3-b00a-f562310323d8
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3913098248 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_common_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 30.i2c_intr_test.3913098248
Directory /workspace/30.i2c_intr_test/latest

Test location /workspace/coverage/cover_reg_top/31.i2c_intr_test.785235866
Short name T1794
Test name
Test status
Simulation time 26831018 ps
CPU time 0.69 seconds
Started Aug 12 04:32:54 PM PDT 24
Finished Aug 12 04:32:55 PM PDT 24
Peak memory 204508 kb
Host smart-4ba8fc53-8273-421f-a197-91df50fac2b9
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=785235866 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_common_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 31.i2c_intr_test.785235866
Directory /workspace/31.i2c_intr_test/latest

Test location /workspace/coverage/cover_reg_top/32.i2c_intr_test.4272581199
Short name T1827
Test name
Test status
Simulation time 18490617 ps
CPU time 0.69 seconds
Started Aug 12 04:33:04 PM PDT 24
Finished Aug 12 04:33:05 PM PDT 24
Peak memory 204560 kb
Host smart-a302b404-1db3-46f7-849f-06365adc8b8c
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4272581199 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_common_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 32.i2c_intr_test.4272581199
Directory /workspace/32.i2c_intr_test/latest

Test location /workspace/coverage/cover_reg_top/33.i2c_intr_test.3668156029
Short name T1806
Test name
Test status
Simulation time 29941003 ps
CPU time 0.67 seconds
Started Aug 12 04:33:05 PM PDT 24
Finished Aug 12 04:33:05 PM PDT 24
Peak memory 204512 kb
Host smart-4a04586a-113b-42fc-8996-cbeb3b5e14d3
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3668156029 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_common_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 33.i2c_intr_test.3668156029
Directory /workspace/33.i2c_intr_test/latest

Test location /workspace/coverage/cover_reg_top/34.i2c_intr_test.3952730547
Short name T1777
Test name
Test status
Simulation time 39179077 ps
CPU time 0.75 seconds
Started Aug 12 04:33:05 PM PDT 24
Finished Aug 12 04:33:06 PM PDT 24
Peak memory 204452 kb
Host smart-92171a0e-a2f6-4964-ab7c-3db3725ed62f
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3952730547 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_common_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 34.i2c_intr_test.3952730547
Directory /workspace/34.i2c_intr_test/latest

Test location /workspace/coverage/cover_reg_top/35.i2c_intr_test.1989237119
Short name T1789
Test name
Test status
Simulation time 59739248 ps
CPU time 0.67 seconds
Started Aug 12 04:32:53 PM PDT 24
Finished Aug 12 04:32:54 PM PDT 24
Peak memory 204472 kb
Host smart-46e1ad7d-2d64-4bd7-9d3a-61abc27cc54a
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1989237119 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_common_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 35.i2c_intr_test.1989237119
Directory /workspace/35.i2c_intr_test/latest

Test location /workspace/coverage/cover_reg_top/36.i2c_intr_test.1198353449
Short name T1826
Test name
Test status
Simulation time 51302111 ps
CPU time 0.68 seconds
Started Aug 12 04:32:51 PM PDT 24
Finished Aug 12 04:32:51 PM PDT 24
Peak memory 204524 kb
Host smart-21817fd5-7167-4843-9cf4-d84ad91af5f4
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1198353449 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_common_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 36.i2c_intr_test.1198353449
Directory /workspace/36.i2c_intr_test/latest

Test location /workspace/coverage/cover_reg_top/37.i2c_intr_test.3391341757
Short name T1790
Test name
Test status
Simulation time 16230661 ps
CPU time 0.69 seconds
Started Aug 12 04:33:03 PM PDT 24
Finished Aug 12 04:33:04 PM PDT 24
Peak memory 204572 kb
Host smart-d37d4446-4730-44ce-910d-9230f29b2d51
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3391341757 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_common_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 37.i2c_intr_test.3391341757
Directory /workspace/37.i2c_intr_test/latest

Test location /workspace/coverage/cover_reg_top/38.i2c_intr_test.1554544831
Short name T1767
Test name
Test status
Simulation time 63707859 ps
CPU time 0.69 seconds
Started Aug 12 04:32:58 PM PDT 24
Finished Aug 12 04:32:58 PM PDT 24
Peak memory 204512 kb
Host smart-2bad6d88-742b-4265-a446-98e4d32cf4bb
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1554544831 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_common_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 38.i2c_intr_test.1554544831
Directory /workspace/38.i2c_intr_test/latest

Test location /workspace/coverage/cover_reg_top/39.i2c_intr_test.1361708974
Short name T1754
Test name
Test status
Simulation time 59033627 ps
CPU time 0.67 seconds
Started Aug 12 04:32:56 PM PDT 24
Finished Aug 12 04:32:57 PM PDT 24
Peak memory 204452 kb
Host smart-bc2ae798-02d3-4231-b711-951ee277fb0c
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1361708974 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_common_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 39.i2c_intr_test.1361708974
Directory /workspace/39.i2c_intr_test/latest

Test location /workspace/coverage/cover_reg_top/4.i2c_csr_aliasing.2137186937
Short name T1764
Test name
Test status
Simulation time 360396244 ps
CPU time 1.75 seconds
Started Aug 12 04:32:49 PM PDT 24
Finished Aug 12 04:32:51 PM PDT 24
Peak memory 204700 kb
Host smart-fdd54ba8-5c8e-49e6-a343-894512fc420f
User root
Command /workspace/cover_reg_top/simv +csr_aliasing +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2137186937 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_common_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.i2c_csr_aliasing.2137186937
Directory /workspace/4.i2c_csr_aliasing/latest

Test location /workspace/coverage/cover_reg_top/4.i2c_csr_bit_bash.1951886815
Short name T237
Test name
Test status
Simulation time 1399749215 ps
CPU time 4.88 seconds
Started Aug 12 04:32:57 PM PDT 24
Finished Aug 12 04:33:03 PM PDT 24
Peak memory 204020 kb
Host smart-e6bb2758-41b2-42af-bbed-263d6a53c0d8
User root
Command /workspace/cover_reg_top/simv +csr_bit_bash +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1951886815 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_common_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.i2c_csr_bit_bash.1951886815
Directory /workspace/4.i2c_csr_bit_bash/latest

Test location /workspace/coverage/cover_reg_top/4.i2c_csr_hw_reset.3678567064
Short name T229
Test name
Test status
Simulation time 49658917 ps
CPU time 0.81 seconds
Started Aug 12 04:32:43 PM PDT 24
Finished Aug 12 04:32:44 PM PDT 24
Peak memory 204492 kb
Host smart-d47a3a79-bc0a-4e31-af20-d7384194c59e
User root
Command /workspace/cover_reg_top/simv +csr_hw_reset +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3678567064 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_common_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.i2c_csr_hw_reset.3678567064
Directory /workspace/4.i2c_csr_hw_reset/latest

Test location /workspace/coverage/cover_reg_top/4.i2c_csr_mem_rw_with_rand_reset.2869663341
Short name T1784
Test name
Test status
Simulation time 29817123 ps
CPU time 1.18 seconds
Started Aug 12 04:32:49 PM PDT 24
Finished Aug 12 04:32:51 PM PDT 24
Peak memory 204832 kb
Host smart-a92508ed-08e2-42ff-91b3-7e1fa071bfa5
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2869663341 -assert nopostproc +UVM_TESTNAME
=i2c_base_test +UVM_TEST_SEQ=i2c_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /
dev/null -cm_name 4.i2c_csr_mem_rw_with_rand_reset.2869663341
Directory /workspace/4.i2c_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/4.i2c_csr_rw.672937626
Short name T1770
Test name
Test status
Simulation time 70163248 ps
CPU time 0.76 seconds
Started Aug 12 04:33:12 PM PDT 24
Finished Aug 12 04:33:12 PM PDT 24
Peak memory 204552 kb
Host smart-14b27af6-23c6-4d2e-a06c-0c9caf192071
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=672937626 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.i2c_csr_rw.672937626
Directory /workspace/4.i2c_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/4.i2c_intr_test.1211146618
Short name T1829
Test name
Test status
Simulation time 18427876 ps
CPU time 0.65 seconds
Started Aug 12 04:32:47 PM PDT 24
Finished Aug 12 04:32:48 PM PDT 24
Peak memory 204548 kb
Host smart-643e4786-0639-4570-b54f-27327ae4a433
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1211146618 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_common_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.i2c_intr_test.1211146618
Directory /workspace/4.i2c_intr_test/latest

Test location /workspace/coverage/cover_reg_top/4.i2c_same_csr_outstanding.1509791109
Short name T239
Test name
Test status
Simulation time 96256521 ps
CPU time 1.08 seconds
Started Aug 12 04:32:56 PM PDT 24
Finished Aug 12 04:32:57 PM PDT 24
Peak memory 204732 kb
Host smart-da45ab09-3612-4a55-b02c-5715e9e70c33
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1509791109 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_co
mmon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.i2c_same_csr_ou
tstanding.1509791109
Directory /workspace/4.i2c_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/4.i2c_tl_errors.1977840336
Short name T1774
Test name
Test status
Simulation time 67709767 ps
CPU time 1.42 seconds
Started Aug 12 04:33:57 PM PDT 24
Finished Aug 12 04:33:58 PM PDT 24
Peak memory 204776 kb
Host smart-44511556-bac8-4567-b165-56d8d78bc5e6
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1977840336 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_common_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.i2c_tl_errors.1977840336
Directory /workspace/4.i2c_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/4.i2c_tl_intg_err.2914847812
Short name T1791
Test name
Test status
Simulation time 141918339 ps
CPU time 1.37 seconds
Started Aug 12 04:33:57 PM PDT 24
Finished Aug 12 04:33:58 PM PDT 24
Peak memory 204656 kb
Host smart-e2a41e18-1cd2-402c-8a62-cd367c3c407c
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2914847812 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.i2c_tl_intg_err.2914847812
Directory /workspace/4.i2c_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/40.i2c_intr_test.420771455
Short name T298
Test name
Test status
Simulation time 17131887 ps
CPU time 0.7 seconds
Started Aug 12 04:33:02 PM PDT 24
Finished Aug 12 04:33:03 PM PDT 24
Peak memory 204512 kb
Host smart-5ccb4d9a-05f0-4a80-bef9-07835822676e
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=420771455 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_common_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 40.i2c_intr_test.420771455
Directory /workspace/40.i2c_intr_test/latest

Test location /workspace/coverage/cover_reg_top/41.i2c_intr_test.3262113125
Short name T1787
Test name
Test status
Simulation time 142998463 ps
CPU time 0.69 seconds
Started Aug 12 04:33:04 PM PDT 24
Finished Aug 12 04:33:05 PM PDT 24
Peak memory 204516 kb
Host smart-c2c92547-9901-4e9a-842b-09f62979727b
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3262113125 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_common_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 41.i2c_intr_test.3262113125
Directory /workspace/41.i2c_intr_test/latest

Test location /workspace/coverage/cover_reg_top/42.i2c_intr_test.871739600
Short name T1748
Test name
Test status
Simulation time 46175636 ps
CPU time 0.66 seconds
Started Aug 12 04:33:07 PM PDT 24
Finished Aug 12 04:33:08 PM PDT 24
Peak memory 204532 kb
Host smart-2c6dbfb6-d770-4f37-826c-034099142f78
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=871739600 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_common_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 42.i2c_intr_test.871739600
Directory /workspace/42.i2c_intr_test/latest

Test location /workspace/coverage/cover_reg_top/43.i2c_intr_test.4209543820
Short name T1755
Test name
Test status
Simulation time 46430807 ps
CPU time 0.64 seconds
Started Aug 12 04:32:54 PM PDT 24
Finished Aug 12 04:32:55 PM PDT 24
Peak memory 204516 kb
Host smart-1c6b6740-8f9f-4766-925a-5dff1607eb7c
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4209543820 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_common_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 43.i2c_intr_test.4209543820
Directory /workspace/43.i2c_intr_test/latest

Test location /workspace/coverage/cover_reg_top/44.i2c_intr_test.747234546
Short name T1809
Test name
Test status
Simulation time 31973065 ps
CPU time 0.66 seconds
Started Aug 12 04:33:02 PM PDT 24
Finished Aug 12 04:33:03 PM PDT 24
Peak memory 204292 kb
Host smart-f120df26-a3a5-4dd2-96b2-cf0d5638851b
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=747234546 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_common_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 44.i2c_intr_test.747234546
Directory /workspace/44.i2c_intr_test/latest

Test location /workspace/coverage/cover_reg_top/45.i2c_intr_test.3571064640
Short name T1848
Test name
Test status
Simulation time 41896904 ps
CPU time 0.68 seconds
Started Aug 12 04:33:05 PM PDT 24
Finished Aug 12 04:33:06 PM PDT 24
Peak memory 204568 kb
Host smart-ee458578-a2b5-4231-8611-2eea33b25d41
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3571064640 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_common_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 45.i2c_intr_test.3571064640
Directory /workspace/45.i2c_intr_test/latest

Test location /workspace/coverage/cover_reg_top/46.i2c_intr_test.1179815386
Short name T1792
Test name
Test status
Simulation time 17443791 ps
CPU time 0.74 seconds
Started Aug 12 04:32:57 PM PDT 24
Finished Aug 12 04:32:58 PM PDT 24
Peak memory 204496 kb
Host smart-8805e15b-fa77-4f86-aa1c-8fc41824ae45
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1179815386 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_common_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 46.i2c_intr_test.1179815386
Directory /workspace/46.i2c_intr_test/latest

Test location /workspace/coverage/cover_reg_top/47.i2c_intr_test.137967506
Short name T1816
Test name
Test status
Simulation time 19087202 ps
CPU time 0.68 seconds
Started Aug 12 04:32:53 PM PDT 24
Finished Aug 12 04:32:54 PM PDT 24
Peak memory 204504 kb
Host smart-beef72cf-4add-485d-a59f-28399e6dea5c
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=137967506 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_common_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 47.i2c_intr_test.137967506
Directory /workspace/47.i2c_intr_test/latest

Test location /workspace/coverage/cover_reg_top/48.i2c_intr_test.767619585
Short name T297
Test name
Test status
Simulation time 25413463 ps
CPU time 0.66 seconds
Started Aug 12 04:32:54 PM PDT 24
Finished Aug 12 04:32:55 PM PDT 24
Peak memory 204508 kb
Host smart-94439c8e-045f-4d85-8ade-aa505841f059
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=767619585 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_common_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 48.i2c_intr_test.767619585
Directory /workspace/48.i2c_intr_test/latest

Test location /workspace/coverage/cover_reg_top/49.i2c_intr_test.4209895137
Short name T1793
Test name
Test status
Simulation time 23632372 ps
CPU time 0.69 seconds
Started Aug 12 04:33:15 PM PDT 24
Finished Aug 12 04:33:16 PM PDT 24
Peak memory 204520 kb
Host smart-00863383-529d-447e-aef1-c00eefddd1ee
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4209895137 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_common_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 49.i2c_intr_test.4209895137
Directory /workspace/49.i2c_intr_test/latest

Test location /workspace/coverage/cover_reg_top/5.i2c_csr_mem_rw_with_rand_reset.3353103366
Short name T209
Test name
Test status
Simulation time 98087529 ps
CPU time 1.3 seconds
Started Aug 12 04:32:42 PM PDT 24
Finished Aug 12 04:32:43 PM PDT 24
Peak memory 212884 kb
Host smart-d86cccec-0630-421c-8671-f9556f5e488e
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3353103366 -assert nopostproc +UVM_TESTNAME
=i2c_base_test +UVM_TEST_SEQ=i2c_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /
dev/null -cm_name 5.i2c_csr_mem_rw_with_rand_reset.3353103366
Directory /workspace/5.i2c_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/5.i2c_csr_rw.303080618
Short name T1780
Test name
Test status
Simulation time 47027943 ps
CPU time 0.72 seconds
Started Aug 12 04:33:02 PM PDT 24
Finished Aug 12 04:33:02 PM PDT 24
Peak memory 204632 kb
Host smart-23563a5f-3a74-49a6-8050-5b54b3fd5f82
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=303080618 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 5.i2c_csr_rw.303080618
Directory /workspace/5.i2c_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/5.i2c_intr_test.2593752126
Short name T1840
Test name
Test status
Simulation time 18284242 ps
CPU time 0.69 seconds
Started Aug 12 04:33:57 PM PDT 24
Finished Aug 12 04:33:58 PM PDT 24
Peak memory 204508 kb
Host smart-859ff70e-d82b-43c4-b59a-136f1edc5b1c
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2593752126 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_common_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 5.i2c_intr_test.2593752126
Directory /workspace/5.i2c_intr_test/latest

Test location /workspace/coverage/cover_reg_top/5.i2c_same_csr_outstanding.3784517121
Short name T1823
Test name
Test status
Simulation time 41419388 ps
CPU time 1.08 seconds
Started Aug 12 04:33:01 PM PDT 24
Finished Aug 12 04:33:02 PM PDT 24
Peak memory 204712 kb
Host smart-580812a0-342c-4d67-9ea1-74b44b6915bb
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3784517121 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_co
mmon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 5.i2c_same_csr_ou
tstanding.3784517121
Directory /workspace/5.i2c_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/5.i2c_tl_errors.2598365995
Short name T1762
Test name
Test status
Simulation time 25489182 ps
CPU time 1.21 seconds
Started Aug 12 04:33:57 PM PDT 24
Finished Aug 12 04:33:58 PM PDT 24
Peak memory 204764 kb
Host smart-26a74a44-e67a-43ac-8372-13519190cf19
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2598365995 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_common_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 5.i2c_tl_errors.2598365995
Directory /workspace/5.i2c_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/5.i2c_tl_intg_err.1058289716
Short name T286
Test name
Test status
Simulation time 82408003 ps
CPU time 1.45 seconds
Started Aug 12 04:32:54 PM PDT 24
Finished Aug 12 04:32:56 PM PDT 24
Peak memory 204760 kb
Host smart-f407f2f3-12ed-4b41-809b-66fe1d34efd9
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1058289716 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 5.i2c_tl_intg_err.1058289716
Directory /workspace/5.i2c_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/6.i2c_csr_mem_rw_with_rand_reset.3262707912
Short name T1802
Test name
Test status
Simulation time 56632472 ps
CPU time 0.96 seconds
Started Aug 12 04:32:57 PM PDT 24
Finished Aug 12 04:32:58 PM PDT 24
Peak memory 204552 kb
Host smart-9e6db6af-12fd-40fc-8e38-4d19656df385
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3262707912 -assert nopostproc +UVM_TESTNAME
=i2c_base_test +UVM_TEST_SEQ=i2c_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /
dev/null -cm_name 6.i2c_csr_mem_rw_with_rand_reset.3262707912
Directory /workspace/6.i2c_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/6.i2c_csr_rw.2190155159
Short name T232
Test name
Test status
Simulation time 47857572 ps
CPU time 0.66 seconds
Started Aug 12 04:33:57 PM PDT 24
Finished Aug 12 04:33:58 PM PDT 24
Peak memory 204496 kb
Host smart-e1169510-6a60-4ce5-99c7-3158414df8cf
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2190155159 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_common_vseq +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 6.i2c_csr_rw.2190155159
Directory /workspace/6.i2c_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/6.i2c_intr_test.621128327
Short name T1760
Test name
Test status
Simulation time 50918651 ps
CPU time 0.65 seconds
Started Aug 12 04:33:05 PM PDT 24
Finished Aug 12 04:33:06 PM PDT 24
Peak memory 204532 kb
Host smart-70200c88-9e4e-4a7c-893e-494419237ca9
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=621128327 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_common_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 6.i2c_intr_test.621128327
Directory /workspace/6.i2c_intr_test/latest

Test location /workspace/coverage/cover_reg_top/6.i2c_same_csr_outstanding.3897825561
Short name T110
Test name
Test status
Simulation time 62122030 ps
CPU time 1.17 seconds
Started Aug 12 04:32:51 PM PDT 24
Finished Aug 12 04:32:52 PM PDT 24
Peak memory 204696 kb
Host smart-4ed95236-2665-4702-b659-24c8269871e8
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3897825561 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_co
mmon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 6.i2c_same_csr_ou
tstanding.3897825561
Directory /workspace/6.i2c_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/6.i2c_tl_errors.3069551422
Short name T1847
Test name
Test status
Simulation time 155105259 ps
CPU time 1.5 seconds
Started Aug 12 04:33:39 PM PDT 24
Finished Aug 12 04:33:42 PM PDT 24
Peak memory 203544 kb
Host smart-a097d433-ad7a-4387-aa30-4b965d0a47f4
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3069551422 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_common_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 6.i2c_tl_errors.3069551422
Directory /workspace/6.i2c_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/6.i2c_tl_intg_err.2858807881
Short name T223
Test name
Test status
Simulation time 177883023 ps
CPU time 1.37 seconds
Started Aug 12 04:32:49 PM PDT 24
Finished Aug 12 04:32:51 PM PDT 24
Peak memory 204708 kb
Host smart-c9d4cb21-9c50-431d-8d5b-72d33ceadf3d
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2858807881 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 6.i2c_tl_intg_err.2858807881
Directory /workspace/6.i2c_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/7.i2c_csr_mem_rw_with_rand_reset.126912289
Short name T225
Test name
Test status
Simulation time 59974722 ps
CPU time 1.02 seconds
Started Aug 12 04:33:12 PM PDT 24
Finished Aug 12 04:33:13 PM PDT 24
Peak memory 204600 kb
Host smart-f6c376e6-cbd5-4b14-8fdd-3c25dc0aea40
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=126912289 -assert nopostproc +UVM_TESTNAME=
i2c_base_test +UVM_TEST_SEQ=i2c_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /d
ev/null -cm_name 7.i2c_csr_mem_rw_with_rand_reset.126912289
Directory /workspace/7.i2c_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/7.i2c_csr_rw.292561984
Short name T111
Test name
Test status
Simulation time 35224626 ps
CPU time 0.7 seconds
Started Aug 12 04:32:55 PM PDT 24
Finished Aug 12 04:32:56 PM PDT 24
Peak memory 204484 kb
Host smart-6a9a9a75-d513-4695-8aff-2129983d6037
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=292561984 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 7.i2c_csr_rw.292561984
Directory /workspace/7.i2c_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/7.i2c_intr_test.883318665
Short name T1759
Test name
Test status
Simulation time 22662611 ps
CPU time 0.76 seconds
Started Aug 12 04:32:58 PM PDT 24
Finished Aug 12 04:32:59 PM PDT 24
Peak memory 203836 kb
Host smart-fc6b3329-d639-4ee3-88de-86baa86dc143
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=883318665 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_common_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 7.i2c_intr_test.883318665
Directory /workspace/7.i2c_intr_test/latest

Test location /workspace/coverage/cover_reg_top/7.i2c_same_csr_outstanding.2569537093
Short name T1773
Test name
Test status
Simulation time 52366251 ps
CPU time 1.14 seconds
Started Aug 12 04:32:57 PM PDT 24
Finished Aug 12 04:32:58 PM PDT 24
Peak memory 204676 kb
Host smart-fa216653-fd14-4f1c-a17e-d4a6b03e40e0
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2569537093 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_co
mmon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 7.i2c_same_csr_ou
tstanding.2569537093
Directory /workspace/7.i2c_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/7.i2c_tl_errors.807271399
Short name T211
Test name
Test status
Simulation time 51666249 ps
CPU time 2.46 seconds
Started Aug 12 04:32:44 PM PDT 24
Finished Aug 12 04:32:46 PM PDT 24
Peak memory 213008 kb
Host smart-6d5fd364-46fd-4f73-ac9d-faf407b1c5ff
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=807271399 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_common_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 7.i2c_tl_errors.807271399
Directory /workspace/7.i2c_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/7.i2c_tl_intg_err.560022794
Short name T217
Test name
Test status
Simulation time 51072036 ps
CPU time 1.38 seconds
Started Aug 12 04:32:47 PM PDT 24
Finished Aug 12 04:32:48 PM PDT 24
Peak memory 204780 kb
Host smart-1ef307d7-13bf-442a-bf9e-b5acc0eeda3e
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=560022794 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 7.i2c_tl_intg_err.560022794
Directory /workspace/7.i2c_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/8.i2c_csr_mem_rw_with_rand_reset.2886882457
Short name T1819
Test name
Test status
Simulation time 66259087 ps
CPU time 0.96 seconds
Started Aug 12 04:32:47 PM PDT 24
Finished Aug 12 04:32:48 PM PDT 24
Peak memory 204608 kb
Host smart-31630b6d-9ed2-49b0-8225-b73564b8f88b
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2886882457 -assert nopostproc +UVM_TESTNAME
=i2c_base_test +UVM_TEST_SEQ=i2c_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /
dev/null -cm_name 8.i2c_csr_mem_rw_with_rand_reset.2886882457
Directory /workspace/8.i2c_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/8.i2c_csr_rw.1715346434
Short name T1795
Test name
Test status
Simulation time 116311851 ps
CPU time 0.68 seconds
Started Aug 12 04:32:51 PM PDT 24
Finished Aug 12 04:32:52 PM PDT 24
Peak memory 204488 kb
Host smart-239c08aa-b885-4b6e-9022-7a4c176bd265
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1715346434 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_common_vseq +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 8.i2c_csr_rw.1715346434
Directory /workspace/8.i2c_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/8.i2c_intr_test.671576801
Short name T1807
Test name
Test status
Simulation time 24948790 ps
CPU time 0.68 seconds
Started Aug 12 04:32:53 PM PDT 24
Finished Aug 12 04:32:53 PM PDT 24
Peak memory 204544 kb
Host smart-38fcfc7f-5502-416c-a82e-8e9717c0753a
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=671576801 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_common_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 8.i2c_intr_test.671576801
Directory /workspace/8.i2c_intr_test/latest

Test location /workspace/coverage/cover_reg_top/8.i2c_tl_errors.3318894869
Short name T1798
Test name
Test status
Simulation time 38342766 ps
CPU time 1.77 seconds
Started Aug 12 04:32:44 PM PDT 24
Finished Aug 12 04:32:46 PM PDT 24
Peak memory 204812 kb
Host smart-e9e441a6-1d31-4d18-aae6-a5f6a171bd7c
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3318894869 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_common_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 8.i2c_tl_errors.3318894869
Directory /workspace/8.i2c_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/8.i2c_tl_intg_err.2824393216
Short name T284
Test name
Test status
Simulation time 411986697 ps
CPU time 1.49 seconds
Started Aug 12 04:32:42 PM PDT 24
Finished Aug 12 04:32:44 PM PDT 24
Peak memory 204704 kb
Host smart-0da91bb8-ba3a-49b4-827a-849015a46c66
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2824393216 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 8.i2c_tl_intg_err.2824393216
Directory /workspace/8.i2c_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/9.i2c_csr_mem_rw_with_rand_reset.1978491007
Short name T194
Test name
Test status
Simulation time 79613399 ps
CPU time 0.92 seconds
Started Aug 12 04:32:58 PM PDT 24
Finished Aug 12 04:32:59 PM PDT 24
Peak memory 204576 kb
Host smart-444226ca-e82e-4d88-8025-9f25645feeba
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1978491007 -assert nopostproc +UVM_TESTNAME
=i2c_base_test +UVM_TEST_SEQ=i2c_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /
dev/null -cm_name 9.i2c_csr_mem_rw_with_rand_reset.1978491007
Directory /workspace/9.i2c_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/9.i2c_csr_rw.4262678178
Short name T1810
Test name
Test status
Simulation time 45201860 ps
CPU time 0.68 seconds
Started Aug 12 04:32:53 PM PDT 24
Finished Aug 12 04:32:53 PM PDT 24
Peak memory 204536 kb
Host smart-e2b83256-37db-43a6-b5f0-9de26a522776
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4262678178 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_common_vseq +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 9.i2c_csr_rw.4262678178
Directory /workspace/9.i2c_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/9.i2c_intr_test.1720793900
Short name T1843
Test name
Test status
Simulation time 50257458 ps
CPU time 0.73 seconds
Started Aug 12 04:32:44 PM PDT 24
Finished Aug 12 04:32:45 PM PDT 24
Peak memory 204528 kb
Host smart-c68bad99-17d9-419e-abc3-aadfe86234c4
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1720793900 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_common_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 9.i2c_intr_test.1720793900
Directory /workspace/9.i2c_intr_test/latest

Test location /workspace/coverage/cover_reg_top/9.i2c_same_csr_outstanding.3922803542
Short name T1813
Test name
Test status
Simulation time 22390982 ps
CPU time 0.82 seconds
Started Aug 12 04:32:50 PM PDT 24
Finished Aug 12 04:32:51 PM PDT 24
Peak memory 204488 kb
Host smart-a45ab712-1daa-4bac-aa76-8fce9740977d
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3922803542 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_co
mmon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 9.i2c_same_csr_ou
tstanding.3922803542
Directory /workspace/9.i2c_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/9.i2c_tl_errors.1513839326
Short name T1765
Test name
Test status
Simulation time 104779074 ps
CPU time 1.92 seconds
Started Aug 12 04:32:52 PM PDT 24
Finished Aug 12 04:32:54 PM PDT 24
Peak memory 212916 kb
Host smart-e79ddd5b-f326-4cc5-9ffd-a62337e26544
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1513839326 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_common_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 9.i2c_tl_errors.1513839326
Directory /workspace/9.i2c_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/9.i2c_tl_intg_err.4175636459
Short name T218
Test name
Test status
Simulation time 123141771 ps
CPU time 1.29 seconds
Started Aug 12 04:32:48 PM PDT 24
Finished Aug 12 04:32:49 PM PDT 24
Peak memory 204708 kb
Host smart-d3b95038-94cb-47c5-9958-ca51eca8919b
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4175636459 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 9.i2c_tl_intg_err.4175636459
Directory /workspace/9.i2c_tl_intg_err/latest

Test location /workspace/coverage/default/0.i2c_alert_test.2731363423
Short name T701
Test name
Test status
Simulation time 18340268 ps
CPU time 0.62 seconds
Started Aug 12 04:40:45 PM PDT 24
Finished Aug 12 04:40:45 PM PDT 24
Peak memory 204556 kb
Host smart-16c46899-ca3d-4cca-bc71-51686e202d07
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2731363423 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_common_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.i2c_alert_test.2731363423
Directory /workspace/0.i2c_alert_test/latest

Test location /workspace/coverage/default/0.i2c_host_error_intr.1817862305
Short name T1418
Test name
Test status
Simulation time 1047053954 ps
CPU time 4.22 seconds
Started Aug 12 04:40:40 PM PDT 24
Finished Aug 12 04:40:44 PM PDT 24
Peak memory 233624 kb
Host smart-f64897be-1062-4ca6-9bbf-c36ea2744cae
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1817862305 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_error_intr_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.i2c_host_error_intr.1817862305
Directory /workspace/0.i2c_host_error_intr/latest

Test location /workspace/coverage/default/0.i2c_host_fifo_fmt_empty.3971113768
Short name T1015
Test name
Test status
Simulation time 161972275 ps
CPU time 7.95 seconds
Started Aug 12 04:40:40 PM PDT 24
Finished Aug 12 04:40:48 PM PDT 24
Peak memory 227964 kb
Host smart-6295c35d-ef5b-42b4-9fa5-1f0264c489c7
User root
Command /workspace/default/simv +test_timeout_ns=10_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3971113768 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_fifo_fmt_em
pty_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.i2c_host_fifo_fmt_empt
y.3971113768
Directory /workspace/0.i2c_host_fifo_fmt_empty/latest

Test location /workspace/coverage/default/0.i2c_host_fifo_full.2634481884
Short name T1034
Test name
Test status
Simulation time 2089119051 ps
CPU time 127.87 seconds
Started Aug 12 04:40:40 PM PDT 24
Finished Aug 12 04:42:48 PM PDT 24
Peak memory 519968 kb
Host smart-c8c90033-3c26-41be-bf3d-45bbdc4b17ca
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2634481884 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_fifo_full_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.i2c_host_fifo_full.2634481884
Directory /workspace/0.i2c_host_fifo_full/latest

Test location /workspace/coverage/default/0.i2c_host_fifo_overflow.3452717968
Short name T849
Test name
Test status
Simulation time 3937401380 ps
CPU time 67 seconds
Started Aug 12 04:40:40 PM PDT 24
Finished Aug 12 04:41:47 PM PDT 24
Peak memory 698172 kb
Host smart-3f83f945-8a2c-482f-b482-a4a9d4562f37
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3452717968 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_fifo_overflow_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.i2c_host_fifo_overflow.3452717968
Directory /workspace/0.i2c_host_fifo_overflow/latest

Test location /workspace/coverage/default/0.i2c_host_fifo_reset_fmt.3202925134
Short name T1039
Test name
Test status
Simulation time 112776075 ps
CPU time 1.14 seconds
Started Aug 12 04:40:37 PM PDT 24
Finished Aug 12 04:40:38 PM PDT 24
Peak memory 204948 kb
Host smart-00538ebc-e477-40ea-8919-a43794d5d13d
User root
Command /workspace/default/simv +test_timeout_ns=10_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3202925134 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_fifo_reset_
fmt_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.i2c_host_fifo_reset_fm
t.3202925134
Directory /workspace/0.i2c_host_fifo_reset_fmt/latest

Test location /workspace/coverage/default/0.i2c_host_fifo_reset_rx.785931828
Short name T1589
Test name
Test status
Simulation time 152811208 ps
CPU time 7.94 seconds
Started Aug 12 04:40:43 PM PDT 24
Finished Aug 12 04:40:51 PM PDT 24
Peak memory 205268 kb
Host smart-93c27f4c-e816-4c17-9866-4d0113b719c3
User root
Command /workspace/default/simv +test_timeout_ns=10_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=785931828 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_fifo_reset_r
x_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.i2c_host_fifo_reset_rx.785931828
Directory /workspace/0.i2c_host_fifo_reset_rx/latest

Test location /workspace/coverage/default/0.i2c_host_fifo_watermark.3318502006
Short name T1070
Test name
Test status
Simulation time 19829154154 ps
CPU time 365.53 seconds
Started Aug 12 04:40:42 PM PDT 24
Finished Aug 12 04:46:47 PM PDT 24
Peak memory 1392768 kb
Host smart-02f1d64f-b9ea-44e3-8f2e-ae50330a0466
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3318502006 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_fifo_watermark_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.i2c_host_fifo_watermark.3318502006
Directory /workspace/0.i2c_host_fifo_watermark/latest

Test location /workspace/coverage/default/0.i2c_host_may_nack.4071986467
Short name T1576
Test name
Test status
Simulation time 233059675 ps
CPU time 3.28 seconds
Started Aug 12 04:40:43 PM PDT 24
Finished Aug 12 04:40:46 PM PDT 24
Peak memory 205200 kb
Host smart-a49183bf-2ec8-4337-8799-6b6b2eb6015a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4071986467 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_may_nack_vseq +en_cov=1 -cm line+cond+f
sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.i2c_host_may_nack.4071986467
Directory /workspace/0.i2c_host_may_nack/latest

Test location /workspace/coverage/default/0.i2c_host_override.707565150
Short name T547
Test name
Test status
Simulation time 19077712 ps
CPU time 0.69 seconds
Started Aug 12 04:40:39 PM PDT 24
Finished Aug 12 04:40:40 PM PDT 24
Peak memory 204904 kb
Host smart-b33f6efb-3bee-483a-8531-076b426cae97
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=707565150 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_override_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.i2c_host_override.707565150
Directory /workspace/0.i2c_host_override/latest

Test location /workspace/coverage/default/0.i2c_host_perf.2609185580
Short name T380
Test name
Test status
Simulation time 6797574530 ps
CPU time 60.88 seconds
Started Aug 12 04:40:40 PM PDT 24
Finished Aug 12 04:41:41 PM PDT 24
Peak memory 471288 kb
Host smart-0fdeccee-bd6a-4563-bca4-a5823d2e21d1
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2609185580 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_perf_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.i2c_host_perf.2609185580
Directory /workspace/0.i2c_host_perf/latest

Test location /workspace/coverage/default/0.i2c_host_perf_precise.1903764048
Short name T350
Test name
Test status
Simulation time 173379864 ps
CPU time 1.13 seconds
Started Aug 12 04:40:39 PM PDT 24
Finished Aug 12 04:40:40 PM PDT 24
Peak memory 213192 kb
Host smart-0c6b94d6-1c7d-4cc2-9850-22eb07887561
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1903764048 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_perf_precise_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.i2c_host_perf_precise.1903764048
Directory /workspace/0.i2c_host_perf_precise/latest

Test location /workspace/coverage/default/0.i2c_host_smoke.277813594
Short name T356
Test name
Test status
Simulation time 2368742598 ps
CPU time 32.18 seconds
Started Aug 12 04:40:41 PM PDT 24
Finished Aug 12 04:41:13 PM PDT 24
Peak memory 332692 kb
Host smart-126ed42f-8fb4-42c6-8cff-eccdc47edfb0
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=277813594 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_smoke_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.i2c_host_smoke.277813594
Directory /workspace/0.i2c_host_smoke/latest

Test location /workspace/coverage/default/0.i2c_host_stretch_timeout.1830649199
Short name T336
Test name
Test status
Simulation time 1502791003 ps
CPU time 11.33 seconds
Started Aug 12 04:40:41 PM PDT 24
Finished Aug 12 04:40:52 PM PDT 24
Peak memory 220996 kb
Host smart-4f12ee9b-2a68-4a37-b006-5cfc9a2b9a97
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1830649199 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_stretch_timeout_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.i2c_host_stretch_timeout.1830649199
Directory /workspace/0.i2c_host_stretch_timeout/latest

Test location /workspace/coverage/default/0.i2c_sec_cm.1359881405
Short name T199
Test name
Test status
Simulation time 382510164 ps
CPU time 0.89 seconds
Started Aug 12 04:40:42 PM PDT 24
Finished Aug 12 04:40:43 PM PDT 24
Peak memory 223296 kb
Host smart-e8eb708a-e1c6-4690-9387-ef7c288df2ca
User root
Command /workspace/default/simv +run_sec_cm_fi +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1359881405 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_common_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.i2c_sec_cm.1359881405
Directory /workspace/0.i2c_sec_cm/latest

Test location /workspace/coverage/default/0.i2c_target_bad_addr.1779069734
Short name T824
Test name
Test status
Simulation time 2730667272 ps
CPU time 3.8 seconds
Started Aug 12 04:40:46 PM PDT 24
Finished Aug 12 04:40:50 PM PDT 24
Peak memory 217672 kb
Host smart-87a81f52-d591-4b1c-bc83-cae510cea0ce
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +i2c_bad_addr_pct=50 +cdc_instrumentation_enabled=1 +UVM_
NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1779069734 -assert nopostproc
+UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_target_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.
vdb -cm_log /dev/null -cm_name 0.i2c_target_bad_addr.1779069734
Directory /workspace/0.i2c_target_bad_addr/latest

Test location /workspace/coverage/default/0.i2c_target_fifo_reset_acq.3330593388
Short name T422
Test name
Test status
Simulation time 628775807 ps
CPU time 0.87 seconds
Started Aug 12 04:40:44 PM PDT 24
Finished Aug 12 04:40:45 PM PDT 24
Peak memory 205256 kb
Host smart-15890d9d-9cb2-454d-9d3f-ca0614e13f80
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3330593388 -assert nopostproc +UVM_TESTNAME=i2c_bas
e_test +UVM_TEST_SEQ=i2c_target_fifo_reset_acq_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log
/dev/null -cm_name 0.i2c_target_fifo_reset_acq.3330593388
Directory /workspace/0.i2c_target_fifo_reset_acq/latest

Test location /workspace/coverage/default/0.i2c_target_fifo_reset_tx.1358939230
Short name T1372
Test name
Test status
Simulation time 204017879 ps
CPU time 1.01 seconds
Started Aug 12 04:40:41 PM PDT 24
Finished Aug 12 04:40:42 PM PDT 24
Peak memory 205288 kb
Host smart-0cc77290-0e6b-4930-9f4b-288263bc8fb7
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1358939230 -assert nopostproc +UVM_TESTNAME=i2c_bas
e_test +UVM_TEST_SEQ=i2c_target_fifo_reset_tx_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /
dev/null -cm_name 0.i2c_target_fifo_reset_tx.1358939230
Directory /workspace/0.i2c_target_fifo_reset_tx/latest

Test location /workspace/coverage/default/0.i2c_target_fifo_watermarks_acq.1257117780
Short name T864
Test name
Test status
Simulation time 666394834 ps
CPU time 3.1 seconds
Started Aug 12 04:40:44 PM PDT 24
Finished Aug 12 04:40:47 PM PDT 24
Peak memory 205440 kb
Host smart-046289fb-8029-4c81-bcd8-ed5f87a02f27
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1257117780 -assert nopostproc +UVM_TESTNAME=i2c_bas
e_test +UVM_TEST_SEQ=i2c_target_fifo_watermarks_acq_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm
_log /dev/null -cm_name 0.i2c_target_fifo_watermarks_acq.1257117780
Directory /workspace/0.i2c_target_fifo_watermarks_acq/latest

Test location /workspace/coverage/default/0.i2c_target_fifo_watermarks_tx.1706529817
Short name T1123
Test name
Test status
Simulation time 544538939 ps
CPU time 1.62 seconds
Started Aug 12 04:40:44 PM PDT 24
Finished Aug 12 04:40:46 PM PDT 24
Peak memory 205268 kb
Host smart-36f40d0b-e9bb-4737-aede-f1e2bd9ede5f
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1706529817 -assert nopostproc +UVM_TESTNAME=i2c_bas
e_test +UVM_TEST_SEQ=i2c_target_fifo_watermarks_tx_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_
log /dev/null -cm_name 0.i2c_target_fifo_watermarks_tx.1706529817
Directory /workspace/0.i2c_target_fifo_watermarks_tx/latest

Test location /workspace/coverage/default/0.i2c_target_hrst.3723514152
Short name T1131
Test name
Test status
Simulation time 718671284 ps
CPU time 2.64 seconds
Started Aug 12 04:40:43 PM PDT 24
Finished Aug 12 04:40:46 PM PDT 24
Peak memory 213800 kb
Host smart-8dc031ad-10ed-4d2f-bacd-d99c74e4b37a
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3723514152 -assert nopostproc +UVM_TESTNAME=i2c_bas
e_test +UVM_TEST_SEQ=i2c_target_hrst_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null
-cm_name 0.i2c_target_hrst.3723514152
Directory /workspace/0.i2c_target_hrst/latest

Test location /workspace/coverage/default/0.i2c_target_intr_smoke.607875150
Short name T1537
Test name
Test status
Simulation time 3907109971 ps
CPU time 5.97 seconds
Started Aug 12 04:40:44 PM PDT 24
Finished Aug 12 04:40:50 PM PDT 24
Peak memory 219748 kb
Host smart-2b667fd1-93a8-4a54-b3e1-3466e95b00e2
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=200_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VER
BOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=607875150 -assert nopostproc +UVM_TESTNAME=i2c_bas
e_test +UVM_TEST_SEQ=i2c_target_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null
-cm_name 0.i2c_target_intr_smoke.607875150
Directory /workspace/0.i2c_target_intr_smoke/latest

Test location /workspace/coverage/default/0.i2c_target_intr_stress_wr.1177171732
Short name T1030
Test name
Test status
Simulation time 20829272822 ps
CPU time 26.52 seconds
Started Aug 12 04:40:41 PM PDT 24
Finished Aug 12 04:41:08 PM PDT 24
Peak memory 722460 kb
Host smart-a51b3526-1726-4b23-9186-167becbd49c3
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=600_000_000 +use_intr_handler=1 +slow_acq=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNO
TES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1177171732 -assert nopostproc +UVM_TES
TNAME=i2c_base_test +UVM_TEST_SEQ=i2c_target_stress_wr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb
-cm_log /dev/null -cm_name 0.i2c_target_intr_stress_wr.1177171732
Directory /workspace/0.i2c_target_intr_stress_wr/latest

Test location /workspace/coverage/default/0.i2c_target_nack_acqfull.3662976379
Short name T1598
Test name
Test status
Simulation time 504573907 ps
CPU time 3.28 seconds
Started Aug 12 04:40:45 PM PDT 24
Finished Aug 12 04:40:49 PM PDT 24
Peak memory 213444 kb
Host smart-7cffbf68-52d3-481a-9938-13dc9d31b210
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3662976379 -assert nopostproc +UVM_TESTNAME=i2c_bas
e_test +UVM_TEST_SEQ=i2c_target_nack_acqfull_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /d
ev/null -cm_name 0.i2c_target_nack_acqfull.3662976379
Directory /workspace/0.i2c_target_nack_acqfull/latest

Test location /workspace/coverage/default/0.i2c_target_nack_acqfull_addr.1900277987
Short name T1253
Test name
Test status
Simulation time 1864314170 ps
CPU time 2.4 seconds
Started Aug 12 04:40:45 PM PDT 24
Finished Aug 12 04:40:48 PM PDT 24
Peak memory 205212 kb
Host smart-b69afe06-ac13-411c-bc6c-9f356152f06d
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1900277987 -assert nopostproc +UVM_TESTNAME=i2c_bas
e_test +UVM_TEST_SEQ=i2c_target_nack_acqfull_addr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_l
og /dev/null -cm_name 0.i2c_target_nack_acqfull_addr.1900277987
Directory /workspace/0.i2c_target_nack_acqfull_addr/latest

Test location /workspace/coverage/default/0.i2c_target_nack_txstretch.411965592
Short name T973
Test name
Test status
Simulation time 546756389 ps
CPU time 1.42 seconds
Started Aug 12 04:40:45 PM PDT 24
Finished Aug 12 04:40:46 PM PDT 24
Peak memory 221908 kb
Host smart-be8ba5ae-2648-4771-b128-b144e419690f
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=411965592 -assert nopostproc +UVM_TESTNAME=i2c_base
_test +UVM_TEST_SEQ=i2c_target_nack_txstretch_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /
dev/null -cm_name 0.i2c_target_nack_txstretch.411965592
Directory /workspace/0.i2c_target_nack_txstretch/latest

Test location /workspace/coverage/default/0.i2c_target_perf.2778787652
Short name T542
Test name
Test status
Simulation time 1059257776 ps
CPU time 8.23 seconds
Started Aug 12 04:40:40 PM PDT 24
Finished Aug 12 04:40:48 PM PDT 24
Peak memory 230128 kb
Host smart-c9af7dec-48c2-4b4b-a691-6008dce8e827
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2778787652 -assert nopostproc +UVM_TESTNAME=i2c_bas
e_test +UVM_TEST_SEQ=i2c_target_perf_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null
-cm_name 0.i2c_target_perf.2778787652
Directory /workspace/0.i2c_target_perf/latest

Test location /workspace/coverage/default/0.i2c_target_smbus_maxlen.2918829250
Short name T1088
Test name
Test status
Simulation time 475716558 ps
CPU time 2.29 seconds
Started Aug 12 04:40:42 PM PDT 24
Finished Aug 12 04:40:44 PM PDT 24
Peak memory 205104 kb
Host smart-99e5389c-5398-49e9-ac04-7f74ad5aa914
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2918829250 -assert nopostproc +UVM_TESTNAME=i2c_bas
e_test +UVM_TEST_SEQ=i2c_target_smbus_maxlen_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /d
ev/null -cm_name 0.i2c_target_smbus_maxlen.2918829250
Directory /workspace/0.i2c_target_smbus_maxlen/latest

Test location /workspace/coverage/default/0.i2c_target_smoke.3753201531
Short name T446
Test name
Test status
Simulation time 4038328170 ps
CPU time 12.61 seconds
Started Aug 12 04:40:38 PM PDT 24
Finished Aug 12 04:40:51 PM PDT 24
Peak memory 213756 kb
Host smart-6168628b-7485-414c-823e-d4d0b01e01c1
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=100_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licq
ueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3753201531 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SE
Q=i2c_target_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.i2c_tar
get_smoke.3753201531
Directory /workspace/0.i2c_target_smoke/latest

Test location /workspace/coverage/default/0.i2c_target_stress_all.4241722357
Short name T557
Test name
Test status
Simulation time 36093675594 ps
CPU time 1126.09 seconds
Started Aug 12 04:40:43 PM PDT 24
Finished Aug 12 04:59:30 PM PDT 24
Peak memory 6841660 kb
Host smart-c8b13f2a-ad94-40ec-bb8f-83d3b2b6ec4c
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=300_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VER
BOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4241722357 -assert nopostproc +UVM_TESTNAME=i2c_ba
se_test +UVM_TEST_SEQ=i2c_target_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /de
v/null -cm_name 0.i2c_target_stress_all.4241722357
Directory /workspace/0.i2c_target_stress_all/latest

Test location /workspace/coverage/default/0.i2c_target_stress_rd.328653
Short name T423
Test name
Test status
Simulation time 634214990 ps
CPU time 28.42 seconds
Started Aug 12 04:40:41 PM PDT 24
Finished Aug 12 04:41:10 PM PDT 24
Peak memory 213720 kb
Host smart-14d914e6-db9e-4d58-b7ba-8e7d805adffc
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=100_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licq
ueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=328653 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2
c_target_stress_rd_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.i2c_tar
get_stress_rd.328653
Directory /workspace/0.i2c_target_stress_rd/latest

Test location /workspace/coverage/default/0.i2c_target_stress_wr.1769186701
Short name T486
Test name
Test status
Simulation time 54978610560 ps
CPU time 195.08 seconds
Started Aug 12 04:40:42 PM PDT 24
Finished Aug 12 04:43:57 PM PDT 24
Peak memory 2171672 kb
Host smart-0a23035d-b18f-4370-a907-33fc1099bd21
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=600_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licq
ueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1769186701 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SE
Q=i2c_target_stress_wr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.i2c
_target_stress_wr.1769186701
Directory /workspace/0.i2c_target_stress_wr/latest

Test location /workspace/coverage/default/0.i2c_target_stretch.352734219
Short name T327
Test name
Test status
Simulation time 1026986871 ps
CPU time 2.39 seconds
Started Aug 12 04:40:42 PM PDT 24
Finished Aug 12 04:40:44 PM PDT 24
Peak memory 221856 kb
Host smart-b2a26e9a-5d19-48a5-9402-6cd378201654
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=400_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licq
ueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=352734219 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ
=i2c_target_stretch_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.i2c_ta
rget_stretch.352734219
Directory /workspace/0.i2c_target_stretch/latest

Test location /workspace/coverage/default/0.i2c_target_timeout.3152371421
Short name T1603
Test name
Test status
Simulation time 2918242468 ps
CPU time 8.15 seconds
Started Aug 12 04:40:45 PM PDT 24
Finished Aug 12 04:40:53 PM PDT 24
Peak memory 230232 kb
Host smart-6b1378f9-af34-4d16-a51b-4584c942eec9
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=50_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3152371421 -assert nopostproc +UVM_TESTNAME=i2c_bas
e_test +UVM_TEST_SEQ=i2c_target_timeout_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/nu
ll -cm_name 0.i2c_target_timeout.3152371421
Directory /workspace/0.i2c_target_timeout/latest

Test location /workspace/coverage/default/0.i2c_target_tx_stretch_ctrl.3475189423
Short name T1298
Test name
Test status
Simulation time 76667921 ps
CPU time 1.75 seconds
Started Aug 12 04:40:42 PM PDT 24
Finished Aug 12 04:40:44 PM PDT 24
Peak memory 205472 kb
Host smart-10bc1313-1c42-479b-a6d0-662a7b79f20f
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3475189423 -assert nopostproc +UVM_TESTNAME=i2c_bas
e_test +UVM_TEST_SEQ=i2c_target_tx_stretch_ctrl_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log
/dev/null -cm_name 0.i2c_target_tx_stretch_ctrl.3475189423
Directory /workspace/0.i2c_target_tx_stretch_ctrl/latest

Test location /workspace/coverage/default/1.i2c_alert_test.3336089772
Short name T863
Test name
Test status
Simulation time 42497466 ps
CPU time 0.63 seconds
Started Aug 12 04:40:50 PM PDT 24
Finished Aug 12 04:40:51 PM PDT 24
Peak memory 204440 kb
Host smart-c46cfb7b-8b61-4f56-a3be-5445df85fcc5
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3336089772 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_common_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.i2c_alert_test.3336089772
Directory /workspace/1.i2c_alert_test/latest

Test location /workspace/coverage/default/1.i2c_host_error_intr.723339669
Short name T515
Test name
Test status
Simulation time 295519834 ps
CPU time 4.76 seconds
Started Aug 12 04:40:53 PM PDT 24
Finished Aug 12 04:40:58 PM PDT 24
Peak memory 236448 kb
Host smart-4d2e909b-ffd5-4b5e-8222-7563472a59aa
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=723339669 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_error_intr_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.i2c_host_error_intr.723339669
Directory /workspace/1.i2c_host_error_intr/latest

Test location /workspace/coverage/default/1.i2c_host_fifo_fmt_empty.4226161628
Short name T360
Test name
Test status
Simulation time 490531746 ps
CPU time 6.03 seconds
Started Aug 12 04:40:53 PM PDT 24
Finished Aug 12 04:40:59 PM PDT 24
Peak memory 273384 kb
Host smart-58acd175-b13f-48d1-91f6-dfa2f116a0e2
User root
Command /workspace/default/simv +test_timeout_ns=10_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4226161628 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_fifo_fmt_em
pty_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.i2c_host_fifo_fmt_empt
y.4226161628
Directory /workspace/1.i2c_host_fifo_fmt_empty/latest

Test location /workspace/coverage/default/1.i2c_host_fifo_full.3968053440
Short name T442
Test name
Test status
Simulation time 5735718846 ps
CPU time 119.41 seconds
Started Aug 12 04:40:49 PM PDT 24
Finished Aug 12 04:42:48 PM PDT 24
Peak memory 736256 kb
Host smart-5174fde4-165d-49cb-a901-920ba157fb23
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3968053440 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_fifo_full_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.i2c_host_fifo_full.3968053440
Directory /workspace/1.i2c_host_fifo_full/latest

Test location /workspace/coverage/default/1.i2c_host_fifo_overflow.1396640165
Short name T1389
Test name
Test status
Simulation time 1668640744 ps
CPU time 121.52 seconds
Started Aug 12 04:40:48 PM PDT 24
Finished Aug 12 04:42:50 PM PDT 24
Peak memory 612396 kb
Host smart-7bb4cd28-0ec0-4824-9c2b-fbc7d97c0d7d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1396640165 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_fifo_overflow_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.i2c_host_fifo_overflow.1396640165
Directory /workspace/1.i2c_host_fifo_overflow/latest

Test location /workspace/coverage/default/1.i2c_host_fifo_reset_rx.1287763435
Short name T1345
Test name
Test status
Simulation time 861333530 ps
CPU time 10.89 seconds
Started Aug 12 04:40:49 PM PDT 24
Finished Aug 12 04:41:00 PM PDT 24
Peak memory 205252 kb
Host smart-3723e62a-9ef2-47b8-bb5a-e9378e8ddce8
User root
Command /workspace/default/simv +test_timeout_ns=10_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1287763435 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_fifo_reset_
rx_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.i2c_host_fifo_reset_rx.
1287763435
Directory /workspace/1.i2c_host_fifo_reset_rx/latest

Test location /workspace/coverage/default/1.i2c_host_override.1485786081
Short name T472
Test name
Test status
Simulation time 79362242 ps
CPU time 0.67 seconds
Started Aug 12 04:40:50 PM PDT 24
Finished Aug 12 04:40:50 PM PDT 24
Peak memory 204936 kb
Host smart-2058f0df-dd15-48df-847b-326d7ac61939
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1485786081 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_override_vseq +en_cov=1 -cm line+cond+f
sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.i2c_host_override.1485786081
Directory /workspace/1.i2c_host_override/latest

Test location /workspace/coverage/default/1.i2c_host_perf.1960263500
Short name T1572
Test name
Test status
Simulation time 6787315770 ps
CPU time 74.68 seconds
Started Aug 12 04:40:48 PM PDT 24
Finished Aug 12 04:42:03 PM PDT 24
Peak memory 213516 kb
Host smart-495cfd83-b8a4-4ad8-941b-39cb1b4d9bcb
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1960263500 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_perf_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.i2c_host_perf.1960263500
Directory /workspace/1.i2c_host_perf/latest

Test location /workspace/coverage/default/1.i2c_host_perf_precise.3500682049
Short name T144
Test name
Test status
Simulation time 1533356239 ps
CPU time 1.63 seconds
Started Aug 12 04:40:49 PM PDT 24
Finished Aug 12 04:40:51 PM PDT 24
Peak memory 205176 kb
Host smart-30586afd-632e-4ae7-a22f-6f097cd9b9fd
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3500682049 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_perf_precise_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.i2c_host_perf_precise.3500682049
Directory /workspace/1.i2c_host_perf_precise/latest

Test location /workspace/coverage/default/1.i2c_host_smoke.792868872
Short name T1630
Test name
Test status
Simulation time 2039695034 ps
CPU time 102.31 seconds
Started Aug 12 04:40:47 PM PDT 24
Finished Aug 12 04:42:29 PM PDT 24
Peak memory 414672 kb
Host smart-6009d89e-9cbc-4a76-8508-54158620b6b4
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=792868872 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_smoke_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.i2c_host_smoke.792868872
Directory /workspace/1.i2c_host_smoke/latest

Test location /workspace/coverage/default/1.i2c_host_stretch_timeout.3993033298
Short name T1214
Test name
Test status
Simulation time 20360067214 ps
CPU time 18.57 seconds
Started Aug 12 04:40:49 PM PDT 24
Finished Aug 12 04:41:07 PM PDT 24
Peak memory 221236 kb
Host smart-795a4893-9a2b-492f-9c44-99396d85e259
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3993033298 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_stretch_timeout_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.i2c_host_stretch_timeout.3993033298
Directory /workspace/1.i2c_host_stretch_timeout/latest

Test location /workspace/coverage/default/1.i2c_target_bad_addr.3442716543
Short name T1665
Test name
Test status
Simulation time 904879409 ps
CPU time 4.33 seconds
Started Aug 12 04:40:50 PM PDT 24
Finished Aug 12 04:40:55 PM PDT 24
Peak memory 213668 kb
Host smart-e4528d7d-80b0-4839-862b-c0717969ad18
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +i2c_bad_addr_pct=50 +cdc_instrumentation_enabled=1 +UVM_
NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3442716543 -assert nopostproc
+UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_target_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.
vdb -cm_log /dev/null -cm_name 1.i2c_target_bad_addr.3442716543
Directory /workspace/1.i2c_target_bad_addr/latest

Test location /workspace/coverage/default/1.i2c_target_fifo_reset_acq.3592981417
Short name T1708
Test name
Test status
Simulation time 347150870 ps
CPU time 0.81 seconds
Started Aug 12 04:40:44 PM PDT 24
Finished Aug 12 04:40:45 PM PDT 24
Peak memory 205288 kb
Host smart-ca5262cd-e341-4cf0-92e7-835b35f82766
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3592981417 -assert nopostproc +UVM_TESTNAME=i2c_bas
e_test +UVM_TEST_SEQ=i2c_target_fifo_reset_acq_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log
/dev/null -cm_name 1.i2c_target_fifo_reset_acq.3592981417
Directory /workspace/1.i2c_target_fifo_reset_acq/latest

Test location /workspace/coverage/default/1.i2c_target_fifo_reset_tx.1586264353
Short name T448
Test name
Test status
Simulation time 115888086 ps
CPU time 0.88 seconds
Started Aug 12 04:40:48 PM PDT 24
Finished Aug 12 04:40:49 PM PDT 24
Peak memory 205224 kb
Host smart-abe0aa1a-0fd0-466b-80a1-374a5a0da77b
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1586264353 -assert nopostproc +UVM_TESTNAME=i2c_bas
e_test +UVM_TEST_SEQ=i2c_target_fifo_reset_tx_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /
dev/null -cm_name 1.i2c_target_fifo_reset_tx.1586264353
Directory /workspace/1.i2c_target_fifo_reset_tx/latest

Test location /workspace/coverage/default/1.i2c_target_fifo_watermarks_acq.2573137747
Short name T1239
Test name
Test status
Simulation time 1393036089 ps
CPU time 2.24 seconds
Started Aug 12 04:40:47 PM PDT 24
Finished Aug 12 04:40:49 PM PDT 24
Peak memory 205544 kb
Host smart-31e102c4-5a3b-4d24-9392-7f80186d30d2
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2573137747 -assert nopostproc +UVM_TESTNAME=i2c_bas
e_test +UVM_TEST_SEQ=i2c_target_fifo_watermarks_acq_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm
_log /dev/null -cm_name 1.i2c_target_fifo_watermarks_acq.2573137747
Directory /workspace/1.i2c_target_fifo_watermarks_acq/latest

Test location /workspace/coverage/default/1.i2c_target_fifo_watermarks_tx.83403380
Short name T1016
Test name
Test status
Simulation time 152794763 ps
CPU time 1.25 seconds
Started Aug 12 04:40:51 PM PDT 24
Finished Aug 12 04:40:52 PM PDT 24
Peak memory 205172 kb
Host smart-92512ceb-bcdd-4196-9ffb-97f4e0d82a35
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=83403380 -assert nopostproc +UVM_TESTNAME=i2c_base_
test +UVM_TEST_SEQ=i2c_target_fifo_watermarks_tx_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_lo
g /dev/null -cm_name 1.i2c_target_fifo_watermarks_tx.83403380
Directory /workspace/1.i2c_target_fifo_watermarks_tx/latest

Test location /workspace/coverage/default/1.i2c_target_glitch.385120034
Short name T52
Test name
Test status
Simulation time 11547060364 ps
CPU time 10.71 seconds
Started Aug 12 04:40:47 PM PDT 24
Finished Aug 12 04:40:58 PM PDT 24
Peak memory 213980 kb
Host smart-3c74f58e-799a-4cd9-a372-c92c2b66b5e4
User root
Command /workspace/default/simv +i2c_agent_mode=Host +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /wor
kspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=385120034 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_glitch_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.i2c_target_glitch.385120034
Directory /workspace/1.i2c_target_glitch/latest

Test location /workspace/coverage/default/1.i2c_target_intr_smoke.3089065471
Short name T837
Test name
Test status
Simulation time 810264178 ps
CPU time 5.02 seconds
Started Aug 12 04:40:50 PM PDT 24
Finished Aug 12 04:40:56 PM PDT 24
Peak memory 217860 kb
Host smart-8bdf51da-35b6-4527-b3f8-ad3d2292df4d
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=200_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VER
BOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3089065471 -assert nopostproc +UVM_TESTNAME=i2c_ba
se_test +UVM_TEST_SEQ=i2c_target_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/nul
l -cm_name 1.i2c_target_intr_smoke.3089065471
Directory /workspace/1.i2c_target_intr_smoke/latest

Test location /workspace/coverage/default/1.i2c_target_intr_stress_wr.2865963722
Short name T174
Test name
Test status
Simulation time 12782989381 ps
CPU time 3.74 seconds
Started Aug 12 04:40:47 PM PDT 24
Finished Aug 12 04:40:50 PM PDT 24
Peak memory 205476 kb
Host smart-e92090b5-b964-46fa-a917-a5ed00ef8af2
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=600_000_000 +use_intr_handler=1 +slow_acq=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNO
TES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2865963722 -assert nopostproc +UVM_TES
TNAME=i2c_base_test +UVM_TEST_SEQ=i2c_target_stress_wr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb
-cm_log /dev/null -cm_name 1.i2c_target_intr_stress_wr.2865963722
Directory /workspace/1.i2c_target_intr_stress_wr/latest

Test location /workspace/coverage/default/1.i2c_target_nack_acqfull.877167679
Short name T1191
Test name
Test status
Simulation time 523215363 ps
CPU time 2.95 seconds
Started Aug 12 04:40:47 PM PDT 24
Finished Aug 12 04:40:50 PM PDT 24
Peak memory 213736 kb
Host smart-8ab01b6e-b698-4a2c-9829-f8a0d7fa8a26
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=877167679 -assert nopostproc +UVM_TESTNAME=i2c_base
_test +UVM_TEST_SEQ=i2c_target_nack_acqfull_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /de
v/null -cm_name 1.i2c_target_nack_acqfull.877167679
Directory /workspace/1.i2c_target_nack_acqfull/latest

Test location /workspace/coverage/default/1.i2c_target_nack_acqfull_addr.4281575083
Short name T1124
Test name
Test status
Simulation time 479797841 ps
CPU time 2.45 seconds
Started Aug 12 04:40:48 PM PDT 24
Finished Aug 12 04:40:51 PM PDT 24
Peak memory 205468 kb
Host smart-58602268-4486-4908-a684-550ed3e02051
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4281575083 -assert nopostproc +UVM_TESTNAME=i2c_bas
e_test +UVM_TEST_SEQ=i2c_target_nack_acqfull_addr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_l
og /dev/null -cm_name 1.i2c_target_nack_acqfull_addr.4281575083
Directory /workspace/1.i2c_target_nack_acqfull_addr/latest

Test location /workspace/coverage/default/1.i2c_target_nack_txstretch.1800529048
Short name T636
Test name
Test status
Simulation time 889001432 ps
CPU time 1.58 seconds
Started Aug 12 04:40:48 PM PDT 24
Finished Aug 12 04:40:49 PM PDT 24
Peak memory 222280 kb
Host smart-892b2dd7-50c3-4460-ab78-b1ae080c2cf4
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1800529048 -assert nopostproc +UVM_TESTNAME=i2c_bas
e_test +UVM_TEST_SEQ=i2c_target_nack_txstretch_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log
/dev/null -cm_name 1.i2c_target_nack_txstretch.1800529048
Directory /workspace/1.i2c_target_nack_txstretch/latest

Test location /workspace/coverage/default/1.i2c_target_perf.2002282480
Short name T637
Test name
Test status
Simulation time 3952147104 ps
CPU time 6.2 seconds
Started Aug 12 04:40:50 PM PDT 24
Finished Aug 12 04:40:57 PM PDT 24
Peak memory 220672 kb
Host smart-60f4a5a0-69f3-4e08-b668-da897caebd39
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2002282480 -assert nopostproc +UVM_TESTNAME=i2c_bas
e_test +UVM_TEST_SEQ=i2c_target_perf_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null
-cm_name 1.i2c_target_perf.2002282480
Directory /workspace/1.i2c_target_perf/latest

Test location /workspace/coverage/default/1.i2c_target_smbus_maxlen.3780614547
Short name T1390
Test name
Test status
Simulation time 3657543131 ps
CPU time 2.48 seconds
Started Aug 12 04:40:47 PM PDT 24
Finished Aug 12 04:40:49 PM PDT 24
Peak memory 205288 kb
Host smart-a76d49d8-f59c-4c76-9c6a-23c6ba209ea6
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3780614547 -assert nopostproc +UVM_TESTNAME=i2c_bas
e_test +UVM_TEST_SEQ=i2c_target_smbus_maxlen_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /d
ev/null -cm_name 1.i2c_target_smbus_maxlen.3780614547
Directory /workspace/1.i2c_target_smbus_maxlen/latest

Test location /workspace/coverage/default/1.i2c_target_smoke.3345462091
Short name T1155
Test name
Test status
Simulation time 851439103 ps
CPU time 27.88 seconds
Started Aug 12 04:40:48 PM PDT 24
Finished Aug 12 04:41:16 PM PDT 24
Peak memory 213672 kb
Host smart-4571fb7f-825a-4a46-a187-c87e4e5e3f67
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=100_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licq
ueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3345462091 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SE
Q=i2c_target_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.i2c_tar
get_smoke.3345462091
Directory /workspace/1.i2c_target_smoke/latest

Test location /workspace/coverage/default/1.i2c_target_stress_all.179306236
Short name T1052
Test name
Test status
Simulation time 103419890663 ps
CPU time 59.29 seconds
Started Aug 12 04:40:49 PM PDT 24
Finished Aug 12 04:41:48 PM PDT 24
Peak memory 237328 kb
Host smart-62c46344-ff73-4ee6-ba7f-db8770b1568e
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=300_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VER
BOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=179306236 -assert nopostproc +UVM_TESTNAME=i2c_bas
e_test +UVM_TEST_SEQ=i2c_target_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev
/null -cm_name 1.i2c_target_stress_all.179306236
Directory /workspace/1.i2c_target_stress_all/latest

Test location /workspace/coverage/default/1.i2c_target_stress_rd.3232604892
Short name T765
Test name
Test status
Simulation time 1301607343 ps
CPU time 57.69 seconds
Started Aug 12 04:40:48 PM PDT 24
Finished Aug 12 04:41:46 PM PDT 24
Peak memory 217424 kb
Host smart-c616af0d-db7f-42ea-86d6-100fabe7af07
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=100_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licq
ueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3232604892 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SE
Q=i2c_target_stress_rd_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.i2c
_target_stress_rd.3232604892
Directory /workspace/1.i2c_target_stress_rd/latest

Test location /workspace/coverage/default/1.i2c_target_stress_wr.488847397
Short name T1471
Test name
Test status
Simulation time 33515905780 ps
CPU time 50.45 seconds
Started Aug 12 04:40:46 PM PDT 24
Finished Aug 12 04:41:37 PM PDT 24
Peak memory 911572 kb
Host smart-55f9457a-907d-4394-b56a-36fe71bea993
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=600_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licq
ueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=488847397 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ
=i2c_target_stress_wr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.i2c_
target_stress_wr.488847397
Directory /workspace/1.i2c_target_stress_wr/latest

Test location /workspace/coverage/default/1.i2c_target_stretch.3502364652
Short name T412
Test name
Test status
Simulation time 3801046938 ps
CPU time 17.53 seconds
Started Aug 12 04:40:49 PM PDT 24
Finished Aug 12 04:41:06 PM PDT 24
Peak memory 713096 kb
Host smart-4db74bd8-2686-4f9b-9ce3-281d22e2a602
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=400_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licq
ueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3502364652 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SE
Q=i2c_target_stretch_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.i2c_t
arget_stretch.3502364652
Directory /workspace/1.i2c_target_stretch/latest

Test location /workspace/coverage/default/1.i2c_target_timeout.779700406
Short name T1273
Test name
Test status
Simulation time 1292014335 ps
CPU time 6.85 seconds
Started Aug 12 04:40:47 PM PDT 24
Finished Aug 12 04:40:54 PM PDT 24
Peak memory 221824 kb
Host smart-f11fc2c4-c8b2-4e2f-bf40-64e88d97604b
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=50_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=779700406 -assert nopostproc +UVM_TESTNAME=i2c_base
_test +UVM_TEST_SEQ=i2c_target_timeout_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/nul
l -cm_name 1.i2c_target_timeout.779700406
Directory /workspace/1.i2c_target_timeout/latest

Test location /workspace/coverage/default/1.i2c_target_tx_stretch_ctrl.2963526147
Short name T133
Test name
Test status
Simulation time 99767474 ps
CPU time 2.05 seconds
Started Aug 12 04:40:53 PM PDT 24
Finished Aug 12 04:40:55 PM PDT 24
Peak memory 205448 kb
Host smart-3982a010-254e-4d16-9cbf-6bc8b8f41c95
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2963526147 -assert nopostproc +UVM_TESTNAME=i2c_bas
e_test +UVM_TEST_SEQ=i2c_target_tx_stretch_ctrl_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log
/dev/null -cm_name 1.i2c_target_tx_stretch_ctrl.2963526147
Directory /workspace/1.i2c_target_tx_stretch_ctrl/latest

Test location /workspace/coverage/default/10.i2c_host_error_intr.755512203
Short name T1511
Test name
Test status
Simulation time 285605229 ps
CPU time 1.4 seconds
Started Aug 12 04:41:53 PM PDT 24
Finished Aug 12 04:41:55 PM PDT 24
Peak memory 213528 kb
Host smart-98e7f88b-9459-4fc4-a2fd-e5075d9d4b4a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=755512203 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_error_intr_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.i2c_host_error_intr.755512203
Directory /workspace/10.i2c_host_error_intr/latest

Test location /workspace/coverage/default/10.i2c_host_fifo_fmt_empty.1641213831
Short name T969
Test name
Test status
Simulation time 675508140 ps
CPU time 6.23 seconds
Started Aug 12 04:41:48 PM PDT 24
Finished Aug 12 04:41:54 PM PDT 24
Peak memory 262108 kb
Host smart-d985433a-e55a-4ad0-8b6d-791ff5348f14
User root
Command /workspace/default/simv +test_timeout_ns=10_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1641213831 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_fifo_fmt_em
pty_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.i2c_host_fifo_fmt_emp
ty.1641213831
Directory /workspace/10.i2c_host_fifo_fmt_empty/latest

Test location /workspace/coverage/default/10.i2c_host_fifo_full.3364208984
Short name T1680
Test name
Test status
Simulation time 17219134156 ps
CPU time 169.75 seconds
Started Aug 12 04:41:55 PM PDT 24
Finished Aug 12 04:44:45 PM PDT 24
Peak memory 691656 kb
Host smart-4b81bae7-82ca-4d34-af29-68c7d6b03bce
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3364208984 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_fifo_full_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.i2c_host_fifo_full.3364208984
Directory /workspace/10.i2c_host_fifo_full/latest

Test location /workspace/coverage/default/10.i2c_host_fifo_overflow.1680918786
Short name T1270
Test name
Test status
Simulation time 2611458097 ps
CPU time 185.65 seconds
Started Aug 12 04:41:50 PM PDT 24
Finished Aug 12 04:44:56 PM PDT 24
Peak memory 792760 kb
Host smart-25a1940b-7bc0-411a-abf3-5e08a1d15f60
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1680918786 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_fifo_overflow_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.i2c_host_fifo_overflow.1680918786
Directory /workspace/10.i2c_host_fifo_overflow/latest

Test location /workspace/coverage/default/10.i2c_host_fifo_reset_fmt.3675537308
Short name T1051
Test name
Test status
Simulation time 208226811 ps
CPU time 1.03 seconds
Started Aug 12 04:41:45 PM PDT 24
Finished Aug 12 04:41:46 PM PDT 24
Peak memory 204960 kb
Host smart-bae40ed9-dc68-4fe5-bff6-f28734dab96e
User root
Command /workspace/default/simv +test_timeout_ns=10_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3675537308 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_fifo_reset_
fmt_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.i2c_host_fifo_reset_f
mt.3675537308
Directory /workspace/10.i2c_host_fifo_reset_fmt/latest

Test location /workspace/coverage/default/10.i2c_host_fifo_reset_rx.224385808
Short name T445
Test name
Test status
Simulation time 193757556 ps
CPU time 5.69 seconds
Started Aug 12 04:41:46 PM PDT 24
Finished Aug 12 04:41:52 PM PDT 24
Peak memory 240172 kb
Host smart-4ad8a922-f314-4f54-934c-5786b61f6992
User root
Command /workspace/default/simv +test_timeout_ns=10_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=224385808 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_fifo_reset_r
x_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.i2c_host_fifo_reset_rx.
224385808
Directory /workspace/10.i2c_host_fifo_reset_rx/latest

Test location /workspace/coverage/default/10.i2c_host_fifo_watermark.1496103542
Short name T183
Test name
Test status
Simulation time 11852667848 ps
CPU time 175.44 seconds
Started Aug 12 04:41:48 PM PDT 24
Finished Aug 12 04:44:44 PM PDT 24
Peak memory 878652 kb
Host smart-0fa73416-aa3d-43a0-a6d4-d287e52b1b7d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1496103542 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_fifo_watermark_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.i2c_host_fifo_watermark.1496103542
Directory /workspace/10.i2c_host_fifo_watermark/latest

Test location /workspace/coverage/default/10.i2c_host_may_nack.2893966324
Short name T903
Test name
Test status
Simulation time 1331753724 ps
CPU time 6.7 seconds
Started Aug 12 04:41:54 PM PDT 24
Finished Aug 12 04:42:01 PM PDT 24
Peak memory 205208 kb
Host smart-7937f46d-c87a-4ec1-9055-356371ef8c91
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2893966324 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_may_nack_vseq +en_cov=1 -cm line+cond+f
sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.i2c_host_may_nack.2893966324
Directory /workspace/10.i2c_host_may_nack/latest

Test location /workspace/coverage/default/10.i2c_host_override.321940901
Short name T157
Test name
Test status
Simulation time 20360927 ps
CPU time 0.66 seconds
Started Aug 12 04:41:45 PM PDT 24
Finished Aug 12 04:41:46 PM PDT 24
Peak memory 204916 kb
Host smart-7b08f0c7-195d-4e0e-95da-a949b6ca7215
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=321940901 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_override_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.i2c_host_override.321940901
Directory /workspace/10.i2c_host_override/latest

Test location /workspace/coverage/default/10.i2c_host_perf.542321666
Short name T1342
Test name
Test status
Simulation time 8086241467 ps
CPU time 58.39 seconds
Started Aug 12 04:41:54 PM PDT 24
Finished Aug 12 04:42:52 PM PDT 24
Peak memory 525712 kb
Host smart-bedc326c-a974-4819-add0-8ba718254df5
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=542321666 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_perf_vseq +en_cov=1 -cm line+cond+fsm+tg
l+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.i2c_host_perf.542321666
Directory /workspace/10.i2c_host_perf/latest

Test location /workspace/coverage/default/10.i2c_host_perf_precise.1333727041
Short name T1470
Test name
Test status
Simulation time 308800784 ps
CPU time 1.66 seconds
Started Aug 12 04:41:57 PM PDT 24
Finished Aug 12 04:41:58 PM PDT 24
Peak memory 213424 kb
Host smart-a9f9a41a-e19d-4e96-b7d4-968bcee02079
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1333727041 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_perf_precise_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.i2c_host_perf_precise.1333727041
Directory /workspace/10.i2c_host_perf_precise/latest

Test location /workspace/coverage/default/10.i2c_host_smoke.2233067199
Short name T858
Test name
Test status
Simulation time 6965318134 ps
CPU time 78.68 seconds
Started Aug 12 04:41:47 PM PDT 24
Finished Aug 12 04:43:06 PM PDT 24
Peak memory 296396 kb
Host smart-e17226c7-7e1a-4bbe-b840-e8d7639f0af1
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2233067199 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_smoke_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.i2c_host_smoke.2233067199
Directory /workspace/10.i2c_host_smoke/latest

Test location /workspace/coverage/default/10.i2c_host_stretch_timeout.3340762753
Short name T31
Test name
Test status
Simulation time 1511937347 ps
CPU time 35.07 seconds
Started Aug 12 04:41:52 PM PDT 24
Finished Aug 12 04:42:27 PM PDT 24
Peak memory 213448 kb
Host smart-2e2c1f03-e6f8-4957-a1e0-afcafee6a501
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3340762753 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_stretch_timeout_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.i2c_host_stretch_timeout.3340762753
Directory /workspace/10.i2c_host_stretch_timeout/latest

Test location /workspace/coverage/default/10.i2c_target_bad_addr.330583565
Short name T413
Test name
Test status
Simulation time 1426929021 ps
CPU time 5.76 seconds
Started Aug 12 04:41:55 PM PDT 24
Finished Aug 12 04:42:01 PM PDT 24
Peak memory 221288 kb
Host smart-945f0aad-1571-4821-b3a0-71a1fab134f0
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +i2c_bad_addr_pct=50 +cdc_instrumentation_enabled=1 +UVM_
NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=330583565 -assert nopostproc +
UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_target_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.v
db -cm_log /dev/null -cm_name 10.i2c_target_bad_addr.330583565
Directory /workspace/10.i2c_target_bad_addr/latest

Test location /workspace/coverage/default/10.i2c_target_fifo_reset_acq.2790078544
Short name T1700
Test name
Test status
Simulation time 134609086 ps
CPU time 0.99 seconds
Started Aug 12 04:41:55 PM PDT 24
Finished Aug 12 04:41:56 PM PDT 24
Peak memory 205112 kb
Host smart-c004bd1c-1311-4887-ac50-cbe8c3ff42c3
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2790078544 -assert nopostproc +UVM_TESTNAME=i2c_bas
e_test +UVM_TEST_SEQ=i2c_target_fifo_reset_acq_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log
/dev/null -cm_name 10.i2c_target_fifo_reset_acq.2790078544
Directory /workspace/10.i2c_target_fifo_reset_acq/latest

Test location /workspace/coverage/default/10.i2c_target_fifo_reset_tx.2341226981
Short name T771
Test name
Test status
Simulation time 225173157 ps
CPU time 1.44 seconds
Started Aug 12 04:41:53 PM PDT 24
Finished Aug 12 04:41:54 PM PDT 24
Peak memory 205260 kb
Host smart-b346f7ca-7012-4664-b17d-bb0978833221
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2341226981 -assert nopostproc +UVM_TESTNAME=i2c_bas
e_test +UVM_TEST_SEQ=i2c_target_fifo_reset_tx_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /
dev/null -cm_name 10.i2c_target_fifo_reset_tx.2341226981
Directory /workspace/10.i2c_target_fifo_reset_tx/latest

Test location /workspace/coverage/default/10.i2c_target_fifo_watermarks_acq.3396276149
Short name T1260
Test name
Test status
Simulation time 836740779 ps
CPU time 2.8 seconds
Started Aug 12 04:41:55 PM PDT 24
Finished Aug 12 04:41:58 PM PDT 24
Peak memory 205496 kb
Host smart-38aff73a-799b-42a2-aee6-165391ccad45
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3396276149 -assert nopostproc +UVM_TESTNAME=i2c_bas
e_test +UVM_TEST_SEQ=i2c_target_fifo_watermarks_acq_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm
_log /dev/null -cm_name 10.i2c_target_fifo_watermarks_acq.3396276149
Directory /workspace/10.i2c_target_fifo_watermarks_acq/latest

Test location /workspace/coverage/default/10.i2c_target_fifo_watermarks_tx.856929792
Short name T757
Test name
Test status
Simulation time 490241032 ps
CPU time 1.19 seconds
Started Aug 12 04:41:55 PM PDT 24
Finished Aug 12 04:41:56 PM PDT 24
Peak memory 205232 kb
Host smart-6eccf818-c6da-4ee5-a802-562c46c3ca84
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=856929792 -assert nopostproc +UVM_TESTNAME=i2c_base
_test +UVM_TEST_SEQ=i2c_target_fifo_watermarks_tx_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_l
og /dev/null -cm_name 10.i2c_target_fifo_watermarks_tx.856929792
Directory /workspace/10.i2c_target_fifo_watermarks_tx/latest

Test location /workspace/coverage/default/10.i2c_target_intr_smoke.1465842037
Short name T425
Test name
Test status
Simulation time 5303383895 ps
CPU time 9.71 seconds
Started Aug 12 04:41:57 PM PDT 24
Finished Aug 12 04:42:06 PM PDT 24
Peak memory 214620 kb
Host smart-b1d8551f-3eae-4a9c-ad0d-512460f29468
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=200_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VER
BOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1465842037 -assert nopostproc +UVM_TESTNAME=i2c_ba
se_test +UVM_TEST_SEQ=i2c_target_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/nul
l -cm_name 10.i2c_target_intr_smoke.1465842037
Directory /workspace/10.i2c_target_intr_smoke/latest

Test location /workspace/coverage/default/10.i2c_target_intr_stress_wr.1622625346
Short name T1437
Test name
Test status
Simulation time 18381080021 ps
CPU time 108.16 seconds
Started Aug 12 04:41:55 PM PDT 24
Finished Aug 12 04:43:44 PM PDT 24
Peak memory 1517780 kb
Host smart-29b54d39-6b5c-409e-9c9a-2232627880b8
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=600_000_000 +use_intr_handler=1 +slow_acq=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNO
TES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1622625346 -assert nopostproc +UVM_TES
TNAME=i2c_base_test +UVM_TEST_SEQ=i2c_target_stress_wr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb
-cm_log /dev/null -cm_name 10.i2c_target_intr_stress_wr.1622625346
Directory /workspace/10.i2c_target_intr_stress_wr/latest

Test location /workspace/coverage/default/10.i2c_target_nack_acqfull.419904910
Short name T1406
Test name
Test status
Simulation time 540093508 ps
CPU time 2.82 seconds
Started Aug 12 04:41:56 PM PDT 24
Finished Aug 12 04:41:59 PM PDT 24
Peak memory 213684 kb
Host smart-dd9161e4-d9d3-437e-8dda-8758823e1285
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=419904910 -assert nopostproc +UVM_TESTNAME=i2c_base
_test +UVM_TEST_SEQ=i2c_target_nack_acqfull_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /de
v/null -cm_name 10.i2c_target_nack_acqfull.419904910
Directory /workspace/10.i2c_target_nack_acqfull/latest

Test location /workspace/coverage/default/10.i2c_target_nack_acqfull_addr.2671212574
Short name T993
Test name
Test status
Simulation time 544187159 ps
CPU time 2.3 seconds
Started Aug 12 04:41:52 PM PDT 24
Finished Aug 12 04:41:54 PM PDT 24
Peak memory 205404 kb
Host smart-64fc0d4a-89f8-4303-826a-9a44a77f2a0c
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2671212574 -assert nopostproc +UVM_TESTNAME=i2c_bas
e_test +UVM_TEST_SEQ=i2c_target_nack_acqfull_addr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_l
og /dev/null -cm_name 10.i2c_target_nack_acqfull_addr.2671212574
Directory /workspace/10.i2c_target_nack_acqfull_addr/latest

Test location /workspace/coverage/default/10.i2c_target_perf.2975134486
Short name T1173
Test name
Test status
Simulation time 779046337 ps
CPU time 5.83 seconds
Started Aug 12 04:41:55 PM PDT 24
Finished Aug 12 04:42:01 PM PDT 24
Peak memory 213772 kb
Host smart-8480998d-3bcd-4a68-a85a-c0725e9ef9c4
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2975134486 -assert nopostproc +UVM_TESTNAME=i2c_bas
e_test +UVM_TEST_SEQ=i2c_target_perf_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null
-cm_name 10.i2c_target_perf.2975134486
Directory /workspace/10.i2c_target_perf/latest

Test location /workspace/coverage/default/10.i2c_target_smbus_maxlen.3409691017
Short name T1056
Test name
Test status
Simulation time 2231500113 ps
CPU time 2.56 seconds
Started Aug 12 04:41:55 PM PDT 24
Finished Aug 12 04:41:58 PM PDT 24
Peak memory 205320 kb
Host smart-a37d7cb5-7704-49f2-8d2c-433e4145b65c
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3409691017 -assert nopostproc +UVM_TESTNAME=i2c_bas
e_test +UVM_TEST_SEQ=i2c_target_smbus_maxlen_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /d
ev/null -cm_name 10.i2c_target_smbus_maxlen.3409691017
Directory /workspace/10.i2c_target_smbus_maxlen/latest

Test location /workspace/coverage/default/10.i2c_target_smoke.2828160529
Short name T1111
Test name
Test status
Simulation time 984799243 ps
CPU time 15.21 seconds
Started Aug 12 04:41:52 PM PDT 24
Finished Aug 12 04:42:07 PM PDT 24
Peak memory 207708 kb
Host smart-b82abe77-53f9-4cbf-8738-2f2c1ed61984
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=100_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licq
ueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2828160529 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SE
Q=i2c_target_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.i2c_ta
rget_smoke.2828160529
Directory /workspace/10.i2c_target_smoke/latest

Test location /workspace/coverage/default/10.i2c_target_stress_all.1632448504
Short name T967
Test name
Test status
Simulation time 40504692870 ps
CPU time 117.15 seconds
Started Aug 12 04:41:52 PM PDT 24
Finished Aug 12 04:43:49 PM PDT 24
Peak memory 1224984 kb
Host smart-d77ce92d-1cfd-46f6-94d4-46336beb967f
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=300_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VER
BOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1632448504 -assert nopostproc +UVM_TESTNAME=i2c_ba
se_test +UVM_TEST_SEQ=i2c_target_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /de
v/null -cm_name 10.i2c_target_stress_all.1632448504
Directory /workspace/10.i2c_target_stress_all/latest

Test location /workspace/coverage/default/10.i2c_target_stress_rd.490385474
Short name T1232
Test name
Test status
Simulation time 811433209 ps
CPU time 9.66 seconds
Started Aug 12 04:41:52 PM PDT 24
Finished Aug 12 04:42:02 PM PDT 24
Peak memory 219264 kb
Host smart-79a07149-6123-4e5c-afe6-cf7b334cd0d9
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=100_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licq
ueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=490385474 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ
=i2c_target_stress_rd_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.i2c
_target_stress_rd.490385474
Directory /workspace/10.i2c_target_stress_rd/latest

Test location /workspace/coverage/default/10.i2c_target_stress_wr.3659345440
Short name T1558
Test name
Test status
Simulation time 71088039848 ps
CPU time 383.99 seconds
Started Aug 12 04:41:54 PM PDT 24
Finished Aug 12 04:48:18 PM PDT 24
Peak memory 3149536 kb
Host smart-a74481d9-c785-42c0-9050-2c0838640fd5
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=600_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licq
ueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3659345440 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SE
Q=i2c_target_stress_wr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.i2
c_target_stress_wr.3659345440
Directory /workspace/10.i2c_target_stress_wr/latest

Test location /workspace/coverage/default/10.i2c_target_stretch.3668741813
Short name T1541
Test name
Test status
Simulation time 2574583235 ps
CPU time 5.34 seconds
Started Aug 12 04:41:53 PM PDT 24
Finished Aug 12 04:41:59 PM PDT 24
Peak memory 268960 kb
Host smart-74021260-fa8f-4f8c-bd43-9960c333ed64
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=400_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licq
ueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3668741813 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SE
Q=i2c_target_stretch_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.i2c_
target_stretch.3668741813
Directory /workspace/10.i2c_target_stretch/latest

Test location /workspace/coverage/default/10.i2c_target_timeout.4225980539
Short name T672
Test name
Test status
Simulation time 1217709382 ps
CPU time 6.78 seconds
Started Aug 12 04:41:55 PM PDT 24
Finished Aug 12 04:42:02 PM PDT 24
Peak memory 218796 kb
Host smart-bcf42b7f-4b88-4d00-8828-514a5c692a9f
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=50_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4225980539 -assert nopostproc +UVM_TESTNAME=i2c_bas
e_test +UVM_TEST_SEQ=i2c_target_timeout_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/nu
ll -cm_name 10.i2c_target_timeout.4225980539
Directory /workspace/10.i2c_target_timeout/latest

Test location /workspace/coverage/default/10.i2c_target_tx_stretch_ctrl.2765573352
Short name T744
Test name
Test status
Simulation time 52091093 ps
CPU time 1.08 seconds
Started Aug 12 04:41:54 PM PDT 24
Finished Aug 12 04:41:55 PM PDT 24
Peak memory 205452 kb
Host smart-d3c672eb-3d41-4aa3-97a5-5502fb5dfc8d
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2765573352 -assert nopostproc +UVM_TESTNAME=i2c_bas
e_test +UVM_TEST_SEQ=i2c_target_tx_stretch_ctrl_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log
/dev/null -cm_name 10.i2c_target_tx_stretch_ctrl.2765573352
Directory /workspace/10.i2c_target_tx_stretch_ctrl/latest

Test location /workspace/coverage/default/11.i2c_alert_test.2164569081
Short name T1
Test name
Test status
Simulation time 16123263 ps
CPU time 0.67 seconds
Started Aug 12 04:42:01 PM PDT 24
Finished Aug 12 04:42:02 PM PDT 24
Peak memory 204552 kb
Host smart-e61e4ed1-7bb8-4fe2-9a42-a2388870d438
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2164569081 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_common_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.i2c_alert_test.2164569081
Directory /workspace/11.i2c_alert_test/latest

Test location /workspace/coverage/default/11.i2c_host_error_intr.4063577278
Short name T1475
Test name
Test status
Simulation time 350621905 ps
CPU time 1.28 seconds
Started Aug 12 04:41:58 PM PDT 24
Finished Aug 12 04:41:59 PM PDT 24
Peak memory 221596 kb
Host smart-09a3ae22-5686-4738-a99e-6baac0bc7759
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4063577278 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_error_intr_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.i2c_host_error_intr.4063577278
Directory /workspace/11.i2c_host_error_intr/latest

Test location /workspace/coverage/default/11.i2c_host_fifo_fmt_empty.2699029557
Short name T690
Test name
Test status
Simulation time 753954920 ps
CPU time 8.25 seconds
Started Aug 12 04:41:59 PM PDT 24
Finished Aug 12 04:42:07 PM PDT 24
Peak memory 267556 kb
Host smart-5ef5e7f0-2090-40f8-86f1-e2e0acdf822c
User root
Command /workspace/default/simv +test_timeout_ns=10_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2699029557 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_fifo_fmt_em
pty_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.i2c_host_fifo_fmt_emp
ty.2699029557
Directory /workspace/11.i2c_host_fifo_fmt_empty/latest

Test location /workspace/coverage/default/11.i2c_host_fifo_full.582869890
Short name T1193
Test name
Test status
Simulation time 2894470679 ps
CPU time 98.81 seconds
Started Aug 12 04:41:58 PM PDT 24
Finished Aug 12 04:43:37 PM PDT 24
Peak memory 634888 kb
Host smart-1985628e-8da7-4a13-8025-8349ddf281d6
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=582869890 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_fifo_full_vseq +en_cov=1 -cm line+cond+f
sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.i2c_host_fifo_full.582869890
Directory /workspace/11.i2c_host_fifo_full/latest

Test location /workspace/coverage/default/11.i2c_host_fifo_overflow.2846188175
Short name T477
Test name
Test status
Simulation time 3562589414 ps
CPU time 49.84 seconds
Started Aug 12 04:42:00 PM PDT 24
Finished Aug 12 04:42:50 PM PDT 24
Peak memory 599144 kb
Host smart-722673ca-2168-4665-b31c-37dfccd6ddc3
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2846188175 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_fifo_overflow_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.i2c_host_fifo_overflow.2846188175
Directory /workspace/11.i2c_host_fifo_overflow/latest

Test location /workspace/coverage/default/11.i2c_host_fifo_reset_fmt.2146174566
Short name T626
Test name
Test status
Simulation time 1984488949 ps
CPU time 1.39 seconds
Started Aug 12 04:41:55 PM PDT 24
Finished Aug 12 04:41:57 PM PDT 24
Peak memory 205168 kb
Host smart-7c6ef724-af0f-4ae5-b7cf-468766d2b47e
User root
Command /workspace/default/simv +test_timeout_ns=10_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2146174566 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_fifo_reset_
fmt_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.i2c_host_fifo_reset_f
mt.2146174566
Directory /workspace/11.i2c_host_fifo_reset_fmt/latest

Test location /workspace/coverage/default/11.i2c_host_fifo_reset_rx.684037458
Short name T816
Test name
Test status
Simulation time 878915171 ps
CPU time 6.11 seconds
Started Aug 12 04:41:59 PM PDT 24
Finished Aug 12 04:42:05 PM PDT 24
Peak memory 245748 kb
Host smart-335745b9-3606-4b2b-a105-4de9c4de0162
User root
Command /workspace/default/simv +test_timeout_ns=10_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=684037458 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_fifo_reset_r
x_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.i2c_host_fifo_reset_rx.
684037458
Directory /workspace/11.i2c_host_fifo_reset_rx/latest

Test location /workspace/coverage/default/11.i2c_host_fifo_watermark.1026200645
Short name T1181
Test name
Test status
Simulation time 5020399382 ps
CPU time 158.38 seconds
Started Aug 12 04:41:55 PM PDT 24
Finished Aug 12 04:44:33 PM PDT 24
Peak memory 1462628 kb
Host smart-63b1d1c0-c544-43a5-8ee0-eebc5a5c1d67
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1026200645 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_fifo_watermark_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.i2c_host_fifo_watermark.1026200645
Directory /workspace/11.i2c_host_fifo_watermark/latest

Test location /workspace/coverage/default/11.i2c_host_override.1734757652
Short name T696
Test name
Test status
Simulation time 81263927 ps
CPU time 0.66 seconds
Started Aug 12 04:41:55 PM PDT 24
Finished Aug 12 04:41:56 PM PDT 24
Peak memory 204940 kb
Host smart-9181fef4-7a35-4082-9c9b-a27da3e632f4
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1734757652 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_override_vseq +en_cov=1 -cm line+cond+f
sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.i2c_host_override.1734757652
Directory /workspace/11.i2c_host_override/latest

Test location /workspace/coverage/default/11.i2c_host_perf.825007980
Short name T1151
Test name
Test status
Simulation time 7535162643 ps
CPU time 46.93 seconds
Started Aug 12 04:41:57 PM PDT 24
Finished Aug 12 04:42:44 PM PDT 24
Peak memory 340176 kb
Host smart-1e6b05b2-93aa-427e-90cc-c5a32da5cb49
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=825007980 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_perf_vseq +en_cov=1 -cm line+cond+fsm+tg
l+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.i2c_host_perf.825007980
Directory /workspace/11.i2c_host_perf/latest

Test location /workspace/coverage/default/11.i2c_host_smoke.301025865
Short name T409
Test name
Test status
Simulation time 12732150477 ps
CPU time 74.58 seconds
Started Aug 12 04:41:54 PM PDT 24
Finished Aug 12 04:43:09 PM PDT 24
Peak memory 347596 kb
Host smart-bdccd78d-d48b-4f41-9e1f-d718d1902de2
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=301025865 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_smoke_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.i2c_host_smoke.301025865
Directory /workspace/11.i2c_host_smoke/latest

Test location /workspace/coverage/default/11.i2c_host_stretch_timeout.265990585
Short name T704
Test name
Test status
Simulation time 855968877 ps
CPU time 39.07 seconds
Started Aug 12 04:41:56 PM PDT 24
Finished Aug 12 04:42:35 PM PDT 24
Peak memory 213504 kb
Host smart-652ec716-80e0-4a3e-b5d0-6bf2fa7fd6ab
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=265990585 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_stretch_timeout_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.i2c_host_stretch_timeout.265990585
Directory /workspace/11.i2c_host_stretch_timeout/latest

Test location /workspace/coverage/default/11.i2c_target_bad_addr.1457736009
Short name T1308
Test name
Test status
Simulation time 4231392281 ps
CPU time 5.77 seconds
Started Aug 12 04:42:04 PM PDT 24
Finished Aug 12 04:42:10 PM PDT 24
Peak memory 213672 kb
Host smart-2231f819-44d7-47c6-852f-1ef0ef5efb25
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +i2c_bad_addr_pct=50 +cdc_instrumentation_enabled=1 +UVM_
NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1457736009 -assert nopostproc
+UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_target_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.
vdb -cm_log /dev/null -cm_name 11.i2c_target_bad_addr.1457736009
Directory /workspace/11.i2c_target_bad_addr/latest

Test location /workspace/coverage/default/11.i2c_target_fifo_reset_acq.1714231223
Short name T644
Test name
Test status
Simulation time 529328873 ps
CPU time 1.29 seconds
Started Aug 12 04:42:01 PM PDT 24
Finished Aug 12 04:42:03 PM PDT 24
Peak memory 205468 kb
Host smart-f2405123-534d-443a-98df-b4e585f91520
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1714231223 -assert nopostproc +UVM_TESTNAME=i2c_bas
e_test +UVM_TEST_SEQ=i2c_target_fifo_reset_acq_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log
/dev/null -cm_name 11.i2c_target_fifo_reset_acq.1714231223
Directory /workspace/11.i2c_target_fifo_reset_acq/latest

Test location /workspace/coverage/default/11.i2c_target_fifo_watermarks_tx.3853045566
Short name T700
Test name
Test status
Simulation time 775238491 ps
CPU time 1.16 seconds
Started Aug 12 04:42:02 PM PDT 24
Finished Aug 12 04:42:04 PM PDT 24
Peak memory 205236 kb
Host smart-47f1c437-5b9c-463c-9bfb-17e66bb39250
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3853045566 -assert nopostproc +UVM_TESTNAME=i2c_bas
e_test +UVM_TEST_SEQ=i2c_target_fifo_watermarks_tx_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_
log /dev/null -cm_name 11.i2c_target_fifo_watermarks_tx.3853045566
Directory /workspace/11.i2c_target_fifo_watermarks_tx/latest

Test location /workspace/coverage/default/11.i2c_target_hrst.2879327939
Short name T772
Test name
Test status
Simulation time 418596457 ps
CPU time 2.97 seconds
Started Aug 12 04:42:02 PM PDT 24
Finished Aug 12 04:42:05 PM PDT 24
Peak memory 213756 kb
Host smart-7b81d23b-a1e6-4e87-ab3d-e4334bb6860d
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2879327939 -assert nopostproc +UVM_TESTNAME=i2c_bas
e_test +UVM_TEST_SEQ=i2c_target_hrst_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null
-cm_name 11.i2c_target_hrst.2879327939
Directory /workspace/11.i2c_target_hrst/latest

Test location /workspace/coverage/default/11.i2c_target_intr_smoke.3469263332
Short name T1497
Test name
Test status
Simulation time 4548712757 ps
CPU time 6.52 seconds
Started Aug 12 04:42:09 PM PDT 24
Finished Aug 12 04:42:16 PM PDT 24
Peak memory 221876 kb
Host smart-9b19f48e-3910-4481-b010-c02656fd9eed
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=200_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VER
BOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3469263332 -assert nopostproc +UVM_TESTNAME=i2c_ba
se_test +UVM_TEST_SEQ=i2c_target_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/nul
l -cm_name 11.i2c_target_intr_smoke.3469263332
Directory /workspace/11.i2c_target_intr_smoke/latest

Test location /workspace/coverage/default/11.i2c_target_intr_stress_wr.3539070343
Short name T920
Test name
Test status
Simulation time 18037836351 ps
CPU time 34.26 seconds
Started Aug 12 04:42:01 PM PDT 24
Finished Aug 12 04:42:35 PM PDT 24
Peak memory 672108 kb
Host smart-a06c8a44-14f6-4bba-8aca-cd2bc8a97a04
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=600_000_000 +use_intr_handler=1 +slow_acq=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNO
TES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3539070343 -assert nopostproc +UVM_TES
TNAME=i2c_base_test +UVM_TEST_SEQ=i2c_target_stress_wr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb
-cm_log /dev/null -cm_name 11.i2c_target_intr_stress_wr.3539070343
Directory /workspace/11.i2c_target_intr_stress_wr/latest

Test location /workspace/coverage/default/11.i2c_target_nack_acqfull.392741335
Short name T1483
Test name
Test status
Simulation time 1273779476 ps
CPU time 2.8 seconds
Started Aug 12 04:42:03 PM PDT 24
Finished Aug 12 04:42:07 PM PDT 24
Peak memory 213536 kb
Host smart-e3df6547-aa82-4a27-b9d8-8e44f7e5df6d
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=392741335 -assert nopostproc +UVM_TESTNAME=i2c_base
_test +UVM_TEST_SEQ=i2c_target_nack_acqfull_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /de
v/null -cm_name 11.i2c_target_nack_acqfull.392741335
Directory /workspace/11.i2c_target_nack_acqfull/latest

Test location /workspace/coverage/default/11.i2c_target_nack_acqfull_addr.352869237
Short name T1457
Test name
Test status
Simulation time 1675570199 ps
CPU time 2.34 seconds
Started Aug 12 04:42:01 PM PDT 24
Finished Aug 12 04:42:04 PM PDT 24
Peak memory 205456 kb
Host smart-be1715b9-a506-4836-ac91-be4f61a32c4d
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=352869237 -assert nopostproc +UVM_TESTNAME=i2c_base
_test +UVM_TEST_SEQ=i2c_target_nack_acqfull_addr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_lo
g /dev/null -cm_name 11.i2c_target_nack_acqfull_addr.352869237
Directory /workspace/11.i2c_target_nack_acqfull_addr/latest

Test location /workspace/coverage/default/11.i2c_target_nack_txstretch.1025496575
Short name T1125
Test name
Test status
Simulation time 567110802 ps
CPU time 1.45 seconds
Started Aug 12 04:42:01 PM PDT 24
Finished Aug 12 04:42:02 PM PDT 24
Peak memory 222100 kb
Host smart-7836d913-733e-418d-9611-f8f3cadef608
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1025496575 -assert nopostproc +UVM_TESTNAME=i2c_bas
e_test +UVM_TEST_SEQ=i2c_target_nack_txstretch_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log
/dev/null -cm_name 11.i2c_target_nack_txstretch.1025496575
Directory /workspace/11.i2c_target_nack_txstretch/latest

Test location /workspace/coverage/default/11.i2c_target_smbus_maxlen.2215705732
Short name T1387
Test name
Test status
Simulation time 529902522 ps
CPU time 2.52 seconds
Started Aug 12 04:42:02 PM PDT 24
Finished Aug 12 04:42:05 PM PDT 24
Peak memory 205216 kb
Host smart-24109bb7-5c02-41d9-9b32-03f96be81869
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2215705732 -assert nopostproc +UVM_TESTNAME=i2c_bas
e_test +UVM_TEST_SEQ=i2c_target_smbus_maxlen_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /d
ev/null -cm_name 11.i2c_target_smbus_maxlen.2215705732
Directory /workspace/11.i2c_target_smbus_maxlen/latest

Test location /workspace/coverage/default/11.i2c_target_smoke.4002188023
Short name T1392
Test name
Test status
Simulation time 10148221791 ps
CPU time 14.76 seconds
Started Aug 12 04:42:00 PM PDT 24
Finished Aug 12 04:42:15 PM PDT 24
Peak memory 222040 kb
Host smart-95f8d3cc-81fe-457c-8e80-2d870b5c8fa0
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=100_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licq
ueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4002188023 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SE
Q=i2c_target_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.i2c_ta
rget_smoke.4002188023
Directory /workspace/11.i2c_target_smoke/latest

Test location /workspace/coverage/default/11.i2c_target_stress_all.3517611232
Short name T1340
Test name
Test status
Simulation time 86491524045 ps
CPU time 39.29 seconds
Started Aug 12 04:42:06 PM PDT 24
Finished Aug 12 04:42:45 PM PDT 24
Peak memory 295796 kb
Host smart-217e9053-6024-4931-9eb5-8a95fbb68678
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=300_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VER
BOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3517611232 -assert nopostproc +UVM_TESTNAME=i2c_ba
se_test +UVM_TEST_SEQ=i2c_target_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /de
v/null -cm_name 11.i2c_target_stress_all.3517611232
Directory /workspace/11.i2c_target_stress_all/latest

Test location /workspace/coverage/default/11.i2c_target_stress_rd.1150870275
Short name T1255
Test name
Test status
Simulation time 4691418246 ps
CPU time 22.04 seconds
Started Aug 12 04:42:02 PM PDT 24
Finished Aug 12 04:42:24 PM PDT 24
Peak memory 213740 kb
Host smart-26ac525c-8e62-43d4-b325-f353ec915f0a
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=100_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licq
ueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1150870275 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SE
Q=i2c_target_stress_rd_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.i2
c_target_stress_rd.1150870275
Directory /workspace/11.i2c_target_stress_rd/latest

Test location /workspace/coverage/default/11.i2c_target_stress_wr.375804471
Short name T658
Test name
Test status
Simulation time 28948035046 ps
CPU time 37.44 seconds
Started Aug 12 04:42:01 PM PDT 24
Finished Aug 12 04:42:38 PM PDT 24
Peak memory 715556 kb
Host smart-b8d23293-0608-4d48-a558-aa1784cc2311
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=600_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licq
ueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=375804471 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ
=i2c_target_stress_wr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.i2c
_target_stress_wr.375804471
Directory /workspace/11.i2c_target_stress_wr/latest

Test location /workspace/coverage/default/11.i2c_target_stretch.1195468768
Short name T289
Test name
Test status
Simulation time 4554922562 ps
CPU time 14.09 seconds
Started Aug 12 04:42:10 PM PDT 24
Finished Aug 12 04:42:24 PM PDT 24
Peak memory 382260 kb
Host smart-869f8d47-3628-426f-b36c-f0bc8277c58f
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=400_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licq
ueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1195468768 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SE
Q=i2c_target_stretch_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.i2c_
target_stretch.1195468768
Directory /workspace/11.i2c_target_stretch/latest

Test location /workspace/coverage/default/11.i2c_target_timeout.4084919369
Short name T751
Test name
Test status
Simulation time 4640415767 ps
CPU time 6.41 seconds
Started Aug 12 04:42:09 PM PDT 24
Finished Aug 12 04:42:16 PM PDT 24
Peak memory 231484 kb
Host smart-dc1b9c78-6090-4d26-817e-87ef89cbb77d
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=50_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4084919369 -assert nopostproc +UVM_TESTNAME=i2c_bas
e_test +UVM_TEST_SEQ=i2c_target_timeout_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/nu
ll -cm_name 11.i2c_target_timeout.4084919369
Directory /workspace/11.i2c_target_timeout/latest

Test location /workspace/coverage/default/11.i2c_target_tx_stretch_ctrl.598063200
Short name T1195
Test name
Test status
Simulation time 452666854 ps
CPU time 6.21 seconds
Started Aug 12 04:42:00 PM PDT 24
Finished Aug 12 04:42:06 PM PDT 24
Peak memory 205536 kb
Host smart-1cc35843-7b09-4a3a-8064-b8e50e63d050
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=598063200 -assert nopostproc +UVM_TESTNAME=i2c_base
_test +UVM_TEST_SEQ=i2c_target_tx_stretch_ctrl_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log
/dev/null -cm_name 11.i2c_target_tx_stretch_ctrl.598063200
Directory /workspace/11.i2c_target_tx_stretch_ctrl/latest

Test location /workspace/coverage/default/12.i2c_alert_test.3530920720
Short name T866
Test name
Test status
Simulation time 43183940 ps
CPU time 0.65 seconds
Started Aug 12 04:42:10 PM PDT 24
Finished Aug 12 04:42:11 PM PDT 24
Peak memory 204452 kb
Host smart-4666dfd2-e581-4577-92e6-c83f055298eb
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3530920720 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_common_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.i2c_alert_test.3530920720
Directory /workspace/12.i2c_alert_test/latest

Test location /workspace/coverage/default/12.i2c_host_error_intr.265104261
Short name T901
Test name
Test status
Simulation time 144902000 ps
CPU time 5.8 seconds
Started Aug 12 04:42:02 PM PDT 24
Finished Aug 12 04:42:08 PM PDT 24
Peak memory 221432 kb
Host smart-923ac72f-59b8-4efe-87d3-0f9c5bda616f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=265104261 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_error_intr_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.i2c_host_error_intr.265104261
Directory /workspace/12.i2c_host_error_intr/latest

Test location /workspace/coverage/default/12.i2c_host_fifo_fmt_empty.1633059750
Short name T844
Test name
Test status
Simulation time 390533925 ps
CPU time 8.45 seconds
Started Aug 12 04:42:02 PM PDT 24
Finished Aug 12 04:42:11 PM PDT 24
Peak memory 277092 kb
Host smart-f72cdcd9-e91d-4e9f-8ce8-53960ddc081d
User root
Command /workspace/default/simv +test_timeout_ns=10_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1633059750 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_fifo_fmt_em
pty_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.i2c_host_fifo_fmt_emp
ty.1633059750
Directory /workspace/12.i2c_host_fifo_fmt_empty/latest

Test location /workspace/coverage/default/12.i2c_host_fifo_full.3200525485
Short name T627
Test name
Test status
Simulation time 3414755578 ps
CPU time 147.3 seconds
Started Aug 12 04:42:08 PM PDT 24
Finished Aug 12 04:44:35 PM PDT 24
Peak memory 674880 kb
Host smart-11468f01-dd7b-4bb7-9581-114f4279acb8
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3200525485 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_fifo_full_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.i2c_host_fifo_full.3200525485
Directory /workspace/12.i2c_host_fifo_full/latest

Test location /workspace/coverage/default/12.i2c_host_fifo_overflow.3113897205
Short name T1087
Test name
Test status
Simulation time 1569388613 ps
CPU time 109.31 seconds
Started Aug 12 04:42:06 PM PDT 24
Finished Aug 12 04:43:56 PM PDT 24
Peak memory 592132 kb
Host smart-be071d10-17d1-47b5-abbd-ccacd3920e46
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3113897205 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_fifo_overflow_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.i2c_host_fifo_overflow.3113897205
Directory /workspace/12.i2c_host_fifo_overflow/latest

Test location /workspace/coverage/default/12.i2c_host_fifo_reset_fmt.910804341
Short name T255
Test name
Test status
Simulation time 180203751 ps
CPU time 1.13 seconds
Started Aug 12 04:42:02 PM PDT 24
Finished Aug 12 04:42:03 PM PDT 24
Peak memory 204944 kb
Host smart-252f3037-cb87-42f7-a1ec-0c3b83d18ebc
User root
Command /workspace/default/simv +test_timeout_ns=10_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=910804341 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_fifo_reset_f
mt_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.i2c_host_fifo_reset_fm
t.910804341
Directory /workspace/12.i2c_host_fifo_reset_fmt/latest

Test location /workspace/coverage/default/12.i2c_host_fifo_reset_rx.3900275152
Short name T769
Test name
Test status
Simulation time 203471620 ps
CPU time 5.33 seconds
Started Aug 12 04:42:02 PM PDT 24
Finished Aug 12 04:42:08 PM PDT 24
Peak memory 243692 kb
Host smart-a4d49409-c589-45e7-baa6-2eaa560bf580
User root
Command /workspace/default/simv +test_timeout_ns=10_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3900275152 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_fifo_reset_
rx_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.i2c_host_fifo_reset_rx
.3900275152
Directory /workspace/12.i2c_host_fifo_reset_rx/latest

Test location /workspace/coverage/default/12.i2c_host_fifo_watermark.733720353
Short name T125
Test name
Test status
Simulation time 21541926137 ps
CPU time 144.11 seconds
Started Aug 12 04:42:00 PM PDT 24
Finished Aug 12 04:44:24 PM PDT 24
Peak memory 1579948 kb
Host smart-429fcc09-93a6-4b3f-b4f1-4282686e3c61
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=733720353 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_fifo_watermark_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.i2c_host_fifo_watermark.733720353
Directory /workspace/12.i2c_host_fifo_watermark/latest

Test location /workspace/coverage/default/12.i2c_host_may_nack.3446880750
Short name T1068
Test name
Test status
Simulation time 389799045 ps
CPU time 15.34 seconds
Started Aug 12 04:42:16 PM PDT 24
Finished Aug 12 04:42:31 PM PDT 24
Peak memory 205168 kb
Host smart-6c1ede80-c6ca-4362-aab9-b976402105fc
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3446880750 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_may_nack_vseq +en_cov=1 -cm line+cond+f
sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.i2c_host_may_nack.3446880750
Directory /workspace/12.i2c_host_may_nack/latest

Test location /workspace/coverage/default/12.i2c_host_override.2620660026
Short name T618
Test name
Test status
Simulation time 187948183 ps
CPU time 0.66 seconds
Started Aug 12 04:42:04 PM PDT 24
Finished Aug 12 04:42:05 PM PDT 24
Peak memory 204892 kb
Host smart-622d282e-cac2-47ce-bf78-aa399c3732db
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2620660026 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_override_vseq +en_cov=1 -cm line+cond+f
sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.i2c_host_override.2620660026
Directory /workspace/12.i2c_host_override/latest

Test location /workspace/coverage/default/12.i2c_host_perf_precise.1434981629
Short name T1110
Test name
Test status
Simulation time 943888978 ps
CPU time 10.31 seconds
Started Aug 12 04:42:01 PM PDT 24
Finished Aug 12 04:42:11 PM PDT 24
Peak memory 205232 kb
Host smart-f28508be-1123-450e-af1f-f28517221308
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1434981629 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_perf_precise_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.i2c_host_perf_precise.1434981629
Directory /workspace/12.i2c_host_perf_precise/latest

Test location /workspace/coverage/default/12.i2c_host_smoke.3685900895
Short name T95
Test name
Test status
Simulation time 8569840197 ps
CPU time 41.48 seconds
Started Aug 12 04:42:00 PM PDT 24
Finished Aug 12 04:42:42 PM PDT 24
Peak memory 373888 kb
Host smart-2bfc2b87-c7d3-4dd7-a616-59525cd33543
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3685900895 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_smoke_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.i2c_host_smoke.3685900895
Directory /workspace/12.i2c_host_smoke/latest

Test location /workspace/coverage/default/12.i2c_host_stretch_timeout.3499073089
Short name T1518
Test name
Test status
Simulation time 518548611 ps
CPU time 7.98 seconds
Started Aug 12 04:42:00 PM PDT 24
Finished Aug 12 04:42:08 PM PDT 24
Peak memory 221288 kb
Host smart-8de6d919-633a-4779-b1ae-32ea36b3b1b3
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3499073089 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_stretch_timeout_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.i2c_host_stretch_timeout.3499073089
Directory /workspace/12.i2c_host_stretch_timeout/latest

Test location /workspace/coverage/default/12.i2c_target_bad_addr.3987671569
Short name T694
Test name
Test status
Simulation time 4250039850 ps
CPU time 5.85 seconds
Started Aug 12 04:42:09 PM PDT 24
Finished Aug 12 04:42:15 PM PDT 24
Peak memory 220160 kb
Host smart-48ff29b4-9dea-4977-8fdf-4b0c68cd1460
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +i2c_bad_addr_pct=50 +cdc_instrumentation_enabled=1 +UVM_
NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3987671569 -assert nopostproc
+UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_target_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.
vdb -cm_log /dev/null -cm_name 12.i2c_target_bad_addr.3987671569
Directory /workspace/12.i2c_target_bad_addr/latest

Test location /workspace/coverage/default/12.i2c_target_fifo_reset_acq.3625470672
Short name T1114
Test name
Test status
Simulation time 209769307 ps
CPU time 1.22 seconds
Started Aug 12 04:42:10 PM PDT 24
Finished Aug 12 04:42:12 PM PDT 24
Peak memory 213472 kb
Host smart-2ea6d59e-a368-4a5c-b4ba-6e584ab20ec5
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3625470672 -assert nopostproc +UVM_TESTNAME=i2c_bas
e_test +UVM_TEST_SEQ=i2c_target_fifo_reset_acq_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log
/dev/null -cm_name 12.i2c_target_fifo_reset_acq.3625470672
Directory /workspace/12.i2c_target_fifo_reset_acq/latest

Test location /workspace/coverage/default/12.i2c_target_fifo_reset_tx.4209208182
Short name T1054
Test name
Test status
Simulation time 559508803 ps
CPU time 1.18 seconds
Started Aug 12 04:42:08 PM PDT 24
Finished Aug 12 04:42:09 PM PDT 24
Peak memory 205536 kb
Host smart-bf229bdf-eacf-4e7a-8630-05db3fe121e1
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4209208182 -assert nopostproc +UVM_TESTNAME=i2c_bas
e_test +UVM_TEST_SEQ=i2c_target_fifo_reset_tx_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /
dev/null -cm_name 12.i2c_target_fifo_reset_tx.4209208182
Directory /workspace/12.i2c_target_fifo_reset_tx/latest

Test location /workspace/coverage/default/12.i2c_target_fifo_watermarks_acq.2851340745
Short name T293
Test name
Test status
Simulation time 1581280865 ps
CPU time 2.42 seconds
Started Aug 12 04:42:10 PM PDT 24
Finished Aug 12 04:42:13 PM PDT 24
Peak memory 205452 kb
Host smart-c5776f72-3bb4-4b5c-b226-9dc06f8746a6
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2851340745 -assert nopostproc +UVM_TESTNAME=i2c_bas
e_test +UVM_TEST_SEQ=i2c_target_fifo_watermarks_acq_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm
_log /dev/null -cm_name 12.i2c_target_fifo_watermarks_acq.2851340745
Directory /workspace/12.i2c_target_fifo_watermarks_acq/latest

Test location /workspace/coverage/default/12.i2c_target_fifo_watermarks_tx.3619696701
Short name T768
Test name
Test status
Simulation time 839127450 ps
CPU time 1.57 seconds
Started Aug 12 04:42:09 PM PDT 24
Finished Aug 12 04:42:11 PM PDT 24
Peak memory 205224 kb
Host smart-109ed8ad-0059-41ad-8051-b0aa3d59bd89
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3619696701 -assert nopostproc +UVM_TESTNAME=i2c_bas
e_test +UVM_TEST_SEQ=i2c_target_fifo_watermarks_tx_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_
log /dev/null -cm_name 12.i2c_target_fifo_watermarks_tx.3619696701
Directory /workspace/12.i2c_target_fifo_watermarks_tx/latest

Test location /workspace/coverage/default/12.i2c_target_intr_smoke.1058638886
Short name T489
Test name
Test status
Simulation time 1124435898 ps
CPU time 6.24 seconds
Started Aug 12 04:42:08 PM PDT 24
Finished Aug 12 04:42:14 PM PDT 24
Peak memory 221880 kb
Host smart-8340e6a6-e142-4a50-9a64-2360971b2989
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=200_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VER
BOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1058638886 -assert nopostproc +UVM_TESTNAME=i2c_ba
se_test +UVM_TEST_SEQ=i2c_target_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/nul
l -cm_name 12.i2c_target_intr_smoke.1058638886
Directory /workspace/12.i2c_target_intr_smoke/latest

Test location /workspace/coverage/default/12.i2c_target_intr_stress_wr.1752735998
Short name T342
Test name
Test status
Simulation time 18945277548 ps
CPU time 76.4 seconds
Started Aug 12 04:42:13 PM PDT 24
Finished Aug 12 04:43:29 PM PDT 24
Peak memory 1394852 kb
Host smart-6e5c4bc9-108f-45a2-ad67-2aadb75323fc
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=600_000_000 +use_intr_handler=1 +slow_acq=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNO
TES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1752735998 -assert nopostproc +UVM_TES
TNAME=i2c_base_test +UVM_TEST_SEQ=i2c_target_stress_wr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb
-cm_log /dev/null -cm_name 12.i2c_target_intr_stress_wr.1752735998
Directory /workspace/12.i2c_target_intr_stress_wr/latest

Test location /workspace/coverage/default/12.i2c_target_nack_acqfull.2921831309
Short name T997
Test name
Test status
Simulation time 3165557693 ps
CPU time 2.87 seconds
Started Aug 12 04:42:12 PM PDT 24
Finished Aug 12 04:42:15 PM PDT 24
Peak memory 213692 kb
Host smart-b5f5ce4c-19b3-4ada-9430-6e36bd27468c
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2921831309 -assert nopostproc +UVM_TESTNAME=i2c_bas
e_test +UVM_TEST_SEQ=i2c_target_nack_acqfull_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /d
ev/null -cm_name 12.i2c_target_nack_acqfull.2921831309
Directory /workspace/12.i2c_target_nack_acqfull/latest

Test location /workspace/coverage/default/12.i2c_target_nack_acqfull_addr.803201815
Short name T62
Test name
Test status
Simulation time 554216891 ps
CPU time 2.95 seconds
Started Aug 12 04:42:10 PM PDT 24
Finished Aug 12 04:42:13 PM PDT 24
Peak memory 205636 kb
Host smart-b70baebf-dc02-4123-bbd0-74d6003c1780
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=803201815 -assert nopostproc +UVM_TESTNAME=i2c_base
_test +UVM_TEST_SEQ=i2c_target_nack_acqfull_addr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_lo
g /dev/null -cm_name 12.i2c_target_nack_acqfull_addr.803201815
Directory /workspace/12.i2c_target_nack_acqfull_addr/latest

Test location /workspace/coverage/default/12.i2c_target_nack_txstretch.1584881054
Short name T1186
Test name
Test status
Simulation time 507239286 ps
CPU time 1.39 seconds
Started Aug 12 04:42:08 PM PDT 24
Finished Aug 12 04:42:10 PM PDT 24
Peak memory 222104 kb
Host smart-c2431d64-013e-40f9-92aa-05db8d7b2b7c
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1584881054 -assert nopostproc +UVM_TESTNAME=i2c_bas
e_test +UVM_TEST_SEQ=i2c_target_nack_txstretch_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log
/dev/null -cm_name 12.i2c_target_nack_txstretch.1584881054
Directory /workspace/12.i2c_target_nack_txstretch/latest

Test location /workspace/coverage/default/12.i2c_target_perf.1703716333
Short name T1228
Test name
Test status
Simulation time 896450956 ps
CPU time 3.47 seconds
Started Aug 12 04:42:09 PM PDT 24
Finished Aug 12 04:42:13 PM PDT 24
Peak memory 221836 kb
Host smart-65be9a5d-9d63-4d7b-acf9-fea58bd7a5d1
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1703716333 -assert nopostproc +UVM_TESTNAME=i2c_bas
e_test +UVM_TEST_SEQ=i2c_target_perf_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null
-cm_name 12.i2c_target_perf.1703716333
Directory /workspace/12.i2c_target_perf/latest

Test location /workspace/coverage/default/12.i2c_target_smbus_maxlen.2221783392
Short name T970
Test name
Test status
Simulation time 3747548653 ps
CPU time 2.4 seconds
Started Aug 12 04:42:12 PM PDT 24
Finished Aug 12 04:42:15 PM PDT 24
Peak memory 205312 kb
Host smart-00951f21-fff5-4ce9-aa56-11b50f69f641
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2221783392 -assert nopostproc +UVM_TESTNAME=i2c_bas
e_test +UVM_TEST_SEQ=i2c_target_smbus_maxlen_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /d
ev/null -cm_name 12.i2c_target_smbus_maxlen.2221783392
Directory /workspace/12.i2c_target_smbus_maxlen/latest

Test location /workspace/coverage/default/12.i2c_target_smoke.1278655429
Short name T88
Test name
Test status
Simulation time 1049223813 ps
CPU time 33.3 seconds
Started Aug 12 04:42:11 PM PDT 24
Finished Aug 12 04:42:45 PM PDT 24
Peak memory 221860 kb
Host smart-3d8e52cf-931f-40fd-b964-90483de768f4
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=100_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licq
ueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1278655429 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SE
Q=i2c_target_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.i2c_ta
rget_smoke.1278655429
Directory /workspace/12.i2c_target_smoke/latest

Test location /workspace/coverage/default/12.i2c_target_stress_all.1068475573
Short name T1154
Test name
Test status
Simulation time 20037733686 ps
CPU time 274.35 seconds
Started Aug 12 04:42:09 PM PDT 24
Finished Aug 12 04:46:44 PM PDT 24
Peak memory 2653228 kb
Host smart-049fb5bc-0898-43f6-940e-5d9bb8f683f4
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=300_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VER
BOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1068475573 -assert nopostproc +UVM_TESTNAME=i2c_ba
se_test +UVM_TEST_SEQ=i2c_target_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /de
v/null -cm_name 12.i2c_target_stress_all.1068475573
Directory /workspace/12.i2c_target_stress_all/latest

Test location /workspace/coverage/default/12.i2c_target_stress_rd.4086110327
Short name T1405
Test name
Test status
Simulation time 377694332 ps
CPU time 5.7 seconds
Started Aug 12 04:42:10 PM PDT 24
Finished Aug 12 04:42:16 PM PDT 24
Peak memory 205516 kb
Host smart-ae93cb22-e20b-41d8-a5d3-230cfb6a7a45
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=100_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licq
ueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4086110327 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SE
Q=i2c_target_stress_rd_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.i2
c_target_stress_rd.4086110327
Directory /workspace/12.i2c_target_stress_rd/latest

Test location /workspace/coverage/default/12.i2c_target_stress_wr.1008818738
Short name T1673
Test name
Test status
Simulation time 63932621637 ps
CPU time 312.22 seconds
Started Aug 12 04:42:11 PM PDT 24
Finished Aug 12 04:47:23 PM PDT 24
Peak memory 2744088 kb
Host smart-c112a6e6-e6ca-4f33-b2ac-95b247471e41
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=600_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licq
ueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1008818738 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SE
Q=i2c_target_stress_wr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.i2
c_target_stress_wr.1008818738
Directory /workspace/12.i2c_target_stress_wr/latest

Test location /workspace/coverage/default/12.i2c_target_stretch.2819085645
Short name T1026
Test name
Test status
Simulation time 1247870400 ps
CPU time 7.71 seconds
Started Aug 12 04:42:11 PM PDT 24
Finished Aug 12 04:42:19 PM PDT 24
Peak memory 280340 kb
Host smart-ac34fa65-56da-4924-8cd2-eee629247533
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=400_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licq
ueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2819085645 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SE
Q=i2c_target_stretch_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.i2c_
target_stretch.2819085645
Directory /workspace/12.i2c_target_stretch/latest

Test location /workspace/coverage/default/12.i2c_target_timeout.3832412161
Short name T469
Test name
Test status
Simulation time 2776724117 ps
CPU time 7.49 seconds
Started Aug 12 04:42:11 PM PDT 24
Finished Aug 12 04:42:19 PM PDT 24
Peak memory 230124 kb
Host smart-c3aab545-1713-473f-a0de-ed5a3ec67570
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=50_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3832412161 -assert nopostproc +UVM_TESTNAME=i2c_bas
e_test +UVM_TEST_SEQ=i2c_target_timeout_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/nu
ll -cm_name 12.i2c_target_timeout.3832412161
Directory /workspace/12.i2c_target_timeout/latest

Test location /workspace/coverage/default/12.i2c_target_tx_stretch_ctrl.1726104962
Short name T1404
Test name
Test status
Simulation time 167586265 ps
CPU time 2.78 seconds
Started Aug 12 04:42:11 PM PDT 24
Finished Aug 12 04:42:14 PM PDT 24
Peak memory 205372 kb
Host smart-2f5f9a00-86c3-418a-9fd4-0b345607860c
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1726104962 -assert nopostproc +UVM_TESTNAME=i2c_bas
e_test +UVM_TEST_SEQ=i2c_target_tx_stretch_ctrl_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log
/dev/null -cm_name 12.i2c_target_tx_stretch_ctrl.1726104962
Directory /workspace/12.i2c_target_tx_stretch_ctrl/latest

Test location /workspace/coverage/default/13.i2c_alert_test.3485479789
Short name T1383
Test name
Test status
Simulation time 42944115 ps
CPU time 0.63 seconds
Started Aug 12 04:42:21 PM PDT 24
Finished Aug 12 04:42:22 PM PDT 24
Peak memory 204368 kb
Host smart-149a0e52-ac53-47da-8ea1-dc36573613c9
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3485479789 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_common_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.i2c_alert_test.3485479789
Directory /workspace/13.i2c_alert_test/latest

Test location /workspace/coverage/default/13.i2c_host_error_intr.884411853
Short name T776
Test name
Test status
Simulation time 185819926 ps
CPU time 1.55 seconds
Started Aug 12 04:42:16 PM PDT 24
Finished Aug 12 04:42:18 PM PDT 24
Peak memory 213524 kb
Host smart-5cc835ca-3c66-4920-8712-538181e3f172
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=884411853 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_error_intr_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.i2c_host_error_intr.884411853
Directory /workspace/13.i2c_host_error_intr/latest

Test location /workspace/coverage/default/13.i2c_host_fifo_fmt_empty.2659460572
Short name T562
Test name
Test status
Simulation time 1232582831 ps
CPU time 5.44 seconds
Started Aug 12 04:42:11 PM PDT 24
Finished Aug 12 04:42:16 PM PDT 24
Peak memory 241060 kb
Host smart-711dab5b-89eb-480b-b7fe-41d6a3644663
User root
Command /workspace/default/simv +test_timeout_ns=10_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2659460572 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_fifo_fmt_em
pty_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.i2c_host_fifo_fmt_emp
ty.2659460572
Directory /workspace/13.i2c_host_fifo_fmt_empty/latest

Test location /workspace/coverage/default/13.i2c_host_fifo_full.423451039
Short name T695
Test name
Test status
Simulation time 13404273653 ps
CPU time 201.88 seconds
Started Aug 12 04:42:10 PM PDT 24
Finished Aug 12 04:45:32 PM PDT 24
Peak memory 531960 kb
Host smart-d9ad9651-16e1-43e6-8c68-b9697c688bc8
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=423451039 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_fifo_full_vseq +en_cov=1 -cm line+cond+f
sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.i2c_host_fifo_full.423451039
Directory /workspace/13.i2c_host_fifo_full/latest

Test location /workspace/coverage/default/13.i2c_host_fifo_overflow.3220969485
Short name T692
Test name
Test status
Simulation time 4565637529 ps
CPU time 187.24 seconds
Started Aug 12 04:42:10 PM PDT 24
Finished Aug 12 04:45:17 PM PDT 24
Peak memory 776104 kb
Host smart-c58e8544-bd8e-4b34-8ebd-47ef06ccd621
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3220969485 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_fifo_overflow_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.i2c_host_fifo_overflow.3220969485
Directory /workspace/13.i2c_host_fifo_overflow/latest

Test location /workspace/coverage/default/13.i2c_host_fifo_reset_fmt.3725876290
Short name T256
Test name
Test status
Simulation time 139135285 ps
CPU time 1.24 seconds
Started Aug 12 04:42:08 PM PDT 24
Finished Aug 12 04:42:10 PM PDT 24
Peak memory 204980 kb
Host smart-bf4c90f5-ad7c-4373-aecf-09bbbdd6664a
User root
Command /workspace/default/simv +test_timeout_ns=10_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3725876290 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_fifo_reset_
fmt_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.i2c_host_fifo_reset_f
mt.3725876290
Directory /workspace/13.i2c_host_fifo_reset_fmt/latest

Test location /workspace/coverage/default/13.i2c_host_fifo_reset_rx.988366936
Short name T860
Test name
Test status
Simulation time 723576244 ps
CPU time 9.19 seconds
Started Aug 12 04:42:11 PM PDT 24
Finished Aug 12 04:42:20 PM PDT 24
Peak memory 205184 kb
Host smart-22533b8c-b201-4827-b1e6-cf4d5cf22690
User root
Command /workspace/default/simv +test_timeout_ns=10_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=988366936 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_fifo_reset_r
x_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.i2c_host_fifo_reset_rx.
988366936
Directory /workspace/13.i2c_host_fifo_reset_rx/latest

Test location /workspace/coverage/default/13.i2c_host_fifo_watermark.226467095
Short name T1509
Test name
Test status
Simulation time 7705251291 ps
CPU time 268.31 seconds
Started Aug 12 04:42:10 PM PDT 24
Finished Aug 12 04:46:39 PM PDT 24
Peak memory 1165504 kb
Host smart-be426f44-366d-4402-a0a0-cbdd60c2f24d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=226467095 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_fifo_watermark_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.i2c_host_fifo_watermark.226467095
Directory /workspace/13.i2c_host_fifo_watermark/latest

Test location /workspace/coverage/default/13.i2c_host_may_nack.251161081
Short name T1358
Test name
Test status
Simulation time 5908016174 ps
CPU time 12.91 seconds
Started Aug 12 04:42:24 PM PDT 24
Finished Aug 12 04:42:37 PM PDT 24
Peak memory 205204 kb
Host smart-35e5ff1d-62a8-4957-b1c5-469baecdf589
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=251161081 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_may_nack_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.i2c_host_may_nack.251161081
Directory /workspace/13.i2c_host_may_nack/latest

Test location /workspace/coverage/default/13.i2c_host_mode_toggle.1487153006
Short name T1069
Test name
Test status
Simulation time 378357786 ps
CPU time 2.44 seconds
Started Aug 12 04:42:16 PM PDT 24
Finished Aug 12 04:42:19 PM PDT 24
Peak memory 205276 kb
Host smart-ba57c9ef-e08f-4546-9867-1a43f6611eb9
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1487153006 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_mode_toggle_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.i2c_host_mode_toggle.1487153006
Directory /workspace/13.i2c_host_mode_toggle/latest

Test location /workspace/coverage/default/13.i2c_host_override.352992234
Short name T354
Test name
Test status
Simulation time 29591795 ps
CPU time 0.64 seconds
Started Aug 12 04:42:09 PM PDT 24
Finished Aug 12 04:42:10 PM PDT 24
Peak memory 204932 kb
Host smart-6965fb66-0f03-417b-8965-ccd1d31b49a9
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=352992234 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_override_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.i2c_host_override.352992234
Directory /workspace/13.i2c_host_override/latest

Test location /workspace/coverage/default/13.i2c_host_perf.430362931
Short name T370
Test name
Test status
Simulation time 3181740587 ps
CPU time 17.12 seconds
Started Aug 12 04:42:12 PM PDT 24
Finished Aug 12 04:42:29 PM PDT 24
Peak memory 388260 kb
Host smart-6c1daf46-67c2-4e08-9172-074a6d219806
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=430362931 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_perf_vseq +en_cov=1 -cm line+cond+fsm+tg
l+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.i2c_host_perf.430362931
Directory /workspace/13.i2c_host_perf/latest

Test location /workspace/coverage/default/13.i2c_host_perf_precise.3422023871
Short name T1234
Test name
Test status
Simulation time 93637799 ps
CPU time 1.35 seconds
Started Aug 12 04:42:13 PM PDT 24
Finished Aug 12 04:42:15 PM PDT 24
Peak memory 213964 kb
Host smart-356ff7b6-5a00-41f9-bceb-6c144975f99e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3422023871 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_perf_precise_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.i2c_host_perf_precise.3422023871
Directory /workspace/13.i2c_host_perf_precise/latest

Test location /workspace/coverage/default/13.i2c_host_smoke.601375208
Short name T892
Test name
Test status
Simulation time 6637241840 ps
CPU time 28.55 seconds
Started Aug 12 04:42:11 PM PDT 24
Finished Aug 12 04:42:40 PM PDT 24
Peak memory 295360 kb
Host smart-95b97175-3d40-4e36-bf59-4f6780c78d58
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=601375208 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_smoke_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.i2c_host_smoke.601375208
Directory /workspace/13.i2c_host_smoke/latest

Test location /workspace/coverage/default/13.i2c_host_stress_all.2421632851
Short name T189
Test name
Test status
Simulation time 93789935014 ps
CPU time 645.14 seconds
Started Aug 12 04:42:15 PM PDT 24
Finished Aug 12 04:53:00 PM PDT 24
Peak memory 2299748 kb
Host smart-d2cc71e9-a5b8-432a-b2cf-e30f116a6771
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2421632851 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_stress_all_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.i2c_host_stress_all.2421632851
Directory /workspace/13.i2c_host_stress_all/latest

Test location /workspace/coverage/default/13.i2c_host_stretch_timeout.2709656744
Short name T1502
Test name
Test status
Simulation time 472664877 ps
CPU time 7.3 seconds
Started Aug 12 04:42:11 PM PDT 24
Finished Aug 12 04:42:18 PM PDT 24
Peak memory 213404 kb
Host smart-d50962e7-ec2f-479d-ae84-acfd2ddccb15
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2709656744 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_stretch_timeout_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.i2c_host_stretch_timeout.2709656744
Directory /workspace/13.i2c_host_stretch_timeout/latest

Test location /workspace/coverage/default/13.i2c_target_bad_addr.159009561
Short name T827
Test name
Test status
Simulation time 999553430 ps
CPU time 4.58 seconds
Started Aug 12 04:42:22 PM PDT 24
Finished Aug 12 04:42:26 PM PDT 24
Peak memory 221884 kb
Host smart-a6642aa8-bcc3-44cb-a4d6-b6b60604d38a
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +i2c_bad_addr_pct=50 +cdc_instrumentation_enabled=1 +UVM_
NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=159009561 -assert nopostproc +
UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_target_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.v
db -cm_log /dev/null -cm_name 13.i2c_target_bad_addr.159009561
Directory /workspace/13.i2c_target_bad_addr/latest

Test location /workspace/coverage/default/13.i2c_target_fifo_reset_acq.60569541
Short name T250
Test name
Test status
Simulation time 2740036114 ps
CPU time 1.23 seconds
Started Aug 12 04:42:15 PM PDT 24
Finished Aug 12 04:42:17 PM PDT 24
Peak memory 205736 kb
Host smart-29ec93f4-6466-427e-bbd9-61c0eecae59a
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=60569541 -assert nopostproc +UVM_TESTNAME=i2c_base_
test +UVM_TEST_SEQ=i2c_target_fifo_reset_acq_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /d
ev/null -cm_name 13.i2c_target_fifo_reset_acq.60569541
Directory /workspace/13.i2c_target_fifo_reset_acq/latest

Test location /workspace/coverage/default/13.i2c_target_fifo_reset_tx.1585397250
Short name T602
Test name
Test status
Simulation time 635360173 ps
CPU time 1.19 seconds
Started Aug 12 04:42:16 PM PDT 24
Finished Aug 12 04:42:18 PM PDT 24
Peak memory 205204 kb
Host smart-f6ab8454-9fa3-40fa-8b8d-20d36d08e4ce
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1585397250 -assert nopostproc +UVM_TESTNAME=i2c_bas
e_test +UVM_TEST_SEQ=i2c_target_fifo_reset_tx_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /
dev/null -cm_name 13.i2c_target_fifo_reset_tx.1585397250
Directory /workspace/13.i2c_target_fifo_reset_tx/latest

Test location /workspace/coverage/default/13.i2c_target_fifo_watermarks_acq.781990830
Short name T408
Test name
Test status
Simulation time 621946275 ps
CPU time 3.24 seconds
Started Aug 12 04:42:18 PM PDT 24
Finished Aug 12 04:42:21 PM PDT 24
Peak memory 205472 kb
Host smart-cb17b740-40c8-48e0-a633-2efb0a82534f
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=781990830 -assert nopostproc +UVM_TESTNAME=i2c_base
_test +UVM_TEST_SEQ=i2c_target_fifo_watermarks_acq_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_
log /dev/null -cm_name 13.i2c_target_fifo_watermarks_acq.781990830
Directory /workspace/13.i2c_target_fifo_watermarks_acq/latest

Test location /workspace/coverage/default/13.i2c_target_fifo_watermarks_tx.732645066
Short name T1398
Test name
Test status
Simulation time 251585732 ps
CPU time 1.17 seconds
Started Aug 12 04:42:24 PM PDT 24
Finished Aug 12 04:42:25 PM PDT 24
Peak memory 205188 kb
Host smart-8f5c22b7-6cef-4f7d-85bd-59e7b4743e3f
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=732645066 -assert nopostproc +UVM_TESTNAME=i2c_base
_test +UVM_TEST_SEQ=i2c_target_fifo_watermarks_tx_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_l
og /dev/null -cm_name 13.i2c_target_fifo_watermarks_tx.732645066
Directory /workspace/13.i2c_target_fifo_watermarks_tx/latest

Test location /workspace/coverage/default/13.i2c_target_intr_smoke.4031751123
Short name T1683
Test name
Test status
Simulation time 3853718604 ps
CPU time 5.78 seconds
Started Aug 12 04:42:16 PM PDT 24
Finished Aug 12 04:42:22 PM PDT 24
Peak memory 213824 kb
Host smart-ea409f71-7447-45cd-a4dd-d49d7e1fa3b8
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=200_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VER
BOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4031751123 -assert nopostproc +UVM_TESTNAME=i2c_ba
se_test +UVM_TEST_SEQ=i2c_target_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/nul
l -cm_name 13.i2c_target_intr_smoke.4031751123
Directory /workspace/13.i2c_target_intr_smoke/latest

Test location /workspace/coverage/default/13.i2c_target_intr_stress_wr.1177368686
Short name T582
Test name
Test status
Simulation time 1668418665 ps
CPU time 2.25 seconds
Started Aug 12 04:42:15 PM PDT 24
Finished Aug 12 04:42:18 PM PDT 24
Peak memory 205492 kb
Host smart-952ede7c-6278-41fb-9806-644f1d6eb7cb
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=600_000_000 +use_intr_handler=1 +slow_acq=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNO
TES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1177368686 -assert nopostproc +UVM_TES
TNAME=i2c_base_test +UVM_TEST_SEQ=i2c_target_stress_wr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb
-cm_log /dev/null -cm_name 13.i2c_target_intr_stress_wr.1177368686
Directory /workspace/13.i2c_target_intr_stress_wr/latest

Test location /workspace/coverage/default/13.i2c_target_nack_acqfull.1114452729
Short name T1200
Test name
Test status
Simulation time 601263508 ps
CPU time 3.22 seconds
Started Aug 12 04:42:24 PM PDT 24
Finished Aug 12 04:42:27 PM PDT 24
Peak memory 213644 kb
Host smart-7008d222-1c4d-4a46-a749-cf30a6c3c3e0
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1114452729 -assert nopostproc +UVM_TESTNAME=i2c_bas
e_test +UVM_TEST_SEQ=i2c_target_nack_acqfull_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /d
ev/null -cm_name 13.i2c_target_nack_acqfull.1114452729
Directory /workspace/13.i2c_target_nack_acqfull/latest

Test location /workspace/coverage/default/13.i2c_target_nack_txstretch.2971677605
Short name T673
Test name
Test status
Simulation time 566142282 ps
CPU time 1.59 seconds
Started Aug 12 04:42:17 PM PDT 24
Finished Aug 12 04:42:19 PM PDT 24
Peak memory 222232 kb
Host smart-41ec81cd-60d7-487f-92a9-8b33eaf6ad24
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2971677605 -assert nopostproc +UVM_TESTNAME=i2c_bas
e_test +UVM_TEST_SEQ=i2c_target_nack_txstretch_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log
/dev/null -cm_name 13.i2c_target_nack_txstretch.2971677605
Directory /workspace/13.i2c_target_nack_txstretch/latest

Test location /workspace/coverage/default/13.i2c_target_perf.188194380
Short name T954
Test name
Test status
Simulation time 449934348 ps
CPU time 3.6 seconds
Started Aug 12 04:42:17 PM PDT 24
Finished Aug 12 04:42:21 PM PDT 24
Peak memory 213768 kb
Host smart-11464ca1-79de-43fe-a6b5-85fb9fd21e42
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=188194380 -assert nopostproc +UVM_TESTNAME=i2c_base
_test +UVM_TEST_SEQ=i2c_target_perf_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -
cm_name 13.i2c_target_perf.188194380
Directory /workspace/13.i2c_target_perf/latest

Test location /workspace/coverage/default/13.i2c_target_smbus_maxlen.3426660049
Short name T468
Test name
Test status
Simulation time 488513918 ps
CPU time 2.46 seconds
Started Aug 12 04:42:21 PM PDT 24
Finished Aug 12 04:42:24 PM PDT 24
Peak memory 205208 kb
Host smart-3c664e9c-e8b7-4aa5-bcad-624aadc67edc
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3426660049 -assert nopostproc +UVM_TESTNAME=i2c_bas
e_test +UVM_TEST_SEQ=i2c_target_smbus_maxlen_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /d
ev/null -cm_name 13.i2c_target_smbus_maxlen.3426660049
Directory /workspace/13.i2c_target_smbus_maxlen/latest

Test location /workspace/coverage/default/13.i2c_target_smoke.1026116784
Short name T91
Test name
Test status
Simulation time 3648637677 ps
CPU time 23.32 seconds
Started Aug 12 04:42:22 PM PDT 24
Finished Aug 12 04:42:45 PM PDT 24
Peak memory 213740 kb
Host smart-e4e317f0-d8dd-4ed2-ae48-c823e4794b3a
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=100_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licq
ueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1026116784 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SE
Q=i2c_target_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.i2c_ta
rget_smoke.1026116784
Directory /workspace/13.i2c_target_smoke/latest

Test location /workspace/coverage/default/13.i2c_target_stress_all.251056889
Short name T287
Test name
Test status
Simulation time 3904686153 ps
CPU time 22.93 seconds
Started Aug 12 04:42:17 PM PDT 24
Finished Aug 12 04:42:40 PM PDT 24
Peak memory 230224 kb
Host smart-5beeab52-2b46-41a1-b399-40e601101f0c
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=300_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VER
BOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=251056889 -assert nopostproc +UVM_TESTNAME=i2c_bas
e_test +UVM_TEST_SEQ=i2c_target_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev
/null -cm_name 13.i2c_target_stress_all.251056889
Directory /workspace/13.i2c_target_stress_all/latest

Test location /workspace/coverage/default/13.i2c_target_stress_rd.2165612300
Short name T1059
Test name
Test status
Simulation time 629054203 ps
CPU time 12.04 seconds
Started Aug 12 04:42:22 PM PDT 24
Finished Aug 12 04:42:34 PM PDT 24
Peak memory 209016 kb
Host smart-b81029a2-cb82-44af-9771-5e64ef9f3b0d
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=100_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licq
ueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2165612300 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SE
Q=i2c_target_stress_rd_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.i2
c_target_stress_rd.2165612300
Directory /workspace/13.i2c_target_stress_rd/latest

Test location /workspace/coverage/default/13.i2c_target_stress_wr.2749532728
Short name T1621
Test name
Test status
Simulation time 31198083319 ps
CPU time 37.29 seconds
Started Aug 12 04:42:17 PM PDT 24
Finished Aug 12 04:42:55 PM PDT 24
Peak memory 755108 kb
Host smart-56ffab68-736f-4116-a934-f542227e1b85
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=600_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licq
ueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2749532728 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SE
Q=i2c_target_stress_wr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.i2
c_target_stress_wr.2749532728
Directory /workspace/13.i2c_target_stress_wr/latest

Test location /workspace/coverage/default/13.i2c_target_stretch.823047349
Short name T1607
Test name
Test status
Simulation time 3611265292 ps
CPU time 29.41 seconds
Started Aug 12 04:42:22 PM PDT 24
Finished Aug 12 04:42:51 PM PDT 24
Peak memory 612976 kb
Host smart-0b8b8700-c857-426c-9316-f6ec2105a098
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=400_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licq
ueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=823047349 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ
=i2c_target_stretch_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.i2c_t
arget_stretch.823047349
Directory /workspace/13.i2c_target_stretch/latest

Test location /workspace/coverage/default/13.i2c_target_timeout.3780745999
Short name T902
Test name
Test status
Simulation time 1493683430 ps
CPU time 7.8 seconds
Started Aug 12 04:42:18 PM PDT 24
Finished Aug 12 04:42:26 PM PDT 24
Peak memory 230120 kb
Host smart-fa5e21af-b193-4113-959c-606a8c964774
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=50_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3780745999 -assert nopostproc +UVM_TESTNAME=i2c_bas
e_test +UVM_TEST_SEQ=i2c_target_timeout_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/nu
ll -cm_name 13.i2c_target_timeout.3780745999
Directory /workspace/13.i2c_target_timeout/latest

Test location /workspace/coverage/default/13.i2c_target_tx_stretch_ctrl.3281211152
Short name T314
Test name
Test status
Simulation time 114576516 ps
CPU time 2.54 seconds
Started Aug 12 04:42:18 PM PDT 24
Finished Aug 12 04:42:20 PM PDT 24
Peak memory 205468 kb
Host smart-77f58f4d-d609-4ff0-9ed8-e93fe26bdd33
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3281211152 -assert nopostproc +UVM_TESTNAME=i2c_bas
e_test +UVM_TEST_SEQ=i2c_target_tx_stretch_ctrl_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log
/dev/null -cm_name 13.i2c_target_tx_stretch_ctrl.3281211152
Directory /workspace/13.i2c_target_tx_stretch_ctrl/latest

Test location /workspace/coverage/default/14.i2c_alert_test.3370985173
Short name T391
Test name
Test status
Simulation time 36611002 ps
CPU time 0.61 seconds
Started Aug 12 04:42:24 PM PDT 24
Finished Aug 12 04:42:25 PM PDT 24
Peak memory 204416 kb
Host smart-0e3ce280-1d17-428c-9c86-b4a608fdde99
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3370985173 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_common_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.i2c_alert_test.3370985173
Directory /workspace/14.i2c_alert_test/latest

Test location /workspace/coverage/default/14.i2c_host_error_intr.878646227
Short name T1360
Test name
Test status
Simulation time 1201494489 ps
CPU time 4.86 seconds
Started Aug 12 04:42:25 PM PDT 24
Finished Aug 12 04:42:30 PM PDT 24
Peak memory 252156 kb
Host smart-6a38db49-daca-4f4f-b343-3d4c879db3b1
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=878646227 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_error_intr_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.i2c_host_error_intr.878646227
Directory /workspace/14.i2c_host_error_intr/latest

Test location /workspace/coverage/default/14.i2c_host_fifo_fmt_empty.1180249151
Short name T374
Test name
Test status
Simulation time 1551398956 ps
CPU time 19.84 seconds
Started Aug 12 04:42:20 PM PDT 24
Finished Aug 12 04:42:40 PM PDT 24
Peak memory 277148 kb
Host smart-25ce3369-4a9d-4974-9289-c02420a80e0f
User root
Command /workspace/default/simv +test_timeout_ns=10_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1180249151 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_fifo_fmt_em
pty_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.i2c_host_fifo_fmt_emp
ty.1180249151
Directory /workspace/14.i2c_host_fifo_fmt_empty/latest

Test location /workspace/coverage/default/14.i2c_host_fifo_full.1611314015
Short name T1492
Test name
Test status
Simulation time 15730488664 ps
CPU time 93.94 seconds
Started Aug 12 04:42:14 PM PDT 24
Finished Aug 12 04:43:48 PM PDT 24
Peak memory 528592 kb
Host smart-75eeaf94-b35e-41a0-8f69-8773b0cca65b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1611314015 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_fifo_full_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.i2c_host_fifo_full.1611314015
Directory /workspace/14.i2c_host_fifo_full/latest

Test location /workspace/coverage/default/14.i2c_host_fifo_overflow.2217068269
Short name T1313
Test name
Test status
Simulation time 3190948152 ps
CPU time 46.44 seconds
Started Aug 12 04:42:17 PM PDT 24
Finished Aug 12 04:43:03 PM PDT 24
Peak memory 537788 kb
Host smart-264f9f89-f58a-4807-8dee-340cbf827dbd
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2217068269 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_fifo_overflow_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.i2c_host_fifo_overflow.2217068269
Directory /workspace/14.i2c_host_fifo_overflow/latest

Test location /workspace/coverage/default/14.i2c_host_fifo_reset_fmt.3220182651
Short name T1316
Test name
Test status
Simulation time 220224552 ps
CPU time 1.07 seconds
Started Aug 12 04:42:21 PM PDT 24
Finished Aug 12 04:42:22 PM PDT 24
Peak memory 204916 kb
Host smart-751a927a-e354-4f8a-b46a-318c29fa3d9c
User root
Command /workspace/default/simv +test_timeout_ns=10_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3220182651 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_fifo_reset_
fmt_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.i2c_host_fifo_reset_f
mt.3220182651
Directory /workspace/14.i2c_host_fifo_reset_fmt/latest

Test location /workspace/coverage/default/14.i2c_host_fifo_reset_rx.2583441614
Short name T987
Test name
Test status
Simulation time 845545706 ps
CPU time 12.12 seconds
Started Aug 12 04:42:16 PM PDT 24
Finished Aug 12 04:42:28 PM PDT 24
Peak memory 246656 kb
Host smart-a33c3375-707c-4478-b445-8eb1d076b648
User root
Command /workspace/default/simv +test_timeout_ns=10_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2583441614 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_fifo_reset_
rx_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.i2c_host_fifo_reset_rx
.2583441614
Directory /workspace/14.i2c_host_fifo_reset_rx/latest

Test location /workspace/coverage/default/14.i2c_host_fifo_watermark.1013031724
Short name T840
Test name
Test status
Simulation time 17089074904 ps
CPU time 282.35 seconds
Started Aug 12 04:42:20 PM PDT 24
Finished Aug 12 04:47:03 PM PDT 24
Peak memory 1173372 kb
Host smart-e6981d99-3b7d-4131-88c6-e9b21791b683
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1013031724 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_fifo_watermark_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.i2c_host_fifo_watermark.1013031724
Directory /workspace/14.i2c_host_fifo_watermark/latest

Test location /workspace/coverage/default/14.i2c_host_may_nack.4136257436
Short name T268
Test name
Test status
Simulation time 2566716933 ps
CPU time 9.91 seconds
Started Aug 12 04:42:28 PM PDT 24
Finished Aug 12 04:42:38 PM PDT 24
Peak memory 205376 kb
Host smart-6a050ff0-65d9-4021-aa68-ad1ce471c876
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4136257436 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_may_nack_vseq +en_cov=1 -cm line+cond+f
sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.i2c_host_may_nack.4136257436
Directory /workspace/14.i2c_host_may_nack/latest

Test location /workspace/coverage/default/14.i2c_host_perf.2662179051
Short name T328
Test name
Test status
Simulation time 547687764 ps
CPU time 4.49 seconds
Started Aug 12 04:42:14 PM PDT 24
Finished Aug 12 04:42:19 PM PDT 24
Peak memory 213988 kb
Host smart-7c557ed5-77e9-44f2-8da4-00f248ecdeac
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2662179051 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_perf_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.i2c_host_perf.2662179051
Directory /workspace/14.i2c_host_perf/latest

Test location /workspace/coverage/default/14.i2c_host_perf_precise.2148175949
Short name T983
Test name
Test status
Simulation time 381170337 ps
CPU time 7.64 seconds
Started Aug 12 04:42:18 PM PDT 24
Finished Aug 12 04:42:26 PM PDT 24
Peak memory 276552 kb
Host smart-34a05324-cd0a-4b80-bd33-17ad71ba579f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2148175949 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_perf_precise_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.i2c_host_perf_precise.2148175949
Directory /workspace/14.i2c_host_perf_precise/latest

Test location /workspace/coverage/default/14.i2c_host_smoke.1286502689
Short name T994
Test name
Test status
Simulation time 1780417365 ps
CPU time 82.79 seconds
Started Aug 12 04:42:15 PM PDT 24
Finished Aug 12 04:43:38 PM PDT 24
Peak memory 351268 kb
Host smart-396bd08a-b256-4e44-b23f-86a46cdfa2c7
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1286502689 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_smoke_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.i2c_host_smoke.1286502689
Directory /workspace/14.i2c_host_smoke/latest

Test location /workspace/coverage/default/14.i2c_host_stretch_timeout.784307666
Short name T332
Test name
Test status
Simulation time 1396345992 ps
CPU time 10.78 seconds
Started Aug 12 04:42:15 PM PDT 24
Finished Aug 12 04:42:26 PM PDT 24
Peak memory 220672 kb
Host smart-04506dd0-62bc-4791-9fbf-8835fae1d610
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=784307666 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_stretch_timeout_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.i2c_host_stretch_timeout.784307666
Directory /workspace/14.i2c_host_stretch_timeout/latest

Test location /workspace/coverage/default/14.i2c_target_bad_addr.3137362864
Short name T1264
Test name
Test status
Simulation time 736155797 ps
CPU time 4.12 seconds
Started Aug 12 04:42:27 PM PDT 24
Finished Aug 12 04:42:31 PM PDT 24
Peak memory 218668 kb
Host smart-44ac1649-1712-43b0-80d0-3806e721eeb2
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +i2c_bad_addr_pct=50 +cdc_instrumentation_enabled=1 +UVM_
NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3137362864 -assert nopostproc
+UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_target_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.
vdb -cm_log /dev/null -cm_name 14.i2c_target_bad_addr.3137362864
Directory /workspace/14.i2c_target_bad_addr/latest

Test location /workspace/coverage/default/14.i2c_target_fifo_reset_acq.999331675
Short name T128
Test name
Test status
Simulation time 397667607 ps
CPU time 1.38 seconds
Started Aug 12 04:42:25 PM PDT 24
Finished Aug 12 04:42:27 PM PDT 24
Peak memory 205404 kb
Host smart-0d623e43-3b29-4ada-aa2d-c623e9399e3d
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=999331675 -assert nopostproc +UVM_TESTNAME=i2c_base
_test +UVM_TEST_SEQ=i2c_target_fifo_reset_acq_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /
dev/null -cm_name 14.i2c_target_fifo_reset_acq.999331675
Directory /workspace/14.i2c_target_fifo_reset_acq/latest

Test location /workspace/coverage/default/14.i2c_target_fifo_reset_tx.1852752452
Short name T1400
Test name
Test status
Simulation time 210499747 ps
CPU time 0.93 seconds
Started Aug 12 04:42:24 PM PDT 24
Finished Aug 12 04:42:25 PM PDT 24
Peak memory 213496 kb
Host smart-cb34d39d-6b5c-46ec-aa6f-833e391d4a7a
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1852752452 -assert nopostproc +UVM_TESTNAME=i2c_bas
e_test +UVM_TEST_SEQ=i2c_target_fifo_reset_tx_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /
dev/null -cm_name 14.i2c_target_fifo_reset_tx.1852752452
Directory /workspace/14.i2c_target_fifo_reset_tx/latest

Test location /workspace/coverage/default/14.i2c_target_fifo_watermarks_acq.389904552
Short name T1103
Test name
Test status
Simulation time 1009404376 ps
CPU time 2.47 seconds
Started Aug 12 04:42:26 PM PDT 24
Finished Aug 12 04:42:29 PM PDT 24
Peak memory 205512 kb
Host smart-7e4ddbe7-bd64-4ec0-bf7a-37a8e5c29fa9
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=389904552 -assert nopostproc +UVM_TESTNAME=i2c_base
_test +UVM_TEST_SEQ=i2c_target_fifo_watermarks_acq_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_
log /dev/null -cm_name 14.i2c_target_fifo_watermarks_acq.389904552
Directory /workspace/14.i2c_target_fifo_watermarks_acq/latest

Test location /workspace/coverage/default/14.i2c_target_fifo_watermarks_tx.492312541
Short name T1465
Test name
Test status
Simulation time 95386251 ps
CPU time 1.07 seconds
Started Aug 12 04:42:26 PM PDT 24
Finished Aug 12 04:42:27 PM PDT 24
Peak memory 205388 kb
Host smart-65e3cf2f-1938-4bd2-838a-f5ce0d1650f7
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=492312541 -assert nopostproc +UVM_TESTNAME=i2c_base
_test +UVM_TEST_SEQ=i2c_target_fifo_watermarks_tx_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_l
og /dev/null -cm_name 14.i2c_target_fifo_watermarks_tx.492312541
Directory /workspace/14.i2c_target_fifo_watermarks_tx/latest

Test location /workspace/coverage/default/14.i2c_target_intr_smoke.687744648
Short name T1615
Test name
Test status
Simulation time 3635405287 ps
CPU time 5.55 seconds
Started Aug 12 04:42:24 PM PDT 24
Finished Aug 12 04:42:30 PM PDT 24
Peak memory 235156 kb
Host smart-5386438e-2be0-4d1d-bf48-306613707840
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=200_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VER
BOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=687744648 -assert nopostproc +UVM_TESTNAME=i2c_bas
e_test +UVM_TEST_SEQ=i2c_target_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null
-cm_name 14.i2c_target_intr_smoke.687744648
Directory /workspace/14.i2c_target_intr_smoke/latest

Test location /workspace/coverage/default/14.i2c_target_intr_stress_wr.674818882
Short name T943
Test name
Test status
Simulation time 937655457 ps
CPU time 1.65 seconds
Started Aug 12 04:42:25 PM PDT 24
Finished Aug 12 04:42:27 PM PDT 24
Peak memory 205244 kb
Host smart-30c49591-8746-4622-8444-af8e4e8abd35
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=600_000_000 +use_intr_handler=1 +slow_acq=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNO
TES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=674818882 -assert nopostproc +UVM_TEST
NAME=i2c_base_test +UVM_TEST_SEQ=i2c_target_stress_wr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -
cm_log /dev/null -cm_name 14.i2c_target_intr_stress_wr.674818882
Directory /workspace/14.i2c_target_intr_stress_wr/latest

Test location /workspace/coverage/default/14.i2c_target_nack_acqfull.2688941396
Short name T1374
Test name
Test status
Simulation time 5247524553 ps
CPU time 3.17 seconds
Started Aug 12 04:42:25 PM PDT 24
Finished Aug 12 04:42:29 PM PDT 24
Peak memory 213668 kb
Host smart-00657b7e-4654-407e-b3fc-516d70109930
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2688941396 -assert nopostproc +UVM_TESTNAME=i2c_bas
e_test +UVM_TEST_SEQ=i2c_target_nack_acqfull_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /d
ev/null -cm_name 14.i2c_target_nack_acqfull.2688941396
Directory /workspace/14.i2c_target_nack_acqfull/latest

Test location /workspace/coverage/default/14.i2c_target_nack_acqfull_addr.52772769
Short name T1355
Test name
Test status
Simulation time 430591152 ps
CPU time 2.32 seconds
Started Aug 12 04:42:29 PM PDT 24
Finished Aug 12 04:42:31 PM PDT 24
Peak memory 205464 kb
Host smart-5baf3482-28c4-46f2-8bc0-5dd6dc1ac867
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=52772769 -assert nopostproc +UVM_TESTNAME=i2c_base_
test +UVM_TEST_SEQ=i2c_target_nack_acqfull_addr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log
/dev/null -cm_name 14.i2c_target_nack_acqfull_addr.52772769
Directory /workspace/14.i2c_target_nack_acqfull_addr/latest

Test location /workspace/coverage/default/14.i2c_target_perf.1287189318
Short name T1676
Test name
Test status
Simulation time 1540240325 ps
CPU time 2.81 seconds
Started Aug 12 04:42:27 PM PDT 24
Finished Aug 12 04:42:30 PM PDT 24
Peak memory 213636 kb
Host smart-56bede19-d2a4-4501-8b8b-5a5d322e5c6c
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1287189318 -assert nopostproc +UVM_TESTNAME=i2c_bas
e_test +UVM_TEST_SEQ=i2c_target_perf_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null
-cm_name 14.i2c_target_perf.1287189318
Directory /workspace/14.i2c_target_perf/latest

Test location /workspace/coverage/default/14.i2c_target_smbus_maxlen.3561427117
Short name T1371
Test name
Test status
Simulation time 507701253 ps
CPU time 2.54 seconds
Started Aug 12 04:42:25 PM PDT 24
Finished Aug 12 04:42:27 PM PDT 24
Peak memory 205252 kb
Host smart-b159f55c-45e6-46ac-a484-2f29eb01a905
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3561427117 -assert nopostproc +UVM_TESTNAME=i2c_bas
e_test +UVM_TEST_SEQ=i2c_target_smbus_maxlen_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /d
ev/null -cm_name 14.i2c_target_smbus_maxlen.3561427117
Directory /workspace/14.i2c_target_smbus_maxlen/latest

Test location /workspace/coverage/default/14.i2c_target_smoke.1567733890
Short name T403
Test name
Test status
Simulation time 821473076 ps
CPU time 12.93 seconds
Started Aug 12 04:42:25 PM PDT 24
Finished Aug 12 04:42:38 PM PDT 24
Peak memory 213696 kb
Host smart-48f7e270-e484-49d3-bbc3-cde12f937bb3
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=100_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licq
ueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1567733890 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SE
Q=i2c_target_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.i2c_ta
rget_smoke.1567733890
Directory /workspace/14.i2c_target_smoke/latest

Test location /workspace/coverage/default/14.i2c_target_stress_all.2174627493
Short name T730
Test name
Test status
Simulation time 86808907952 ps
CPU time 291.35 seconds
Started Aug 12 04:42:25 PM PDT 24
Finished Aug 12 04:47:17 PM PDT 24
Peak memory 2453452 kb
Host smart-27227186-008c-479f-8e2b-b3c2347a998e
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=300_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VER
BOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2174627493 -assert nopostproc +UVM_TESTNAME=i2c_ba
se_test +UVM_TEST_SEQ=i2c_target_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /de
v/null -cm_name 14.i2c_target_stress_all.2174627493
Directory /workspace/14.i2c_target_stress_all/latest

Test location /workspace/coverage/default/14.i2c_target_stress_rd.3510362353
Short name T1595
Test name
Test status
Simulation time 2237720281 ps
CPU time 50.08 seconds
Started Aug 12 04:42:29 PM PDT 24
Finished Aug 12 04:43:19 PM PDT 24
Peak memory 216364 kb
Host smart-215e28b2-0035-49ab-8075-ef707893a3ba
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=100_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licq
ueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3510362353 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SE
Q=i2c_target_stress_rd_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.i2
c_target_stress_rd.3510362353
Directory /workspace/14.i2c_target_stress_rd/latest

Test location /workspace/coverage/default/14.i2c_target_stress_wr.206473449
Short name T1501
Test name
Test status
Simulation time 22796562856 ps
CPU time 17.84 seconds
Started Aug 12 04:42:26 PM PDT 24
Finished Aug 12 04:42:44 PM PDT 24
Peak memory 282736 kb
Host smart-86c82b2d-059f-4230-a164-f05cd3489800
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=600_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licq
ueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=206473449 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ
=i2c_target_stress_wr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.i2c
_target_stress_wr.206473449
Directory /workspace/14.i2c_target_stress_wr/latest

Test location /workspace/coverage/default/14.i2c_target_stretch.1598826805
Short name T1448
Test name
Test status
Simulation time 5274478291 ps
CPU time 59.25 seconds
Started Aug 12 04:42:25 PM PDT 24
Finished Aug 12 04:43:25 PM PDT 24
Peak memory 485804 kb
Host smart-7b3cea9e-8351-4a11-965b-96f180a916eb
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=400_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licq
ueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1598826805 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SE
Q=i2c_target_stretch_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.i2c_
target_stretch.1598826805
Directory /workspace/14.i2c_target_stretch/latest

Test location /workspace/coverage/default/14.i2c_target_timeout.2990957944
Short name T910
Test name
Test status
Simulation time 1748897311 ps
CPU time 7.34 seconds
Started Aug 12 04:42:30 PM PDT 24
Finished Aug 12 04:42:38 PM PDT 24
Peak memory 221772 kb
Host smart-750cdbc7-89d2-4aa4-aa75-62a833ae4774
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=50_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2990957944 -assert nopostproc +UVM_TESTNAME=i2c_bas
e_test +UVM_TEST_SEQ=i2c_target_timeout_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/nu
ll -cm_name 14.i2c_target_timeout.2990957944
Directory /workspace/14.i2c_target_timeout/latest

Test location /workspace/coverage/default/14.i2c_target_tx_stretch_ctrl.4087358085
Short name T976
Test name
Test status
Simulation time 241646618 ps
CPU time 3.37 seconds
Started Aug 12 04:42:25 PM PDT 24
Finished Aug 12 04:42:29 PM PDT 24
Peak memory 213704 kb
Host smart-a74f8247-a507-4490-8f4d-0634019fa64d
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4087358085 -assert nopostproc +UVM_TESTNAME=i2c_bas
e_test +UVM_TEST_SEQ=i2c_target_tx_stretch_ctrl_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log
/dev/null -cm_name 14.i2c_target_tx_stretch_ctrl.4087358085
Directory /workspace/14.i2c_target_tx_stretch_ctrl/latest

Test location /workspace/coverage/default/15.i2c_alert_test.234575781
Short name T344
Test name
Test status
Simulation time 17672538 ps
CPU time 0.63 seconds
Started Aug 12 04:42:33 PM PDT 24
Finished Aug 12 04:42:34 PM PDT 24
Peak memory 204616 kb
Host smart-6cffd441-e835-4061-9ac2-ea99eee9fdf2
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=234575781 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_common_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.i2c_alert_test.234575781
Directory /workspace/15.i2c_alert_test/latest

Test location /workspace/coverage/default/15.i2c_host_error_intr.4135887883
Short name T1583
Test name
Test status
Simulation time 228997176 ps
CPU time 3.24 seconds
Started Aug 12 04:42:25 PM PDT 24
Finished Aug 12 04:42:28 PM PDT 24
Peak memory 213524 kb
Host smart-82ae18aa-2ad9-4c48-a3d2-2473816c99fb
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4135887883 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_error_intr_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.i2c_host_error_intr.4135887883
Directory /workspace/15.i2c_host_error_intr/latest

Test location /workspace/coverage/default/15.i2c_host_fifo_fmt_empty.1436219835
Short name T1464
Test name
Test status
Simulation time 439792493 ps
CPU time 8.34 seconds
Started Aug 12 04:42:27 PM PDT 24
Finished Aug 12 04:42:35 PM PDT 24
Peak memory 299460 kb
Host smart-c25ae0f4-50f8-4b69-bb6a-9d00068aea07
User root
Command /workspace/default/simv +test_timeout_ns=10_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1436219835 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_fifo_fmt_em
pty_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.i2c_host_fifo_fmt_emp
ty.1436219835
Directory /workspace/15.i2c_host_fifo_fmt_empty/latest

Test location /workspace/coverage/default/15.i2c_host_fifo_full.2957580652
Short name T1121
Test name
Test status
Simulation time 33075725645 ps
CPU time 96.9 seconds
Started Aug 12 04:42:25 PM PDT 24
Finished Aug 12 04:44:02 PM PDT 24
Peak memory 473200 kb
Host smart-6d761df4-d75c-46f8-832a-530f728aca8e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2957580652 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_fifo_full_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.i2c_host_fifo_full.2957580652
Directory /workspace/15.i2c_host_fifo_full/latest

Test location /workspace/coverage/default/15.i2c_host_fifo_overflow.3883545325
Short name T839
Test name
Test status
Simulation time 3665475252 ps
CPU time 63.13 seconds
Started Aug 12 04:42:24 PM PDT 24
Finished Aug 12 04:43:27 PM PDT 24
Peak memory 664372 kb
Host smart-c86ee04b-be4f-4c7c-bc1a-93fe97ea469b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3883545325 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_fifo_overflow_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.i2c_host_fifo_overflow.3883545325
Directory /workspace/15.i2c_host_fifo_overflow/latest

Test location /workspace/coverage/default/15.i2c_host_fifo_reset_fmt.571806173
Short name T1610
Test name
Test status
Simulation time 1138509070 ps
CPU time 1.03 seconds
Started Aug 12 04:42:27 PM PDT 24
Finished Aug 12 04:42:28 PM PDT 24
Peak memory 204952 kb
Host smart-cc848fa2-7f7d-4d3f-9f99-851671474378
User root
Command /workspace/default/simv +test_timeout_ns=10_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=571806173 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_fifo_reset_f
mt_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.i2c_host_fifo_reset_fm
t.571806173
Directory /workspace/15.i2c_host_fifo_reset_fmt/latest

Test location /workspace/coverage/default/15.i2c_host_fifo_reset_rx.3883777517
Short name T365
Test name
Test status
Simulation time 876382733 ps
CPU time 11.76 seconds
Started Aug 12 04:42:27 PM PDT 24
Finished Aug 12 04:42:39 PM PDT 24
Peak memory 205272 kb
Host smart-bf8ed840-3821-434f-991b-6b7f3b3d3900
User root
Command /workspace/default/simv +test_timeout_ns=10_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3883777517 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_fifo_reset_
rx_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.i2c_host_fifo_reset_rx
.3883777517
Directory /workspace/15.i2c_host_fifo_reset_rx/latest

Test location /workspace/coverage/default/15.i2c_host_fifo_watermark.4037500027
Short name T1459
Test name
Test status
Simulation time 16188112756 ps
CPU time 107.73 seconds
Started Aug 12 04:42:24 PM PDT 24
Finished Aug 12 04:44:12 PM PDT 24
Peak memory 1107800 kb
Host smart-299eec83-dd3b-45e9-8ecd-dd1b1d23c02e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4037500027 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_fifo_watermark_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.i2c_host_fifo_watermark.4037500027
Directory /workspace/15.i2c_host_fifo_watermark/latest

Test location /workspace/coverage/default/15.i2c_host_may_nack.1262514783
Short name T271
Test name
Test status
Simulation time 1478253773 ps
CPU time 4.51 seconds
Started Aug 12 04:42:32 PM PDT 24
Finished Aug 12 04:42:37 PM PDT 24
Peak memory 205252 kb
Host smart-8c9f7cb4-bd37-4264-8008-6e5b1fd552df
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1262514783 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_may_nack_vseq +en_cov=1 -cm line+cond+f
sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.i2c_host_may_nack.1262514783
Directory /workspace/15.i2c_host_may_nack/latest

Test location /workspace/coverage/default/15.i2c_host_override.1170524333
Short name T155
Test name
Test status
Simulation time 285834434 ps
CPU time 0.7 seconds
Started Aug 12 04:42:25 PM PDT 24
Finished Aug 12 04:42:26 PM PDT 24
Peak memory 204912 kb
Host smart-e1b127c6-1dd6-4909-81af-e75fecfb6ee5
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1170524333 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_override_vseq +en_cov=1 -cm line+cond+f
sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.i2c_host_override.1170524333
Directory /workspace/15.i2c_host_override/latest

Test location /workspace/coverage/default/15.i2c_host_perf_precise.3290233337
Short name T662
Test name
Test status
Simulation time 563640922 ps
CPU time 11.34 seconds
Started Aug 12 04:42:28 PM PDT 24
Finished Aug 12 04:42:40 PM PDT 24
Peak memory 213396 kb
Host smart-8c0573dc-ae4c-4599-9392-4d2076e68346
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3290233337 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_perf_precise_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.i2c_host_perf_precise.3290233337
Directory /workspace/15.i2c_host_perf_precise/latest

Test location /workspace/coverage/default/15.i2c_host_smoke.1042343788
Short name T393
Test name
Test status
Simulation time 3521579372 ps
CPU time 89.06 seconds
Started Aug 12 04:42:28 PM PDT 24
Finished Aug 12 04:43:57 PM PDT 24
Peak memory 414408 kb
Host smart-cdebdae1-5b01-46a6-8c39-67af709b980f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1042343788 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_smoke_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.i2c_host_smoke.1042343788
Directory /workspace/15.i2c_host_smoke/latest

Test location /workspace/coverage/default/15.i2c_host_stretch_timeout.3781190957
Short name T146
Test name
Test status
Simulation time 598331231 ps
CPU time 25.87 seconds
Started Aug 12 04:42:24 PM PDT 24
Finished Aug 12 04:42:50 PM PDT 24
Peak memory 213428 kb
Host smart-98593cd6-dc39-4c88-9d87-1ca8eb23e809
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3781190957 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_stretch_timeout_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.i2c_host_stretch_timeout.3781190957
Directory /workspace/15.i2c_host_stretch_timeout/latest

Test location /workspace/coverage/default/15.i2c_target_bad_addr.1623260695
Short name T916
Test name
Test status
Simulation time 1568332018 ps
CPU time 6.57 seconds
Started Aug 12 04:42:35 PM PDT 24
Finished Aug 12 04:42:42 PM PDT 24
Peak memory 221804 kb
Host smart-4d975140-701a-42a9-bd8d-2543c09d70f7
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +i2c_bad_addr_pct=50 +cdc_instrumentation_enabled=1 +UVM_
NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1623260695 -assert nopostproc
+UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_target_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.
vdb -cm_log /dev/null -cm_name 15.i2c_target_bad_addr.1623260695
Directory /workspace/15.i2c_target_bad_addr/latest

Test location /workspace/coverage/default/15.i2c_target_fifo_reset_tx.4137143953
Short name T1284
Test name
Test status
Simulation time 187803526 ps
CPU time 1.24 seconds
Started Aug 12 04:42:34 PM PDT 24
Finished Aug 12 04:42:35 PM PDT 24
Peak memory 205772 kb
Host smart-0319e090-4306-4f44-8f90-5932c4385654
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4137143953 -assert nopostproc +UVM_TESTNAME=i2c_bas
e_test +UVM_TEST_SEQ=i2c_target_fifo_reset_tx_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /
dev/null -cm_name 15.i2c_target_fifo_reset_tx.4137143953
Directory /workspace/15.i2c_target_fifo_reset_tx/latest

Test location /workspace/coverage/default/15.i2c_target_fifo_watermarks_acq.1346813751
Short name T94
Test name
Test status
Simulation time 770366509 ps
CPU time 2.66 seconds
Started Aug 12 04:42:34 PM PDT 24
Finished Aug 12 04:42:37 PM PDT 24
Peak memory 205472 kb
Host smart-605aa5f3-ddda-46d2-825e-e80c53229cb0
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1346813751 -assert nopostproc +UVM_TESTNAME=i2c_bas
e_test +UVM_TEST_SEQ=i2c_target_fifo_watermarks_acq_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm
_log /dev/null -cm_name 15.i2c_target_fifo_watermarks_acq.1346813751
Directory /workspace/15.i2c_target_fifo_watermarks_acq/latest

Test location /workspace/coverage/default/15.i2c_target_fifo_watermarks_tx.197617511
Short name T617
Test name
Test status
Simulation time 876070267 ps
CPU time 1.68 seconds
Started Aug 12 04:42:34 PM PDT 24
Finished Aug 12 04:42:36 PM PDT 24
Peak memory 205272 kb
Host smart-9b0524df-d9c3-4ef5-9c18-1d692197882f
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=197617511 -assert nopostproc +UVM_TESTNAME=i2c_base
_test +UVM_TEST_SEQ=i2c_target_fifo_watermarks_tx_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_l
og /dev/null -cm_name 15.i2c_target_fifo_watermarks_tx.197617511
Directory /workspace/15.i2c_target_fifo_watermarks_tx/latest

Test location /workspace/coverage/default/15.i2c_target_hrst.2824705452
Short name T1619
Test name
Test status
Simulation time 364407001 ps
CPU time 1.78 seconds
Started Aug 12 04:42:33 PM PDT 24
Finished Aug 12 04:42:35 PM PDT 24
Peak memory 213664 kb
Host smart-def5b035-781c-41c7-90f4-24b82ffb892d
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2824705452 -assert nopostproc +UVM_TESTNAME=i2c_bas
e_test +UVM_TEST_SEQ=i2c_target_hrst_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null
-cm_name 15.i2c_target_hrst.2824705452
Directory /workspace/15.i2c_target_hrst/latest

Test location /workspace/coverage/default/15.i2c_target_intr_smoke.1087801811
Short name T1386
Test name
Test status
Simulation time 1800987540 ps
CPU time 5.59 seconds
Started Aug 12 04:42:34 PM PDT 24
Finished Aug 12 04:42:40 PM PDT 24
Peak memory 217040 kb
Host smart-546b3557-1a9a-4097-8681-cfc36a8c599c
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=200_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VER
BOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1087801811 -assert nopostproc +UVM_TESTNAME=i2c_ba
se_test +UVM_TEST_SEQ=i2c_target_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/nul
l -cm_name 15.i2c_target_intr_smoke.1087801811
Directory /workspace/15.i2c_target_intr_smoke/latest

Test location /workspace/coverage/default/15.i2c_target_intr_stress_wr.1744851435
Short name T961
Test name
Test status
Simulation time 3178764849 ps
CPU time 7.71 seconds
Started Aug 12 04:42:37 PM PDT 24
Finished Aug 12 04:42:45 PM PDT 24
Peak memory 205436 kb
Host smart-4348eab3-8882-4e5c-8d0c-4cc2341819e9
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=600_000_000 +use_intr_handler=1 +slow_acq=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNO
TES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1744851435 -assert nopostproc +UVM_TES
TNAME=i2c_base_test +UVM_TEST_SEQ=i2c_target_stress_wr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb
-cm_log /dev/null -cm_name 15.i2c_target_intr_stress_wr.1744851435
Directory /workspace/15.i2c_target_intr_stress_wr/latest

Test location /workspace/coverage/default/15.i2c_target_nack_acqfull.862846795
Short name T1514
Test name
Test status
Simulation time 494394584 ps
CPU time 2.9 seconds
Started Aug 12 04:42:34 PM PDT 24
Finished Aug 12 04:42:37 PM PDT 24
Peak memory 213768 kb
Host smart-3694e273-7990-41f9-afe0-be7d8cf3c23a
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=862846795 -assert nopostproc +UVM_TESTNAME=i2c_base
_test +UVM_TEST_SEQ=i2c_target_nack_acqfull_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /de
v/null -cm_name 15.i2c_target_nack_acqfull.862846795
Directory /workspace/15.i2c_target_nack_acqfull/latest

Test location /workspace/coverage/default/15.i2c_target_nack_acqfull_addr.388736875
Short name T366
Test name
Test status
Simulation time 705001470 ps
CPU time 2.83 seconds
Started Aug 12 04:42:33 PM PDT 24
Finished Aug 12 04:42:36 PM PDT 24
Peak memory 205444 kb
Host smart-abb3a359-44e0-4fe4-837e-904601fa09fa
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=388736875 -assert nopostproc +UVM_TESTNAME=i2c_base
_test +UVM_TEST_SEQ=i2c_target_nack_acqfull_addr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_lo
g /dev/null -cm_name 15.i2c_target_nack_acqfull_addr.388736875
Directory /workspace/15.i2c_target_nack_acqfull_addr/latest

Test location /workspace/coverage/default/15.i2c_target_nack_txstretch.2610619187
Short name T49
Test name
Test status
Simulation time 175503698 ps
CPU time 1.55 seconds
Started Aug 12 04:42:38 PM PDT 24
Finished Aug 12 04:42:40 PM PDT 24
Peak memory 222024 kb
Host smart-b569c561-6f89-4caf-8286-ab12e93bda42
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2610619187 -assert nopostproc +UVM_TESTNAME=i2c_bas
e_test +UVM_TEST_SEQ=i2c_target_nack_txstretch_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log
/dev/null -cm_name 15.i2c_target_nack_txstretch.2610619187
Directory /workspace/15.i2c_target_nack_txstretch/latest

Test location /workspace/coverage/default/15.i2c_target_perf.2488647439
Short name T809
Test name
Test status
Simulation time 609954587 ps
CPU time 4.92 seconds
Started Aug 12 04:42:33 PM PDT 24
Finished Aug 12 04:42:38 PM PDT 24
Peak memory 215856 kb
Host smart-d7753192-3474-4b00-9192-f3e1ddcae60d
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2488647439 -assert nopostproc +UVM_TESTNAME=i2c_bas
e_test +UVM_TEST_SEQ=i2c_target_perf_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null
-cm_name 15.i2c_target_perf.2488647439
Directory /workspace/15.i2c_target_perf/latest

Test location /workspace/coverage/default/15.i2c_target_smbus_maxlen.1459301978
Short name T497
Test name
Test status
Simulation time 1985137181 ps
CPU time 2.37 seconds
Started Aug 12 04:42:32 PM PDT 24
Finished Aug 12 04:42:35 PM PDT 24
Peak memory 205164 kb
Host smart-a06d3052-b88d-4e06-8fd6-10f31a6a21b5
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1459301978 -assert nopostproc +UVM_TESTNAME=i2c_bas
e_test +UVM_TEST_SEQ=i2c_target_smbus_maxlen_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /d
ev/null -cm_name 15.i2c_target_smbus_maxlen.1459301978
Directory /workspace/15.i2c_target_smbus_maxlen/latest

Test location /workspace/coverage/default/15.i2c_target_smoke.2299998769
Short name T1282
Test name
Test status
Simulation time 11193284799 ps
CPU time 12.07 seconds
Started Aug 12 04:42:31 PM PDT 24
Finished Aug 12 04:42:43 PM PDT 24
Peak memory 221896 kb
Host smart-175cbb19-f1b4-488d-981f-de87826b7390
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=100_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licq
ueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2299998769 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SE
Q=i2c_target_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.i2c_ta
rget_smoke.2299998769
Directory /workspace/15.i2c_target_smoke/latest

Test location /workspace/coverage/default/15.i2c_target_stress_all.269166964
Short name T1467
Test name
Test status
Simulation time 48931633860 ps
CPU time 81.1 seconds
Started Aug 12 04:42:33 PM PDT 24
Finished Aug 12 04:43:55 PM PDT 24
Peak memory 887016 kb
Host smart-0fca58d3-0974-453d-a756-4ec9dfd5be2b
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=300_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VER
BOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=269166964 -assert nopostproc +UVM_TESTNAME=i2c_bas
e_test +UVM_TEST_SEQ=i2c_target_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev
/null -cm_name 15.i2c_target_stress_all.269166964
Directory /workspace/15.i2c_target_stress_all/latest

Test location /workspace/coverage/default/15.i2c_target_stress_rd.4011266063
Short name T1738
Test name
Test status
Simulation time 2671769319 ps
CPU time 24.92 seconds
Started Aug 12 04:42:33 PM PDT 24
Finished Aug 12 04:42:58 PM PDT 24
Peak memory 223376 kb
Host smart-b5c3e9c4-f846-4509-b56a-3504cea516f8
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=100_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licq
ueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4011266063 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SE
Q=i2c_target_stress_rd_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.i2
c_target_stress_rd.4011266063
Directory /workspace/15.i2c_target_stress_rd/latest

Test location /workspace/coverage/default/15.i2c_target_stress_wr.111087740
Short name T1542
Test name
Test status
Simulation time 43499063876 ps
CPU time 66.8 seconds
Started Aug 12 04:42:32 PM PDT 24
Finished Aug 12 04:43:39 PM PDT 24
Peak memory 1079736 kb
Host smart-3c36cf30-083e-4144-9da3-ff9ba8cfbf7a
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=600_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licq
ueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=111087740 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ
=i2c_target_stress_wr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.i2c
_target_stress_wr.111087740
Directory /workspace/15.i2c_target_stress_wr/latest

Test location /workspace/coverage/default/15.i2c_target_stretch.911077155
Short name T1290
Test name
Test status
Simulation time 4381109521 ps
CPU time 8.15 seconds
Started Aug 12 04:42:33 PM PDT 24
Finished Aug 12 04:42:42 PM PDT 24
Peak memory 437976 kb
Host smart-7f102620-ce9c-411e-845b-e9d5ef71305b
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=400_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licq
ueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=911077155 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ
=i2c_target_stretch_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.i2c_t
arget_stretch.911077155
Directory /workspace/15.i2c_target_stretch/latest

Test location /workspace/coverage/default/15.i2c_target_timeout.1576712677
Short name T1119
Test name
Test status
Simulation time 5276514650 ps
CPU time 5.82 seconds
Started Aug 12 04:42:33 PM PDT 24
Finished Aug 12 04:42:39 PM PDT 24
Peak memory 219576 kb
Host smart-8e8fa985-8692-405e-a44f-540ff939dd9e
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=50_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1576712677 -assert nopostproc +UVM_TESTNAME=i2c_bas
e_test +UVM_TEST_SEQ=i2c_target_timeout_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/nu
ll -cm_name 15.i2c_target_timeout.1576712677
Directory /workspace/15.i2c_target_timeout/latest

Test location /workspace/coverage/default/15.i2c_target_tx_stretch_ctrl.1345211847
Short name T1166
Test name
Test status
Simulation time 126116817 ps
CPU time 2.84 seconds
Started Aug 12 04:42:34 PM PDT 24
Finished Aug 12 04:42:37 PM PDT 24
Peak memory 205464 kb
Host smart-6a3dc90d-8943-42bc-b1d9-41461d344a69
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1345211847 -assert nopostproc +UVM_TESTNAME=i2c_bas
e_test +UVM_TEST_SEQ=i2c_target_tx_stretch_ctrl_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log
/dev/null -cm_name 15.i2c_target_tx_stretch_ctrl.1345211847
Directory /workspace/15.i2c_target_tx_stretch_ctrl/latest

Test location /workspace/coverage/default/16.i2c_alert_test.3322344009
Short name T546
Test name
Test status
Simulation time 16308728 ps
CPU time 0.71 seconds
Started Aug 12 04:42:42 PM PDT 24
Finished Aug 12 04:42:43 PM PDT 24
Peak memory 204432 kb
Host smart-5909cc74-c71f-46c7-b315-3813fc47f466
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3322344009 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_common_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.i2c_alert_test.3322344009
Directory /workspace/16.i2c_alert_test/latest

Test location /workspace/coverage/default/16.i2c_host_error_intr.1824957025
Short name T19
Test name
Test status
Simulation time 1084484178 ps
CPU time 5.72 seconds
Started Aug 12 04:42:34 PM PDT 24
Finished Aug 12 04:42:39 PM PDT 24
Peak memory 236252 kb
Host smart-64a6f5e1-d3a5-4776-8ccb-42eab12f487a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1824957025 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_error_intr_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.i2c_host_error_intr.1824957025
Directory /workspace/16.i2c_host_error_intr/latest

Test location /workspace/coverage/default/16.i2c_host_fifo_fmt_empty.1325514457
Short name T42
Test name
Test status
Simulation time 130401357 ps
CPU time 3.19 seconds
Started Aug 12 04:42:35 PM PDT 24
Finished Aug 12 04:42:39 PM PDT 24
Peak memory 226404 kb
Host smart-92f1788d-69bc-44f1-8899-5d718397f03e
User root
Command /workspace/default/simv +test_timeout_ns=10_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1325514457 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_fifo_fmt_em
pty_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.i2c_host_fifo_fmt_emp
ty.1325514457
Directory /workspace/16.i2c_host_fifo_fmt_empty/latest

Test location /workspace/coverage/default/16.i2c_host_fifo_full.2063298602
Short name T1460
Test name
Test status
Simulation time 9960243323 ps
CPU time 146.18 seconds
Started Aug 12 04:42:35 PM PDT 24
Finished Aug 12 04:45:01 PM PDT 24
Peak memory 462764 kb
Host smart-1b33e922-60b8-4bca-881e-13f7cc136b87
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2063298602 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_fifo_full_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.i2c_host_fifo_full.2063298602
Directory /workspace/16.i2c_host_fifo_full/latest

Test location /workspace/coverage/default/16.i2c_host_fifo_overflow.1235382979
Short name T1226
Test name
Test status
Simulation time 6503610463 ps
CPU time 46.26 seconds
Started Aug 12 04:42:33 PM PDT 24
Finished Aug 12 04:43:19 PM PDT 24
Peak memory 500832 kb
Host smart-726468e5-5447-48ba-833e-1d4aa285ed75
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1235382979 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_fifo_overflow_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.i2c_host_fifo_overflow.1235382979
Directory /workspace/16.i2c_host_fifo_overflow/latest

Test location /workspace/coverage/default/16.i2c_host_fifo_reset_fmt.3285122766
Short name T1409
Test name
Test status
Simulation time 224173351 ps
CPU time 1.05 seconds
Started Aug 12 04:42:34 PM PDT 24
Finished Aug 12 04:42:36 PM PDT 24
Peak memory 204980 kb
Host smart-83cd4acd-9e8e-451f-878b-a1b1afad4721
User root
Command /workspace/default/simv +test_timeout_ns=10_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3285122766 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_fifo_reset_
fmt_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.i2c_host_fifo_reset_f
mt.3285122766
Directory /workspace/16.i2c_host_fifo_reset_fmt/latest

Test location /workspace/coverage/default/16.i2c_host_fifo_reset_rx.444992123
Short name T574
Test name
Test status
Simulation time 1377972510 ps
CPU time 3.24 seconds
Started Aug 12 04:42:34 PM PDT 24
Finished Aug 12 04:42:37 PM PDT 24
Peak memory 223520 kb
Host smart-318650d0-102d-4602-b69d-871c91c24603
User root
Command /workspace/default/simv +test_timeout_ns=10_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=444992123 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_fifo_reset_r
x_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.i2c_host_fifo_reset_rx.
444992123
Directory /workspace/16.i2c_host_fifo_reset_rx/latest

Test location /workspace/coverage/default/16.i2c_host_fifo_watermark.3379868735
Short name T117
Test name
Test status
Simulation time 4936077357 ps
CPU time 127.2 seconds
Started Aug 12 04:42:32 PM PDT 24
Finished Aug 12 04:44:39 PM PDT 24
Peak memory 1327484 kb
Host smart-2c1e2219-dd0a-462c-a695-63fe133c0920
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3379868735 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_fifo_watermark_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.i2c_host_fifo_watermark.3379868735
Directory /workspace/16.i2c_host_fifo_watermark/latest

Test location /workspace/coverage/default/16.i2c_host_may_nack.1736750366
Short name T266
Test name
Test status
Simulation time 1250637295 ps
CPU time 25.7 seconds
Started Aug 12 04:42:43 PM PDT 24
Finished Aug 12 04:43:09 PM PDT 24
Peak memory 205176 kb
Host smart-f14f362b-045d-4cba-991e-afe48ff1fff9
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1736750366 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_may_nack_vseq +en_cov=1 -cm line+cond+f
sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.i2c_host_may_nack.1736750366
Directory /workspace/16.i2c_host_may_nack/latest

Test location /workspace/coverage/default/16.i2c_host_override.1484488346
Short name T1373
Test name
Test status
Simulation time 66130688 ps
CPU time 0.67 seconds
Started Aug 12 04:42:35 PM PDT 24
Finished Aug 12 04:42:36 PM PDT 24
Peak memory 204916 kb
Host smart-a2d75790-e196-4399-81cc-133cd461d5ed
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1484488346 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_override_vseq +en_cov=1 -cm line+cond+f
sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.i2c_host_override.1484488346
Directory /workspace/16.i2c_host_override/latest

Test location /workspace/coverage/default/16.i2c_host_perf_precise.772259972
Short name T1669
Test name
Test status
Simulation time 7694693470 ps
CPU time 12.59 seconds
Started Aug 12 04:42:33 PM PDT 24
Finished Aug 12 04:42:46 PM PDT 24
Peak memory 329232 kb
Host smart-83690632-f6d6-4917-82d4-9106be396a6c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=772259972 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_perf_precise_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.i2c_host_perf_precise.772259972
Directory /workspace/16.i2c_host_perf_precise/latest

Test location /workspace/coverage/default/16.i2c_host_smoke.3614663698
Short name T1737
Test name
Test status
Simulation time 1565935042 ps
CPU time 29.21 seconds
Started Aug 12 04:42:34 PM PDT 24
Finished Aug 12 04:43:04 PM PDT 24
Peak memory 302616 kb
Host smart-69a5eea3-d4f4-46b5-92bd-62f4853ed343
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3614663698 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_smoke_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.i2c_host_smoke.3614663698
Directory /workspace/16.i2c_host_smoke/latest

Test location /workspace/coverage/default/16.i2c_host_stretch_timeout.1284580093
Short name T428
Test name
Test status
Simulation time 1242528154 ps
CPU time 9.4 seconds
Started Aug 12 04:42:38 PM PDT 24
Finished Aug 12 04:42:47 PM PDT 24
Peak memory 219228 kb
Host smart-13833f66-38b1-4244-be1d-2e7295b5b456
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1284580093 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_stretch_timeout_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.i2c_host_stretch_timeout.1284580093
Directory /workspace/16.i2c_host_stretch_timeout/latest

Test location /workspace/coverage/default/16.i2c_target_bad_addr.2474373608
Short name T1446
Test name
Test status
Simulation time 994293379 ps
CPU time 5.62 seconds
Started Aug 12 04:42:42 PM PDT 24
Finished Aug 12 04:42:48 PM PDT 24
Peak memory 221080 kb
Host smart-bc766f63-d98b-462b-885e-4bb0548ef5c9
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +i2c_bad_addr_pct=50 +cdc_instrumentation_enabled=1 +UVM_
NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2474373608 -assert nopostproc
+UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_target_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.
vdb -cm_log /dev/null -cm_name 16.i2c_target_bad_addr.2474373608
Directory /workspace/16.i2c_target_bad_addr/latest

Test location /workspace/coverage/default/16.i2c_target_fifo_reset_acq.757242960
Short name T948
Test name
Test status
Simulation time 1471608768 ps
CPU time 1.15 seconds
Started Aug 12 04:42:42 PM PDT 24
Finished Aug 12 04:42:43 PM PDT 24
Peak memory 205388 kb
Host smart-ef7407ce-d32c-4d95-9a10-80f345ef7f77
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=757242960 -assert nopostproc +UVM_TESTNAME=i2c_base
_test +UVM_TEST_SEQ=i2c_target_fifo_reset_acq_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /
dev/null -cm_name 16.i2c_target_fifo_reset_acq.757242960
Directory /workspace/16.i2c_target_fifo_reset_acq/latest

Test location /workspace/coverage/default/16.i2c_target_fifo_reset_tx.120004588
Short name T956
Test name
Test status
Simulation time 500051112 ps
CPU time 1.03 seconds
Started Aug 12 04:42:42 PM PDT 24
Finished Aug 12 04:42:43 PM PDT 24
Peak memory 205532 kb
Host smart-96cbc968-99e2-426a-b80f-59536620921c
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=120004588 -assert nopostproc +UVM_TESTNAME=i2c_base
_test +UVM_TEST_SEQ=i2c_target_fifo_reset_tx_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /d
ev/null -cm_name 16.i2c_target_fifo_reset_tx.120004588
Directory /workspace/16.i2c_target_fifo_reset_tx/latest

Test location /workspace/coverage/default/16.i2c_target_fifo_watermarks_acq.209112412
Short name T1573
Test name
Test status
Simulation time 857127445 ps
CPU time 2.63 seconds
Started Aug 12 04:42:41 PM PDT 24
Finished Aug 12 04:42:43 PM PDT 24
Peak memory 205484 kb
Host smart-a63d6fae-41ac-4a87-b80e-036684616971
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=209112412 -assert nopostproc +UVM_TESTNAME=i2c_base
_test +UVM_TEST_SEQ=i2c_target_fifo_watermarks_acq_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_
log /dev/null -cm_name 16.i2c_target_fifo_watermarks_acq.209112412
Directory /workspace/16.i2c_target_fifo_watermarks_acq/latest

Test location /workspace/coverage/default/16.i2c_target_fifo_watermarks_tx.3959861662
Short name T1444
Test name
Test status
Simulation time 345361940 ps
CPU time 1.13 seconds
Started Aug 12 04:42:43 PM PDT 24
Finished Aug 12 04:42:44 PM PDT 24
Peak memory 205228 kb
Host smart-e7dfa846-2e48-4881-82f1-603d0ced273d
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3959861662 -assert nopostproc +UVM_TESTNAME=i2c_bas
e_test +UVM_TEST_SEQ=i2c_target_fifo_watermarks_tx_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_
log /dev/null -cm_name 16.i2c_target_fifo_watermarks_tx.3959861662
Directory /workspace/16.i2c_target_fifo_watermarks_tx/latest

Test location /workspace/coverage/default/16.i2c_target_hrst.4027676176
Short name T1522
Test name
Test status
Simulation time 1472525491 ps
CPU time 2.03 seconds
Started Aug 12 04:42:42 PM PDT 24
Finished Aug 12 04:42:44 PM PDT 24
Peak memory 221804 kb
Host smart-236d9556-5b68-49a0-a969-0715e41b161f
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4027676176 -assert nopostproc +UVM_TESTNAME=i2c_bas
e_test +UVM_TEST_SEQ=i2c_target_hrst_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null
-cm_name 16.i2c_target_hrst.4027676176
Directory /workspace/16.i2c_target_hrst/latest

Test location /workspace/coverage/default/16.i2c_target_intr_smoke.1177783253
Short name T817
Test name
Test status
Simulation time 1958945145 ps
CPU time 6.58 seconds
Started Aug 12 04:42:33 PM PDT 24
Finished Aug 12 04:42:40 PM PDT 24
Peak memory 219080 kb
Host smart-3680fb3d-a5a2-492f-adcf-482b20605962
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=200_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VER
BOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1177783253 -assert nopostproc +UVM_TESTNAME=i2c_ba
se_test +UVM_TEST_SEQ=i2c_target_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/nul
l -cm_name 16.i2c_target_intr_smoke.1177783253
Directory /workspace/16.i2c_target_intr_smoke/latest

Test location /workspace/coverage/default/16.i2c_target_intr_stress_wr.4197616027
Short name T1504
Test name
Test status
Simulation time 8267227922 ps
CPU time 42.05 seconds
Started Aug 12 04:42:34 PM PDT 24
Finished Aug 12 04:43:16 PM PDT 24
Peak memory 1117396 kb
Host smart-a15f3354-6675-459c-867c-05a2eb69f0d6
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=600_000_000 +use_intr_handler=1 +slow_acq=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNO
TES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4197616027 -assert nopostproc +UVM_TES
TNAME=i2c_base_test +UVM_TEST_SEQ=i2c_target_stress_wr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb
-cm_log /dev/null -cm_name 16.i2c_target_intr_stress_wr.4197616027
Directory /workspace/16.i2c_target_intr_stress_wr/latest

Test location /workspace/coverage/default/16.i2c_target_nack_acqfull.517124994
Short name T1182
Test name
Test status
Simulation time 2391523058 ps
CPU time 3.08 seconds
Started Aug 12 04:42:43 PM PDT 24
Finished Aug 12 04:42:47 PM PDT 24
Peak memory 213768 kb
Host smart-695afdc2-9597-45f7-9b00-4929352ecb45
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=517124994 -assert nopostproc +UVM_TESTNAME=i2c_base
_test +UVM_TEST_SEQ=i2c_target_nack_acqfull_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /de
v/null -cm_name 16.i2c_target_nack_acqfull.517124994
Directory /workspace/16.i2c_target_nack_acqfull/latest

Test location /workspace/coverage/default/16.i2c_target_nack_acqfull_addr.2045566240
Short name T1566
Test name
Test status
Simulation time 7216370181 ps
CPU time 2.5 seconds
Started Aug 12 04:42:48 PM PDT 24
Finished Aug 12 04:42:50 PM PDT 24
Peak memory 205480 kb
Host smart-1e53f06d-be56-4e9a-bbb8-70c9b7983868
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2045566240 -assert nopostproc +UVM_TESTNAME=i2c_bas
e_test +UVM_TEST_SEQ=i2c_target_nack_acqfull_addr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_l
og /dev/null -cm_name 16.i2c_target_nack_acqfull_addr.2045566240
Directory /workspace/16.i2c_target_nack_acqfull_addr/latest

Test location /workspace/coverage/default/16.i2c_target_nack_txstretch.1430081290
Short name T179
Test name
Test status
Simulation time 141756276 ps
CPU time 1.53 seconds
Started Aug 12 04:42:41 PM PDT 24
Finished Aug 12 04:42:43 PM PDT 24
Peak memory 222128 kb
Host smart-286e56ec-b9a3-417d-a94f-d4d2fd57a42e
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1430081290 -assert nopostproc +UVM_TESTNAME=i2c_bas
e_test +UVM_TEST_SEQ=i2c_target_nack_txstretch_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log
/dev/null -cm_name 16.i2c_target_nack_txstretch.1430081290
Directory /workspace/16.i2c_target_nack_txstretch/latest

Test location /workspace/coverage/default/16.i2c_target_perf.2456986490
Short name T487
Test name
Test status
Simulation time 1132062399 ps
CPU time 3.83 seconds
Started Aug 12 04:42:43 PM PDT 24
Finished Aug 12 04:42:47 PM PDT 24
Peak memory 213680 kb
Host smart-1d5d3683-4f43-4661-8706-d253c861a80b
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2456986490 -assert nopostproc +UVM_TESTNAME=i2c_bas
e_test +UVM_TEST_SEQ=i2c_target_perf_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null
-cm_name 16.i2c_target_perf.2456986490
Directory /workspace/16.i2c_target_perf/latest

Test location /workspace/coverage/default/16.i2c_target_smbus_maxlen.183678457
Short name T1480
Test name
Test status
Simulation time 2282768050 ps
CPU time 2.35 seconds
Started Aug 12 04:42:41 PM PDT 24
Finished Aug 12 04:42:44 PM PDT 24
Peak memory 205300 kb
Host smart-c4836799-fc92-44a6-8011-a5e6f47d4361
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=183678457 -assert nopostproc +UVM_TESTNAME=i2c_base
_test +UVM_TEST_SEQ=i2c_target_smbus_maxlen_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /de
v/null -cm_name 16.i2c_target_smbus_maxlen.183678457
Directory /workspace/16.i2c_target_smbus_maxlen/latest

Test location /workspace/coverage/default/16.i2c_target_smoke.2819579644
Short name T90
Test name
Test status
Simulation time 5245532348 ps
CPU time 15.69 seconds
Started Aug 12 04:42:34 PM PDT 24
Finished Aug 12 04:42:50 PM PDT 24
Peak memory 213808 kb
Host smart-511f3269-6420-498d-809a-8d4e834aaa16
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=100_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licq
ueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2819579644 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SE
Q=i2c_target_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.i2c_ta
rget_smoke.2819579644
Directory /workspace/16.i2c_target_smoke/latest

Test location /workspace/coverage/default/16.i2c_target_stress_all.2440531533
Short name T441
Test name
Test status
Simulation time 4694439851 ps
CPU time 24.39 seconds
Started Aug 12 04:42:48 PM PDT 24
Finished Aug 12 04:43:12 PM PDT 24
Peak memory 233852 kb
Host smart-fd5ff6fe-a10d-466e-834b-b3df631fe70c
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=300_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VER
BOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2440531533 -assert nopostproc +UVM_TESTNAME=i2c_ba
se_test +UVM_TEST_SEQ=i2c_target_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /de
v/null -cm_name 16.i2c_target_stress_all.2440531533
Directory /workspace/16.i2c_target_stress_all/latest

Test location /workspace/coverage/default/16.i2c_target_stress_rd.1146957074
Short name T1032
Test name
Test status
Simulation time 2071789806 ps
CPU time 24.53 seconds
Started Aug 12 04:42:36 PM PDT 24
Finished Aug 12 04:43:01 PM PDT 24
Peak memory 232768 kb
Host smart-1e871fdb-46a6-47d1-bb2e-8d2aa9775fb8
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=100_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licq
ueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1146957074 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SE
Q=i2c_target_stress_rd_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.i2
c_target_stress_rd.1146957074
Directory /workspace/16.i2c_target_stress_rd/latest

Test location /workspace/coverage/default/16.i2c_target_stress_wr.3290638658
Short name T963
Test name
Test status
Simulation time 63514011890 ps
CPU time 3094.91 seconds
Started Aug 12 04:42:34 PM PDT 24
Finished Aug 12 05:34:10 PM PDT 24
Peak memory 10878516 kb
Host smart-63e57230-cffc-45c5-b110-56a224af4b04
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=600_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licq
ueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3290638658 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SE
Q=i2c_target_stress_wr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.i2
c_target_stress_wr.3290638658
Directory /workspace/16.i2c_target_stress_wr/latest

Test location /workspace/coverage/default/16.i2c_target_stretch.1536721039
Short name T1606
Test name
Test status
Simulation time 1045593965 ps
CPU time 4.18 seconds
Started Aug 12 04:42:32 PM PDT 24
Finished Aug 12 04:42:37 PM PDT 24
Peak memory 217352 kb
Host smart-0fc01409-5946-47d0-9244-d782095ff91e
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=400_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licq
ueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1536721039 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SE
Q=i2c_target_stretch_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.i2c_
target_stretch.1536721039
Directory /workspace/16.i2c_target_stretch/latest

Test location /workspace/coverage/default/16.i2c_target_timeout.3761237399
Short name T1557
Test name
Test status
Simulation time 2946588733 ps
CPU time 6.89 seconds
Started Aug 12 04:42:38 PM PDT 24
Finished Aug 12 04:42:45 PM PDT 24
Peak memory 213664 kb
Host smart-ecdbb276-c3f3-42b9-a95a-bc41033e8193
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=50_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3761237399 -assert nopostproc +UVM_TESTNAME=i2c_bas
e_test +UVM_TEST_SEQ=i2c_target_timeout_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/nu
ll -cm_name 16.i2c_target_timeout.3761237399
Directory /workspace/16.i2c_target_timeout/latest

Test location /workspace/coverage/default/16.i2c_target_tx_stretch_ctrl.4248996172
Short name T1227
Test name
Test status
Simulation time 139692059 ps
CPU time 3.17 seconds
Started Aug 12 04:42:43 PM PDT 24
Finished Aug 12 04:42:46 PM PDT 24
Peak memory 206264 kb
Host smart-e90a23da-49d9-4e87-9b06-b7f08699d8e2
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4248996172 -assert nopostproc +UVM_TESTNAME=i2c_bas
e_test +UVM_TEST_SEQ=i2c_target_tx_stretch_ctrl_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log
/dev/null -cm_name 16.i2c_target_tx_stretch_ctrl.4248996172
Directory /workspace/16.i2c_target_tx_stretch_ctrl/latest

Test location /workspace/coverage/default/17.i2c_alert_test.2381168080
Short name T1192
Test name
Test status
Simulation time 18340059 ps
CPU time 0.63 seconds
Started Aug 12 04:42:49 PM PDT 24
Finished Aug 12 04:42:50 PM PDT 24
Peak memory 204300 kb
Host smart-a8c73703-9544-4fe9-9ad7-fa1102a9959c
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2381168080 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_common_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.i2c_alert_test.2381168080
Directory /workspace/17.i2c_alert_test/latest

Test location /workspace/coverage/default/17.i2c_host_error_intr.3887092507
Short name T29
Test name
Test status
Simulation time 973141064 ps
CPU time 4.54 seconds
Started Aug 12 04:42:46 PM PDT 24
Finished Aug 12 04:42:51 PM PDT 24
Peak memory 229644 kb
Host smart-cb8e0286-60ab-4a73-b25b-67826051c592
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3887092507 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_error_intr_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.i2c_host_error_intr.3887092507
Directory /workspace/17.i2c_host_error_intr/latest

Test location /workspace/coverage/default/17.i2c_host_fifo_fmt_empty.2667426540
Short name T804
Test name
Test status
Simulation time 6008964883 ps
CPU time 19.28 seconds
Started Aug 12 04:42:44 PM PDT 24
Finished Aug 12 04:43:03 PM PDT 24
Peak memory 284128 kb
Host smart-3b7d8923-bc47-4e48-8877-3b0300c580d0
User root
Command /workspace/default/simv +test_timeout_ns=10_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2667426540 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_fifo_fmt_em
pty_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.i2c_host_fifo_fmt_emp
ty.2667426540
Directory /workspace/17.i2c_host_fifo_fmt_empty/latest

Test location /workspace/coverage/default/17.i2c_host_fifo_full.2252711427
Short name T1296
Test name
Test status
Simulation time 2028350992 ps
CPU time 114.1 seconds
Started Aug 12 04:42:43 PM PDT 24
Finished Aug 12 04:44:37 PM PDT 24
Peak memory 436804 kb
Host smart-9fec3e8a-4d38-4552-98b2-c2a3039ad43a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2252711427 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_fifo_full_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.i2c_host_fifo_full.2252711427
Directory /workspace/17.i2c_host_fifo_full/latest

Test location /workspace/coverage/default/17.i2c_host_fifo_overflow.1194345224
Short name T1074
Test name
Test status
Simulation time 4895215316 ps
CPU time 197.41 seconds
Started Aug 12 04:42:43 PM PDT 24
Finished Aug 12 04:46:01 PM PDT 24
Peak memory 793276 kb
Host smart-fd71ffbb-3632-4ec3-b6c2-85d9689d9851
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1194345224 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_fifo_overflow_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.i2c_host_fifo_overflow.1194345224
Directory /workspace/17.i2c_host_fifo_overflow/latest

Test location /workspace/coverage/default/17.i2c_host_fifo_reset_fmt.3159278950
Short name T1726
Test name
Test status
Simulation time 251907547 ps
CPU time 1.37 seconds
Started Aug 12 04:42:44 PM PDT 24
Finished Aug 12 04:42:45 PM PDT 24
Peak memory 205116 kb
Host smart-d9ed4c03-ae04-4da8-b334-b6ce497863de
User root
Command /workspace/default/simv +test_timeout_ns=10_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3159278950 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_fifo_reset_
fmt_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.i2c_host_fifo_reset_f
mt.3159278950
Directory /workspace/17.i2c_host_fifo_reset_fmt/latest

Test location /workspace/coverage/default/17.i2c_host_fifo_reset_rx.1967402345
Short name T1323
Test name
Test status
Simulation time 394131219 ps
CPU time 7.16 seconds
Started Aug 12 04:42:42 PM PDT 24
Finished Aug 12 04:42:49 PM PDT 24
Peak memory 257964 kb
Host smart-94efab34-11d6-4377-947f-d93784decaea
User root
Command /workspace/default/simv +test_timeout_ns=10_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1967402345 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_fifo_reset_
rx_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.i2c_host_fifo_reset_rx
.1967402345
Directory /workspace/17.i2c_host_fifo_reset_rx/latest

Test location /workspace/coverage/default/17.i2c_host_fifo_watermark.4187996006
Short name T638
Test name
Test status
Simulation time 4281043634 ps
CPU time 315.93 seconds
Started Aug 12 04:42:42 PM PDT 24
Finished Aug 12 04:47:58 PM PDT 24
Peak memory 1271548 kb
Host smart-270a758f-2d02-4940-b60c-5b4c320d60f1
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4187996006 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_fifo_watermark_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.i2c_host_fifo_watermark.4187996006
Directory /workspace/17.i2c_host_fifo_watermark/latest

Test location /workspace/coverage/default/17.i2c_host_may_nack.1308012313
Short name T259
Test name
Test status
Simulation time 455153604 ps
CPU time 5.39 seconds
Started Aug 12 04:42:50 PM PDT 24
Finished Aug 12 04:42:55 PM PDT 24
Peak memory 205256 kb
Host smart-d6bff409-20fa-47ad-b045-c46b60f64df0
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1308012313 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_may_nack_vseq +en_cov=1 -cm line+cond+f
sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.i2c_host_may_nack.1308012313
Directory /workspace/17.i2c_host_may_nack/latest

Test location /workspace/coverage/default/17.i2c_host_override.3713298600
Short name T905
Test name
Test status
Simulation time 103147035 ps
CPU time 0.69 seconds
Started Aug 12 04:42:40 PM PDT 24
Finished Aug 12 04:42:41 PM PDT 24
Peak memory 204884 kb
Host smart-caabb7d7-dfa2-46e1-ac53-dc3cdfd80db4
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3713298600 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_override_vseq +en_cov=1 -cm line+cond+f
sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.i2c_host_override.3713298600
Directory /workspace/17.i2c_host_override/latest

Test location /workspace/coverage/default/17.i2c_host_perf.3782791814
Short name T463
Test name
Test status
Simulation time 47591375780 ps
CPU time 237.09 seconds
Started Aug 12 04:42:42 PM PDT 24
Finished Aug 12 04:46:40 PM PDT 24
Peak memory 235992 kb
Host smart-bb402ead-df9e-4371-aed4-0006ac7b57d0
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3782791814 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_perf_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.i2c_host_perf.3782791814
Directory /workspace/17.i2c_host_perf/latest

Test location /workspace/coverage/default/17.i2c_host_perf_precise.3111185751
Short name T1484
Test name
Test status
Simulation time 236554749 ps
CPU time 4 seconds
Started Aug 12 04:42:40 PM PDT 24
Finished Aug 12 04:42:44 PM PDT 24
Peak memory 205176 kb
Host smart-fc93da75-75e6-43d5-8688-1495ad59c4a0
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3111185751 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_perf_precise_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.i2c_host_perf_precise.3111185751
Directory /workspace/17.i2c_host_perf_precise/latest

Test location /workspace/coverage/default/17.i2c_host_smoke.3998029484
Short name T930
Test name
Test status
Simulation time 4629423257 ps
CPU time 58.27 seconds
Started Aug 12 04:42:43 PM PDT 24
Finished Aug 12 04:43:42 PM PDT 24
Peak memory 318876 kb
Host smart-42be6271-0a01-4094-b025-e67a3951d5ed
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3998029484 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_smoke_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.i2c_host_smoke.3998029484
Directory /workspace/17.i2c_host_smoke/latest

Test location /workspace/coverage/default/17.i2c_host_stretch_timeout.3334052897
Short name T791
Test name
Test status
Simulation time 663033004 ps
CPU time 10.41 seconds
Started Aug 12 04:42:43 PM PDT 24
Finished Aug 12 04:42:53 PM PDT 24
Peak memory 221604 kb
Host smart-476d7111-d052-4b08-a247-a65411cac02a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3334052897 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_stretch_timeout_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.i2c_host_stretch_timeout.3334052897
Directory /workspace/17.i2c_host_stretch_timeout/latest

Test location /workspace/coverage/default/17.i2c_target_bad_addr.1484556896
Short name T1563
Test name
Test status
Simulation time 1546801518 ps
CPU time 4.12 seconds
Started Aug 12 04:42:51 PM PDT 24
Finished Aug 12 04:42:56 PM PDT 24
Peak memory 214008 kb
Host smart-3827c59d-9a19-433d-bef4-0836a95d7694
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +i2c_bad_addr_pct=50 +cdc_instrumentation_enabled=1 +UVM_
NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1484556896 -assert nopostproc
+UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_target_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.
vdb -cm_log /dev/null -cm_name 17.i2c_target_bad_addr.1484556896
Directory /workspace/17.i2c_target_bad_addr/latest

Test location /workspace/coverage/default/17.i2c_target_fifo_reset_acq.54626820
Short name T663
Test name
Test status
Simulation time 938466589 ps
CPU time 1.36 seconds
Started Aug 12 04:42:45 PM PDT 24
Finished Aug 12 04:42:47 PM PDT 24
Peak memory 205496 kb
Host smart-13aa3ea3-e34c-4260-8de8-c0f733dc868a
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=54626820 -assert nopostproc +UVM_TESTNAME=i2c_base_
test +UVM_TEST_SEQ=i2c_target_fifo_reset_acq_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /d
ev/null -cm_name 17.i2c_target_fifo_reset_acq.54626820
Directory /workspace/17.i2c_target_fifo_reset_acq/latest

Test location /workspace/coverage/default/17.i2c_target_fifo_reset_tx.1082645898
Short name T1179
Test name
Test status
Simulation time 126852494 ps
CPU time 0.81 seconds
Started Aug 12 04:42:42 PM PDT 24
Finished Aug 12 04:42:43 PM PDT 24
Peak memory 205212 kb
Host smart-0fbbec9a-ac63-4b06-a52a-62a143b45ea3
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1082645898 -assert nopostproc +UVM_TESTNAME=i2c_bas
e_test +UVM_TEST_SEQ=i2c_target_fifo_reset_tx_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /
dev/null -cm_name 17.i2c_target_fifo_reset_tx.1082645898
Directory /workspace/17.i2c_target_fifo_reset_tx/latest

Test location /workspace/coverage/default/17.i2c_target_fifo_watermarks_acq.329918179
Short name T529
Test name
Test status
Simulation time 1948868739 ps
CPU time 2.85 seconds
Started Aug 12 04:42:50 PM PDT 24
Finished Aug 12 04:42:53 PM PDT 24
Peak memory 205476 kb
Host smart-83685094-8c2b-4549-87f0-02d3137355ec
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=329918179 -assert nopostproc +UVM_TESTNAME=i2c_base
_test +UVM_TEST_SEQ=i2c_target_fifo_watermarks_acq_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_
log /dev/null -cm_name 17.i2c_target_fifo_watermarks_acq.329918179
Directory /workspace/17.i2c_target_fifo_watermarks_acq/latest

Test location /workspace/coverage/default/17.i2c_target_fifo_watermarks_tx.1494389419
Short name T1010
Test name
Test status
Simulation time 243567583 ps
CPU time 1.35 seconds
Started Aug 12 04:42:49 PM PDT 24
Finished Aug 12 04:42:51 PM PDT 24
Peak memory 205280 kb
Host smart-ef7e08c1-31fc-4918-bc40-f2bcec8707ee
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1494389419 -assert nopostproc +UVM_TESTNAME=i2c_bas
e_test +UVM_TEST_SEQ=i2c_target_fifo_watermarks_tx_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_
log /dev/null -cm_name 17.i2c_target_fifo_watermarks_tx.1494389419
Directory /workspace/17.i2c_target_fifo_watermarks_tx/latest

Test location /workspace/coverage/default/17.i2c_target_hrst.1516016801
Short name T511
Test name
Test status
Simulation time 530212041 ps
CPU time 1.89 seconds
Started Aug 12 04:42:55 PM PDT 24
Finished Aug 12 04:42:57 PM PDT 24
Peak memory 205444 kb
Host smart-1a606ffb-aafd-4eb7-9ed8-d47a56ada701
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1516016801 -assert nopostproc +UVM_TESTNAME=i2c_bas
e_test +UVM_TEST_SEQ=i2c_target_hrst_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null
-cm_name 17.i2c_target_hrst.1516016801
Directory /workspace/17.i2c_target_hrst/latest

Test location /workspace/coverage/default/17.i2c_target_intr_smoke.2518419234
Short name T1622
Test name
Test status
Simulation time 8385087147 ps
CPU time 5.61 seconds
Started Aug 12 04:42:41 PM PDT 24
Finished Aug 12 04:42:47 PM PDT 24
Peak memory 217956 kb
Host smart-d45b112c-dfd6-4f6b-8eb2-a8c713f3cabd
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=200_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VER
BOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2518419234 -assert nopostproc +UVM_TESTNAME=i2c_ba
se_test +UVM_TEST_SEQ=i2c_target_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/nul
l -cm_name 17.i2c_target_intr_smoke.2518419234
Directory /workspace/17.i2c_target_intr_smoke/latest

Test location /workspace/coverage/default/17.i2c_target_intr_stress_wr.1006874006
Short name T1385
Test name
Test status
Simulation time 8640130727 ps
CPU time 17.98 seconds
Started Aug 12 04:42:40 PM PDT 24
Finished Aug 12 04:42:58 PM PDT 24
Peak memory 618792 kb
Host smart-3e94f8cb-04ed-455d-a00f-9b5485f7d30a
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=600_000_000 +use_intr_handler=1 +slow_acq=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNO
TES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1006874006 -assert nopostproc +UVM_TES
TNAME=i2c_base_test +UVM_TEST_SEQ=i2c_target_stress_wr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb
-cm_log /dev/null -cm_name 17.i2c_target_intr_stress_wr.1006874006
Directory /workspace/17.i2c_target_intr_stress_wr/latest

Test location /workspace/coverage/default/17.i2c_target_nack_acqfull.1776446475
Short name T1633
Test name
Test status
Simulation time 883717058 ps
CPU time 2.84 seconds
Started Aug 12 04:42:51 PM PDT 24
Finished Aug 12 04:42:54 PM PDT 24
Peak memory 213656 kb
Host smart-46317eed-1e75-44ce-9dd7-4a5d71f85298
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1776446475 -assert nopostproc +UVM_TESTNAME=i2c_bas
e_test +UVM_TEST_SEQ=i2c_target_nack_acqfull_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /d
ev/null -cm_name 17.i2c_target_nack_acqfull.1776446475
Directory /workspace/17.i2c_target_nack_acqfull/latest

Test location /workspace/coverage/default/17.i2c_target_nack_acqfull_addr.617572921
Short name T1274
Test name
Test status
Simulation time 2049273725 ps
CPU time 2.64 seconds
Started Aug 12 04:42:50 PM PDT 24
Finished Aug 12 04:42:53 PM PDT 24
Peak memory 205444 kb
Host smart-0d86ce81-7a4e-415c-87ca-9eae7da3e4d3
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=617572921 -assert nopostproc +UVM_TESTNAME=i2c_base
_test +UVM_TEST_SEQ=i2c_target_nack_acqfull_addr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_lo
g /dev/null -cm_name 17.i2c_target_nack_acqfull_addr.617572921
Directory /workspace/17.i2c_target_nack_acqfull_addr/latest

Test location /workspace/coverage/default/17.i2c_target_nack_txstretch.2644674296
Short name T1743
Test name
Test status
Simulation time 2252269575 ps
CPU time 1.41 seconds
Started Aug 12 04:42:51 PM PDT 24
Finished Aug 12 04:42:52 PM PDT 24
Peak memory 222072 kb
Host smart-cf6f8661-8f88-438f-af16-2f8b9b094080
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2644674296 -assert nopostproc +UVM_TESTNAME=i2c_bas
e_test +UVM_TEST_SEQ=i2c_target_nack_txstretch_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log
/dev/null -cm_name 17.i2c_target_nack_txstretch.2644674296
Directory /workspace/17.i2c_target_nack_txstretch/latest

Test location /workspace/coverage/default/17.i2c_target_perf.3975987049
Short name T1531
Test name
Test status
Simulation time 1440732049 ps
CPU time 5.27 seconds
Started Aug 12 04:42:40 PM PDT 24
Finished Aug 12 04:42:45 PM PDT 24
Peak memory 218860 kb
Host smart-d93749ef-8085-4799-8d99-7d57ffccbb6a
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3975987049 -assert nopostproc +UVM_TESTNAME=i2c_bas
e_test +UVM_TEST_SEQ=i2c_target_perf_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null
-cm_name 17.i2c_target_perf.3975987049
Directory /workspace/17.i2c_target_perf/latest

Test location /workspace/coverage/default/17.i2c_target_smbus_maxlen.1725473195
Short name T1413
Test name
Test status
Simulation time 553934502 ps
CPU time 2.6 seconds
Started Aug 12 04:42:49 PM PDT 24
Finished Aug 12 04:42:52 PM PDT 24
Peak memory 205248 kb
Host smart-a97a1579-77b2-4587-a9a4-fdea77304c46
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1725473195 -assert nopostproc +UVM_TESTNAME=i2c_bas
e_test +UVM_TEST_SEQ=i2c_target_smbus_maxlen_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /d
ev/null -cm_name 17.i2c_target_smbus_maxlen.1725473195
Directory /workspace/17.i2c_target_smbus_maxlen/latest

Test location /workspace/coverage/default/17.i2c_target_smoke.1475417253
Short name T1412
Test name
Test status
Simulation time 3980119067 ps
CPU time 15.32 seconds
Started Aug 12 04:42:41 PM PDT 24
Finished Aug 12 04:42:57 PM PDT 24
Peak memory 214000 kb
Host smart-81e180d6-b5cb-462a-a5bb-683b6fd578ce
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=100_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licq
ueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1475417253 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SE
Q=i2c_target_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.i2c_ta
rget_smoke.1475417253
Directory /workspace/17.i2c_target_smoke/latest

Test location /workspace/coverage/default/17.i2c_target_stress_all.3751047239
Short name T1653
Test name
Test status
Simulation time 25956523525 ps
CPU time 376.78 seconds
Started Aug 12 04:42:42 PM PDT 24
Finished Aug 12 04:48:59 PM PDT 24
Peak memory 3296152 kb
Host smart-77080b10-1ab1-4aa9-909d-2e711564e11a
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=300_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VER
BOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3751047239 -assert nopostproc +UVM_TESTNAME=i2c_ba
se_test +UVM_TEST_SEQ=i2c_target_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /de
v/null -cm_name 17.i2c_target_stress_all.3751047239
Directory /workspace/17.i2c_target_stress_all/latest

Test location /workspace/coverage/default/17.i2c_target_stress_rd.303245916
Short name T502
Test name
Test status
Simulation time 1541227123 ps
CPU time 70.75 seconds
Started Aug 12 04:42:43 PM PDT 24
Finished Aug 12 04:43:54 PM PDT 24
Peak memory 217500 kb
Host smart-22ce5072-969c-4efb-875e-0559a31a721c
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=100_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licq
ueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=303245916 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ
=i2c_target_stress_rd_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.i2c
_target_stress_rd.303245916
Directory /workspace/17.i2c_target_stress_rd/latest

Test location /workspace/coverage/default/17.i2c_target_stress_wr.830175901
Short name T1092
Test name
Test status
Simulation time 18926722414 ps
CPU time 6.39 seconds
Started Aug 12 04:42:43 PM PDT 24
Finished Aug 12 04:42:49 PM PDT 24
Peak memory 205524 kb
Host smart-99b02272-5ce2-4206-b407-228f4d0a5733
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=600_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licq
ueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=830175901 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ
=i2c_target_stress_wr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.i2c
_target_stress_wr.830175901
Directory /workspace/17.i2c_target_stress_wr/latest

Test location /workspace/coverage/default/17.i2c_target_stretch.1845020256
Short name T4
Test name
Test status
Simulation time 1575879857 ps
CPU time 6.7 seconds
Started Aug 12 04:42:43 PM PDT 24
Finished Aug 12 04:42:49 PM PDT 24
Peak memory 274016 kb
Host smart-97010351-f668-4a07-a53a-e96341f958b6
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=400_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licq
ueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1845020256 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SE
Q=i2c_target_stretch_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.i2c_
target_stretch.1845020256
Directory /workspace/17.i2c_target_stretch/latest

Test location /workspace/coverage/default/17.i2c_target_timeout.3786197155
Short name T1523
Test name
Test status
Simulation time 4635413327 ps
CPU time 6.32 seconds
Started Aug 12 04:42:42 PM PDT 24
Finished Aug 12 04:42:48 PM PDT 24
Peak memory 213744 kb
Host smart-d58f5d0a-92c9-4523-a808-1ff90b7abf6d
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=50_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3786197155 -assert nopostproc +UVM_TESTNAME=i2c_bas
e_test +UVM_TEST_SEQ=i2c_target_timeout_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/nu
ll -cm_name 17.i2c_target_timeout.3786197155
Directory /workspace/17.i2c_target_timeout/latest

Test location /workspace/coverage/default/17.i2c_target_tx_stretch_ctrl.2058253008
Short name T1099
Test name
Test status
Simulation time 282142064 ps
CPU time 5.09 seconds
Started Aug 12 04:42:51 PM PDT 24
Finished Aug 12 04:42:56 PM PDT 24
Peak memory 205592 kb
Host smart-05a47b7c-7098-49a6-bec6-7bacdb226336
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2058253008 -assert nopostproc +UVM_TESTNAME=i2c_bas
e_test +UVM_TEST_SEQ=i2c_target_tx_stretch_ctrl_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log
/dev/null -cm_name 17.i2c_target_tx_stretch_ctrl.2058253008
Directory /workspace/17.i2c_target_tx_stretch_ctrl/latest

Test location /workspace/coverage/default/18.i2c_alert_test.704191880
Short name T722
Test name
Test status
Simulation time 21516284 ps
CPU time 0.64 seconds
Started Aug 12 04:42:58 PM PDT 24
Finished Aug 12 04:42:59 PM PDT 24
Peak memory 204852 kb
Host smart-635385e8-e47f-46fe-8270-e38959607633
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=704191880 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_common_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.i2c_alert_test.704191880
Directory /workspace/18.i2c_alert_test/latest

Test location /workspace/coverage/default/18.i2c_host_error_intr.1757496193
Short name T1042
Test name
Test status
Simulation time 242045156 ps
CPU time 2.44 seconds
Started Aug 12 04:42:49 PM PDT 24
Finished Aug 12 04:42:52 PM PDT 24
Peak memory 213460 kb
Host smart-f693c3ef-53a8-47b0-9b65-623bb0bd1e53
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1757496193 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_error_intr_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.i2c_host_error_intr.1757496193
Directory /workspace/18.i2c_host_error_intr/latest

Test location /workspace/coverage/default/18.i2c_host_fifo_fmt_empty.932618335
Short name T1592
Test name
Test status
Simulation time 636128172 ps
CPU time 7 seconds
Started Aug 12 04:42:49 PM PDT 24
Finished Aug 12 04:42:57 PM PDT 24
Peak memory 273664 kb
Host smart-37144d5e-2103-431c-b718-3786b504cbed
User root
Command /workspace/default/simv +test_timeout_ns=10_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=932618335 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_fifo_fmt_emp
ty_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.i2c_host_fifo_fmt_empt
y.932618335
Directory /workspace/18.i2c_host_fifo_fmt_empty/latest

Test location /workspace/coverage/default/18.i2c_host_fifo_full.4203047720
Short name T1325
Test name
Test status
Simulation time 50900178321 ps
CPU time 124.86 seconds
Started Aug 12 04:42:49 PM PDT 24
Finished Aug 12 04:44:54 PM PDT 24
Peak memory 783256 kb
Host smart-5499f03e-91b6-4732-a6c3-1ca615dfd8a3
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4203047720 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_fifo_full_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.i2c_host_fifo_full.4203047720
Directory /workspace/18.i2c_host_fifo_full/latest

Test location /workspace/coverage/default/18.i2c_host_fifo_overflow.2923316531
Short name T1037
Test name
Test status
Simulation time 6047132322 ps
CPU time 45.84 seconds
Started Aug 12 04:42:55 PM PDT 24
Finished Aug 12 04:43:41 PM PDT 24
Peak memory 496952 kb
Host smart-a116f22c-89ae-482c-8e04-4a0395360da2
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2923316531 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_fifo_overflow_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.i2c_host_fifo_overflow.2923316531
Directory /workspace/18.i2c_host_fifo_overflow/latest

Test location /workspace/coverage/default/18.i2c_host_fifo_reset_fmt.2135161785
Short name T603
Test name
Test status
Simulation time 296673437 ps
CPU time 0.95 seconds
Started Aug 12 04:42:49 PM PDT 24
Finished Aug 12 04:42:50 PM PDT 24
Peak memory 204984 kb
Host smart-332723fd-aba2-42b7-ab76-924414a21d73
User root
Command /workspace/default/simv +test_timeout_ns=10_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2135161785 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_fifo_reset_
fmt_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.i2c_host_fifo_reset_f
mt.2135161785
Directory /workspace/18.i2c_host_fifo_reset_fmt/latest

Test location /workspace/coverage/default/18.i2c_host_fifo_reset_rx.922755963
Short name T1650
Test name
Test status
Simulation time 128778201 ps
CPU time 3.89 seconds
Started Aug 12 04:42:49 PM PDT 24
Finished Aug 12 04:42:53 PM PDT 24
Peak memory 225728 kb
Host smart-0b8ae394-c97f-4b93-8d06-8ffba9b3028f
User root
Command /workspace/default/simv +test_timeout_ns=10_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=922755963 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_fifo_reset_r
x_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.i2c_host_fifo_reset_rx.
922755963
Directory /workspace/18.i2c_host_fifo_reset_rx/latest

Test location /workspace/coverage/default/18.i2c_host_fifo_watermark.3067553842
Short name T116
Test name
Test status
Simulation time 37182479360 ps
CPU time 102.42 seconds
Started Aug 12 04:42:53 PM PDT 24
Finished Aug 12 04:44:36 PM PDT 24
Peak memory 1185632 kb
Host smart-746c5dc3-5db3-436d-b268-e30291f4dcda
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3067553842 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_fifo_watermark_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.i2c_host_fifo_watermark.3067553842
Directory /workspace/18.i2c_host_fifo_watermark/latest

Test location /workspace/coverage/default/18.i2c_host_may_nack.2357897689
Short name T1021
Test name
Test status
Simulation time 6001095852 ps
CPU time 8.08 seconds
Started Aug 12 04:42:56 PM PDT 24
Finished Aug 12 04:43:04 PM PDT 24
Peak memory 205192 kb
Host smart-7b105521-64f5-41b9-8b50-b88a8b1da214
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2357897689 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_may_nack_vseq +en_cov=1 -cm line+cond+f
sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.i2c_host_may_nack.2357897689
Directory /workspace/18.i2c_host_may_nack/latest

Test location /workspace/coverage/default/18.i2c_host_override.193280182
Short name T1327
Test name
Test status
Simulation time 30176556 ps
CPU time 0.64 seconds
Started Aug 12 04:42:49 PM PDT 24
Finished Aug 12 04:42:49 PM PDT 24
Peak memory 204900 kb
Host smart-db83617d-e5d1-42c2-b7a6-fe94c2ada19e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=193280182 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_override_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.i2c_host_override.193280182
Directory /workspace/18.i2c_host_override/latest

Test location /workspace/coverage/default/18.i2c_host_perf.1242121736
Short name T612
Test name
Test status
Simulation time 7070340508 ps
CPU time 65.98 seconds
Started Aug 12 04:42:49 PM PDT 24
Finished Aug 12 04:43:55 PM PDT 24
Peak memory 205392 kb
Host smart-183bf032-0255-410c-8372-e32b0c992b47
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1242121736 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_perf_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.i2c_host_perf.1242121736
Directory /workspace/18.i2c_host_perf/latest

Test location /workspace/coverage/default/18.i2c_host_perf_precise.1262830917
Short name T549
Test name
Test status
Simulation time 135315496 ps
CPU time 1.39 seconds
Started Aug 12 04:42:51 PM PDT 24
Finished Aug 12 04:42:52 PM PDT 24
Peak memory 229724 kb
Host smart-40e6213b-5450-43f1-87d3-742d69bd8126
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1262830917 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_perf_precise_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.i2c_host_perf_precise.1262830917
Directory /workspace/18.i2c_host_perf_precise/latest

Test location /workspace/coverage/default/18.i2c_host_smoke.3733756437
Short name T1281
Test name
Test status
Simulation time 6318041873 ps
CPU time 76.48 seconds
Started Aug 12 04:42:51 PM PDT 24
Finished Aug 12 04:44:07 PM PDT 24
Peak memory 366912 kb
Host smart-e58e2c0a-91c2-423d-8aba-7a199bdf9541
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3733756437 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_smoke_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.i2c_host_smoke.3733756437
Directory /workspace/18.i2c_host_smoke/latest

Test location /workspace/coverage/default/18.i2c_host_stress_all.3668383301
Short name T27
Test name
Test status
Simulation time 13788926386 ps
CPU time 671.19 seconds
Started Aug 12 04:42:49 PM PDT 24
Finished Aug 12 04:54:01 PM PDT 24
Peak memory 2040168 kb
Host smart-d375b1dc-db8b-4ffc-9070-8291d60d9092
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3668383301 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_stress_all_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.i2c_host_stress_all.3668383301
Directory /workspace/18.i2c_host_stress_all/latest

Test location /workspace/coverage/default/18.i2c_host_stretch_timeout.460034115
Short name T803
Test name
Test status
Simulation time 2515574431 ps
CPU time 11.44 seconds
Started Aug 12 04:42:51 PM PDT 24
Finished Aug 12 04:43:02 PM PDT 24
Peak memory 229724 kb
Host smart-75e1043c-df39-4224-9bb2-265b8307eeb2
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=460034115 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_stretch_timeout_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.i2c_host_stretch_timeout.460034115
Directory /workspace/18.i2c_host_stretch_timeout/latest

Test location /workspace/coverage/default/18.i2c_target_bad_addr.320896017
Short name T537
Test name
Test status
Simulation time 2664836533 ps
CPU time 5.4 seconds
Started Aug 12 04:42:58 PM PDT 24
Finished Aug 12 04:43:04 PM PDT 24
Peak memory 213752 kb
Host smart-f9a1fc1d-847a-4952-af5e-12f7c109c262
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +i2c_bad_addr_pct=50 +cdc_instrumentation_enabled=1 +UVM_
NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=320896017 -assert nopostproc +
UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_target_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.v
db -cm_log /dev/null -cm_name 18.i2c_target_bad_addr.320896017
Directory /workspace/18.i2c_target_bad_addr/latest

Test location /workspace/coverage/default/18.i2c_target_fifo_reset_acq.350294724
Short name T834
Test name
Test status
Simulation time 251398399 ps
CPU time 1.39 seconds
Started Aug 12 04:42:50 PM PDT 24
Finished Aug 12 04:42:51 PM PDT 24
Peak memory 205276 kb
Host smart-cccb15c8-cf8a-46f4-aa4b-6a5106f7ee1f
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=350294724 -assert nopostproc +UVM_TESTNAME=i2c_base
_test +UVM_TEST_SEQ=i2c_target_fifo_reset_acq_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /
dev/null -cm_name 18.i2c_target_fifo_reset_acq.350294724
Directory /workspace/18.i2c_target_fifo_reset_acq/latest

Test location /workspace/coverage/default/18.i2c_target_fifo_reset_tx.903618720
Short name T396
Test name
Test status
Simulation time 673326758 ps
CPU time 1.26 seconds
Started Aug 12 04:43:05 PM PDT 24
Finished Aug 12 04:43:07 PM PDT 24
Peak memory 213524 kb
Host smart-117a17a6-c7d0-4769-8536-6cb6de1da31c
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=903618720 -assert nopostproc +UVM_TESTNAME=i2c_base
_test +UVM_TEST_SEQ=i2c_target_fifo_reset_tx_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /d
ev/null -cm_name 18.i2c_target_fifo_reset_tx.903618720
Directory /workspace/18.i2c_target_fifo_reset_tx/latest

Test location /workspace/coverage/default/18.i2c_target_fifo_watermarks_acq.2953507280
Short name T1027
Test name
Test status
Simulation time 1376733615 ps
CPU time 3.7 seconds
Started Aug 12 04:42:58 PM PDT 24
Finished Aug 12 04:43:01 PM PDT 24
Peak memory 205436 kb
Host smart-2f9a92c9-70a5-4e65-99fa-7d07268cf355
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2953507280 -assert nopostproc +UVM_TESTNAME=i2c_bas
e_test +UVM_TEST_SEQ=i2c_target_fifo_watermarks_acq_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm
_log /dev/null -cm_name 18.i2c_target_fifo_watermarks_acq.2953507280
Directory /workspace/18.i2c_target_fifo_watermarks_acq/latest

Test location /workspace/coverage/default/18.i2c_target_fifo_watermarks_tx.1301409421
Short name T1302
Test name
Test status
Simulation time 1015543446 ps
CPU time 1.07 seconds
Started Aug 12 04:43:05 PM PDT 24
Finished Aug 12 04:43:06 PM PDT 24
Peak memory 205256 kb
Host smart-76f4d794-fdfb-465e-8fd7-c6c2cc1b84e4
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1301409421 -assert nopostproc +UVM_TESTNAME=i2c_bas
e_test +UVM_TEST_SEQ=i2c_target_fifo_watermarks_tx_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_
log /dev/null -cm_name 18.i2c_target_fifo_watermarks_tx.1301409421
Directory /workspace/18.i2c_target_fifo_watermarks_tx/latest

Test location /workspace/coverage/default/18.i2c_target_intr_smoke.2651905817
Short name T1293
Test name
Test status
Simulation time 802900061 ps
CPU time 4.73 seconds
Started Aug 12 04:42:51 PM PDT 24
Finished Aug 12 04:42:56 PM PDT 24
Peak memory 221796 kb
Host smart-3df49e52-1278-4c63-bc21-65171c401b4d
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=200_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VER
BOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2651905817 -assert nopostproc +UVM_TESTNAME=i2c_ba
se_test +UVM_TEST_SEQ=i2c_target_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/nul
l -cm_name 18.i2c_target_intr_smoke.2651905817
Directory /workspace/18.i2c_target_intr_smoke/latest

Test location /workspace/coverage/default/18.i2c_target_intr_stress_wr.1213374653
Short name T597
Test name
Test status
Simulation time 19907215018 ps
CPU time 19.07 seconds
Started Aug 12 04:42:55 PM PDT 24
Finished Aug 12 04:43:14 PM PDT 24
Peak memory 424244 kb
Host smart-f4663a4d-7016-4e93-bbea-21e3ff6902d5
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=600_000_000 +use_intr_handler=1 +slow_acq=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNO
TES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1213374653 -assert nopostproc +UVM_TES
TNAME=i2c_base_test +UVM_TEST_SEQ=i2c_target_stress_wr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb
-cm_log /dev/null -cm_name 18.i2c_target_intr_stress_wr.1213374653
Directory /workspace/18.i2c_target_intr_stress_wr/latest

Test location /workspace/coverage/default/18.i2c_target_nack_acqfull.3597943965
Short name T1652
Test name
Test status
Simulation time 2152495772 ps
CPU time 2.7 seconds
Started Aug 12 04:43:10 PM PDT 24
Finished Aug 12 04:43:13 PM PDT 24
Peak memory 213760 kb
Host smart-1b0c31fc-014a-4d0a-8ab1-26112d15c81e
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3597943965 -assert nopostproc +UVM_TESTNAME=i2c_bas
e_test +UVM_TEST_SEQ=i2c_target_nack_acqfull_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /d
ev/null -cm_name 18.i2c_target_nack_acqfull.3597943965
Directory /workspace/18.i2c_target_nack_acqfull/latest

Test location /workspace/coverage/default/18.i2c_target_nack_acqfull_addr.1980055909
Short name T1611
Test name
Test status
Simulation time 2109868329 ps
CPU time 2.55 seconds
Started Aug 12 04:42:57 PM PDT 24
Finished Aug 12 04:42:59 PM PDT 24
Peak memory 205560 kb
Host smart-2ac0c794-2267-43a5-bdb3-980f4859f6f7
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1980055909 -assert nopostproc +UVM_TESTNAME=i2c_bas
e_test +UVM_TEST_SEQ=i2c_target_nack_acqfull_addr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_l
og /dev/null -cm_name 18.i2c_target_nack_acqfull_addr.1980055909
Directory /workspace/18.i2c_target_nack_acqfull_addr/latest

Test location /workspace/coverage/default/18.i2c_target_nack_txstretch.981327738
Short name T1442
Test name
Test status
Simulation time 158550485 ps
CPU time 1.37 seconds
Started Aug 12 04:43:06 PM PDT 24
Finished Aug 12 04:43:07 PM PDT 24
Peak memory 222372 kb
Host smart-caa349cc-a01c-4ceb-a690-f7e8d4608ed3
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=981327738 -assert nopostproc +UVM_TESTNAME=i2c_base
_test +UVM_TEST_SEQ=i2c_target_nack_txstretch_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /
dev/null -cm_name 18.i2c_target_nack_txstretch.981327738
Directory /workspace/18.i2c_target_nack_txstretch/latest

Test location /workspace/coverage/default/18.i2c_target_perf.194363344
Short name T545
Test name
Test status
Simulation time 1708966162 ps
CPU time 3.27 seconds
Started Aug 12 04:42:57 PM PDT 24
Finished Aug 12 04:43:01 PM PDT 24
Peak memory 216660 kb
Host smart-76ced58e-5359-41ac-b0cd-9f573e46acb5
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=194363344 -assert nopostproc +UVM_TESTNAME=i2c_base
_test +UVM_TEST_SEQ=i2c_target_perf_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -
cm_name 18.i2c_target_perf.194363344
Directory /workspace/18.i2c_target_perf/latest

Test location /workspace/coverage/default/18.i2c_target_smbus_maxlen.2354095128
Short name T1638
Test name
Test status
Simulation time 919185091 ps
CPU time 2.38 seconds
Started Aug 12 04:42:56 PM PDT 24
Finished Aug 12 04:42:58 PM PDT 24
Peak memory 205232 kb
Host smart-44578f42-b400-400b-8c5a-e5cc8af03f25
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2354095128 -assert nopostproc +UVM_TESTNAME=i2c_bas
e_test +UVM_TEST_SEQ=i2c_target_smbus_maxlen_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /d
ev/null -cm_name 18.i2c_target_smbus_maxlen.2354095128
Directory /workspace/18.i2c_target_smbus_maxlen/latest

Test location /workspace/coverage/default/18.i2c_target_smoke.1962477326
Short name T5
Test name
Test status
Simulation time 723972842 ps
CPU time 11.39 seconds
Started Aug 12 04:42:55 PM PDT 24
Finished Aug 12 04:43:06 PM PDT 24
Peak memory 213612 kb
Host smart-c8b8b58a-001f-4f29-a54e-5dfd1e7a85b0
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=100_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licq
ueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1962477326 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SE
Q=i2c_target_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.i2c_ta
rget_smoke.1962477326
Directory /workspace/18.i2c_target_smoke/latest

Test location /workspace/coverage/default/18.i2c_target_stress_all.3939259586
Short name T411
Test name
Test status
Simulation time 78420718337 ps
CPU time 72.36 seconds
Started Aug 12 04:42:58 PM PDT 24
Finished Aug 12 04:44:10 PM PDT 24
Peak memory 839464 kb
Host smart-bfc82fbf-55da-43c1-b763-fe52bf8b6d96
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=300_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VER
BOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3939259586 -assert nopostproc +UVM_TESTNAME=i2c_ba
se_test +UVM_TEST_SEQ=i2c_target_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /de
v/null -cm_name 18.i2c_target_stress_all.3939259586
Directory /workspace/18.i2c_target_stress_all/latest

Test location /workspace/coverage/default/18.i2c_target_stress_rd.2100174541
Short name T932
Test name
Test status
Simulation time 256950351 ps
CPU time 9.79 seconds
Started Aug 12 04:42:55 PM PDT 24
Finished Aug 12 04:43:05 PM PDT 24
Peak memory 205456 kb
Host smart-4e6ddd1a-6d7a-41a6-8180-c69049a46c2d
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=100_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licq
ueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2100174541 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SE
Q=i2c_target_stress_rd_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.i2
c_target_stress_rd.2100174541
Directory /workspace/18.i2c_target_stress_rd/latest

Test location /workspace/coverage/default/18.i2c_target_stress_wr.2349230724
Short name T519
Test name
Test status
Simulation time 52760934811 ps
CPU time 1499.39 seconds
Started Aug 12 04:42:49 PM PDT 24
Finished Aug 12 05:07:49 PM PDT 24
Peak memory 8386680 kb
Host smart-3bc12e4d-8c7c-49f2-848d-fe03a6b55ca2
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=600_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licq
ueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2349230724 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SE
Q=i2c_target_stress_wr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.i2
c_target_stress_wr.2349230724
Directory /workspace/18.i2c_target_stress_wr/latest

Test location /workspace/coverage/default/18.i2c_target_stretch.3430800803
Short name T331
Test name
Test status
Simulation time 1025807833 ps
CPU time 1.16 seconds
Started Aug 12 04:42:53 PM PDT 24
Finished Aug 12 04:42:54 PM PDT 24
Peak memory 205240 kb
Host smart-953734d0-e69d-4371-bb36-e37e74346424
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=400_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licq
ueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3430800803 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SE
Q=i2c_target_stretch_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.i2c_
target_stretch.3430800803
Directory /workspace/18.i2c_target_stretch/latest

Test location /workspace/coverage/default/18.i2c_target_timeout.1248688819
Short name T1601
Test name
Test status
Simulation time 1201253881 ps
CPU time 6.82 seconds
Started Aug 12 04:42:49 PM PDT 24
Finished Aug 12 04:42:56 PM PDT 24
Peak memory 233224 kb
Host smart-34c12ab7-e1e7-4e23-a57c-9cbbef627449
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=50_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1248688819 -assert nopostproc +UVM_TESTNAME=i2c_bas
e_test +UVM_TEST_SEQ=i2c_target_timeout_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/nu
ll -cm_name 18.i2c_target_timeout.1248688819
Directory /workspace/18.i2c_target_timeout/latest

Test location /workspace/coverage/default/18.i2c_target_tx_stretch_ctrl.521868027
Short name T601
Test name
Test status
Simulation time 255494195 ps
CPU time 3.16 seconds
Started Aug 12 04:42:57 PM PDT 24
Finished Aug 12 04:43:00 PM PDT 24
Peak memory 205448 kb
Host smart-7a7d173c-55c1-4123-b71e-ac57972108f9
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=521868027 -assert nopostproc +UVM_TESTNAME=i2c_base
_test +UVM_TEST_SEQ=i2c_target_tx_stretch_ctrl_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log
/dev/null -cm_name 18.i2c_target_tx_stretch_ctrl.521868027
Directory /workspace/18.i2c_target_tx_stretch_ctrl/latest

Test location /workspace/coverage/default/19.i2c_alert_test.2199799749
Short name T1534
Test name
Test status
Simulation time 50882231 ps
CPU time 0.61 seconds
Started Aug 12 04:43:05 PM PDT 24
Finished Aug 12 04:43:06 PM PDT 24
Peak memory 204340 kb
Host smart-caa99382-655f-499b-90c9-6af7f0d4c7dd
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2199799749 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_common_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.i2c_alert_test.2199799749
Directory /workspace/19.i2c_alert_test/latest

Test location /workspace/coverage/default/19.i2c_host_error_intr.187288420
Short name T1697
Test name
Test status
Simulation time 502979784 ps
CPU time 4.41 seconds
Started Aug 12 04:42:58 PM PDT 24
Finished Aug 12 04:43:03 PM PDT 24
Peak memory 232972 kb
Host smart-c3a061b1-169d-4fdb-8901-aa2fe10310e1
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=187288420 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_error_intr_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.i2c_host_error_intr.187288420
Directory /workspace/19.i2c_host_error_intr/latest

Test location /workspace/coverage/default/19.i2c_host_fifo_fmt_empty.2505315822
Short name T340
Test name
Test status
Simulation time 380760579 ps
CPU time 5.34 seconds
Started Aug 12 04:43:05 PM PDT 24
Finished Aug 12 04:43:11 PM PDT 24
Peak memory 263828 kb
Host smart-05fc1346-9efa-4b68-a5e5-6ebe9903fafe
User root
Command /workspace/default/simv +test_timeout_ns=10_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2505315822 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_fifo_fmt_em
pty_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.i2c_host_fifo_fmt_emp
ty.2505315822
Directory /workspace/19.i2c_host_fifo_fmt_empty/latest

Test location /workspace/coverage/default/19.i2c_host_fifo_full.3037368013
Short name T490
Test name
Test status
Simulation time 3608076873 ps
CPU time 215.42 seconds
Started Aug 12 04:42:55 PM PDT 24
Finished Aug 12 04:46:31 PM PDT 24
Peak memory 550892 kb
Host smart-a194e972-8705-4f0a-a0b2-5c189f0dcfd8
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3037368013 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_fifo_full_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.i2c_host_fifo_full.3037368013
Directory /workspace/19.i2c_host_fifo_full/latest

Test location /workspace/coverage/default/19.i2c_host_fifo_overflow.1827766829
Short name T453
Test name
Test status
Simulation time 5181965326 ps
CPU time 31.35 seconds
Started Aug 12 04:42:56 PM PDT 24
Finished Aug 12 04:43:28 PM PDT 24
Peak memory 358524 kb
Host smart-16d539fd-227d-422a-be02-ba38b965b148
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1827766829 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_fifo_overflow_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.i2c_host_fifo_overflow.1827766829
Directory /workspace/19.i2c_host_fifo_overflow/latest

Test location /workspace/coverage/default/19.i2c_host_fifo_reset_fmt.2208454980
Short name T674
Test name
Test status
Simulation time 608868671 ps
CPU time 1.36 seconds
Started Aug 12 04:43:02 PM PDT 24
Finished Aug 12 04:43:03 PM PDT 24
Peak memory 205112 kb
Host smart-f3fb9099-11bc-48b8-8160-53c5535bf87a
User root
Command /workspace/default/simv +test_timeout_ns=10_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2208454980 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_fifo_reset_
fmt_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.i2c_host_fifo_reset_f
mt.2208454980
Directory /workspace/19.i2c_host_fifo_reset_fmt/latest

Test location /workspace/coverage/default/19.i2c_host_fifo_reset_rx.4264309517
Short name T909
Test name
Test status
Simulation time 901562296 ps
CPU time 5.87 seconds
Started Aug 12 04:42:59 PM PDT 24
Finished Aug 12 04:43:05 PM PDT 24
Peak memory 251664 kb
Host smart-3c3cb730-67f3-4150-9da2-28ceddf1a616
User root
Command /workspace/default/simv +test_timeout_ns=10_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4264309517 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_fifo_reset_
rx_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.i2c_host_fifo_reset_rx
.4264309517
Directory /workspace/19.i2c_host_fifo_reset_rx/latest

Test location /workspace/coverage/default/19.i2c_host_fifo_watermark.3888586047
Short name T1706
Test name
Test status
Simulation time 7665163049 ps
CPU time 88.88 seconds
Started Aug 12 04:43:01 PM PDT 24
Finished Aug 12 04:44:30 PM PDT 24
Peak memory 1124560 kb
Host smart-754235db-f4bb-4ae7-8a36-7e618fd51d87
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3888586047 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_fifo_watermark_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.i2c_host_fifo_watermark.3888586047
Directory /workspace/19.i2c_host_fifo_watermark/latest

Test location /workspace/coverage/default/19.i2c_host_may_nack.2612816990
Short name T279
Test name
Test status
Simulation time 604094279 ps
CPU time 9.96 seconds
Started Aug 12 04:43:05 PM PDT 24
Finished Aug 12 04:43:15 PM PDT 24
Peak memory 205320 kb
Host smart-6c297117-5251-4b88-90a9-b0f214f369d4
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2612816990 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_may_nack_vseq +en_cov=1 -cm line+cond+f
sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.i2c_host_may_nack.2612816990
Directory /workspace/19.i2c_host_may_nack/latest

Test location /workspace/coverage/default/19.i2c_host_override.1680759887
Short name T1466
Test name
Test status
Simulation time 151642061 ps
CPU time 0.65 seconds
Started Aug 12 04:43:04 PM PDT 24
Finished Aug 12 04:43:05 PM PDT 24
Peak memory 204908 kb
Host smart-eb0bcd33-c08d-41cd-a06a-0cacf149894c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1680759887 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_override_vseq +en_cov=1 -cm line+cond+f
sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.i2c_host_override.1680759887
Directory /workspace/19.i2c_host_override/latest

Test location /workspace/coverage/default/19.i2c_host_perf.4154116552
Short name T797
Test name
Test status
Simulation time 11868108423 ps
CPU time 193.94 seconds
Started Aug 12 04:42:56 PM PDT 24
Finished Aug 12 04:46:10 PM PDT 24
Peak memory 884676 kb
Host smart-fe18eb9b-5ba7-4662-b278-c4de25c4dc8b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4154116552 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_perf_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.i2c_host_perf.4154116552
Directory /workspace/19.i2c_host_perf/latest

Test location /workspace/coverage/default/19.i2c_host_perf_precise.3855972033
Short name T143
Test name
Test status
Simulation time 3179850378 ps
CPU time 25.65 seconds
Started Aug 12 04:42:56 PM PDT 24
Finished Aug 12 04:43:22 PM PDT 24
Peak memory 205180 kb
Host smart-e2dad79c-19df-4397-b57a-08ee53b8011e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3855972033 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_perf_precise_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.i2c_host_perf_precise.3855972033
Directory /workspace/19.i2c_host_perf_precise/latest

Test location /workspace/coverage/default/19.i2c_host_smoke.2085356457
Short name T698
Test name
Test status
Simulation time 25884252693 ps
CPU time 29.39 seconds
Started Aug 12 04:42:56 PM PDT 24
Finished Aug 12 04:43:25 PM PDT 24
Peak memory 345520 kb
Host smart-679d8cd5-bb69-470c-bacb-2961f5b65cc2
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2085356457 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_smoke_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.i2c_host_smoke.2085356457
Directory /workspace/19.i2c_host_smoke/latest

Test location /workspace/coverage/default/19.i2c_host_stretch_timeout.3658471493
Short name T100
Test name
Test status
Simulation time 3243434220 ps
CPU time 11.92 seconds
Started Aug 12 04:42:59 PM PDT 24
Finished Aug 12 04:43:11 PM PDT 24
Peak memory 220800 kb
Host smart-5c3e7847-3ede-45b2-ae29-94218e94a35b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3658471493 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_stretch_timeout_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.i2c_host_stretch_timeout.3658471493
Directory /workspace/19.i2c_host_stretch_timeout/latest

Test location /workspace/coverage/default/19.i2c_target_bad_addr.2878237211
Short name T1241
Test name
Test status
Simulation time 6530395758 ps
CPU time 5.23 seconds
Started Aug 12 04:43:05 PM PDT 24
Finished Aug 12 04:43:10 PM PDT 24
Peak memory 214224 kb
Host smart-ae98dd53-f2e3-4070-919c-07cc84b52475
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +i2c_bad_addr_pct=50 +cdc_instrumentation_enabled=1 +UVM_
NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2878237211 -assert nopostproc
+UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_target_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.
vdb -cm_log /dev/null -cm_name 19.i2c_target_bad_addr.2878237211
Directory /workspace/19.i2c_target_bad_addr/latest

Test location /workspace/coverage/default/19.i2c_target_fifo_reset_acq.343515906
Short name T616
Test name
Test status
Simulation time 287142964 ps
CPU time 1.18 seconds
Started Aug 12 04:43:08 PM PDT 24
Finished Aug 12 04:43:10 PM PDT 24
Peak memory 205212 kb
Host smart-8a9f4352-9a70-43ee-8a7b-380b3f594e2a
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=343515906 -assert nopostproc +UVM_TESTNAME=i2c_base
_test +UVM_TEST_SEQ=i2c_target_fifo_reset_acq_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /
dev/null -cm_name 19.i2c_target_fifo_reset_acq.343515906
Directory /workspace/19.i2c_target_fifo_reset_acq/latest

Test location /workspace/coverage/default/19.i2c_target_fifo_reset_tx.290483642
Short name T573
Test name
Test status
Simulation time 254537016 ps
CPU time 1.59 seconds
Started Aug 12 04:43:02 PM PDT 24
Finished Aug 12 04:43:04 PM PDT 24
Peak memory 207836 kb
Host smart-10edadc4-596c-4365-ab28-c9e51dea461b
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=290483642 -assert nopostproc +UVM_TESTNAME=i2c_base
_test +UVM_TEST_SEQ=i2c_target_fifo_reset_tx_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /d
ev/null -cm_name 19.i2c_target_fifo_reset_tx.290483642
Directory /workspace/19.i2c_target_fifo_reset_tx/latest

Test location /workspace/coverage/default/19.i2c_target_fifo_watermarks_acq.2638162010
Short name T1722
Test name
Test status
Simulation time 1294718268 ps
CPU time 2.27 seconds
Started Aug 12 04:43:03 PM PDT 24
Finished Aug 12 04:43:05 PM PDT 24
Peak memory 205492 kb
Host smart-5b500c97-7f1e-4f97-85cc-5839ee86ce7e
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2638162010 -assert nopostproc +UVM_TESTNAME=i2c_bas
e_test +UVM_TEST_SEQ=i2c_target_fifo_watermarks_acq_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm
_log /dev/null -cm_name 19.i2c_target_fifo_watermarks_acq.2638162010
Directory /workspace/19.i2c_target_fifo_watermarks_acq/latest

Test location /workspace/coverage/default/19.i2c_target_fifo_watermarks_tx.4164413561
Short name T1258
Test name
Test status
Simulation time 288899144 ps
CPU time 1.31 seconds
Started Aug 12 04:43:04 PM PDT 24
Finished Aug 12 04:43:06 PM PDT 24
Peak memory 205292 kb
Host smart-b25d8a13-b84e-493a-bebb-e587cfaeb630
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4164413561 -assert nopostproc +UVM_TESTNAME=i2c_bas
e_test +UVM_TEST_SEQ=i2c_target_fifo_watermarks_tx_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_
log /dev/null -cm_name 19.i2c_target_fifo_watermarks_tx.4164413561
Directory /workspace/19.i2c_target_fifo_watermarks_tx/latest

Test location /workspace/coverage/default/19.i2c_target_intr_smoke.1724187985
Short name T945
Test name
Test status
Simulation time 708578679 ps
CPU time 4.4 seconds
Started Aug 12 04:42:57 PM PDT 24
Finished Aug 12 04:43:02 PM PDT 24
Peak memory 208672 kb
Host smart-0599b3aa-a014-4d3b-990b-ecac04cbecfe
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=200_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VER
BOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1724187985 -assert nopostproc +UVM_TESTNAME=i2c_ba
se_test +UVM_TEST_SEQ=i2c_target_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/nul
l -cm_name 19.i2c_target_intr_smoke.1724187985
Directory /workspace/19.i2c_target_intr_smoke/latest

Test location /workspace/coverage/default/19.i2c_target_intr_stress_wr.795224748
Short name T349
Test name
Test status
Simulation time 10056732735 ps
CPU time 151.34 seconds
Started Aug 12 04:43:10 PM PDT 24
Finished Aug 12 04:45:42 PM PDT 24
Peak memory 2534500 kb
Host smart-ea03eb26-0992-42ab-8e62-436ae11c81fe
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=600_000_000 +use_intr_handler=1 +slow_acq=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNO
TES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=795224748 -assert nopostproc +UVM_TEST
NAME=i2c_base_test +UVM_TEST_SEQ=i2c_target_stress_wr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -
cm_log /dev/null -cm_name 19.i2c_target_intr_stress_wr.795224748
Directory /workspace/19.i2c_target_intr_stress_wr/latest

Test location /workspace/coverage/default/19.i2c_target_nack_acqfull.3185498392
Short name T693
Test name
Test status
Simulation time 2136521927 ps
CPU time 3.27 seconds
Started Aug 12 04:43:06 PM PDT 24
Finished Aug 12 04:43:09 PM PDT 24
Peak memory 213800 kb
Host smart-df1ef47d-05a4-4d78-9fff-e49570c7c0b7
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3185498392 -assert nopostproc +UVM_TESTNAME=i2c_bas
e_test +UVM_TEST_SEQ=i2c_target_nack_acqfull_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /d
ev/null -cm_name 19.i2c_target_nack_acqfull.3185498392
Directory /workspace/19.i2c_target_nack_acqfull/latest

Test location /workspace/coverage/default/19.i2c_target_nack_acqfull_addr.3358753651
Short name T1616
Test name
Test status
Simulation time 1204387556 ps
CPU time 2.92 seconds
Started Aug 12 04:43:03 PM PDT 24
Finished Aug 12 04:43:06 PM PDT 24
Peak memory 205432 kb
Host smart-273acc56-8b22-4f4d-a3f2-8908d9e2e54c
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3358753651 -assert nopostproc +UVM_TESTNAME=i2c_bas
e_test +UVM_TEST_SEQ=i2c_target_nack_acqfull_addr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_l
og /dev/null -cm_name 19.i2c_target_nack_acqfull_addr.3358753651
Directory /workspace/19.i2c_target_nack_acqfull_addr/latest

Test location /workspace/coverage/default/19.i2c_target_nack_txstretch.2610112458
Short name T1612
Test name
Test status
Simulation time 483298338 ps
CPU time 1.39 seconds
Started Aug 12 04:43:04 PM PDT 24
Finished Aug 12 04:43:06 PM PDT 24
Peak memory 222424 kb
Host smart-bcaf8c6c-6b55-4310-89f9-2d2b9c58381d
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2610112458 -assert nopostproc +UVM_TESTNAME=i2c_bas
e_test +UVM_TEST_SEQ=i2c_target_nack_txstretch_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log
/dev/null -cm_name 19.i2c_target_nack_txstretch.2610112458
Directory /workspace/19.i2c_target_nack_txstretch/latest

Test location /workspace/coverage/default/19.i2c_target_perf.2216680692
Short name T308
Test name
Test status
Simulation time 962206212 ps
CPU time 6.92 seconds
Started Aug 12 04:43:03 PM PDT 24
Finished Aug 12 04:43:10 PM PDT 24
Peak memory 221712 kb
Host smart-3604b02d-8aa4-48cc-baa8-e53f3a148e52
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2216680692 -assert nopostproc +UVM_TESTNAME=i2c_bas
e_test +UVM_TEST_SEQ=i2c_target_perf_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null
-cm_name 19.i2c_target_perf.2216680692
Directory /workspace/19.i2c_target_perf/latest

Test location /workspace/coverage/default/19.i2c_target_smbus_maxlen.3491728470
Short name T1495
Test name
Test status
Simulation time 1064279219 ps
CPU time 2.37 seconds
Started Aug 12 04:43:08 PM PDT 24
Finished Aug 12 04:43:11 PM PDT 24
Peak memory 205228 kb
Host smart-250e35e2-18ff-4e61-aaad-688d052925ce
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3491728470 -assert nopostproc +UVM_TESTNAME=i2c_bas
e_test +UVM_TEST_SEQ=i2c_target_smbus_maxlen_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /d
ev/null -cm_name 19.i2c_target_smbus_maxlen.3491728470
Directory /workspace/19.i2c_target_smbus_maxlen/latest

Test location /workspace/coverage/default/19.i2c_target_smoke.705916806
Short name T1525
Test name
Test status
Simulation time 10202302261 ps
CPU time 17.11 seconds
Started Aug 12 04:42:59 PM PDT 24
Finished Aug 12 04:43:16 PM PDT 24
Peak memory 216480 kb
Host smart-ff03b770-d204-4078-9918-d81e6c8578c4
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=100_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licq
ueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=705916806 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ
=i2c_target_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.i2c_tar
get_smoke.705916806
Directory /workspace/19.i2c_target_smoke/latest

Test location /workspace/coverage/default/19.i2c_target_stress_rd.3842267152
Short name T1538
Test name
Test status
Simulation time 8913114355 ps
CPU time 47.34 seconds
Started Aug 12 04:42:56 PM PDT 24
Finished Aug 12 04:43:43 PM PDT 24
Peak memory 217180 kb
Host smart-77ce8544-46c9-4333-b8dc-cda98979e32f
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=100_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licq
ueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3842267152 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SE
Q=i2c_target_stress_rd_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.i2
c_target_stress_rd.3842267152
Directory /workspace/19.i2c_target_stress_rd/latest

Test location /workspace/coverage/default/19.i2c_target_stress_wr.2314911307
Short name T414
Test name
Test status
Simulation time 52680740954 ps
CPU time 191.96 seconds
Started Aug 12 04:42:58 PM PDT 24
Finished Aug 12 04:46:10 PM PDT 24
Peak memory 2092332 kb
Host smart-f909e599-a4d6-46b9-b9ed-fac5edb63bb7
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=600_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licq
ueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2314911307 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SE
Q=i2c_target_stress_wr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.i2
c_target_stress_wr.2314911307
Directory /workspace/19.i2c_target_stress_wr/latest

Test location /workspace/coverage/default/19.i2c_target_stretch.290977794
Short name T204
Test name
Test status
Simulation time 1988644301 ps
CPU time 19.35 seconds
Started Aug 12 04:42:56 PM PDT 24
Finished Aug 12 04:43:16 PM PDT 24
Peak memory 293088 kb
Host smart-c3cf4aef-caf3-4eca-b5d3-820d75e1f770
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=400_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licq
ueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=290977794 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ
=i2c_target_stretch_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.i2c_t
arget_stretch.290977794
Directory /workspace/19.i2c_target_stretch/latest

Test location /workspace/coverage/default/19.i2c_target_timeout.595434678
Short name T1667
Test name
Test status
Simulation time 1455739889 ps
CPU time 7.52 seconds
Started Aug 12 04:43:04 PM PDT 24
Finished Aug 12 04:43:11 PM PDT 24
Peak memory 213676 kb
Host smart-dbe498f4-c107-4d36-8c95-4315693eaec3
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=50_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=595434678 -assert nopostproc +UVM_TESTNAME=i2c_base
_test +UVM_TEST_SEQ=i2c_target_timeout_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/nul
l -cm_name 19.i2c_target_timeout.595434678
Directory /workspace/19.i2c_target_timeout/latest

Test location /workspace/coverage/default/19.i2c_target_tx_stretch_ctrl.374143565
Short name T343
Test name
Test status
Simulation time 394817382 ps
CPU time 5.53 seconds
Started Aug 12 04:43:05 PM PDT 24
Finished Aug 12 04:43:11 PM PDT 24
Peak memory 213620 kb
Host smart-f74e4c66-8afc-4e4a-b9ff-599f07a4e44b
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=374143565 -assert nopostproc +UVM_TESTNAME=i2c_base
_test +UVM_TEST_SEQ=i2c_target_tx_stretch_ctrl_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log
/dev/null -cm_name 19.i2c_target_tx_stretch_ctrl.374143565
Directory /workspace/19.i2c_target_tx_stretch_ctrl/latest

Test location /workspace/coverage/default/2.i2c_alert_test.1867606459
Short name T789
Test name
Test status
Simulation time 15588494 ps
CPU time 0.65 seconds
Started Aug 12 04:40:54 PM PDT 24
Finished Aug 12 04:40:54 PM PDT 24
Peak memory 204352 kb
Host smart-566ff4bd-c1f0-44be-9807-d54c1afc19da
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1867606459 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_common_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.i2c_alert_test.1867606459
Directory /workspace/2.i2c_alert_test/latest

Test location /workspace/coverage/default/2.i2c_host_error_intr.1036178657
Short name T1062
Test name
Test status
Simulation time 259199378 ps
CPU time 2.46 seconds
Started Aug 12 04:40:53 PM PDT 24
Finished Aug 12 04:40:56 PM PDT 24
Peak memory 213132 kb
Host smart-6c7913ff-dcd9-4aea-b4da-f0f39e7ea660
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1036178657 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_error_intr_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.i2c_host_error_intr.1036178657
Directory /workspace/2.i2c_host_error_intr/latest

Test location /workspace/coverage/default/2.i2c_host_fifo_fmt_empty.2217706746
Short name T655
Test name
Test status
Simulation time 366012217 ps
CPU time 6.9 seconds
Started Aug 12 04:40:53 PM PDT 24
Finished Aug 12 04:41:00 PM PDT 24
Peak memory 282876 kb
Host smart-098cb6dc-ba66-4ee3-81fe-d2c76174bc52
User root
Command /workspace/default/simv +test_timeout_ns=10_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2217706746 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_fifo_fmt_em
pty_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.i2c_host_fifo_fmt_empt
y.2217706746
Directory /workspace/2.i2c_host_fifo_fmt_empty/latest

Test location /workspace/coverage/default/2.i2c_host_fifo_full.713438072
Short name T1061
Test name
Test status
Simulation time 3475181160 ps
CPU time 103.77 seconds
Started Aug 12 04:40:53 PM PDT 24
Finished Aug 12 04:42:37 PM PDT 24
Peak memory 634336 kb
Host smart-fb4c05e1-7ee0-4929-b9ec-5fcbd8013afa
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=713438072 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_fifo_full_vseq +en_cov=1 -cm line+cond+f
sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.i2c_host_fifo_full.713438072
Directory /workspace/2.i2c_host_fifo_full/latest

Test location /workspace/coverage/default/2.i2c_host_fifo_overflow.3191460432
Short name T869
Test name
Test status
Simulation time 3988326824 ps
CPU time 123.46 seconds
Started Aug 12 04:40:47 PM PDT 24
Finished Aug 12 04:42:50 PM PDT 24
Peak memory 538372 kb
Host smart-414b93f6-82ea-4190-9854-95ff4b01b8b1
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3191460432 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_fifo_overflow_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.i2c_host_fifo_overflow.3191460432
Directory /workspace/2.i2c_host_fifo_overflow/latest

Test location /workspace/coverage/default/2.i2c_host_fifo_reset_fmt.1838134144
Short name T1649
Test name
Test status
Simulation time 163875700 ps
CPU time 1.29 seconds
Started Aug 12 04:40:53 PM PDT 24
Finished Aug 12 04:40:54 PM PDT 24
Peak memory 205108 kb
Host smart-a8e98bce-bb95-4cdc-8296-4b5a85d1588a
User root
Command /workspace/default/simv +test_timeout_ns=10_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1838134144 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_fifo_reset_
fmt_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.i2c_host_fifo_reset_fm
t.1838134144
Directory /workspace/2.i2c_host_fifo_reset_fmt/latest

Test location /workspace/coverage/default/2.i2c_host_fifo_reset_rx.3382896584
Short name T520
Test name
Test status
Simulation time 138715286 ps
CPU time 4.21 seconds
Started Aug 12 04:40:53 PM PDT 24
Finished Aug 12 04:40:57 PM PDT 24
Peak memory 228656 kb
Host smart-db6f32ed-21d8-433e-976d-c980410aea13
User root
Command /workspace/default/simv +test_timeout_ns=10_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3382896584 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_fifo_reset_
rx_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.i2c_host_fifo_reset_rx.
3382896584
Directory /workspace/2.i2c_host_fifo_reset_rx/latest

Test location /workspace/coverage/default/2.i2c_host_fifo_watermark.4120839358
Short name T667
Test name
Test status
Simulation time 5561575078 ps
CPU time 162.28 seconds
Started Aug 12 04:40:52 PM PDT 24
Finished Aug 12 04:43:35 PM PDT 24
Peak memory 835004 kb
Host smart-dbbae651-039d-4356-9c34-69614391f7fd
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4120839358 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_fifo_watermark_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.i2c_host_fifo_watermark.4120839358
Directory /workspace/2.i2c_host_fifo_watermark/latest

Test location /workspace/coverage/default/2.i2c_host_may_nack.3740790920
Short name T277
Test name
Test status
Simulation time 1219035169 ps
CPU time 4.1 seconds
Started Aug 12 04:40:54 PM PDT 24
Finished Aug 12 04:40:58 PM PDT 24
Peak memory 205216 kb
Host smart-430661af-b35d-435d-b3d9-68c7a817f794
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3740790920 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_may_nack_vseq +en_cov=1 -cm line+cond+f
sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.i2c_host_may_nack.3740790920
Directory /workspace/2.i2c_host_may_nack/latest

Test location /workspace/coverage/default/2.i2c_host_override.3832565703
Short name T1663
Test name
Test status
Simulation time 25259381 ps
CPU time 0.7 seconds
Started Aug 12 04:40:53 PM PDT 24
Finished Aug 12 04:40:54 PM PDT 24
Peak memory 204896 kb
Host smart-d6f60231-0be2-44c7-be5a-9e3319d9da58
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3832565703 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_override_vseq +en_cov=1 -cm line+cond+f
sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.i2c_host_override.3832565703
Directory /workspace/2.i2c_host_override/latest

Test location /workspace/coverage/default/2.i2c_host_perf.1801870834
Short name T962
Test name
Test status
Simulation time 51336638055 ps
CPU time 557.35 seconds
Started Aug 12 04:41:00 PM PDT 24
Finished Aug 12 04:50:18 PM PDT 24
Peak memory 936888 kb
Host smart-92942a85-e4ed-4026-8865-63efc02e0391
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1801870834 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_perf_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.i2c_host_perf.1801870834
Directory /workspace/2.i2c_host_perf/latest

Test location /workspace/coverage/default/2.i2c_host_perf_precise.2225542969
Short name T624
Test name
Test status
Simulation time 54704087 ps
CPU time 1.08 seconds
Started Aug 12 04:41:00 PM PDT 24
Finished Aug 12 04:41:01 PM PDT 24
Peak memory 205440 kb
Host smart-e6a6711d-9e18-4ba1-be90-b9a90e5a24cb
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2225542969 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_perf_precise_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.i2c_host_perf_precise.2225542969
Directory /workspace/2.i2c_host_perf_precise/latest

Test location /workspace/coverage/default/2.i2c_host_smoke.868098749
Short name T842
Test name
Test status
Simulation time 2166852314 ps
CPU time 103.01 seconds
Started Aug 12 04:40:53 PM PDT 24
Finished Aug 12 04:42:36 PM PDT 24
Peak memory 343720 kb
Host smart-240b4554-ec4b-43bb-910b-87c60353bea3
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=868098749 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_smoke_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.i2c_host_smoke.868098749
Directory /workspace/2.i2c_host_smoke/latest

Test location /workspace/coverage/default/2.i2c_host_stretch_timeout.4110118004
Short name T525
Test name
Test status
Simulation time 1404474502 ps
CPU time 15.29 seconds
Started Aug 12 04:41:00 PM PDT 24
Finished Aug 12 04:41:16 PM PDT 24
Peak memory 213412 kb
Host smart-8197b37b-3b98-4a5d-b7c0-c5b2ba9ac58b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4110118004 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_stretch_timeout_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.i2c_host_stretch_timeout.4110118004
Directory /workspace/2.i2c_host_stretch_timeout/latest

Test location /workspace/coverage/default/2.i2c_sec_cm.595805633
Short name T195
Test name
Test status
Simulation time 146201456 ps
CPU time 0.94 seconds
Started Aug 12 04:40:59 PM PDT 24
Finished Aug 12 04:41:00 PM PDT 24
Peak memory 223576 kb
Host smart-f46f076b-044a-4351-8fea-56428c489511
User root
Command /workspace/default/simv +run_sec_cm_fi +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=595805633 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_common_vseq +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.i2c_sec_cm.595805633
Directory /workspace/2.i2c_sec_cm/latest

Test location /workspace/coverage/default/2.i2c_target_bad_addr.641955869
Short name T1338
Test name
Test status
Simulation time 3905056726 ps
CPU time 3.95 seconds
Started Aug 12 04:40:54 PM PDT 24
Finished Aug 12 04:40:58 PM PDT 24
Peak memory 213784 kb
Host smart-f979ea5f-6008-4de2-a826-7dd4f448f335
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +i2c_bad_addr_pct=50 +cdc_instrumentation_enabled=1 +UVM_
NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=641955869 -assert nopostproc +
UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_target_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.v
db -cm_log /dev/null -cm_name 2.i2c_target_bad_addr.641955869
Directory /workspace/2.i2c_target_bad_addr/latest

Test location /workspace/coverage/default/2.i2c_target_fifo_reset_acq.4119259540
Short name T48
Test name
Test status
Simulation time 1529163985 ps
CPU time 0.91 seconds
Started Aug 12 04:40:54 PM PDT 24
Finished Aug 12 04:40:55 PM PDT 24
Peak memory 205280 kb
Host smart-703fc96a-d6d9-4e11-b91d-95acf671fa2c
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4119259540 -assert nopostproc +UVM_TESTNAME=i2c_bas
e_test +UVM_TEST_SEQ=i2c_target_fifo_reset_acq_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log
/dev/null -cm_name 2.i2c_target_fifo_reset_acq.4119259540
Directory /workspace/2.i2c_target_fifo_reset_acq/latest

Test location /workspace/coverage/default/2.i2c_target_fifo_reset_tx.2540932170
Short name T1334
Test name
Test status
Simulation time 392022497 ps
CPU time 1.68 seconds
Started Aug 12 04:41:00 PM PDT 24
Finished Aug 12 04:41:02 PM PDT 24
Peak memory 205464 kb
Host smart-a3247b04-a977-4c23-9e9b-25d06a4c0dc4
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2540932170 -assert nopostproc +UVM_TESTNAME=i2c_bas
e_test +UVM_TEST_SEQ=i2c_target_fifo_reset_tx_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /
dev/null -cm_name 2.i2c_target_fifo_reset_tx.2540932170
Directory /workspace/2.i2c_target_fifo_reset_tx/latest

Test location /workspace/coverage/default/2.i2c_target_fifo_watermarks_acq.327090604
Short name T1318
Test name
Test status
Simulation time 2201023713 ps
CPU time 3.21 seconds
Started Aug 12 04:40:56 PM PDT 24
Finished Aug 12 04:40:59 PM PDT 24
Peak memory 205556 kb
Host smart-a5d68a10-fe5a-4c76-a36e-a02d74eecdc4
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=327090604 -assert nopostproc +UVM_TESTNAME=i2c_base
_test +UVM_TEST_SEQ=i2c_target_fifo_watermarks_acq_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_
log /dev/null -cm_name 2.i2c_target_fifo_watermarks_acq.327090604
Directory /workspace/2.i2c_target_fifo_watermarks_acq/latest

Test location /workspace/coverage/default/2.i2c_target_fifo_watermarks_tx.2182958807
Short name T364
Test name
Test status
Simulation time 135658294 ps
CPU time 0.9 seconds
Started Aug 12 04:40:54 PM PDT 24
Finished Aug 12 04:40:55 PM PDT 24
Peak memory 205216 kb
Host smart-8460d33d-25d3-4290-aae4-7a0e1d7f5132
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2182958807 -assert nopostproc +UVM_TESTNAME=i2c_bas
e_test +UVM_TEST_SEQ=i2c_target_fifo_watermarks_tx_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_
log /dev/null -cm_name 2.i2c_target_fifo_watermarks_tx.2182958807
Directory /workspace/2.i2c_target_fifo_watermarks_tx/latest

Test location /workspace/coverage/default/2.i2c_target_hrst.792157071
Short name T509
Test name
Test status
Simulation time 319006073 ps
CPU time 2.89 seconds
Started Aug 12 04:40:54 PM PDT 24
Finished Aug 12 04:40:57 PM PDT 24
Peak memory 213756 kb
Host smart-80b96e65-c238-4d55-bc57-d1f7dc539392
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=792157071 -assert nopostproc +UVM_TESTNAME=i2c_base
_test +UVM_TEST_SEQ=i2c_target_hrst_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -
cm_name 2.i2c_target_hrst.792157071
Directory /workspace/2.i2c_target_hrst/latest

Test location /workspace/coverage/default/2.i2c_target_intr_smoke.271995341
Short name T46
Test name
Test status
Simulation time 1149160471 ps
CPU time 6.06 seconds
Started Aug 12 04:40:52 PM PDT 24
Finished Aug 12 04:40:58 PM PDT 24
Peak memory 215936 kb
Host smart-9bece7d3-339f-45ac-a729-2964e8ed0d51
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=200_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VER
BOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=271995341 -assert nopostproc +UVM_TESTNAME=i2c_bas
e_test +UVM_TEST_SEQ=i2c_target_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null
-cm_name 2.i2c_target_intr_smoke.271995341
Directory /workspace/2.i2c_target_intr_smoke/latest

Test location /workspace/coverage/default/2.i2c_target_intr_stress_wr.2222909426
Short name T1705
Test name
Test status
Simulation time 17978605835 ps
CPU time 286.72 seconds
Started Aug 12 04:41:01 PM PDT 24
Finished Aug 12 04:45:48 PM PDT 24
Peak memory 2918056 kb
Host smart-947f285b-d91d-4b4d-96a8-ca2ad3e7a167
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=600_000_000 +use_intr_handler=1 +slow_acq=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNO
TES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2222909426 -assert nopostproc +UVM_TES
TNAME=i2c_base_test +UVM_TEST_SEQ=i2c_target_stress_wr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb
-cm_log /dev/null -cm_name 2.i2c_target_intr_stress_wr.2222909426
Directory /workspace/2.i2c_target_intr_stress_wr/latest

Test location /workspace/coverage/default/2.i2c_target_nack_acqfull.2730301304
Short name T1693
Test name
Test status
Simulation time 2177645284 ps
CPU time 3.03 seconds
Started Aug 12 04:40:58 PM PDT 24
Finished Aug 12 04:41:01 PM PDT 24
Peak memory 213732 kb
Host smart-b38d724d-28f9-47c0-932d-b9d46c183ef0
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2730301304 -assert nopostproc +UVM_TESTNAME=i2c_bas
e_test +UVM_TEST_SEQ=i2c_target_nack_acqfull_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /d
ev/null -cm_name 2.i2c_target_nack_acqfull.2730301304
Directory /workspace/2.i2c_target_nack_acqfull/latest

Test location /workspace/coverage/default/2.i2c_target_nack_acqfull_addr.3639175832
Short name T493
Test name
Test status
Simulation time 441510740 ps
CPU time 2.39 seconds
Started Aug 12 04:41:01 PM PDT 24
Finished Aug 12 04:41:03 PM PDT 24
Peak memory 205480 kb
Host smart-3722be9c-f38c-4499-a920-678b179cf08e
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3639175832 -assert nopostproc +UVM_TESTNAME=i2c_bas
e_test +UVM_TEST_SEQ=i2c_target_nack_acqfull_addr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_l
og /dev/null -cm_name 2.i2c_target_nack_acqfull_addr.3639175832
Directory /workspace/2.i2c_target_nack_acqfull_addr/latest

Test location /workspace/coverage/default/2.i2c_target_perf.2122127962
Short name T958
Test name
Test status
Simulation time 3052472619 ps
CPU time 5.3 seconds
Started Aug 12 04:40:54 PM PDT 24
Finished Aug 12 04:41:00 PM PDT 24
Peak memory 213904 kb
Host smart-7f01d4bf-3108-42d8-ac32-3959708d43c0
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2122127962 -assert nopostproc +UVM_TESTNAME=i2c_bas
e_test +UVM_TEST_SEQ=i2c_target_perf_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null
-cm_name 2.i2c_target_perf.2122127962
Directory /workspace/2.i2c_target_perf/latest

Test location /workspace/coverage/default/2.i2c_target_smbus_maxlen.3149278889
Short name T419
Test name
Test status
Simulation time 1928823710 ps
CPU time 2.3 seconds
Started Aug 12 04:41:01 PM PDT 24
Finished Aug 12 04:41:03 PM PDT 24
Peak memory 205240 kb
Host smart-e24a42b9-92a5-4299-bb08-91a53f40b9f0
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3149278889 -assert nopostproc +UVM_TESTNAME=i2c_bas
e_test +UVM_TEST_SEQ=i2c_target_smbus_maxlen_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /d
ev/null -cm_name 2.i2c_target_smbus_maxlen.3149278889
Directory /workspace/2.i2c_target_smbus_maxlen/latest

Test location /workspace/coverage/default/2.i2c_target_smoke.2225885264
Short name T650
Test name
Test status
Simulation time 7574279024 ps
CPU time 16.68 seconds
Started Aug 12 04:40:54 PM PDT 24
Finished Aug 12 04:41:11 PM PDT 24
Peak memory 221960 kb
Host smart-11961cea-78ae-46a5-8ba6-2857eb99581a
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=100_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licq
ueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2225885264 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SE
Q=i2c_target_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.i2c_tar
get_smoke.2225885264
Directory /workspace/2.i2c_target_smoke/latest

Test location /workspace/coverage/default/2.i2c_target_stress_all.1644508837
Short name T1198
Test name
Test status
Simulation time 23578711182 ps
CPU time 34.91 seconds
Started Aug 12 04:41:00 PM PDT 24
Finished Aug 12 04:41:35 PM PDT 24
Peak memory 238272 kb
Host smart-3b1aa1ac-dea3-4965-985f-44af76edf9a3
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=300_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VER
BOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1644508837 -assert nopostproc +UVM_TESTNAME=i2c_ba
se_test +UVM_TEST_SEQ=i2c_target_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /de
v/null -cm_name 2.i2c_target_stress_all.1644508837
Directory /workspace/2.i2c_target_stress_all/latest

Test location /workspace/coverage/default/2.i2c_target_stress_rd.1333710932
Short name T1378
Test name
Test status
Simulation time 1357147731 ps
CPU time 21.45 seconds
Started Aug 12 04:40:53 PM PDT 24
Finished Aug 12 04:41:15 PM PDT 24
Peak memory 229872 kb
Host smart-a6c969ce-6138-4568-b4c0-48c1e4ce63c7
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=100_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licq
ueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1333710932 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SE
Q=i2c_target_stress_rd_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.i2c
_target_stress_rd.1333710932
Directory /workspace/2.i2c_target_stress_rd/latest

Test location /workspace/coverage/default/2.i2c_target_stress_wr.129907824
Short name T981
Test name
Test status
Simulation time 18978999300 ps
CPU time 37 seconds
Started Aug 12 04:40:55 PM PDT 24
Finished Aug 12 04:41:32 PM PDT 24
Peak memory 205648 kb
Host smart-dee8092a-c190-4eee-9b72-2042e99752a1
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=600_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licq
ueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=129907824 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ
=i2c_target_stress_wr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.i2c_
target_stress_wr.129907824
Directory /workspace/2.i2c_target_stress_wr/latest

Test location /workspace/coverage/default/2.i2c_target_stretch.3254390877
Short name T319
Test name
Test status
Simulation time 2507193132 ps
CPU time 19.19 seconds
Started Aug 12 04:40:55 PM PDT 24
Finished Aug 12 04:41:14 PM PDT 24
Peak memory 325584 kb
Host smart-ccaa0ed5-ed9b-46b8-8fa9-e6240590a4ab
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=400_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licq
ueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3254390877 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SE
Q=i2c_target_stretch_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.i2c_t
arget_stretch.3254390877
Directory /workspace/2.i2c_target_stretch/latest

Test location /workspace/coverage/default/2.i2c_target_timeout.3837190913
Short name T1628
Test name
Test status
Simulation time 1381071976 ps
CPU time 7.38 seconds
Started Aug 12 04:40:54 PM PDT 24
Finished Aug 12 04:41:02 PM PDT 24
Peak memory 213676 kb
Host smart-b96b37e2-e309-4757-88a1-ec45948bcdaa
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=50_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3837190913 -assert nopostproc +UVM_TESTNAME=i2c_bas
e_test +UVM_TEST_SEQ=i2c_target_timeout_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/nu
ll -cm_name 2.i2c_target_timeout.3837190913
Directory /workspace/2.i2c_target_timeout/latest

Test location /workspace/coverage/default/2.i2c_target_tx_stretch_ctrl.2112209651
Short name T337
Test name
Test status
Simulation time 151492738 ps
CPU time 2.38 seconds
Started Aug 12 04:41:01 PM PDT 24
Finished Aug 12 04:41:04 PM PDT 24
Peak memory 205472 kb
Host smart-38d4b614-d32d-4175-a5f6-6b19485607f8
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2112209651 -assert nopostproc +UVM_TESTNAME=i2c_bas
e_test +UVM_TEST_SEQ=i2c_target_tx_stretch_ctrl_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log
/dev/null -cm_name 2.i2c_target_tx_stretch_ctrl.2112209651
Directory /workspace/2.i2c_target_tx_stretch_ctrl/latest

Test location /workspace/coverage/default/20.i2c_alert_test.310186462
Short name T1331
Test name
Test status
Simulation time 32564758 ps
CPU time 0.65 seconds
Started Aug 12 04:43:15 PM PDT 24
Finished Aug 12 04:43:16 PM PDT 24
Peak memory 204420 kb
Host smart-b334dd46-d2be-483d-8a46-91dd0c3cf9e0
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=310186462 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_common_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.i2c_alert_test.310186462
Directory /workspace/20.i2c_alert_test/latest

Test location /workspace/coverage/default/20.i2c_host_error_intr.3713292975
Short name T417
Test name
Test status
Simulation time 182975052 ps
CPU time 3.04 seconds
Started Aug 12 04:43:04 PM PDT 24
Finished Aug 12 04:43:08 PM PDT 24
Peak memory 236332 kb
Host smart-90b26ecc-f8de-45e3-8fb1-1effe0f12beb
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3713292975 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_error_intr_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.i2c_host_error_intr.3713292975
Directory /workspace/20.i2c_host_error_intr/latest

Test location /workspace/coverage/default/20.i2c_host_fifo_fmt_empty.3190850646
Short name T1267
Test name
Test status
Simulation time 994776459 ps
CPU time 11.34 seconds
Started Aug 12 04:43:03 PM PDT 24
Finished Aug 12 04:43:14 PM PDT 24
Peak memory 314528 kb
Host smart-a2ea1869-d245-4e2f-8942-bf77377a4ff0
User root
Command /workspace/default/simv +test_timeout_ns=10_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3190850646 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_fifo_fmt_em
pty_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.i2c_host_fifo_fmt_emp
ty.3190850646
Directory /workspace/20.i2c_host_fifo_fmt_empty/latest

Test location /workspace/coverage/default/20.i2c_host_fifo_full.4045376425
Short name T1117
Test name
Test status
Simulation time 6580424090 ps
CPU time 199.22 seconds
Started Aug 12 04:43:05 PM PDT 24
Finished Aug 12 04:46:24 PM PDT 24
Peak memory 499152 kb
Host smart-d6581f9a-2976-48d2-a46d-7cba3b3c9cde
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4045376425 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_fifo_full_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.i2c_host_fifo_full.4045376425
Directory /workspace/20.i2c_host_fifo_full/latest

Test location /workspace/coverage/default/20.i2c_host_fifo_overflow.3069133307
Short name T622
Test name
Test status
Simulation time 2065054148 ps
CPU time 140.02 seconds
Started Aug 12 04:43:10 PM PDT 24
Finished Aug 12 04:45:30 PM PDT 24
Peak memory 624280 kb
Host smart-a41cd733-2427-4102-893a-441102446e4b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3069133307 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_fifo_overflow_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.i2c_host_fifo_overflow.3069133307
Directory /workspace/20.i2c_host_fifo_overflow/latest

Test location /workspace/coverage/default/20.i2c_host_fifo_reset_fmt.2250032806
Short name T649
Test name
Test status
Simulation time 711704863 ps
CPU time 1.18 seconds
Started Aug 12 04:43:10 PM PDT 24
Finished Aug 12 04:43:11 PM PDT 24
Peak memory 204932 kb
Host smart-4dda7531-cdf8-41b0-8023-be69b328f8fd
User root
Command /workspace/default/simv +test_timeout_ns=10_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2250032806 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_fifo_reset_
fmt_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.i2c_host_fifo_reset_f
mt.2250032806
Directory /workspace/20.i2c_host_fifo_reset_fmt/latest

Test location /workspace/coverage/default/20.i2c_host_fifo_reset_rx.954949315
Short name T181
Test name
Test status
Simulation time 123566261 ps
CPU time 3.88 seconds
Started Aug 12 04:43:04 PM PDT 24
Finished Aug 12 04:43:08 PM PDT 24
Peak memory 225044 kb
Host smart-9e3e0e3d-a145-4b29-b7ce-98616c5a8ddb
User root
Command /workspace/default/simv +test_timeout_ns=10_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=954949315 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_fifo_reset_r
x_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.i2c_host_fifo_reset_rx.
954949315
Directory /workspace/20.i2c_host_fifo_reset_rx/latest

Test location /workspace/coverage/default/20.i2c_host_fifo_watermark.2541026873
Short name T32
Test name
Test status
Simulation time 9193318771 ps
CPU time 137.85 seconds
Started Aug 12 04:43:05 PM PDT 24
Finished Aug 12 04:45:23 PM PDT 24
Peak memory 1288540 kb
Host smart-cdc21eda-8c1d-484d-8f2a-4d15e1f5b8cb
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2541026873 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_fifo_watermark_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.i2c_host_fifo_watermark.2541026873
Directory /workspace/20.i2c_host_fifo_watermark/latest

Test location /workspace/coverage/default/20.i2c_host_may_nack.2462391970
Short name T1169
Test name
Test status
Simulation time 307305280 ps
CPU time 3.92 seconds
Started Aug 12 04:43:11 PM PDT 24
Finished Aug 12 04:43:16 PM PDT 24
Peak memory 205232 kb
Host smart-cb54ecc7-b0c7-4f8e-b503-b732baf8f501
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2462391970 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_may_nack_vseq +en_cov=1 -cm line+cond+f
sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.i2c_host_may_nack.2462391970
Directory /workspace/20.i2c_host_may_nack/latest

Test location /workspace/coverage/default/20.i2c_host_mode_toggle.2780697183
Short name T1190
Test name
Test status
Simulation time 77220441 ps
CPU time 2.11 seconds
Started Aug 12 04:43:15 PM PDT 24
Finished Aug 12 04:43:17 PM PDT 24
Peak memory 213492 kb
Host smart-f83ed91a-ed13-410c-8fbd-b1063cabd2e2
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2780697183 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_mode_toggle_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.i2c_host_mode_toggle.2780697183
Directory /workspace/20.i2c_host_mode_toggle/latest

Test location /workspace/coverage/default/20.i2c_host_override.1337873405
Short name T1139
Test name
Test status
Simulation time 46492312 ps
CPU time 0.74 seconds
Started Aug 12 04:43:04 PM PDT 24
Finished Aug 12 04:43:05 PM PDT 24
Peak memory 205016 kb
Host smart-fd80bae4-7ac7-4260-9d6b-ac445e02f616
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1337873405 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_override_vseq +en_cov=1 -cm line+cond+f
sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.i2c_host_override.1337873405
Directory /workspace/20.i2c_host_override/latest

Test location /workspace/coverage/default/20.i2c_host_perf.2564212055
Short name T592
Test name
Test status
Simulation time 2883240472 ps
CPU time 72.88 seconds
Started Aug 12 04:43:04 PM PDT 24
Finished Aug 12 04:44:18 PM PDT 24
Peak memory 789508 kb
Host smart-0d0a87ca-de54-4afb-a968-859e04048bff
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2564212055 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_perf_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.i2c_host_perf.2564212055
Directory /workspace/20.i2c_host_perf/latest

Test location /workspace/coverage/default/20.i2c_host_perf_precise.2664389352
Short name T536
Test name
Test status
Simulation time 77846731 ps
CPU time 1.81 seconds
Started Aug 12 04:43:10 PM PDT 24
Finished Aug 12 04:43:12 PM PDT 24
Peak memory 223712 kb
Host smart-c210dfd5-e2d7-4466-bf80-c70ef19d6e8a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2664389352 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_perf_precise_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.i2c_host_perf_precise.2664389352
Directory /workspace/20.i2c_host_perf_precise/latest

Test location /workspace/coverage/default/20.i2c_host_smoke.610201987
Short name T1567
Test name
Test status
Simulation time 21280882675 ps
CPU time 97.9 seconds
Started Aug 12 04:43:03 PM PDT 24
Finished Aug 12 04:44:42 PM PDT 24
Peak memory 421172 kb
Host smart-741892ed-eefe-4fd0-8686-7ccff124108b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=610201987 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_smoke_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.i2c_host_smoke.610201987
Directory /workspace/20.i2c_host_smoke/latest

Test location /workspace/coverage/default/20.i2c_host_stretch_timeout.4284718043
Short name T462
Test name
Test status
Simulation time 2597384837 ps
CPU time 11.35 seconds
Started Aug 12 04:43:04 PM PDT 24
Finished Aug 12 04:43:16 PM PDT 24
Peak memory 221696 kb
Host smart-c067e65d-6644-449b-be33-cc14eb113c82
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4284718043 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_stretch_timeout_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.i2c_host_stretch_timeout.4284718043
Directory /workspace/20.i2c_host_stretch_timeout/latest

Test location /workspace/coverage/default/20.i2c_target_bad_addr.222609868
Short name T145
Test name
Test status
Simulation time 3793246263 ps
CPU time 5.69 seconds
Started Aug 12 04:43:13 PM PDT 24
Finished Aug 12 04:43:19 PM PDT 24
Peak memory 222132 kb
Host smart-e2b53f53-6eab-4e9e-8a61-d68e4c08d794
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +i2c_bad_addr_pct=50 +cdc_instrumentation_enabled=1 +UVM_
NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=222609868 -assert nopostproc +
UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_target_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.v
db -cm_log /dev/null -cm_name 20.i2c_target_bad_addr.222609868
Directory /workspace/20.i2c_target_bad_addr/latest

Test location /workspace/coverage/default/20.i2c_target_fifo_reset_acq.4130461083
Short name T830
Test name
Test status
Simulation time 206908223 ps
CPU time 1.04 seconds
Started Aug 12 04:43:03 PM PDT 24
Finished Aug 12 04:43:04 PM PDT 24
Peak memory 205292 kb
Host smart-70a8ebc4-5100-4c57-a808-f6517bba7085
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4130461083 -assert nopostproc +UVM_TESTNAME=i2c_bas
e_test +UVM_TEST_SEQ=i2c_target_fifo_reset_acq_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log
/dev/null -cm_name 20.i2c_target_fifo_reset_acq.4130461083
Directory /workspace/20.i2c_target_fifo_reset_acq/latest

Test location /workspace/coverage/default/20.i2c_target_fifo_reset_tx.2961412933
Short name T102
Test name
Test status
Simulation time 1086497804 ps
CPU time 1.14 seconds
Started Aug 12 04:43:15 PM PDT 24
Finished Aug 12 04:43:16 PM PDT 24
Peak memory 205272 kb
Host smart-3f192825-804f-4c60-aa67-f94ecd3b72a3
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2961412933 -assert nopostproc +UVM_TESTNAME=i2c_bas
e_test +UVM_TEST_SEQ=i2c_target_fifo_reset_tx_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /
dev/null -cm_name 20.i2c_target_fifo_reset_tx.2961412933
Directory /workspace/20.i2c_target_fifo_reset_tx/latest

Test location /workspace/coverage/default/20.i2c_target_fifo_watermarks_acq.2470237855
Short name T429
Test name
Test status
Simulation time 1191258311 ps
CPU time 2.01 seconds
Started Aug 12 04:43:13 PM PDT 24
Finished Aug 12 04:43:15 PM PDT 24
Peak memory 205136 kb
Host smart-ebdb1e7f-212d-4584-ad76-7a6aea5d164c
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2470237855 -assert nopostproc +UVM_TESTNAME=i2c_bas
e_test +UVM_TEST_SEQ=i2c_target_fifo_watermarks_acq_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm
_log /dev/null -cm_name 20.i2c_target_fifo_watermarks_acq.2470237855
Directory /workspace/20.i2c_target_fifo_watermarks_acq/latest

Test location /workspace/coverage/default/20.i2c_target_fifo_watermarks_tx.2127445747
Short name T1268
Test name
Test status
Simulation time 304676985 ps
CPU time 0.95 seconds
Started Aug 12 04:43:13 PM PDT 24
Finished Aug 12 04:43:14 PM PDT 24
Peak memory 205224 kb
Host smart-9ae76325-244e-4f37-8c06-b267d53b437a
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2127445747 -assert nopostproc +UVM_TESTNAME=i2c_bas
e_test +UVM_TEST_SEQ=i2c_target_fifo_watermarks_tx_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_
log /dev/null -cm_name 20.i2c_target_fifo_watermarks_tx.2127445747
Directory /workspace/20.i2c_target_fifo_watermarks_tx/latest

Test location /workspace/coverage/default/20.i2c_target_intr_smoke.2525223249
Short name T544
Test name
Test status
Simulation time 980126660 ps
CPU time 5.63 seconds
Started Aug 12 04:43:05 PM PDT 24
Finished Aug 12 04:43:11 PM PDT 24
Peak memory 218424 kb
Host smart-3a43b8ad-4cd6-4eea-96e5-92c007f5413a
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=200_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VER
BOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2525223249 -assert nopostproc +UVM_TESTNAME=i2c_ba
se_test +UVM_TEST_SEQ=i2c_target_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/nul
l -cm_name 20.i2c_target_intr_smoke.2525223249
Directory /workspace/20.i2c_target_intr_smoke/latest

Test location /workspace/coverage/default/20.i2c_target_nack_acqfull_addr.2371440249
Short name T1453
Test name
Test status
Simulation time 531966038 ps
CPU time 2.6 seconds
Started Aug 12 04:43:12 PM PDT 24
Finished Aug 12 04:43:15 PM PDT 24
Peak memory 205468 kb
Host smart-c29c1cca-0386-4e15-83f7-8e80fc7c73e1
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2371440249 -assert nopostproc +UVM_TESTNAME=i2c_bas
e_test +UVM_TEST_SEQ=i2c_target_nack_acqfull_addr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_l
og /dev/null -cm_name 20.i2c_target_nack_acqfull_addr.2371440249
Directory /workspace/20.i2c_target_nack_acqfull_addr/latest

Test location /workspace/coverage/default/20.i2c_target_nack_txstretch.448922582
Short name T882
Test name
Test status
Simulation time 599424585 ps
CPU time 1.44 seconds
Started Aug 12 04:43:12 PM PDT 24
Finished Aug 12 04:43:13 PM PDT 24
Peak memory 222192 kb
Host smart-40a41954-1cb0-49f5-bb03-e280ee0cd12f
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=448922582 -assert nopostproc +UVM_TESTNAME=i2c_base
_test +UVM_TEST_SEQ=i2c_target_nack_txstretch_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /
dev/null -cm_name 20.i2c_target_nack_txstretch.448922582
Directory /workspace/20.i2c_target_nack_txstretch/latest

Test location /workspace/coverage/default/20.i2c_target_perf.1552408127
Short name T1724
Test name
Test status
Simulation time 7240421136 ps
CPU time 3.94 seconds
Started Aug 12 04:43:15 PM PDT 24
Finished Aug 12 04:43:19 PM PDT 24
Peak memory 213736 kb
Host smart-e26fb2e0-5640-44c0-b99d-887bd06ac61c
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1552408127 -assert nopostproc +UVM_TESTNAME=i2c_bas
e_test +UVM_TEST_SEQ=i2c_target_perf_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null
-cm_name 20.i2c_target_perf.1552408127
Directory /workspace/20.i2c_target_perf/latest

Test location /workspace/coverage/default/20.i2c_target_smbus_maxlen.1619188439
Short name T503
Test name
Test status
Simulation time 824668973 ps
CPU time 2.43 seconds
Started Aug 12 04:43:14 PM PDT 24
Finished Aug 12 04:43:16 PM PDT 24
Peak memory 205228 kb
Host smart-dd48cd76-4f3b-4577-bfe3-2dc369573599
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1619188439 -assert nopostproc +UVM_TESTNAME=i2c_bas
e_test +UVM_TEST_SEQ=i2c_target_smbus_maxlen_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /d
ev/null -cm_name 20.i2c_target_smbus_maxlen.1619188439
Directory /workspace/20.i2c_target_smbus_maxlen/latest

Test location /workspace/coverage/default/20.i2c_target_smoke.3917647633
Short name T7
Test name
Test status
Simulation time 1966953810 ps
CPU time 16.32 seconds
Started Aug 12 04:43:04 PM PDT 24
Finished Aug 12 04:43:20 PM PDT 24
Peak memory 213652 kb
Host smart-6e8c73bc-8ba8-4e14-8551-c01caaa19140
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=100_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licq
ueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3917647633 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SE
Q=i2c_target_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.i2c_ta
rget_smoke.3917647633
Directory /workspace/20.i2c_target_smoke/latest

Test location /workspace/coverage/default/20.i2c_target_stress_all.910001216
Short name T1223
Test name
Test status
Simulation time 72499167656 ps
CPU time 3454.1 seconds
Started Aug 12 04:43:13 PM PDT 24
Finished Aug 12 05:40:47 PM PDT 24
Peak memory 9413148 kb
Host smart-ba3d516a-9085-4a6a-b2bc-6af0452e1116
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=300_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VER
BOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=910001216 -assert nopostproc +UVM_TESTNAME=i2c_bas
e_test +UVM_TEST_SEQ=i2c_target_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev
/null -cm_name 20.i2c_target_stress_all.910001216
Directory /workspace/20.i2c_target_stress_all/latest

Test location /workspace/coverage/default/20.i2c_target_stress_rd.1020952266
Short name T625
Test name
Test status
Simulation time 1299202188 ps
CPU time 24.29 seconds
Started Aug 12 04:43:04 PM PDT 24
Finished Aug 12 04:43:28 PM PDT 24
Peak memory 221764 kb
Host smart-9024b88f-c70b-4bb3-bf76-1e0a6ff35c59
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=100_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licq
ueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1020952266 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SE
Q=i2c_target_stress_rd_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.i2
c_target_stress_rd.1020952266
Directory /workspace/20.i2c_target_stress_rd/latest

Test location /workspace/coverage/default/20.i2c_target_stress_wr.95682401
Short name T914
Test name
Test status
Simulation time 9150716097 ps
CPU time 5.44 seconds
Started Aug 12 04:43:04 PM PDT 24
Finished Aug 12 04:43:10 PM PDT 24
Peak memory 205532 kb
Host smart-80a471c2-7385-4537-98fa-aadbc40724c7
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=600_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licq
ueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=95682401 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=
i2c_target_stress_wr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.i2c_
target_stress_wr.95682401
Directory /workspace/20.i2c_target_stress_wr/latest

Test location /workspace/coverage/default/20.i2c_target_stretch.26916989
Short name T433
Test name
Test status
Simulation time 2306627545 ps
CPU time 22.17 seconds
Started Aug 12 04:43:03 PM PDT 24
Finished Aug 12 04:43:25 PM PDT 24
Peak memory 308932 kb
Host smart-5aff6f56-d855-4312-b0a9-275d9b680404
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=400_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licq
ueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=26916989 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=
i2c_target_stretch_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.i2c_ta
rget_stretch.26916989
Directory /workspace/20.i2c_target_stretch/latest

Test location /workspace/coverage/default/20.i2c_target_timeout.733678367
Short name T586
Test name
Test status
Simulation time 1126667719 ps
CPU time 6.57 seconds
Started Aug 12 04:43:03 PM PDT 24
Finished Aug 12 04:43:10 PM PDT 24
Peak memory 219096 kb
Host smart-99da4c54-cd64-4913-b70d-06a5d0b9a081
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=50_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=733678367 -assert nopostproc +UVM_TESTNAME=i2c_base
_test +UVM_TEST_SEQ=i2c_target_timeout_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/nul
l -cm_name 20.i2c_target_timeout.733678367
Directory /workspace/20.i2c_target_timeout/latest

Test location /workspace/coverage/default/20.i2c_target_tx_stretch_ctrl.1597496404
Short name T1426
Test name
Test status
Simulation time 456946210 ps
CPU time 6.53 seconds
Started Aug 12 04:43:13 PM PDT 24
Finished Aug 12 04:43:19 PM PDT 24
Peak memory 214628 kb
Host smart-be23afca-d531-44cb-b67c-e684a29c5bb4
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1597496404 -assert nopostproc +UVM_TESTNAME=i2c_bas
e_test +UVM_TEST_SEQ=i2c_target_tx_stretch_ctrl_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log
/dev/null -cm_name 20.i2c_target_tx_stretch_ctrl.1597496404
Directory /workspace/20.i2c_target_tx_stretch_ctrl/latest

Test location /workspace/coverage/default/21.i2c_alert_test.3032866016
Short name T191
Test name
Test status
Simulation time 46885214 ps
CPU time 0.7 seconds
Started Aug 12 04:43:21 PM PDT 24
Finished Aug 12 04:43:22 PM PDT 24
Peak memory 204580 kb
Host smart-cef4084e-4a8f-459e-99dc-8583ab481d47
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3032866016 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_common_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.i2c_alert_test.3032866016
Directory /workspace/21.i2c_alert_test/latest

Test location /workspace/coverage/default/21.i2c_host_error_intr.1140029980
Short name T874
Test name
Test status
Simulation time 180094624 ps
CPU time 3.24 seconds
Started Aug 12 04:43:22 PM PDT 24
Finished Aug 12 04:43:25 PM PDT 24
Peak memory 235500 kb
Host smart-fcc9e5d9-87c6-4ad4-ade9-b6a0ed62ded1
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1140029980 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_error_intr_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.i2c_host_error_intr.1140029980
Directory /workspace/21.i2c_host_error_intr/latest

Test location /workspace/coverage/default/21.i2c_host_fifo_fmt_empty.1562040366
Short name T643
Test name
Test status
Simulation time 482124542 ps
CPU time 8 seconds
Started Aug 12 04:43:14 PM PDT 24
Finished Aug 12 04:43:22 PM PDT 24
Peak memory 292520 kb
Host smart-7bb1bc6b-4bc4-4e07-b5d7-29304a31e8d1
User root
Command /workspace/default/simv +test_timeout_ns=10_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1562040366 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_fifo_fmt_em
pty_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.i2c_host_fifo_fmt_emp
ty.1562040366
Directory /workspace/21.i2c_host_fifo_fmt_empty/latest

Test location /workspace/coverage/default/21.i2c_host_fifo_full.3427789453
Short name T387
Test name
Test status
Simulation time 3101758684 ps
CPU time 106.02 seconds
Started Aug 12 04:43:13 PM PDT 24
Finished Aug 12 04:44:59 PM PDT 24
Peak memory 575740 kb
Host smart-6e40dd32-0509-4d6f-9622-db727b371564
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3427789453 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_fifo_full_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.i2c_host_fifo_full.3427789453
Directory /workspace/21.i2c_host_fifo_full/latest

Test location /workspace/coverage/default/21.i2c_host_fifo_overflow.4137691631
Short name T1659
Test name
Test status
Simulation time 3325947918 ps
CPU time 57.38 seconds
Started Aug 12 04:43:12 PM PDT 24
Finished Aug 12 04:44:10 PM PDT 24
Peak memory 621872 kb
Host smart-e7c27f59-7e3a-4739-a7e5-a127ed572299
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4137691631 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_fifo_overflow_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.i2c_host_fifo_overflow.4137691631
Directory /workspace/21.i2c_host_fifo_overflow/latest

Test location /workspace/coverage/default/21.i2c_host_fifo_reset_fmt.4192616056
Short name T571
Test name
Test status
Simulation time 378108173 ps
CPU time 1.15 seconds
Started Aug 12 04:43:13 PM PDT 24
Finished Aug 12 04:43:15 PM PDT 24
Peak memory 205104 kb
Host smart-c9a57a7f-7afb-4203-a632-4a98fe985a89
User root
Command /workspace/default/simv +test_timeout_ns=10_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4192616056 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_fifo_reset_
fmt_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.i2c_host_fifo_reset_f
mt.4192616056
Directory /workspace/21.i2c_host_fifo_reset_fmt/latest

Test location /workspace/coverage/default/21.i2c_host_fifo_reset_rx.1352109365
Short name T907
Test name
Test status
Simulation time 367278974 ps
CPU time 4.74 seconds
Started Aug 12 04:43:12 PM PDT 24
Finished Aug 12 04:43:18 PM PDT 24
Peak memory 238120 kb
Host smart-bb3b6840-2981-4a50-a227-9993cb2d5fd9
User root
Command /workspace/default/simv +test_timeout_ns=10_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1352109365 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_fifo_reset_
rx_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.i2c_host_fifo_reset_rx
.1352109365
Directory /workspace/21.i2c_host_fifo_reset_rx/latest

Test location /workspace/coverage/default/21.i2c_host_fifo_watermark.2959247033
Short name T121
Test name
Test status
Simulation time 8774710889 ps
CPU time 120.65 seconds
Started Aug 12 04:43:15 PM PDT 24
Finished Aug 12 04:45:16 PM PDT 24
Peak memory 1323736 kb
Host smart-7c5102c1-b915-4d66-9001-eba57f5db485
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2959247033 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_fifo_watermark_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.i2c_host_fifo_watermark.2959247033
Directory /workspace/21.i2c_host_fifo_watermark/latest

Test location /workspace/coverage/default/21.i2c_host_may_nack.3766428332
Short name T968
Test name
Test status
Simulation time 438251790 ps
CPU time 17.81 seconds
Started Aug 12 04:43:19 PM PDT 24
Finished Aug 12 04:43:37 PM PDT 24
Peak memory 205116 kb
Host smart-cf84d4aa-4894-428e-8d66-9b8a2de28ca0
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3766428332 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_may_nack_vseq +en_cov=1 -cm line+cond+f
sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.i2c_host_may_nack.3766428332
Directory /workspace/21.i2c_host_may_nack/latest

Test location /workspace/coverage/default/21.i2c_host_mode_toggle.4037557462
Short name T276
Test name
Test status
Simulation time 238563252 ps
CPU time 2.08 seconds
Started Aug 12 04:43:19 PM PDT 24
Finished Aug 12 04:43:22 PM PDT 24
Peak memory 213428 kb
Host smart-143a3cc8-a7c0-4246-b065-9f3c0aa63bf9
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4037557462 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_mode_toggle_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.i2c_host_mode_toggle.4037557462
Directory /workspace/21.i2c_host_mode_toggle/latest

Test location /workspace/coverage/default/21.i2c_host_override.1427967750
Short name T540
Test name
Test status
Simulation time 47735319 ps
CPU time 0.66 seconds
Started Aug 12 04:43:16 PM PDT 24
Finished Aug 12 04:43:16 PM PDT 24
Peak memory 204868 kb
Host smart-de9bd24c-3d90-453e-8c21-11daedf6e2b4
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1427967750 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_override_vseq +en_cov=1 -cm line+cond+f
sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.i2c_host_override.1427967750
Directory /workspace/21.i2c_host_override/latest

Test location /workspace/coverage/default/21.i2c_host_perf.1271907287
Short name T1218
Test name
Test status
Simulation time 5666062555 ps
CPU time 80.53 seconds
Started Aug 12 04:43:12 PM PDT 24
Finished Aug 12 04:44:33 PM PDT 24
Peak memory 562344 kb
Host smart-cb49be87-df88-4d52-90da-8c821c689945
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1271907287 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_perf_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.i2c_host_perf.1271907287
Directory /workspace/21.i2c_host_perf/latest

Test location /workspace/coverage/default/21.i2c_host_perf_precise.2244122896
Short name T703
Test name
Test status
Simulation time 270434506 ps
CPU time 3.3 seconds
Started Aug 12 04:43:13 PM PDT 24
Finished Aug 12 04:43:16 PM PDT 24
Peak memory 205112 kb
Host smart-f48507cd-e466-4c70-b252-a22ae9cab069
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2244122896 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_perf_precise_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.i2c_host_perf_precise.2244122896
Directory /workspace/21.i2c_host_perf_precise/latest

Test location /workspace/coverage/default/21.i2c_host_smoke.142342893
Short name T1526
Test name
Test status
Simulation time 13471615849 ps
CPU time 18.12 seconds
Started Aug 12 04:43:11 PM PDT 24
Finished Aug 12 04:43:29 PM PDT 24
Peak memory 302432 kb
Host smart-bcc973ed-bc96-478e-a0ff-0050e0243d73
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=142342893 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_smoke_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.i2c_host_smoke.142342893
Directory /workspace/21.i2c_host_smoke/latest

Test location /workspace/coverage/default/21.i2c_host_stretch_timeout.2150312368
Short name T666
Test name
Test status
Simulation time 1567610969 ps
CPU time 33.58 seconds
Started Aug 12 04:43:12 PM PDT 24
Finished Aug 12 04:43:46 PM PDT 24
Peak memory 213508 kb
Host smart-99c93817-c16b-43f9-a982-619a6de0a1be
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2150312368 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_stretch_timeout_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.i2c_host_stretch_timeout.2150312368
Directory /workspace/21.i2c_host_stretch_timeout/latest

Test location /workspace/coverage/default/21.i2c_target_bad_addr.3517536737
Short name T1512
Test name
Test status
Simulation time 2283547267 ps
CPU time 6.47 seconds
Started Aug 12 04:43:21 PM PDT 24
Finished Aug 12 04:43:27 PM PDT 24
Peak memory 221996 kb
Host smart-cda5973a-0fcb-4e06-ab31-de8e88f8d9ba
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +i2c_bad_addr_pct=50 +cdc_instrumentation_enabled=1 +UVM_
NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3517536737 -assert nopostproc
+UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_target_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.
vdb -cm_log /dev/null -cm_name 21.i2c_target_bad_addr.3517536737
Directory /workspace/21.i2c_target_bad_addr/latest

Test location /workspace/coverage/default/21.i2c_target_fifo_reset_acq.916905917
Short name T1517
Test name
Test status
Simulation time 180305324 ps
CPU time 1.24 seconds
Started Aug 12 04:43:19 PM PDT 24
Finished Aug 12 04:43:20 PM PDT 24
Peak memory 205632 kb
Host smart-4a124823-3c61-4ced-a895-8a5709551825
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=916905917 -assert nopostproc +UVM_TESTNAME=i2c_base
_test +UVM_TEST_SEQ=i2c_target_fifo_reset_acq_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /
dev/null -cm_name 21.i2c_target_fifo_reset_acq.916905917
Directory /workspace/21.i2c_target_fifo_reset_acq/latest

Test location /workspace/coverage/default/21.i2c_target_fifo_reset_tx.3758904390
Short name T984
Test name
Test status
Simulation time 522842152 ps
CPU time 1.12 seconds
Started Aug 12 04:43:19 PM PDT 24
Finished Aug 12 04:43:21 PM PDT 24
Peak memory 205228 kb
Host smart-b0732bd9-f3e8-44d7-82bd-be40bda7c588
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3758904390 -assert nopostproc +UVM_TESTNAME=i2c_bas
e_test +UVM_TEST_SEQ=i2c_target_fifo_reset_tx_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /
dev/null -cm_name 21.i2c_target_fifo_reset_tx.3758904390
Directory /workspace/21.i2c_target_fifo_reset_tx/latest

Test location /workspace/coverage/default/21.i2c_target_fifo_watermarks_acq.2357924514
Short name T764
Test name
Test status
Simulation time 399725610 ps
CPU time 2.25 seconds
Started Aug 12 04:43:26 PM PDT 24
Finished Aug 12 04:43:29 PM PDT 24
Peak memory 205540 kb
Host smart-43918f8f-3546-46fa-9e1e-83960f0a6099
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2357924514 -assert nopostproc +UVM_TESTNAME=i2c_bas
e_test +UVM_TEST_SEQ=i2c_target_fifo_watermarks_acq_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm
_log /dev/null -cm_name 21.i2c_target_fifo_watermarks_acq.2357924514
Directory /workspace/21.i2c_target_fifo_watermarks_acq/latest

Test location /workspace/coverage/default/21.i2c_target_fifo_watermarks_tx.1814409274
Short name T1004
Test name
Test status
Simulation time 73353655 ps
CPU time 0.94 seconds
Started Aug 12 04:43:20 PM PDT 24
Finished Aug 12 04:43:21 PM PDT 24
Peak memory 205228 kb
Host smart-1565ab1d-2f4d-4265-b776-4bbba2a9a69c
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1814409274 -assert nopostproc +UVM_TESTNAME=i2c_bas
e_test +UVM_TEST_SEQ=i2c_target_fifo_watermarks_tx_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_
log /dev/null -cm_name 21.i2c_target_fifo_watermarks_tx.1814409274
Directory /workspace/21.i2c_target_fifo_watermarks_tx/latest

Test location /workspace/coverage/default/21.i2c_target_hrst.2187668185
Short name T1040
Test name
Test status
Simulation time 5207841823 ps
CPU time 2.64 seconds
Started Aug 12 04:43:22 PM PDT 24
Finished Aug 12 04:43:25 PM PDT 24
Peak memory 213700 kb
Host smart-5e7d3d65-bb5b-47ee-949e-871391f26d55
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2187668185 -assert nopostproc +UVM_TESTNAME=i2c_bas
e_test +UVM_TEST_SEQ=i2c_target_hrst_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null
-cm_name 21.i2c_target_hrst.2187668185
Directory /workspace/21.i2c_target_hrst/latest

Test location /workspace/coverage/default/21.i2c_target_intr_smoke.1747803503
Short name T334
Test name
Test status
Simulation time 3402985823 ps
CPU time 5.45 seconds
Started Aug 12 04:43:22 PM PDT 24
Finished Aug 12 04:43:28 PM PDT 24
Peak memory 213728 kb
Host smart-8bfd76ce-2eb4-455d-8256-a0db8a47370f
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=200_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VER
BOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1747803503 -assert nopostproc +UVM_TESTNAME=i2c_ba
se_test +UVM_TEST_SEQ=i2c_target_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/nul
l -cm_name 21.i2c_target_intr_smoke.1747803503
Directory /workspace/21.i2c_target_intr_smoke/latest

Test location /workspace/coverage/default/21.i2c_target_intr_stress_wr.3198423447
Short name T1516
Test name
Test status
Simulation time 31596096907 ps
CPU time 1140.3 seconds
Started Aug 12 04:43:22 PM PDT 24
Finished Aug 12 05:02:23 PM PDT 24
Peak memory 7850440 kb
Host smart-0e7e20cc-0edb-4210-86e2-542a79ca63ab
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=600_000_000 +use_intr_handler=1 +slow_acq=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNO
TES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3198423447 -assert nopostproc +UVM_TES
TNAME=i2c_base_test +UVM_TEST_SEQ=i2c_target_stress_wr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb
-cm_log /dev/null -cm_name 21.i2c_target_intr_stress_wr.3198423447
Directory /workspace/21.i2c_target_intr_stress_wr/latest

Test location /workspace/coverage/default/21.i2c_target_nack_acqfull.968822673
Short name T172
Test name
Test status
Simulation time 3664623789 ps
CPU time 2.64 seconds
Started Aug 12 04:43:18 PM PDT 24
Finished Aug 12 04:43:21 PM PDT 24
Peak memory 213712 kb
Host smart-7b59a476-6fcd-4d68-b144-c7d3bdaf458c
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=968822673 -assert nopostproc +UVM_TESTNAME=i2c_base
_test +UVM_TEST_SEQ=i2c_target_nack_acqfull_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /de
v/null -cm_name 21.i2c_target_nack_acqfull.968822673
Directory /workspace/21.i2c_target_nack_acqfull/latest

Test location /workspace/coverage/default/21.i2c_target_nack_acqfull_addr.2035226586
Short name T1662
Test name
Test status
Simulation time 1066691868 ps
CPU time 2.6 seconds
Started Aug 12 04:43:22 PM PDT 24
Finished Aug 12 04:43:25 PM PDT 24
Peak memory 205468 kb
Host smart-3f4f21ff-a35e-4122-b891-fb1d3e244344
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2035226586 -assert nopostproc +UVM_TESTNAME=i2c_bas
e_test +UVM_TEST_SEQ=i2c_target_nack_acqfull_addr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_l
og /dev/null -cm_name 21.i2c_target_nack_acqfull_addr.2035226586
Directory /workspace/21.i2c_target_nack_acqfull_addr/latest

Test location /workspace/coverage/default/21.i2c_target_perf.3199401401
Short name T1248
Test name
Test status
Simulation time 16756709027 ps
CPU time 7.22 seconds
Started Aug 12 04:43:22 PM PDT 24
Finished Aug 12 04:43:30 PM PDT 24
Peak memory 223172 kb
Host smart-22196699-ee31-4846-ba3b-5a497de366ad
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3199401401 -assert nopostproc +UVM_TESTNAME=i2c_bas
e_test +UVM_TEST_SEQ=i2c_target_perf_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null
-cm_name 21.i2c_target_perf.3199401401
Directory /workspace/21.i2c_target_perf/latest

Test location /workspace/coverage/default/21.i2c_target_smbus_maxlen.255442953
Short name T1645
Test name
Test status
Simulation time 726129219 ps
CPU time 2.43 seconds
Started Aug 12 04:43:22 PM PDT 24
Finished Aug 12 04:43:25 PM PDT 24
Peak memory 205236 kb
Host smart-b97fee78-d15b-488f-9c63-f5c768e89faa
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=255442953 -assert nopostproc +UVM_TESTNAME=i2c_base
_test +UVM_TEST_SEQ=i2c_target_smbus_maxlen_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /de
v/null -cm_name 21.i2c_target_smbus_maxlen.255442953
Directory /workspace/21.i2c_target_smbus_maxlen/latest

Test location /workspace/coverage/default/21.i2c_target_smoke.658991735
Short name T431
Test name
Test status
Simulation time 4004357295 ps
CPU time 36 seconds
Started Aug 12 04:43:20 PM PDT 24
Finished Aug 12 04:43:56 PM PDT 24
Peak memory 213724 kb
Host smart-8aab9501-8ff8-4f97-9fb6-f14625ad057e
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=100_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licq
ueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=658991735 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ
=i2c_target_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.i2c_tar
get_smoke.658991735
Directory /workspace/21.i2c_target_smoke/latest

Test location /workspace/coverage/default/21.i2c_target_stress_all.4072542765
Short name T382
Test name
Test status
Simulation time 55220790076 ps
CPU time 130.86 seconds
Started Aug 12 04:43:25 PM PDT 24
Finished Aug 12 04:45:36 PM PDT 24
Peak memory 1221364 kb
Host smart-73d2e964-6adb-4597-a811-662850442d3d
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=300_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VER
BOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4072542765 -assert nopostproc +UVM_TESTNAME=i2c_ba
se_test +UVM_TEST_SEQ=i2c_target_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /de
v/null -cm_name 21.i2c_target_stress_all.4072542765
Directory /workspace/21.i2c_target_stress_all/latest

Test location /workspace/coverage/default/21.i2c_target_stress_rd.850925498
Short name T280
Test name
Test status
Simulation time 1543814053 ps
CPU time 14.36 seconds
Started Aug 12 04:43:20 PM PDT 24
Finished Aug 12 04:43:34 PM PDT 24
Peak memory 213688 kb
Host smart-796d7658-7ef9-450f-bde2-7c26d3dc8b2e
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=100_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licq
ueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=850925498 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ
=i2c_target_stress_rd_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.i2c
_target_stress_rd.850925498
Directory /workspace/21.i2c_target_stress_rd/latest

Test location /workspace/coverage/default/21.i2c_target_stress_wr.1814258531
Short name T1428
Test name
Test status
Simulation time 18094519028 ps
CPU time 34.09 seconds
Started Aug 12 04:43:24 PM PDT 24
Finished Aug 12 04:43:58 PM PDT 24
Peak memory 205496 kb
Host smart-db8c718d-4f75-441a-b74c-a05df1ba5d66
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=600_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licq
ueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1814258531 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SE
Q=i2c_target_stress_wr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.i2
c_target_stress_wr.1814258531
Directory /workspace/21.i2c_target_stress_wr/latest

Test location /workspace/coverage/default/21.i2c_target_stretch.758188411
Short name T1133
Test name
Test status
Simulation time 2843169023 ps
CPU time 109.79 seconds
Started Aug 12 04:43:20 PM PDT 24
Finished Aug 12 04:45:10 PM PDT 24
Peak memory 697660 kb
Host smart-e03ce839-884d-4283-82c9-6e915f54fd0c
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=400_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licq
ueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=758188411 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ
=i2c_target_stretch_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.i2c_t
arget_stretch.758188411
Directory /workspace/21.i2c_target_stretch/latest

Test location /workspace/coverage/default/21.i2c_target_timeout.2024682860
Short name T724
Test name
Test status
Simulation time 1614604888 ps
CPU time 8.29 seconds
Started Aug 12 04:43:22 PM PDT 24
Finished Aug 12 04:43:31 PM PDT 24
Peak memory 213624 kb
Host smart-1307f216-7038-4e55-bd7e-ea502caace6e
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=50_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2024682860 -assert nopostproc +UVM_TESTNAME=i2c_bas
e_test +UVM_TEST_SEQ=i2c_target_timeout_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/nu
ll -cm_name 21.i2c_target_timeout.2024682860
Directory /workspace/21.i2c_target_timeout/latest

Test location /workspace/coverage/default/22.i2c_alert_test.3490796543
Short name T1189
Test name
Test status
Simulation time 36474866 ps
CPU time 0.66 seconds
Started Aug 12 04:43:21 PM PDT 24
Finished Aug 12 04:43:22 PM PDT 24
Peak memory 204372 kb
Host smart-164deef8-9c94-4029-aed2-707e84153ac2
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3490796543 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_common_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.i2c_alert_test.3490796543
Directory /workspace/22.i2c_alert_test/latest

Test location /workspace/coverage/default/22.i2c_host_error_intr.3346066868
Short name T852
Test name
Test status
Simulation time 101963736 ps
CPU time 1.85 seconds
Started Aug 12 04:43:21 PM PDT 24
Finished Aug 12 04:43:23 PM PDT 24
Peak memory 213528 kb
Host smart-441c82e3-e50a-4b4a-8aaa-8e532db5e8aa
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3346066868 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_error_intr_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.i2c_host_error_intr.3346066868
Directory /workspace/22.i2c_host_error_intr/latest

Test location /workspace/coverage/default/22.i2c_host_fifo_fmt_empty.1119506106
Short name T333
Test name
Test status
Simulation time 812925794 ps
CPU time 20.88 seconds
Started Aug 12 04:43:22 PM PDT 24
Finished Aug 12 04:43:43 PM PDT 24
Peak memory 295068 kb
Host smart-fd41d4b4-a842-4631-ad70-ffeeea00c03e
User root
Command /workspace/default/simv +test_timeout_ns=10_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1119506106 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_fifo_fmt_em
pty_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.i2c_host_fifo_fmt_emp
ty.1119506106
Directory /workspace/22.i2c_host_fifo_fmt_empty/latest

Test location /workspace/coverage/default/22.i2c_host_fifo_full.3085677888
Short name T800
Test name
Test status
Simulation time 8813024692 ps
CPU time 53.81 seconds
Started Aug 12 04:43:23 PM PDT 24
Finished Aug 12 04:44:17 PM PDT 24
Peak memory 418320 kb
Host smart-545571eb-05c2-4b53-89b7-01ebea0925f3
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3085677888 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_fifo_full_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.i2c_host_fifo_full.3085677888
Directory /workspace/22.i2c_host_fifo_full/latest

Test location /workspace/coverage/default/22.i2c_host_fifo_overflow.2247827576
Short name T1101
Test name
Test status
Simulation time 4850690760 ps
CPU time 57.97 seconds
Started Aug 12 04:43:24 PM PDT 24
Finished Aug 12 04:44:22 PM PDT 24
Peak memory 607264 kb
Host smart-4e793ea3-e750-40c7-8a1b-ea6109f5032e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2247827576 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_fifo_overflow_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.i2c_host_fifo_overflow.2247827576
Directory /workspace/22.i2c_host_fifo_overflow/latest

Test location /workspace/coverage/default/22.i2c_host_fifo_reset_rx.452576315
Short name T379
Test name
Test status
Simulation time 136996402 ps
CPU time 3.08 seconds
Started Aug 12 04:43:22 PM PDT 24
Finished Aug 12 04:43:25 PM PDT 24
Peak memory 205304 kb
Host smart-e4008b2a-58d0-4223-aa85-b1defa98dbdf
User root
Command /workspace/default/simv +test_timeout_ns=10_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=452576315 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_fifo_reset_r
x_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.i2c_host_fifo_reset_rx.
452576315
Directory /workspace/22.i2c_host_fifo_reset_rx/latest

Test location /workspace/coverage/default/22.i2c_host_fifo_watermark.1599318098
Short name T1220
Test name
Test status
Simulation time 41390755659 ps
CPU time 144.81 seconds
Started Aug 12 04:43:21 PM PDT 24
Finished Aug 12 04:45:46 PM PDT 24
Peak memory 1343688 kb
Host smart-4d5cc4e9-b557-48ba-9680-2926f34c60fb
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1599318098 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_fifo_watermark_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.i2c_host_fifo_watermark.1599318098
Directory /workspace/22.i2c_host_fifo_watermark/latest

Test location /workspace/coverage/default/22.i2c_host_may_nack.3477414456
Short name T142
Test name
Test status
Simulation time 746927079 ps
CPU time 14.64 seconds
Started Aug 12 04:43:26 PM PDT 24
Finished Aug 12 04:43:41 PM PDT 24
Peak memory 205196 kb
Host smart-ab84ae97-ae81-4b47-9026-9a6098bcf50d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3477414456 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_may_nack_vseq +en_cov=1 -cm line+cond+f
sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.i2c_host_may_nack.3477414456
Directory /workspace/22.i2c_host_may_nack/latest

Test location /workspace/coverage/default/22.i2c_host_override.1586065838
Short name T733
Test name
Test status
Simulation time 53193243 ps
CPU time 0.71 seconds
Started Aug 12 04:43:20 PM PDT 24
Finished Aug 12 04:43:21 PM PDT 24
Peak memory 204892 kb
Host smart-58cf440a-afd4-4356-8076-4ddbf8328291
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1586065838 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_override_vseq +en_cov=1 -cm line+cond+f
sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.i2c_host_override.1586065838
Directory /workspace/22.i2c_host_override/latest

Test location /workspace/coverage/default/22.i2c_host_perf.225866208
Short name T36
Test name
Test status
Simulation time 2707032564 ps
CPU time 104.6 seconds
Started Aug 12 04:43:21 PM PDT 24
Finished Aug 12 04:45:05 PM PDT 24
Peak memory 214064 kb
Host smart-93a81c84-50d5-414b-b14d-5a0a1c2053c6
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=225866208 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_perf_vseq +en_cov=1 -cm line+cond+fsm+tg
l+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.i2c_host_perf.225866208
Directory /workspace/22.i2c_host_perf/latest

Test location /workspace/coverage/default/22.i2c_host_perf_precise.3922222444
Short name T1126
Test name
Test status
Simulation time 279356290 ps
CPU time 2.47 seconds
Started Aug 12 04:43:21 PM PDT 24
Finished Aug 12 04:43:24 PM PDT 24
Peak memory 222904 kb
Host smart-eecff8c4-c282-47a4-8888-48e8998b5161
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3922222444 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_perf_precise_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.i2c_host_perf_precise.3922222444
Directory /workspace/22.i2c_host_perf_precise/latest

Test location /workspace/coverage/default/22.i2c_host_smoke.2647177017
Short name T998
Test name
Test status
Simulation time 1689144037 ps
CPU time 78.73 seconds
Started Aug 12 04:43:26 PM PDT 24
Finished Aug 12 04:44:45 PM PDT 24
Peak memory 350424 kb
Host smart-45b75424-252b-44bf-9fc5-9e08d1dcaa9a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2647177017 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_smoke_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.i2c_host_smoke.2647177017
Directory /workspace/22.i2c_host_smoke/latest

Test location /workspace/coverage/default/22.i2c_host_stretch_timeout.2744804760
Short name T1493
Test name
Test status
Simulation time 1559019683 ps
CPU time 12.49 seconds
Started Aug 12 04:43:22 PM PDT 24
Finished Aug 12 04:43:35 PM PDT 24
Peak memory 221612 kb
Host smart-0110c34e-45db-4efc-a504-9b076e0d42be
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2744804760 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_stretch_timeout_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.i2c_host_stretch_timeout.2744804760
Directory /workspace/22.i2c_host_stretch_timeout/latest

Test location /workspace/coverage/default/22.i2c_target_bad_addr.4037309342
Short name T1362
Test name
Test status
Simulation time 3240247009 ps
CPU time 4.01 seconds
Started Aug 12 04:43:25 PM PDT 24
Finished Aug 12 04:43:29 PM PDT 24
Peak memory 213812 kb
Host smart-5ee4a0c6-2bc4-4b7b-9e9d-8ba2fd3287a7
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +i2c_bad_addr_pct=50 +cdc_instrumentation_enabled=1 +UVM_
NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4037309342 -assert nopostproc
+UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_target_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.
vdb -cm_log /dev/null -cm_name 22.i2c_target_bad_addr.4037309342
Directory /workspace/22.i2c_target_bad_addr/latest

Test location /workspace/coverage/default/22.i2c_target_fifo_reset_acq.3526071930
Short name T868
Test name
Test status
Simulation time 198587000 ps
CPU time 1.35 seconds
Started Aug 12 04:43:26 PM PDT 24
Finished Aug 12 04:43:28 PM PDT 24
Peak memory 206232 kb
Host smart-274d05f6-1af4-4ffd-a63e-b4d895cde72f
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3526071930 -assert nopostproc +UVM_TESTNAME=i2c_bas
e_test +UVM_TEST_SEQ=i2c_target_fifo_reset_acq_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log
/dev/null -cm_name 22.i2c_target_fifo_reset_acq.3526071930
Directory /workspace/22.i2c_target_fifo_reset_acq/latest

Test location /workspace/coverage/default/22.i2c_target_fifo_reset_tx.140232689
Short name T1146
Test name
Test status
Simulation time 145564468 ps
CPU time 1.05 seconds
Started Aug 12 04:43:21 PM PDT 24
Finished Aug 12 04:43:23 PM PDT 24
Peak memory 213460 kb
Host smart-4d4f0d92-18ea-4892-b6a1-a2f19ad4fa44
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=140232689 -assert nopostproc +UVM_TESTNAME=i2c_base
_test +UVM_TEST_SEQ=i2c_target_fifo_reset_tx_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /d
ev/null -cm_name 22.i2c_target_fifo_reset_tx.140232689
Directory /workspace/22.i2c_target_fifo_reset_tx/latest

Test location /workspace/coverage/default/22.i2c_target_fifo_watermarks_acq.1765850760
Short name T1660
Test name
Test status
Simulation time 4196688070 ps
CPU time 2.62 seconds
Started Aug 12 04:43:21 PM PDT 24
Finished Aug 12 04:43:23 PM PDT 24
Peak memory 205532 kb
Host smart-11e9fbe0-fa68-493d-a205-28c4c3aae354
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1765850760 -assert nopostproc +UVM_TESTNAME=i2c_bas
e_test +UVM_TEST_SEQ=i2c_target_fifo_watermarks_acq_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm
_log /dev/null -cm_name 22.i2c_target_fifo_watermarks_acq.1765850760
Directory /workspace/22.i2c_target_fifo_watermarks_acq/latest

Test location /workspace/coverage/default/22.i2c_target_fifo_watermarks_tx.1984275300
Short name T1654
Test name
Test status
Simulation time 572422951 ps
CPU time 1.56 seconds
Started Aug 12 04:43:26 PM PDT 24
Finished Aug 12 04:43:27 PM PDT 24
Peak memory 205260 kb
Host smart-3bb69395-a9f8-44b1-b850-a5dc4e3c2e2d
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1984275300 -assert nopostproc +UVM_TESTNAME=i2c_bas
e_test +UVM_TEST_SEQ=i2c_target_fifo_watermarks_tx_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_
log /dev/null -cm_name 22.i2c_target_fifo_watermarks_tx.1984275300
Directory /workspace/22.i2c_target_fifo_watermarks_tx/latest

Test location /workspace/coverage/default/22.i2c_target_hrst.4036697519
Short name T1468
Test name
Test status
Simulation time 378284261 ps
CPU time 2.77 seconds
Started Aug 12 04:43:20 PM PDT 24
Finished Aug 12 04:43:23 PM PDT 24
Peak memory 217356 kb
Host smart-4c0f1074-dcb9-4a27-be53-4a10cc3060c1
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4036697519 -assert nopostproc +UVM_TESTNAME=i2c_bas
e_test +UVM_TEST_SEQ=i2c_target_hrst_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null
-cm_name 22.i2c_target_hrst.4036697519
Directory /workspace/22.i2c_target_hrst/latest

Test location /workspace/coverage/default/22.i2c_target_intr_smoke.2341618396
Short name T639
Test name
Test status
Simulation time 1185230132 ps
CPU time 7.45 seconds
Started Aug 12 04:43:20 PM PDT 24
Finished Aug 12 04:43:27 PM PDT 24
Peak memory 220544 kb
Host smart-2a5c21f0-f19d-467c-8e80-c1b5f331b2ce
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=200_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VER
BOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2341618396 -assert nopostproc +UVM_TESTNAME=i2c_ba
se_test +UVM_TEST_SEQ=i2c_target_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/nul
l -cm_name 22.i2c_target_intr_smoke.2341618396
Directory /workspace/22.i2c_target_intr_smoke/latest

Test location /workspace/coverage/default/22.i2c_target_intr_stress_wr.620887313
Short name T785
Test name
Test status
Simulation time 3456198365 ps
CPU time 5.74 seconds
Started Aug 12 04:43:21 PM PDT 24
Finished Aug 12 04:43:27 PM PDT 24
Peak memory 205556 kb
Host smart-bb7e6294-45a8-41d4-a9bd-b9f6396f624e
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=600_000_000 +use_intr_handler=1 +slow_acq=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNO
TES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=620887313 -assert nopostproc +UVM_TEST
NAME=i2c_base_test +UVM_TEST_SEQ=i2c_target_stress_wr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -
cm_log /dev/null -cm_name 22.i2c_target_intr_stress_wr.620887313
Directory /workspace/22.i2c_target_intr_stress_wr/latest

Test location /workspace/coverage/default/22.i2c_target_nack_acqfull.632874511
Short name T443
Test name
Test status
Simulation time 594618784 ps
CPU time 3.08 seconds
Started Aug 12 04:43:25 PM PDT 24
Finished Aug 12 04:43:28 PM PDT 24
Peak memory 213684 kb
Host smart-6c05781f-d6ad-49ae-9d09-a7ceb8eaf20e
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=632874511 -assert nopostproc +UVM_TESTNAME=i2c_base
_test +UVM_TEST_SEQ=i2c_target_nack_acqfull_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /de
v/null -cm_name 22.i2c_target_nack_acqfull.632874511
Directory /workspace/22.i2c_target_nack_acqfull/latest

Test location /workspace/coverage/default/22.i2c_target_nack_acqfull_addr.61562643
Short name T1343
Test name
Test status
Simulation time 553541555 ps
CPU time 2.82 seconds
Started Aug 12 04:43:24 PM PDT 24
Finished Aug 12 04:43:27 PM PDT 24
Peak memory 205444 kb
Host smart-e7336437-2008-4f94-8fdd-4741187f6d8e
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=61562643 -assert nopostproc +UVM_TESTNAME=i2c_base_
test +UVM_TEST_SEQ=i2c_target_nack_acqfull_addr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log
/dev/null -cm_name 22.i2c_target_nack_acqfull_addr.61562643
Directory /workspace/22.i2c_target_nack_acqfull_addr/latest

Test location /workspace/coverage/default/22.i2c_target_perf.1725938988
Short name T228
Test name
Test status
Simulation time 2659003114 ps
CPU time 5.02 seconds
Started Aug 12 04:43:26 PM PDT 24
Finished Aug 12 04:43:31 PM PDT 24
Peak memory 221996 kb
Host smart-feb46a17-8c2e-41ab-98cc-b1d63d815339
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1725938988 -assert nopostproc +UVM_TESTNAME=i2c_bas
e_test +UVM_TEST_SEQ=i2c_target_perf_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null
-cm_name 22.i2c_target_perf.1725938988
Directory /workspace/22.i2c_target_perf/latest

Test location /workspace/coverage/default/22.i2c_target_smbus_maxlen.1423181487
Short name T1632
Test name
Test status
Simulation time 2285998027 ps
CPU time 2.53 seconds
Started Aug 12 04:43:24 PM PDT 24
Finished Aug 12 04:43:27 PM PDT 24
Peak memory 205268 kb
Host smart-c7939436-81ac-40e6-828c-9e96ce4aec5f
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1423181487 -assert nopostproc +UVM_TESTNAME=i2c_bas
e_test +UVM_TEST_SEQ=i2c_target_smbus_maxlen_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /d
ev/null -cm_name 22.i2c_target_smbus_maxlen.1423181487
Directory /workspace/22.i2c_target_smbus_maxlen/latest

Test location /workspace/coverage/default/22.i2c_target_smoke.4204819311
Short name T1588
Test name
Test status
Simulation time 4640893413 ps
CPU time 17.98 seconds
Started Aug 12 04:43:26 PM PDT 24
Finished Aug 12 04:43:44 PM PDT 24
Peak memory 213748 kb
Host smart-79a7f489-7eea-4ed7-a8e6-90e8fc936b36
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=100_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licq
ueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4204819311 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SE
Q=i2c_target_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.i2c_ta
rget_smoke.4204819311
Directory /workspace/22.i2c_target_smoke/latest

Test location /workspace/coverage/default/22.i2c_target_stress_all.2553853790
Short name T1201
Test name
Test status
Simulation time 41810476368 ps
CPU time 50.26 seconds
Started Aug 12 04:43:25 PM PDT 24
Finished Aug 12 04:44:16 PM PDT 24
Peak memory 238424 kb
Host smart-acb07fe4-f881-4b3a-8b9b-c85d040f2e49
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=300_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VER
BOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2553853790 -assert nopostproc +UVM_TESTNAME=i2c_ba
se_test +UVM_TEST_SEQ=i2c_target_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /de
v/null -cm_name 22.i2c_target_stress_all.2553853790
Directory /workspace/22.i2c_target_stress_all/latest

Test location /workspace/coverage/default/22.i2c_target_stress_rd.3577530230
Short name T281
Test name
Test status
Simulation time 1199946602 ps
CPU time 9.65 seconds
Started Aug 12 04:43:27 PM PDT 24
Finished Aug 12 04:43:37 PM PDT 24
Peak memory 218528 kb
Host smart-f1aa43ea-af56-47b3-8858-181080342d4c
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=100_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licq
ueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3577530230 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SE
Q=i2c_target_stress_rd_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.i2
c_target_stress_rd.3577530230
Directory /workspace/22.i2c_target_stress_rd/latest

Test location /workspace/coverage/default/22.i2c_target_stress_wr.3059157521
Short name T952
Test name
Test status
Simulation time 26748666124 ps
CPU time 133.54 seconds
Started Aug 12 04:43:23 PM PDT 24
Finished Aug 12 04:45:37 PM PDT 24
Peak memory 1815116 kb
Host smart-63967f0d-f137-4aa8-929d-88014a4cbc51
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=600_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licq
ueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3059157521 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SE
Q=i2c_target_stress_wr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.i2
c_target_stress_wr.3059157521
Directory /workspace/22.i2c_target_stress_wr/latest

Test location /workspace/coverage/default/22.i2c_target_timeout.2097362216
Short name T449
Test name
Test status
Simulation time 1267253784 ps
CPU time 7.68 seconds
Started Aug 12 04:43:25 PM PDT 24
Finished Aug 12 04:43:33 PM PDT 24
Peak memory 221904 kb
Host smart-36671da2-21bd-4279-8a0b-ea838ce4030e
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=50_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2097362216 -assert nopostproc +UVM_TESTNAME=i2c_bas
e_test +UVM_TEST_SEQ=i2c_target_timeout_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/nu
ll -cm_name 22.i2c_target_timeout.2097362216
Directory /workspace/22.i2c_target_timeout/latest

Test location /workspace/coverage/default/22.i2c_target_tx_stretch_ctrl.1780826520
Short name T304
Test name
Test status
Simulation time 441818759 ps
CPU time 5.84 seconds
Started Aug 12 04:43:19 PM PDT 24
Finished Aug 12 04:43:25 PM PDT 24
Peak memory 213648 kb
Host smart-50380775-13e9-4d6c-b4f6-59c6b8acc887
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1780826520 -assert nopostproc +UVM_TESTNAME=i2c_bas
e_test +UVM_TEST_SEQ=i2c_target_tx_stretch_ctrl_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log
/dev/null -cm_name 22.i2c_target_tx_stretch_ctrl.1780826520
Directory /workspace/22.i2c_target_tx_stretch_ctrl/latest

Test location /workspace/coverage/default/23.i2c_alert_test.1896107090
Short name T782
Test name
Test status
Simulation time 40777137 ps
CPU time 0.64 seconds
Started Aug 12 04:43:32 PM PDT 24
Finished Aug 12 04:43:33 PM PDT 24
Peak memory 204816 kb
Host smart-408b68e7-bc09-4962-b753-10ec8123ba46
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1896107090 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_common_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.i2c_alert_test.1896107090
Directory /workspace/23.i2c_alert_test/latest

Test location /workspace/coverage/default/23.i2c_host_error_intr.715966862
Short name T1539
Test name
Test status
Simulation time 1084787536 ps
CPU time 3.08 seconds
Started Aug 12 04:43:30 PM PDT 24
Finished Aug 12 04:43:33 PM PDT 24
Peak memory 235796 kb
Host smart-a5808b6a-22d6-40a6-a749-a545b8da832c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=715966862 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_error_intr_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.i2c_host_error_intr.715966862
Directory /workspace/23.i2c_host_error_intr/latest

Test location /workspace/coverage/default/23.i2c_host_fifo_fmt_empty.3585618883
Short name T1275
Test name
Test status
Simulation time 348119727 ps
CPU time 6.84 seconds
Started Aug 12 04:43:29 PM PDT 24
Finished Aug 12 04:43:36 PM PDT 24
Peak memory 280560 kb
Host smart-2ca3149e-ff1a-4db5-93e6-77c2f313642d
User root
Command /workspace/default/simv +test_timeout_ns=10_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3585618883 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_fifo_fmt_em
pty_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.i2c_host_fifo_fmt_emp
ty.3585618883
Directory /workspace/23.i2c_host_fifo_fmt_empty/latest

Test location /workspace/coverage/default/23.i2c_host_fifo_full.64512473
Short name T1617
Test name
Test status
Simulation time 2886127644 ps
CPU time 74.91 seconds
Started Aug 12 04:43:28 PM PDT 24
Finished Aug 12 04:44:43 PM PDT 24
Peak memory 364684 kb
Host smart-d8246e01-808c-48a5-991b-9f9630f5eb6e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=64512473 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_fifo_full_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.i2c_host_fifo_full.64512473
Directory /workspace/23.i2c_host_fifo_full/latest

Test location /workspace/coverage/default/23.i2c_host_fifo_overflow.4018104834
Short name T485
Test name
Test status
Simulation time 1570265208 ps
CPU time 72.47 seconds
Started Aug 12 04:43:31 PM PDT 24
Finished Aug 12 04:44:44 PM PDT 24
Peak memory 459560 kb
Host smart-1f679ba5-7f18-420c-9460-818f475cd9f5
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4018104834 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_fifo_overflow_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.i2c_host_fifo_overflow.4018104834
Directory /workspace/23.i2c_host_fifo_overflow/latest

Test location /workspace/coverage/default/23.i2c_host_fifo_reset_fmt.2508527238
Short name T629
Test name
Test status
Simulation time 100646725 ps
CPU time 1.06 seconds
Started Aug 12 04:43:30 PM PDT 24
Finished Aug 12 04:43:31 PM PDT 24
Peak memory 204964 kb
Host smart-c768b9f5-7542-40e3-8ecb-aa414159345a
User root
Command /workspace/default/simv +test_timeout_ns=10_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2508527238 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_fifo_reset_
fmt_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.i2c_host_fifo_reset_f
mt.2508527238
Directory /workspace/23.i2c_host_fifo_reset_fmt/latest

Test location /workspace/coverage/default/23.i2c_host_fifo_reset_rx.1498097910
Short name T1436
Test name
Test status
Simulation time 332448740 ps
CPU time 8.68 seconds
Started Aug 12 04:43:31 PM PDT 24
Finished Aug 12 04:43:40 PM PDT 24
Peak memory 229988 kb
Host smart-e0d6d77c-17a0-41bb-b7b4-4ef4731fa56e
User root
Command /workspace/default/simv +test_timeout_ns=10_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1498097910 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_fifo_reset_
rx_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.i2c_host_fifo_reset_rx
.1498097910
Directory /workspace/23.i2c_host_fifo_reset_rx/latest

Test location /workspace/coverage/default/23.i2c_host_fifo_watermark.931256649
Short name T432
Test name
Test status
Simulation time 6617228196 ps
CPU time 293.27 seconds
Started Aug 12 04:43:32 PM PDT 24
Finished Aug 12 04:48:26 PM PDT 24
Peak memory 1071008 kb
Host smart-66e342f5-c536-4dfb-970d-f1411a34ec5e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=931256649 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_fifo_watermark_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.i2c_host_fifo_watermark.931256649
Directory /workspace/23.i2c_host_fifo_watermark/latest

Test location /workspace/coverage/default/23.i2c_host_may_nack.1700533931
Short name T635
Test name
Test status
Simulation time 685087636 ps
CPU time 13.51 seconds
Started Aug 12 04:43:30 PM PDT 24
Finished Aug 12 04:43:43 PM PDT 24
Peak memory 205256 kb
Host smart-bbda0c88-0ab4-4cc2-b1f8-bb213d1dc306
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1700533931 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_may_nack_vseq +en_cov=1 -cm line+cond+f
sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.i2c_host_may_nack.1700533931
Directory /workspace/23.i2c_host_may_nack/latest

Test location /workspace/coverage/default/23.i2c_host_mode_toggle.3729913275
Short name T13
Test name
Test status
Simulation time 883988247 ps
CPU time 4.34 seconds
Started Aug 12 04:43:29 PM PDT 24
Finished Aug 12 04:43:34 PM PDT 24
Peak memory 205212 kb
Host smart-f7052eaa-6c40-4a25-b3fc-65e2a9fb9ee0
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3729913275 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_mode_toggle_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.i2c_host_mode_toggle.3729913275
Directory /workspace/23.i2c_host_mode_toggle/latest

Test location /workspace/coverage/default/23.i2c_host_override.1749158911
Short name T648
Test name
Test status
Simulation time 262409502 ps
CPU time 0.72 seconds
Started Aug 12 04:43:34 PM PDT 24
Finished Aug 12 04:43:35 PM PDT 24
Peak memory 204936 kb
Host smart-b2184009-e5ae-4587-9338-b4279d047321
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1749158911 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_override_vseq +en_cov=1 -cm line+cond+f
sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.i2c_host_override.1749158911
Directory /workspace/23.i2c_host_override/latest

Test location /workspace/coverage/default/23.i2c_host_perf.2410331196
Short name T798
Test name
Test status
Simulation time 28074179702 ps
CPU time 241.64 seconds
Started Aug 12 04:43:30 PM PDT 24
Finished Aug 12 04:47:32 PM PDT 24
Peak memory 221548 kb
Host smart-a6983134-3736-4104-8ea9-7164b0071042
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2410331196 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_perf_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.i2c_host_perf.2410331196
Directory /workspace/23.i2c_host_perf/latest

Test location /workspace/coverage/default/23.i2c_host_perf_precise.2299252065
Short name T3
Test name
Test status
Simulation time 6848059238 ps
CPU time 34.4 seconds
Started Aug 12 04:43:30 PM PDT 24
Finished Aug 12 04:44:05 PM PDT 24
Peak memory 365360 kb
Host smart-8f9dce37-c9d7-40a2-bf87-742498da01e2
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2299252065 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_perf_precise_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.i2c_host_perf_precise.2299252065
Directory /workspace/23.i2c_host_perf_precise/latest

Test location /workspace/coverage/default/23.i2c_host_smoke.1372261573
Short name T605
Test name
Test status
Simulation time 3963735232 ps
CPU time 27.2 seconds
Started Aug 12 04:43:21 PM PDT 24
Finished Aug 12 04:43:49 PM PDT 24
Peak memory 349588 kb
Host smart-4870ebd4-c45c-4d0d-b500-4c014a6f2224
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1372261573 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_smoke_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.i2c_host_smoke.1372261573
Directory /workspace/23.i2c_host_smoke/latest

Test location /workspace/coverage/default/23.i2c_host_stretch_timeout.2358707396
Short name T1261
Test name
Test status
Simulation time 840183163 ps
CPU time 10.83 seconds
Started Aug 12 04:43:33 PM PDT 24
Finished Aug 12 04:43:44 PM PDT 24
Peak memory 218724 kb
Host smart-1fdf0286-6e5a-446b-8d10-7629a7c4635a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2358707396 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_stretch_timeout_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.i2c_host_stretch_timeout.2358707396
Directory /workspace/23.i2c_host_stretch_timeout/latest

Test location /workspace/coverage/default/23.i2c_target_bad_addr.1360294141
Short name T1452
Test name
Test status
Simulation time 11288142186 ps
CPU time 5.29 seconds
Started Aug 12 04:43:33 PM PDT 24
Finished Aug 12 04:43:39 PM PDT 24
Peak memory 219960 kb
Host smart-8eba4093-bc97-4a18-a568-7ffe717cf862
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +i2c_bad_addr_pct=50 +cdc_instrumentation_enabled=1 +UVM_
NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1360294141 -assert nopostproc
+UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_target_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.
vdb -cm_log /dev/null -cm_name 23.i2c_target_bad_addr.1360294141
Directory /workspace/23.i2c_target_bad_addr/latest

Test location /workspace/coverage/default/23.i2c_target_fifo_reset_acq.1039723069
Short name T320
Test name
Test status
Simulation time 2060738084 ps
CPU time 1.1 seconds
Started Aug 12 04:43:30 PM PDT 24
Finished Aug 12 04:43:32 PM PDT 24
Peak memory 205496 kb
Host smart-f50ea282-9cc7-4d72-a086-691fbfb46565
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1039723069 -assert nopostproc +UVM_TESTNAME=i2c_bas
e_test +UVM_TEST_SEQ=i2c_target_fifo_reset_acq_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log
/dev/null -cm_name 23.i2c_target_fifo_reset_acq.1039723069
Directory /workspace/23.i2c_target_fifo_reset_acq/latest

Test location /workspace/coverage/default/23.i2c_target_fifo_reset_tx.2621039819
Short name T376
Test name
Test status
Simulation time 285606505 ps
CPU time 1.1 seconds
Started Aug 12 04:43:30 PM PDT 24
Finished Aug 12 04:43:32 PM PDT 24
Peak memory 205480 kb
Host smart-5b784d37-36cd-43ca-9a12-79e7e87fd71f
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2621039819 -assert nopostproc +UVM_TESTNAME=i2c_bas
e_test +UVM_TEST_SEQ=i2c_target_fifo_reset_tx_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /
dev/null -cm_name 23.i2c_target_fifo_reset_tx.2621039819
Directory /workspace/23.i2c_target_fifo_reset_tx/latest

Test location /workspace/coverage/default/23.i2c_target_fifo_watermarks_acq.3104784170
Short name T1716
Test name
Test status
Simulation time 372763104 ps
CPU time 2.4 seconds
Started Aug 12 04:43:34 PM PDT 24
Finished Aug 12 04:43:37 PM PDT 24
Peak memory 205376 kb
Host smart-d5135a2a-1f9b-4040-b809-d28198b8c4bb
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3104784170 -assert nopostproc +UVM_TESTNAME=i2c_bas
e_test +UVM_TEST_SEQ=i2c_target_fifo_watermarks_acq_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm
_log /dev/null -cm_name 23.i2c_target_fifo_watermarks_acq.3104784170
Directory /workspace/23.i2c_target_fifo_watermarks_acq/latest

Test location /workspace/coverage/default/23.i2c_target_fifo_watermarks_tx.1029219435
Short name T831
Test name
Test status
Simulation time 145934081 ps
CPU time 1.15 seconds
Started Aug 12 04:43:31 PM PDT 24
Finished Aug 12 04:43:32 PM PDT 24
Peak memory 205296 kb
Host smart-8d53239e-c966-4a6f-b2d8-8a7b21a2b7b0
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1029219435 -assert nopostproc +UVM_TESTNAME=i2c_bas
e_test +UVM_TEST_SEQ=i2c_target_fifo_watermarks_tx_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_
log /dev/null -cm_name 23.i2c_target_fifo_watermarks_tx.1029219435
Directory /workspace/23.i2c_target_fifo_watermarks_tx/latest

Test location /workspace/coverage/default/23.i2c_target_hrst.3128238492
Short name T1082
Test name
Test status
Simulation time 1147619785 ps
CPU time 2.14 seconds
Started Aug 12 04:43:34 PM PDT 24
Finished Aug 12 04:43:36 PM PDT 24
Peak memory 213952 kb
Host smart-adcd88c3-8d52-4819-b931-080879c13912
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3128238492 -assert nopostproc +UVM_TESTNAME=i2c_bas
e_test +UVM_TEST_SEQ=i2c_target_hrst_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null
-cm_name 23.i2c_target_hrst.3128238492
Directory /workspace/23.i2c_target_hrst/latest

Test location /workspace/coverage/default/23.i2c_target_intr_smoke.3524864935
Short name T402
Test name
Test status
Simulation time 6608619740 ps
CPU time 10.01 seconds
Started Aug 12 04:43:33 PM PDT 24
Finished Aug 12 04:43:43 PM PDT 24
Peak memory 235272 kb
Host smart-0162035a-9e5d-48d1-a4f2-e2d726894557
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=200_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VER
BOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3524864935 -assert nopostproc +UVM_TESTNAME=i2c_ba
se_test +UVM_TEST_SEQ=i2c_target_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/nul
l -cm_name 23.i2c_target_intr_smoke.3524864935
Directory /workspace/23.i2c_target_intr_smoke/latest

Test location /workspace/coverage/default/23.i2c_target_intr_stress_wr.3946038703
Short name T1028
Test name
Test status
Simulation time 18663193476 ps
CPU time 40.99 seconds
Started Aug 12 04:43:34 PM PDT 24
Finished Aug 12 04:44:15 PM PDT 24
Peak memory 726128 kb
Host smart-4db01089-ff9f-4851-8d51-49b8f2fd04ab
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=600_000_000 +use_intr_handler=1 +slow_acq=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNO
TES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3946038703 -assert nopostproc +UVM_TES
TNAME=i2c_base_test +UVM_TEST_SEQ=i2c_target_stress_wr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb
-cm_log /dev/null -cm_name 23.i2c_target_intr_stress_wr.3946038703
Directory /workspace/23.i2c_target_intr_stress_wr/latest

Test location /workspace/coverage/default/23.i2c_target_nack_acqfull.1542602943
Short name T1209
Test name
Test status
Simulation time 1805417848 ps
CPU time 2.64 seconds
Started Aug 12 04:43:32 PM PDT 24
Finished Aug 12 04:43:35 PM PDT 24
Peak memory 213756 kb
Host smart-280da430-79a1-4ef3-ab24-a93e802f2aa6
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1542602943 -assert nopostproc +UVM_TESTNAME=i2c_bas
e_test +UVM_TEST_SEQ=i2c_target_nack_acqfull_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /d
ev/null -cm_name 23.i2c_target_nack_acqfull.1542602943
Directory /workspace/23.i2c_target_nack_acqfull/latest

Test location /workspace/coverage/default/23.i2c_target_nack_acqfull_addr.2491220565
Short name T1740
Test name
Test status
Simulation time 1013064797 ps
CPU time 2.62 seconds
Started Aug 12 04:43:30 PM PDT 24
Finished Aug 12 04:43:32 PM PDT 24
Peak memory 205448 kb
Host smart-09772e95-b368-40f5-aa85-9ac92bf90302
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2491220565 -assert nopostproc +UVM_TESTNAME=i2c_bas
e_test +UVM_TEST_SEQ=i2c_target_nack_acqfull_addr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_l
og /dev/null -cm_name 23.i2c_target_nack_acqfull_addr.2491220565
Directory /workspace/23.i2c_target_nack_acqfull_addr/latest

Test location /workspace/coverage/default/23.i2c_target_nack_txstretch.208866774
Short name T1156
Test name
Test status
Simulation time 183997760 ps
CPU time 1.45 seconds
Started Aug 12 04:43:33 PM PDT 24
Finished Aug 12 04:43:35 PM PDT 24
Peak memory 222064 kb
Host smart-498c6524-2ea4-4c59-bce2-81958345fda7
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=208866774 -assert nopostproc +UVM_TESTNAME=i2c_base
_test +UVM_TEST_SEQ=i2c_target_nack_txstretch_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /
dev/null -cm_name 23.i2c_target_nack_txstretch.208866774
Directory /workspace/23.i2c_target_nack_txstretch/latest

Test location /workspace/coverage/default/23.i2c_target_perf.3403148557
Short name T1602
Test name
Test status
Simulation time 5189541977 ps
CPU time 6.94 seconds
Started Aug 12 04:43:34 PM PDT 24
Finished Aug 12 04:43:41 PM PDT 24
Peak memory 221876 kb
Host smart-c4b50baf-e785-47e6-8f5a-09ddb59c087b
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3403148557 -assert nopostproc +UVM_TESTNAME=i2c_bas
e_test +UVM_TEST_SEQ=i2c_target_perf_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null
-cm_name 23.i2c_target_perf.3403148557
Directory /workspace/23.i2c_target_perf/latest

Test location /workspace/coverage/default/23.i2c_target_smbus_maxlen.2041446168
Short name T1266
Test name
Test status
Simulation time 416265092 ps
CPU time 2.2 seconds
Started Aug 12 04:43:31 PM PDT 24
Finished Aug 12 04:43:34 PM PDT 24
Peak memory 205296 kb
Host smart-fe9443c0-6581-49dc-8c3e-e72507389f3f
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2041446168 -assert nopostproc +UVM_TESTNAME=i2c_bas
e_test +UVM_TEST_SEQ=i2c_target_smbus_maxlen_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /d
ev/null -cm_name 23.i2c_target_smbus_maxlen.2041446168
Directory /workspace/23.i2c_target_smbus_maxlen/latest

Test location /workspace/coverage/default/23.i2c_target_smoke.2807855069
Short name T1498
Test name
Test status
Simulation time 7401274174 ps
CPU time 46.89 seconds
Started Aug 12 04:43:32 PM PDT 24
Finished Aug 12 04:44:19 PM PDT 24
Peak memory 218188 kb
Host smart-81cac2bf-5c19-46f3-9eac-72a1d01b757a
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=100_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licq
ueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2807855069 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SE
Q=i2c_target_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.i2c_ta
rget_smoke.2807855069
Directory /workspace/23.i2c_target_smoke/latest

Test location /workspace/coverage/default/23.i2c_target_stress_all.652787483
Short name T1235
Test name
Test status
Simulation time 101502810028 ps
CPU time 604.04 seconds
Started Aug 12 04:43:29 PM PDT 24
Finished Aug 12 04:53:34 PM PDT 24
Peak memory 3350784 kb
Host smart-369a4b9f-1a62-4bba-8cb5-f74be68c65b1
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=300_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VER
BOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=652787483 -assert nopostproc +UVM_TESTNAME=i2c_bas
e_test +UVM_TEST_SEQ=i2c_target_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev
/null -cm_name 23.i2c_target_stress_all.652787483
Directory /workspace/23.i2c_target_stress_all/latest

Test location /workspace/coverage/default/23.i2c_target_stress_rd.646183453
Short name T572
Test name
Test status
Simulation time 611527573 ps
CPU time 10.16 seconds
Started Aug 12 04:43:30 PM PDT 24
Finished Aug 12 04:43:40 PM PDT 24
Peak memory 218188 kb
Host smart-2e2c6a51-98d6-4e4b-93c6-bc4d33f76fa1
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=100_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licq
ueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=646183453 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ
=i2c_target_stress_rd_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.i2c
_target_stress_rd.646183453
Directory /workspace/23.i2c_target_stress_rd/latest

Test location /workspace/coverage/default/23.i2c_target_stress_wr.1047326127
Short name T1399
Test name
Test status
Simulation time 40890394820 ps
CPU time 19.38 seconds
Started Aug 12 04:43:30 PM PDT 24
Finished Aug 12 04:43:49 PM PDT 24
Peak memory 440012 kb
Host smart-d56cb4be-4d1b-4574-88b9-303feea2292a
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=600_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licq
ueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1047326127 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SE
Q=i2c_target_stress_wr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.i2
c_target_stress_wr.1047326127
Directory /workspace/23.i2c_target_stress_wr/latest

Test location /workspace/coverage/default/23.i2c_target_stretch.3942044951
Short name T862
Test name
Test status
Simulation time 2192961002 ps
CPU time 22.63 seconds
Started Aug 12 04:43:32 PM PDT 24
Finished Aug 12 04:43:55 PM PDT 24
Peak memory 298508 kb
Host smart-5c150421-37be-4531-983b-13fb10d04fe9
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=400_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licq
ueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3942044951 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SE
Q=i2c_target_stretch_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.i2c_
target_stretch.3942044951
Directory /workspace/23.i2c_target_stretch/latest

Test location /workspace/coverage/default/23.i2c_target_timeout.1194123564
Short name T1259
Test name
Test status
Simulation time 1538492437 ps
CPU time 7.43 seconds
Started Aug 12 04:43:29 PM PDT 24
Finished Aug 12 04:43:36 PM PDT 24
Peak memory 232048 kb
Host smart-e7607f4e-5df9-4613-ad97-c152fb123dd6
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=50_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1194123564 -assert nopostproc +UVM_TESTNAME=i2c_bas
e_test +UVM_TEST_SEQ=i2c_target_timeout_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/nu
ll -cm_name 23.i2c_target_timeout.1194123564
Directory /workspace/23.i2c_target_timeout/latest

Test location /workspace/coverage/default/23.i2c_target_tx_stretch_ctrl.4234152468
Short name T1073
Test name
Test status
Simulation time 101325143 ps
CPU time 1.78 seconds
Started Aug 12 04:43:31 PM PDT 24
Finished Aug 12 04:43:34 PM PDT 24
Peak memory 205492 kb
Host smart-727c4659-f971-4ab3-b36e-d30ed54b4731
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4234152468 -assert nopostproc +UVM_TESTNAME=i2c_bas
e_test +UVM_TEST_SEQ=i2c_target_tx_stretch_ctrl_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log
/dev/null -cm_name 23.i2c_target_tx_stretch_ctrl.4234152468
Directory /workspace/23.i2c_target_tx_stretch_ctrl/latest

Test location /workspace/coverage/default/24.i2c_alert_test.77206172
Short name T1507
Test name
Test status
Simulation time 70691683 ps
CPU time 0.74 seconds
Started Aug 12 04:43:46 PM PDT 24
Finished Aug 12 04:43:47 PM PDT 24
Peak memory 204596 kb
Host smart-e7187ddf-a25e-41da-a077-950515d9c278
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=77206172 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_common_vseq +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.i2c_alert_test.77206172
Directory /workspace/24.i2c_alert_test/latest

Test location /workspace/coverage/default/24.i2c_host_error_intr.2688956534
Short name T20
Test name
Test status
Simulation time 432185671 ps
CPU time 2.36 seconds
Started Aug 12 04:43:37 PM PDT 24
Finished Aug 12 04:43:40 PM PDT 24
Peak memory 213452 kb
Host smart-e2d1c0f2-d71f-43ab-9f3e-9dac9dbf603a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2688956534 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_error_intr_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.i2c_host_error_intr.2688956534
Directory /workspace/24.i2c_host_error_intr/latest

Test location /workspace/coverage/default/24.i2c_host_fifo_fmt_empty.2844951135
Short name T1527
Test name
Test status
Simulation time 1337987621 ps
CPU time 6.97 seconds
Started Aug 12 04:43:40 PM PDT 24
Finished Aug 12 04:43:47 PM PDT 24
Peak memory 259360 kb
Host smart-635a1eb6-860a-4388-8882-e22ec44ef663
User root
Command /workspace/default/simv +test_timeout_ns=10_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2844951135 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_fifo_fmt_em
pty_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.i2c_host_fifo_fmt_emp
ty.2844951135
Directory /workspace/24.i2c_host_fifo_fmt_empty/latest

Test location /workspace/coverage/default/24.i2c_host_fifo_full.938985188
Short name T1038
Test name
Test status
Simulation time 21498834779 ps
CPU time 87.99 seconds
Started Aug 12 04:43:41 PM PDT 24
Finished Aug 12 04:45:10 PM PDT 24
Peak memory 505920 kb
Host smart-89144513-0a74-4bc0-bd0d-fb52c65d071a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=938985188 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_fifo_full_vseq +en_cov=1 -cm line+cond+f
sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.i2c_host_fifo_full.938985188
Directory /workspace/24.i2c_host_fifo_full/latest

Test location /workspace/coverage/default/24.i2c_host_fifo_overflow.3235041771
Short name T1312
Test name
Test status
Simulation time 10837440094 ps
CPU time 79.5 seconds
Started Aug 12 04:43:30 PM PDT 24
Finished Aug 12 04:44:50 PM PDT 24
Peak memory 795128 kb
Host smart-af627099-48cd-476c-9855-2a3ca8dfb097
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3235041771 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_fifo_overflow_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.i2c_host_fifo_overflow.3235041771
Directory /workspace/24.i2c_host_fifo_overflow/latest

Test location /workspace/coverage/default/24.i2c_host_fifo_reset_fmt.1478168535
Short name T253
Test name
Test status
Simulation time 117165856 ps
CPU time 1.2 seconds
Started Aug 12 04:43:40 PM PDT 24
Finished Aug 12 04:43:41 PM PDT 24
Peak memory 205264 kb
Host smart-f3d46e68-4785-4a90-a74b-22451f5182de
User root
Command /workspace/default/simv +test_timeout_ns=10_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1478168535 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_fifo_reset_
fmt_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.i2c_host_fifo_reset_f
mt.1478168535
Directory /workspace/24.i2c_host_fifo_reset_fmt/latest

Test location /workspace/coverage/default/24.i2c_host_fifo_reset_rx.1683707633
Short name T1682
Test name
Test status
Simulation time 508690565 ps
CPU time 3.67 seconds
Started Aug 12 04:43:37 PM PDT 24
Finished Aug 12 04:43:41 PM PDT 24
Peak memory 224020 kb
Host smart-4342cc8f-1bb2-44c6-a4e9-70b6ba044c95
User root
Command /workspace/default/simv +test_timeout_ns=10_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1683707633 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_fifo_reset_
rx_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.i2c_host_fifo_reset_rx
.1683707633
Directory /workspace/24.i2c_host_fifo_reset_rx/latest

Test location /workspace/coverage/default/24.i2c_host_fifo_watermark.1820369793
Short name T828
Test name
Test status
Simulation time 2996705280 ps
CPU time 197.78 seconds
Started Aug 12 04:43:33 PM PDT 24
Finished Aug 12 04:46:51 PM PDT 24
Peak memory 895320 kb
Host smart-d47a1325-5814-4337-8fb3-1a1aad47fd53
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1820369793 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_fifo_watermark_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.i2c_host_fifo_watermark.1820369793
Directory /workspace/24.i2c_host_fifo_watermark/latest

Test location /workspace/coverage/default/24.i2c_host_may_nack.3465398802
Short name T1304
Test name
Test status
Simulation time 1708598400 ps
CPU time 6.29 seconds
Started Aug 12 04:43:37 PM PDT 24
Finished Aug 12 04:43:44 PM PDT 24
Peak memory 205300 kb
Host smart-29a5fc42-15be-4dbb-ab0c-a1a6a25a84b0
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3465398802 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_may_nack_vseq +en_cov=1 -cm line+cond+f
sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.i2c_host_may_nack.3465398802
Directory /workspace/24.i2c_host_may_nack/latest

Test location /workspace/coverage/default/24.i2c_host_override.995305118
Short name T151
Test name
Test status
Simulation time 26956109 ps
CPU time 0.7 seconds
Started Aug 12 04:43:32 PM PDT 24
Finished Aug 12 04:43:33 PM PDT 24
Peak memory 204920 kb
Host smart-53e06f76-12fc-4b4c-9cac-ce724134ea32
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=995305118 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_override_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.i2c_host_override.995305118
Directory /workspace/24.i2c_host_override/latest

Test location /workspace/coverage/default/24.i2c_host_perf.3206115595
Short name T499
Test name
Test status
Simulation time 7576069114 ps
CPU time 72.67 seconds
Started Aug 12 04:43:40 PM PDT 24
Finished Aug 12 04:44:53 PM PDT 24
Peak memory 204660 kb
Host smart-867c25fa-6935-46c5-877b-b8b7b44d6003
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3206115595 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_perf_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.i2c_host_perf.3206115595
Directory /workspace/24.i2c_host_perf/latest

Test location /workspace/coverage/default/24.i2c_host_perf_precise.3294349948
Short name T1530
Test name
Test status
Simulation time 403612925 ps
CPU time 2.3 seconds
Started Aug 12 04:43:43 PM PDT 24
Finished Aug 12 04:43:46 PM PDT 24
Peak memory 205084 kb
Host smart-d73da7d6-d238-486f-9e22-0f95c7a4551b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3294349948 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_perf_precise_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.i2c_host_perf_precise.3294349948
Directory /workspace/24.i2c_host_perf_precise/latest

Test location /workspace/coverage/default/24.i2c_host_smoke.2949281540
Short name T1180
Test name
Test status
Simulation time 2084719634 ps
CPU time 49.09 seconds
Started Aug 12 04:43:32 PM PDT 24
Finished Aug 12 04:44:22 PM PDT 24
Peak memory 304804 kb
Host smart-eb1037a1-1d52-46b7-895b-7e7ef3befd2f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2949281540 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_smoke_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.i2c_host_smoke.2949281540
Directory /workspace/24.i2c_host_smoke/latest

Test location /workspace/coverage/default/24.i2c_host_stress_all.2262859953
Short name T275
Test name
Test status
Simulation time 16598418945 ps
CPU time 603 seconds
Started Aug 12 04:43:37 PM PDT 24
Finished Aug 12 04:53:40 PM PDT 24
Peak memory 1593972 kb
Host smart-036125d9-68bf-4312-82a7-85a2aead9aa9
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2262859953 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_stress_all_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.i2c_host_stress_all.2262859953
Directory /workspace/24.i2c_host_stress_all/latest

Test location /workspace/coverage/default/24.i2c_host_stretch_timeout.460626597
Short name T699
Test name
Test status
Simulation time 3021353002 ps
CPU time 13 seconds
Started Aug 12 04:43:38 PM PDT 24
Finished Aug 12 04:43:51 PM PDT 24
Peak memory 218596 kb
Host smart-ab9cfc27-3fb8-4ccf-8034-d8f58fa8f7eb
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=460626597 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_stretch_timeout_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.i2c_host_stretch_timeout.460626597
Directory /workspace/24.i2c_host_stretch_timeout/latest

Test location /workspace/coverage/default/24.i2c_target_bad_addr.1306028683
Short name T451
Test name
Test status
Simulation time 3759959450 ps
CPU time 3.69 seconds
Started Aug 12 04:43:38 PM PDT 24
Finished Aug 12 04:43:42 PM PDT 24
Peak memory 221864 kb
Host smart-a4e4ed0c-4398-446d-bc92-7925d780b7d3
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +i2c_bad_addr_pct=50 +cdc_instrumentation_enabled=1 +UVM_
NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1306028683 -assert nopostproc
+UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_target_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.
vdb -cm_log /dev/null -cm_name 24.i2c_target_bad_addr.1306028683
Directory /workspace/24.i2c_target_bad_addr/latest

Test location /workspace/coverage/default/24.i2c_target_fifo_reset_acq.3402554307
Short name T164
Test name
Test status
Simulation time 214165584 ps
CPU time 1.27 seconds
Started Aug 12 04:43:40 PM PDT 24
Finished Aug 12 04:43:41 PM PDT 24
Peak memory 204448 kb
Host smart-05036573-1ce0-463d-8377-a90b36effded
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3402554307 -assert nopostproc +UVM_TESTNAME=i2c_bas
e_test +UVM_TEST_SEQ=i2c_target_fifo_reset_acq_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log
/dev/null -cm_name 24.i2c_target_fifo_reset_acq.3402554307
Directory /workspace/24.i2c_target_fifo_reset_acq/latest

Test location /workspace/coverage/default/24.i2c_target_fifo_reset_tx.4066305848
Short name T726
Test name
Test status
Simulation time 240981504 ps
CPU time 1.33 seconds
Started Aug 12 04:43:37 PM PDT 24
Finished Aug 12 04:43:38 PM PDT 24
Peak memory 205372 kb
Host smart-35dcfd9e-5c21-4d66-be73-c47cfd6e1595
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4066305848 -assert nopostproc +UVM_TESTNAME=i2c_bas
e_test +UVM_TEST_SEQ=i2c_target_fifo_reset_tx_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /
dev/null -cm_name 24.i2c_target_fifo_reset_tx.4066305848
Directory /workspace/24.i2c_target_fifo_reset_tx/latest

Test location /workspace/coverage/default/24.i2c_target_fifo_watermarks_acq.947452409
Short name T1118
Test name
Test status
Simulation time 2098661990 ps
CPU time 2.93 seconds
Started Aug 12 04:43:38 PM PDT 24
Finished Aug 12 04:43:41 PM PDT 24
Peak memory 205488 kb
Host smart-5af0e850-e23a-4873-ad4c-c591e17db004
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=947452409 -assert nopostproc +UVM_TESTNAME=i2c_base
_test +UVM_TEST_SEQ=i2c_target_fifo_watermarks_acq_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_
log /dev/null -cm_name 24.i2c_target_fifo_watermarks_acq.947452409
Directory /workspace/24.i2c_target_fifo_watermarks_acq/latest

Test location /workspace/coverage/default/24.i2c_target_fifo_watermarks_tx.6589394
Short name T1674
Test name
Test status
Simulation time 572278435 ps
CPU time 1.49 seconds
Started Aug 12 04:43:42 PM PDT 24
Finished Aug 12 04:43:43 PM PDT 24
Peak memory 205168 kb
Host smart-158be966-b490-4950-93c7-334117b4d6c3
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=6589394 -assert nopostproc +UVM_TESTNAME=i2c_base_t
est +UVM_TEST_SEQ=i2c_target_fifo_watermarks_tx_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log
/dev/null -cm_name 24.i2c_target_fifo_watermarks_tx.6589394
Directory /workspace/24.i2c_target_fifo_watermarks_tx/latest

Test location /workspace/coverage/default/24.i2c_target_hrst.1632235400
Short name T1596
Test name
Test status
Simulation time 794086873 ps
CPU time 2.36 seconds
Started Aug 12 04:43:39 PM PDT 24
Finished Aug 12 04:43:42 PM PDT 24
Peak memory 221120 kb
Host smart-6ca7fa3e-28e4-4a9e-ae3d-c0f153dfd885
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1632235400 -assert nopostproc +UVM_TESTNAME=i2c_bas
e_test +UVM_TEST_SEQ=i2c_target_hrst_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null
-cm_name 24.i2c_target_hrst.1632235400
Directory /workspace/24.i2c_target_hrst/latest

Test location /workspace/coverage/default/24.i2c_target_intr_smoke.1391411565
Short name T1691
Test name
Test status
Simulation time 2840358847 ps
CPU time 8.62 seconds
Started Aug 12 04:43:40 PM PDT 24
Finished Aug 12 04:43:48 PM PDT 24
Peak memory 230112 kb
Host smart-8d999c14-1a5a-494f-ae1f-0b6d5d2ca4d2
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=200_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VER
BOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1391411565 -assert nopostproc +UVM_TESTNAME=i2c_ba
se_test +UVM_TEST_SEQ=i2c_target_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/nul
l -cm_name 24.i2c_target_intr_smoke.1391411565
Directory /workspace/24.i2c_target_intr_smoke/latest

Test location /workspace/coverage/default/24.i2c_target_intr_stress_wr.3878756397
Short name T705
Test name
Test status
Simulation time 20520167179 ps
CPU time 63.78 seconds
Started Aug 12 04:43:36 PM PDT 24
Finished Aug 12 04:44:40 PM PDT 24
Peak memory 1243404 kb
Host smart-420667ca-ca47-4490-b1f2-bc4b1cc6fef1
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=600_000_000 +use_intr_handler=1 +slow_acq=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNO
TES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3878756397 -assert nopostproc +UVM_TES
TNAME=i2c_base_test +UVM_TEST_SEQ=i2c_target_stress_wr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb
-cm_log /dev/null -cm_name 24.i2c_target_intr_stress_wr.3878756397
Directory /workspace/24.i2c_target_intr_stress_wr/latest

Test location /workspace/coverage/default/24.i2c_target_nack_acqfull.3896460624
Short name T345
Test name
Test status
Simulation time 514355565 ps
CPU time 2.61 seconds
Started Aug 12 04:43:42 PM PDT 24
Finished Aug 12 04:43:45 PM PDT 24
Peak memory 213724 kb
Host smart-7febd774-fc9d-4929-a03b-618fac545558
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3896460624 -assert nopostproc +UVM_TESTNAME=i2c_bas
e_test +UVM_TEST_SEQ=i2c_target_nack_acqfull_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /d
ev/null -cm_name 24.i2c_target_nack_acqfull.3896460624
Directory /workspace/24.i2c_target_nack_acqfull/latest

Test location /workspace/coverage/default/24.i2c_target_nack_acqfull_addr.624848093
Short name T1257
Test name
Test status
Simulation time 1821104163 ps
CPU time 2.43 seconds
Started Aug 12 04:43:40 PM PDT 24
Finished Aug 12 04:43:43 PM PDT 24
Peak memory 205444 kb
Host smart-5e4ff72f-e69b-487f-bbae-dc9ba0494871
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=624848093 -assert nopostproc +UVM_TESTNAME=i2c_base
_test +UVM_TEST_SEQ=i2c_target_nack_acqfull_addr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_lo
g /dev/null -cm_name 24.i2c_target_nack_acqfull_addr.624848093
Directory /workspace/24.i2c_target_nack_acqfull_addr/latest

Test location /workspace/coverage/default/24.i2c_target_nack_txstretch.116674550
Short name T855
Test name
Test status
Simulation time 733279204 ps
CPU time 1.54 seconds
Started Aug 12 04:43:46 PM PDT 24
Finished Aug 12 04:43:47 PM PDT 24
Peak memory 222152 kb
Host smart-e2a479a9-f9de-4ffc-b17a-0b84c0354809
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=116674550 -assert nopostproc +UVM_TESTNAME=i2c_base
_test +UVM_TEST_SEQ=i2c_target_nack_txstretch_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /
dev/null -cm_name 24.i2c_target_nack_txstretch.116674550
Directory /workspace/24.i2c_target_nack_txstretch/latest

Test location /workspace/coverage/default/24.i2c_target_perf.2312553312
Short name T1272
Test name
Test status
Simulation time 7402848224 ps
CPU time 6.7 seconds
Started Aug 12 04:43:37 PM PDT 24
Finished Aug 12 04:43:44 PM PDT 24
Peak memory 230052 kb
Host smart-9210bf31-e4b2-4e72-a400-43a6fba70357
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2312553312 -assert nopostproc +UVM_TESTNAME=i2c_bas
e_test +UVM_TEST_SEQ=i2c_target_perf_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null
-cm_name 24.i2c_target_perf.2312553312
Directory /workspace/24.i2c_target_perf/latest

Test location /workspace/coverage/default/24.i2c_target_smbus_maxlen.3912363633
Short name T738
Test name
Test status
Simulation time 1803594316 ps
CPU time 2.31 seconds
Started Aug 12 04:43:40 PM PDT 24
Finished Aug 12 04:43:43 PM PDT 24
Peak memory 205236 kb
Host smart-af98621c-925c-4cc8-b2b3-c21fb7c83bdc
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3912363633 -assert nopostproc +UVM_TESTNAME=i2c_bas
e_test +UVM_TEST_SEQ=i2c_target_smbus_maxlen_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /d
ev/null -cm_name 24.i2c_target_smbus_maxlen.3912363633
Directory /workspace/24.i2c_target_smbus_maxlen/latest

Test location /workspace/coverage/default/24.i2c_target_smoke.320837500
Short name T507
Test name
Test status
Simulation time 3550481575 ps
CPU time 26.99 seconds
Started Aug 12 04:43:37 PM PDT 24
Finished Aug 12 04:44:04 PM PDT 24
Peak memory 213772 kb
Host smart-ae2f893a-300b-4190-8765-58617754cf31
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=100_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licq
ueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=320837500 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ
=i2c_target_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.i2c_tar
get_smoke.320837500
Directory /workspace/24.i2c_target_smoke/latest

Test location /workspace/coverage/default/24.i2c_target_stress_all.2417957111
Short name T79
Test name
Test status
Simulation time 50202802460 ps
CPU time 96.91 seconds
Started Aug 12 04:43:42 PM PDT 24
Finished Aug 12 04:45:19 PM PDT 24
Peak memory 1115020 kb
Host smart-dc24ed4d-3a0d-41a6-92c7-7c2ee6d3c0f0
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=300_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VER
BOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2417957111 -assert nopostproc +UVM_TESTNAME=i2c_ba
se_test +UVM_TEST_SEQ=i2c_target_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /de
v/null -cm_name 24.i2c_target_stress_all.2417957111
Directory /workspace/24.i2c_target_stress_all/latest

Test location /workspace/coverage/default/24.i2c_target_stress_rd.27515053
Short name T6
Test name
Test status
Simulation time 1934416290 ps
CPU time 33.46 seconds
Started Aug 12 04:43:41 PM PDT 24
Finished Aug 12 04:44:15 PM PDT 24
Peak memory 230148 kb
Host smart-9ddbb499-49d6-4ce9-bc11-97502b4e7496
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=100_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licq
ueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=27515053 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=
i2c_target_stress_rd_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.i2c_
target_stress_rd.27515053
Directory /workspace/24.i2c_target_stress_rd/latest

Test location /workspace/coverage/default/24.i2c_target_stress_wr.944396744
Short name T312
Test name
Test status
Simulation time 30997128025 ps
CPU time 90.46 seconds
Started Aug 12 04:43:36 PM PDT 24
Finished Aug 12 04:45:07 PM PDT 24
Peak memory 1505236 kb
Host smart-e40b20c7-65b3-47ad-85e6-2e4b252898d2
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=600_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licq
ueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=944396744 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ
=i2c_target_stress_wr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.i2c
_target_stress_wr.944396744
Directory /workspace/24.i2c_target_stress_wr/latest

Test location /workspace/coverage/default/24.i2c_target_stretch.4006491305
Short name T475
Test name
Test status
Simulation time 1972927494 ps
CPU time 11.54 seconds
Started Aug 12 04:43:39 PM PDT 24
Finished Aug 12 04:43:51 PM PDT 24
Peak memory 251244 kb
Host smart-a5f9a8f6-8026-41a7-a0c4-1a79807f961b
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=400_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licq
ueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4006491305 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SE
Q=i2c_target_stretch_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.i2c_
target_stretch.4006491305
Directory /workspace/24.i2c_target_stretch/latest

Test location /workspace/coverage/default/24.i2c_target_timeout.2563482056
Short name T1397
Test name
Test status
Simulation time 7200111581 ps
CPU time 7.73 seconds
Started Aug 12 04:43:38 PM PDT 24
Finished Aug 12 04:43:46 PM PDT 24
Peak memory 221876 kb
Host smart-ae07653c-daa4-49d9-ae9c-4b3f72f956d2
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=50_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2563482056 -assert nopostproc +UVM_TESTNAME=i2c_bas
e_test +UVM_TEST_SEQ=i2c_target_timeout_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/nu
ll -cm_name 24.i2c_target_timeout.2563482056
Directory /workspace/24.i2c_target_timeout/latest

Test location /workspace/coverage/default/24.i2c_target_tx_stretch_ctrl.1299372120
Short name T1158
Test name
Test status
Simulation time 516639299 ps
CPU time 7.03 seconds
Started Aug 12 04:43:37 PM PDT 24
Finished Aug 12 04:43:44 PM PDT 24
Peak memory 205564 kb
Host smart-f9557baf-e769-4f7a-a038-96aeedcecca4
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1299372120 -assert nopostproc +UVM_TESTNAME=i2c_bas
e_test +UVM_TEST_SEQ=i2c_target_tx_stretch_ctrl_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log
/dev/null -cm_name 24.i2c_target_tx_stretch_ctrl.1299372120
Directory /workspace/24.i2c_target_tx_stretch_ctrl/latest

Test location /workspace/coverage/default/25.i2c_alert_test.1536576217
Short name T894
Test name
Test status
Simulation time 55804656 ps
CPU time 0.67 seconds
Started Aug 12 04:43:52 PM PDT 24
Finished Aug 12 04:43:52 PM PDT 24
Peak memory 204460 kb
Host smart-024e4958-06ef-4588-a08e-61b67c2727b3
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1536576217 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_common_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.i2c_alert_test.1536576217
Directory /workspace/25.i2c_alert_test/latest

Test location /workspace/coverage/default/25.i2c_host_error_intr.2874064428
Short name T1644
Test name
Test status
Simulation time 203433605 ps
CPU time 2.91 seconds
Started Aug 12 04:43:45 PM PDT 24
Finished Aug 12 04:43:48 PM PDT 24
Peak memory 213516 kb
Host smart-826d5907-3ee9-4b61-8c59-022b3fd9d310
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2874064428 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_error_intr_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.i2c_host_error_intr.2874064428
Directory /workspace/25.i2c_host_error_intr/latest

Test location /workspace/coverage/default/25.i2c_host_fifo_fmt_empty.2069116154
Short name T709
Test name
Test status
Simulation time 466781722 ps
CPU time 4.29 seconds
Started Aug 12 04:43:46 PM PDT 24
Finished Aug 12 04:43:50 PM PDT 24
Peak memory 251732 kb
Host smart-c1038a3d-7472-42d6-97cb-ea8de45f21ab
User root
Command /workspace/default/simv +test_timeout_ns=10_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2069116154 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_fifo_fmt_em
pty_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.i2c_host_fifo_fmt_emp
ty.2069116154
Directory /workspace/25.i2c_host_fifo_fmt_empty/latest

Test location /workspace/coverage/default/25.i2c_host_fifo_full.264729492
Short name T1604
Test name
Test status
Simulation time 5657291609 ps
CPU time 95.45 seconds
Started Aug 12 04:43:48 PM PDT 24
Finished Aug 12 04:45:24 PM PDT 24
Peak memory 542812 kb
Host smart-f5cad1ff-2163-42fd-8659-7b41aa1e09c3
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=264729492 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_fifo_full_vseq +en_cov=1 -cm line+cond+f
sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.i2c_host_fifo_full.264729492
Directory /workspace/25.i2c_host_fifo_full/latest

Test location /workspace/coverage/default/25.i2c_host_fifo_overflow.1962845699
Short name T450
Test name
Test status
Simulation time 2445046789 ps
CPU time 178.31 seconds
Started Aug 12 04:43:45 PM PDT 24
Finished Aug 12 04:46:44 PM PDT 24
Peak memory 746288 kb
Host smart-b5cc3ec3-6e5a-4a18-bf0c-9919f9da8b4e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1962845699 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_fifo_overflow_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.i2c_host_fifo_overflow.1962845699
Directory /workspace/25.i2c_host_fifo_overflow/latest

Test location /workspace/coverage/default/25.i2c_host_fifo_reset_fmt.1668210430
Short name T34
Test name
Test status
Simulation time 383179643 ps
CPU time 1.17 seconds
Started Aug 12 04:43:44 PM PDT 24
Finished Aug 12 04:43:46 PM PDT 24
Peak memory 204984 kb
Host smart-c2b165d0-c124-40f8-b86d-747c1a3bd09f
User root
Command /workspace/default/simv +test_timeout_ns=10_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1668210430 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_fifo_reset_
fmt_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.i2c_host_fifo_reset_f
mt.1668210430
Directory /workspace/25.i2c_host_fifo_reset_fmt/latest

Test location /workspace/coverage/default/25.i2c_host_fifo_reset_rx.66855643
Short name T710
Test name
Test status
Simulation time 932410192 ps
CPU time 4.71 seconds
Started Aug 12 04:43:45 PM PDT 24
Finished Aug 12 04:43:49 PM PDT 24
Peak memory 205232 kb
Host smart-3ae91296-f7fd-4f8b-a959-270fb92310e7
User root
Command /workspace/default/simv +test_timeout_ns=10_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=66855643 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_fifo_reset_rx
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.i2c_host_fifo_reset_rx.66855643
Directory /workspace/25.i2c_host_fifo_reset_rx/latest

Test location /workspace/coverage/default/25.i2c_host_fifo_watermark.3962249319
Short name T84
Test name
Test status
Simulation time 27334054053 ps
CPU time 258.29 seconds
Started Aug 12 04:43:46 PM PDT 24
Finished Aug 12 04:48:04 PM PDT 24
Peak memory 1094284 kb
Host smart-19a940ce-02ac-4b64-87ee-e5ac8850620b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3962249319 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_fifo_watermark_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.i2c_host_fifo_watermark.3962249319
Directory /workspace/25.i2c_host_fifo_watermark/latest

Test location /workspace/coverage/default/25.i2c_host_may_nack.12723093
Short name T24
Test name
Test status
Simulation time 241897075 ps
CPU time 10.03 seconds
Started Aug 12 04:43:45 PM PDT 24
Finished Aug 12 04:43:55 PM PDT 24
Peak memory 205228 kb
Host smart-4b7dbee0-e52d-4595-abd6-95b6f14547aa
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=12723093 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_may_nack_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.i2c_host_may_nack.12723093
Directory /workspace/25.i2c_host_may_nack/latest

Test location /workspace/coverage/default/25.i2c_host_override.1023149098
Short name T1106
Test name
Test status
Simulation time 23747510 ps
CPU time 0.65 seconds
Started Aug 12 04:43:45 PM PDT 24
Finished Aug 12 04:43:46 PM PDT 24
Peak memory 205032 kb
Host smart-5a1769c1-89c0-463e-9813-35657d584efa
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1023149098 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_override_vseq +en_cov=1 -cm line+cond+f
sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.i2c_host_override.1023149098
Directory /workspace/25.i2c_host_override/latest

Test location /workspace/coverage/default/25.i2c_host_perf.2119815898
Short name T1089
Test name
Test status
Simulation time 2626530262 ps
CPU time 6.86 seconds
Started Aug 12 04:43:48 PM PDT 24
Finished Aug 12 04:43:55 PM PDT 24
Peak memory 205248 kb
Host smart-d393f59f-f0af-40b1-9c2b-ae98dbd72de0
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2119815898 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_perf_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.i2c_host_perf.2119815898
Directory /workspace/25.i2c_host_perf/latest

Test location /workspace/coverage/default/25.i2c_host_perf_precise.4294104952
Short name T897
Test name
Test status
Simulation time 400509746 ps
CPU time 8.12 seconds
Started Aug 12 04:43:44 PM PDT 24
Finished Aug 12 04:43:52 PM PDT 24
Peak memory 280260 kb
Host smart-fc754dc3-279f-431d-a6f0-2751f83df01e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4294104952 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_perf_precise_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.i2c_host_perf_precise.4294104952
Directory /workspace/25.i2c_host_perf_precise/latest

Test location /workspace/coverage/default/25.i2c_host_smoke.1291891293
Short name T548
Test name
Test status
Simulation time 1226733701 ps
CPU time 19.32 seconds
Started Aug 12 04:43:44 PM PDT 24
Finished Aug 12 04:44:04 PM PDT 24
Peak memory 328816 kb
Host smart-371177da-7832-4c62-b7ab-c0f44f888700
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1291891293 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_smoke_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.i2c_host_smoke.1291891293
Directory /workspace/25.i2c_host_smoke/latest

Test location /workspace/coverage/default/25.i2c_host_stretch_timeout.4094876404
Short name T1250
Test name
Test status
Simulation time 1129450534 ps
CPU time 10.77 seconds
Started Aug 12 04:43:46 PM PDT 24
Finished Aug 12 04:43:57 PM PDT 24
Peak memory 214676 kb
Host smart-9c65f307-b8f2-4639-9622-5665e16bd146
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4094876404 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_stretch_timeout_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.i2c_host_stretch_timeout.4094876404
Directory /workspace/25.i2c_host_stretch_timeout/latest

Test location /workspace/coverage/default/25.i2c_target_bad_addr.1124991942
Short name T937
Test name
Test status
Simulation time 771511988 ps
CPU time 4.73 seconds
Started Aug 12 04:43:44 PM PDT 24
Finished Aug 12 04:43:49 PM PDT 24
Peak memory 217140 kb
Host smart-49b4cc90-838e-4a32-baf1-d51de999ef7a
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +i2c_bad_addr_pct=50 +cdc_instrumentation_enabled=1 +UVM_
NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1124991942 -assert nopostproc
+UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_target_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.
vdb -cm_log /dev/null -cm_name 25.i2c_target_bad_addr.1124991942
Directory /workspace/25.i2c_target_bad_addr/latest

Test location /workspace/coverage/default/25.i2c_target_fifo_reset_acq.1701302518
Short name T1269
Test name
Test status
Simulation time 451189411 ps
CPU time 1.02 seconds
Started Aug 12 04:43:43 PM PDT 24
Finished Aug 12 04:43:45 PM PDT 24
Peak memory 205268 kb
Host smart-486231e6-3f84-4c93-b767-669eeb96f70a
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1701302518 -assert nopostproc +UVM_TESTNAME=i2c_bas
e_test +UVM_TEST_SEQ=i2c_target_fifo_reset_acq_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log
/dev/null -cm_name 25.i2c_target_fifo_reset_acq.1701302518
Directory /workspace/25.i2c_target_fifo_reset_acq/latest

Test location /workspace/coverage/default/25.i2c_target_fifo_reset_tx.290453955
Short name T1520
Test name
Test status
Simulation time 244577230 ps
CPU time 1.44 seconds
Started Aug 12 04:43:44 PM PDT 24
Finished Aug 12 04:43:46 PM PDT 24
Peak memory 205432 kb
Host smart-057867a0-600f-472e-bedf-5e92218f927c
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=290453955 -assert nopostproc +UVM_TESTNAME=i2c_base
_test +UVM_TEST_SEQ=i2c_target_fifo_reset_tx_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /d
ev/null -cm_name 25.i2c_target_fifo_reset_tx.290453955
Directory /workspace/25.i2c_target_fifo_reset_tx/latest

Test location /workspace/coverage/default/25.i2c_target_fifo_watermarks_acq.1809595643
Short name T1500
Test name
Test status
Simulation time 8014366886 ps
CPU time 3.34 seconds
Started Aug 12 04:43:48 PM PDT 24
Finished Aug 12 04:43:51 PM PDT 24
Peak memory 213660 kb
Host smart-942205ed-73f3-4156-b599-2072d7201904
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1809595643 -assert nopostproc +UVM_TESTNAME=i2c_bas
e_test +UVM_TEST_SEQ=i2c_target_fifo_watermarks_acq_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm
_log /dev/null -cm_name 25.i2c_target_fifo_watermarks_acq.1809595643
Directory /workspace/25.i2c_target_fifo_watermarks_acq/latest

Test location /workspace/coverage/default/25.i2c_target_fifo_watermarks_tx.221692797
Short name T676
Test name
Test status
Simulation time 2076989726 ps
CPU time 1.23 seconds
Started Aug 12 04:43:46 PM PDT 24
Finished Aug 12 04:43:47 PM PDT 24
Peak memory 205280 kb
Host smart-60028a3d-873e-477b-bda1-cd29f7945498
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=221692797 -assert nopostproc +UVM_TESTNAME=i2c_base
_test +UVM_TEST_SEQ=i2c_target_fifo_watermarks_tx_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_l
og /dev/null -cm_name 25.i2c_target_fifo_watermarks_tx.221692797
Directory /workspace/25.i2c_target_fifo_watermarks_tx/latest

Test location /workspace/coverage/default/25.i2c_target_hrst.4220965338
Short name T206
Test name
Test status
Simulation time 279394844 ps
CPU time 1.88 seconds
Started Aug 12 04:43:45 PM PDT 24
Finished Aug 12 04:43:47 PM PDT 24
Peak memory 213676 kb
Host smart-aa1b1483-4b8d-4fd8-81d5-b8c00b42b75f
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4220965338 -assert nopostproc +UVM_TESTNAME=i2c_bas
e_test +UVM_TEST_SEQ=i2c_target_hrst_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null
-cm_name 25.i2c_target_hrst.4220965338
Directory /workspace/25.i2c_target_hrst/latest

Test location /workspace/coverage/default/25.i2c_target_intr_smoke.3649704704
Short name T1238
Test name
Test status
Simulation time 4191384687 ps
CPU time 6.3 seconds
Started Aug 12 04:43:43 PM PDT 24
Finished Aug 12 04:43:50 PM PDT 24
Peak memory 221924 kb
Host smart-b269ec21-f38b-4c65-9d1b-7726618709f2
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=200_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VER
BOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3649704704 -assert nopostproc +UVM_TESTNAME=i2c_ba
se_test +UVM_TEST_SEQ=i2c_target_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/nul
l -cm_name 25.i2c_target_intr_smoke.3649704704
Directory /workspace/25.i2c_target_intr_smoke/latest

Test location /workspace/coverage/default/25.i2c_target_intr_stress_wr.1502138650
Short name T833
Test name
Test status
Simulation time 6515465746 ps
CPU time 80.16 seconds
Started Aug 12 04:43:43 PM PDT 24
Finished Aug 12 04:45:04 PM PDT 24
Peak memory 1680688 kb
Host smart-5fd016b2-f3ce-4d53-a028-28abf240be75
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=600_000_000 +use_intr_handler=1 +slow_acq=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNO
TES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1502138650 -assert nopostproc +UVM_TES
TNAME=i2c_base_test +UVM_TEST_SEQ=i2c_target_stress_wr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb
-cm_log /dev/null -cm_name 25.i2c_target_intr_stress_wr.1502138650
Directory /workspace/25.i2c_target_intr_stress_wr/latest

Test location /workspace/coverage/default/25.i2c_target_nack_acqfull.3319648601
Short name T1732
Test name
Test status
Simulation time 1095486197 ps
CPU time 2.95 seconds
Started Aug 12 04:43:48 PM PDT 24
Finished Aug 12 04:43:51 PM PDT 24
Peak memory 213620 kb
Host smart-e86d4d80-f19e-4650-8a39-d48d29117e6b
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3319648601 -assert nopostproc +UVM_TESTNAME=i2c_bas
e_test +UVM_TEST_SEQ=i2c_target_nack_acqfull_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /d
ev/null -cm_name 25.i2c_target_nack_acqfull.3319648601
Directory /workspace/25.i2c_target_nack_acqfull/latest

Test location /workspace/coverage/default/25.i2c_target_nack_txstretch.3790847958
Short name T1291
Test name
Test status
Simulation time 1164130387 ps
CPU time 1.31 seconds
Started Aug 12 04:43:51 PM PDT 24
Finished Aug 12 04:43:53 PM PDT 24
Peak memory 221980 kb
Host smart-a9101bd4-200e-4771-8910-17edfbe96725
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3790847958 -assert nopostproc +UVM_TESTNAME=i2c_bas
e_test +UVM_TEST_SEQ=i2c_target_nack_txstretch_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log
/dev/null -cm_name 25.i2c_target_nack_txstretch.3790847958
Directory /workspace/25.i2c_target_nack_txstretch/latest

Test location /workspace/coverage/default/25.i2c_target_perf.2706950534
Short name T697
Test name
Test status
Simulation time 3273331456 ps
CPU time 5.71 seconds
Started Aug 12 04:43:45 PM PDT 24
Finished Aug 12 04:43:51 PM PDT 24
Peak memory 221956 kb
Host smart-6c146cfe-047d-472a-9c02-984a16768fc0
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2706950534 -assert nopostproc +UVM_TESTNAME=i2c_bas
e_test +UVM_TEST_SEQ=i2c_target_perf_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null
-cm_name 25.i2c_target_perf.2706950534
Directory /workspace/25.i2c_target_perf/latest

Test location /workspace/coverage/default/25.i2c_target_smbus_maxlen.1142793676
Short name T1561
Test name
Test status
Simulation time 1580956209 ps
CPU time 2.09 seconds
Started Aug 12 04:43:44 PM PDT 24
Finished Aug 12 04:43:47 PM PDT 24
Peak memory 205200 kb
Host smart-792957f0-6e16-49b1-ab27-c2df01bedd81
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1142793676 -assert nopostproc +UVM_TESTNAME=i2c_bas
e_test +UVM_TEST_SEQ=i2c_target_smbus_maxlen_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /d
ev/null -cm_name 25.i2c_target_smbus_maxlen.1142793676
Directory /workspace/25.i2c_target_smbus_maxlen/latest

Test location /workspace/coverage/default/25.i2c_target_smoke.815029218
Short name T887
Test name
Test status
Simulation time 1390561678 ps
CPU time 9.97 seconds
Started Aug 12 04:43:44 PM PDT 24
Finished Aug 12 04:43:54 PM PDT 24
Peak memory 213628 kb
Host smart-fe62b667-0c2f-43f4-8d65-350b3fda0482
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=100_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licq
ueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=815029218 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ
=i2c_target_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.i2c_tar
get_smoke.815029218
Directory /workspace/25.i2c_target_smoke/latest

Test location /workspace/coverage/default/25.i2c_target_stress_all.23543936
Short name T1627
Test name
Test status
Simulation time 11984962654 ps
CPU time 74.55 seconds
Started Aug 12 04:43:50 PM PDT 24
Finished Aug 12 04:45:05 PM PDT 24
Peak memory 352220 kb
Host smart-04cc8207-6431-4a90-8a76-a71a50670f9d
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=300_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VER
BOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=23543936 -assert nopostproc +UVM_TESTNAME=i2c_base
_test +UVM_TEST_SEQ=i2c_target_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/
null -cm_name 25.i2c_target_stress_all.23543936
Directory /workspace/25.i2c_target_stress_all/latest

Test location /workspace/coverage/default/25.i2c_target_stress_rd.3674514749
Short name T810
Test name
Test status
Simulation time 2681304819 ps
CPU time 13.31 seconds
Started Aug 12 04:43:46 PM PDT 24
Finished Aug 12 04:43:59 PM PDT 24
Peak memory 216116 kb
Host smart-fdc70dca-ef69-425d-95bf-7824338fab0d
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=100_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licq
ueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3674514749 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SE
Q=i2c_target_stress_rd_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.i2
c_target_stress_rd.3674514749
Directory /workspace/25.i2c_target_stress_rd/latest

Test location /workspace/coverage/default/25.i2c_target_stress_wr.2574667254
Short name T1090
Test name
Test status
Simulation time 20371106401 ps
CPU time 21.83 seconds
Started Aug 12 04:43:44 PM PDT 24
Finished Aug 12 04:44:06 PM PDT 24
Peak memory 205600 kb
Host smart-08529821-1ca5-4f01-916d-b67e662299f2
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=600_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licq
ueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2574667254 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SE
Q=i2c_target_stress_wr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.i2
c_target_stress_wr.2574667254
Directory /workspace/25.i2c_target_stress_wr/latest

Test location /workspace/coverage/default/25.i2c_target_stretch.4143020982
Short name T1152
Test name
Test status
Simulation time 3352263471 ps
CPU time 3.3 seconds
Started Aug 12 04:43:50 PM PDT 24
Finished Aug 12 04:43:53 PM PDT 24
Peak memory 237940 kb
Host smart-a95718bf-7b15-4583-8445-7567580b232f
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=400_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licq
ueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4143020982 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SE
Q=i2c_target_stretch_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.i2c_
target_stretch.4143020982
Directory /workspace/25.i2c_target_stretch/latest

Test location /workspace/coverage/default/25.i2c_target_timeout.3625254366
Short name T1001
Test name
Test status
Simulation time 5275250084 ps
CPU time 7.45 seconds
Started Aug 12 04:43:46 PM PDT 24
Finished Aug 12 04:43:53 PM PDT 24
Peak memory 220464 kb
Host smart-4337f0f1-2eb1-40c7-b37d-15af135acfc8
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=50_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3625254366 -assert nopostproc +UVM_TESTNAME=i2c_bas
e_test +UVM_TEST_SEQ=i2c_target_timeout_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/nu
ll -cm_name 25.i2c_target_timeout.3625254366
Directory /workspace/25.i2c_target_timeout/latest

Test location /workspace/coverage/default/25.i2c_target_tx_stretch_ctrl.2791452097
Short name T1554
Test name
Test status
Simulation time 69261928 ps
CPU time 1.36 seconds
Started Aug 12 04:43:46 PM PDT 24
Finished Aug 12 04:43:47 PM PDT 24
Peak memory 205376 kb
Host smart-da2fbf38-b2a9-4739-abea-5d620b2574c1
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2791452097 -assert nopostproc +UVM_TESTNAME=i2c_bas
e_test +UVM_TEST_SEQ=i2c_target_tx_stretch_ctrl_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log
/dev/null -cm_name 25.i2c_target_tx_stretch_ctrl.2791452097
Directory /workspace/25.i2c_target_tx_stretch_ctrl/latest

Test location /workspace/coverage/default/26.i2c_alert_test.2389035875
Short name T97
Test name
Test status
Simulation time 18597665 ps
CPU time 0.63 seconds
Started Aug 12 04:44:04 PM PDT 24
Finished Aug 12 04:44:04 PM PDT 24
Peak memory 204484 kb
Host smart-312d6d66-9535-4614-9f41-68ba0c476e67
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2389035875 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_common_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.i2c_alert_test.2389035875
Directory /workspace/26.i2c_alert_test/latest

Test location /workspace/coverage/default/26.i2c_host_error_intr.582712993
Short name T583
Test name
Test status
Simulation time 201966403 ps
CPU time 3.41 seconds
Started Aug 12 04:43:54 PM PDT 24
Finished Aug 12 04:43:58 PM PDT 24
Peak memory 234828 kb
Host smart-73622f00-46dc-4891-8c10-da7d69729153
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=582712993 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_error_intr_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.i2c_host_error_intr.582712993
Directory /workspace/26.i2c_host_error_intr/latest

Test location /workspace/coverage/default/26.i2c_host_fifo_fmt_empty.1489570738
Short name T677
Test name
Test status
Simulation time 587964412 ps
CPU time 6.53 seconds
Started Aug 12 04:43:51 PM PDT 24
Finished Aug 12 04:43:57 PM PDT 24
Peak memory 269752 kb
Host smart-b3ec4fbc-8c68-4649-933a-99ebd3576a6f
User root
Command /workspace/default/simv +test_timeout_ns=10_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1489570738 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_fifo_fmt_em
pty_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.i2c_host_fifo_fmt_emp
ty.1489570738
Directory /workspace/26.i2c_host_fifo_fmt_empty/latest

Test location /workspace/coverage/default/26.i2c_host_fifo_full.938259021
Short name T1590
Test name
Test status
Simulation time 9941707940 ps
CPU time 70.02 seconds
Started Aug 12 04:43:56 PM PDT 24
Finished Aug 12 04:45:06 PM PDT 24
Peak memory 381724 kb
Host smart-7941235c-3815-4513-9504-394863785a5a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=938259021 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_fifo_full_vseq +en_cov=1 -cm line+cond+f
sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.i2c_host_fifo_full.938259021
Directory /workspace/26.i2c_host_fifo_full/latest

Test location /workspace/coverage/default/26.i2c_host_fifo_overflow.2645127784
Short name T759
Test name
Test status
Simulation time 56584030570 ps
CPU time 99.8 seconds
Started Aug 12 04:43:52 PM PDT 24
Finished Aug 12 04:45:31 PM PDT 24
Peak memory 915824 kb
Host smart-274420cb-c6d5-48a4-adbe-ae195de29ac8
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2645127784 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_fifo_overflow_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.i2c_host_fifo_overflow.2645127784
Directory /workspace/26.i2c_host_fifo_overflow/latest

Test location /workspace/coverage/default/26.i2c_host_fifo_reset_fmt.2806585474
Short name T784
Test name
Test status
Simulation time 162347380 ps
CPU time 1.33 seconds
Started Aug 12 04:43:51 PM PDT 24
Finished Aug 12 04:43:53 PM PDT 24
Peak memory 205104 kb
Host smart-6d44929d-2da6-4852-aa99-70e7f19ff7a7
User root
Command /workspace/default/simv +test_timeout_ns=10_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2806585474 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_fifo_reset_
fmt_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.i2c_host_fifo_reset_f
mt.2806585474
Directory /workspace/26.i2c_host_fifo_reset_fmt/latest

Test location /workspace/coverage/default/26.i2c_host_fifo_reset_rx.1507969792
Short name T1045
Test name
Test status
Simulation time 123209993 ps
CPU time 2.72 seconds
Started Aug 12 04:43:52 PM PDT 24
Finished Aug 12 04:43:54 PM PDT 24
Peak memory 205216 kb
Host smart-dfbafd79-0e43-4725-8071-46041c8bf1bb
User root
Command /workspace/default/simv +test_timeout_ns=10_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1507969792 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_fifo_reset_
rx_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.i2c_host_fifo_reset_rx
.1507969792
Directory /workspace/26.i2c_host_fifo_reset_rx/latest

Test location /workspace/coverage/default/26.i2c_host_fifo_watermark.2106350862
Short name T1533
Test name
Test status
Simulation time 9214576524 ps
CPU time 277.13 seconds
Started Aug 12 04:43:52 PM PDT 24
Finished Aug 12 04:48:29 PM PDT 24
Peak memory 1172896 kb
Host smart-8a40cfee-767f-430c-90ad-50945989e841
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2106350862 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_fifo_watermark_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.i2c_host_fifo_watermark.2106350862
Directory /workspace/26.i2c_host_fifo_watermark/latest

Test location /workspace/coverage/default/26.i2c_host_override.971934385
Short name T158
Test name
Test status
Simulation time 31051908 ps
CPU time 0.67 seconds
Started Aug 12 04:43:53 PM PDT 24
Finished Aug 12 04:43:54 PM PDT 24
Peak memory 204876 kb
Host smart-71c2ee72-ba61-4d9e-bfb7-c83fa738eedf
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=971934385 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_override_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.i2c_host_override.971934385
Directory /workspace/26.i2c_host_override/latest

Test location /workspace/coverage/default/26.i2c_host_perf.12999651
Short name T876
Test name
Test status
Simulation time 4831755931 ps
CPU time 184.57 seconds
Started Aug 12 04:43:54 PM PDT 24
Finished Aug 12 04:46:59 PM PDT 24
Peak memory 205360 kb
Host smart-cb39d30a-b8cb-44e3-a29a-1af76c6735ee
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=12999651 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_perf_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.i2c_host_perf.12999651
Directory /workspace/26.i2c_host_perf/latest

Test location /workspace/coverage/default/26.i2c_host_perf_precise.2507564911
Short name T528
Test name
Test status
Simulation time 776718555 ps
CPU time 8.74 seconds
Started Aug 12 04:43:54 PM PDT 24
Finished Aug 12 04:44:02 PM PDT 24
Peak memory 205216 kb
Host smart-a79a67cc-f915-41a9-9864-b4bb61c428d3
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2507564911 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_perf_precise_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.i2c_host_perf_precise.2507564911
Directory /workspace/26.i2c_host_perf_precise/latest

Test location /workspace/coverage/default/26.i2c_host_smoke.459611712
Short name T1346
Test name
Test status
Simulation time 1743577598 ps
CPU time 26.99 seconds
Started Aug 12 04:43:55 PM PDT 24
Finished Aug 12 04:44:22 PM PDT 24
Peak memory 329772 kb
Host smart-bd22259a-376b-4f72-ab5f-44e1c4b698dc
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=459611712 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_smoke_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.i2c_host_smoke.459611712
Directory /workspace/26.i2c_host_smoke/latest

Test location /workspace/coverage/default/26.i2c_host_stretch_timeout.2705309649
Short name T561
Test name
Test status
Simulation time 1944486414 ps
CPU time 8 seconds
Started Aug 12 04:43:52 PM PDT 24
Finished Aug 12 04:44:00 PM PDT 24
Peak memory 213412 kb
Host smart-3553d747-9df8-4286-bbc2-aa6488ae5f53
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2705309649 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_stretch_timeout_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.i2c_host_stretch_timeout.2705309649
Directory /workspace/26.i2c_host_stretch_timeout/latest

Test location /workspace/coverage/default/26.i2c_target_bad_addr.2932251660
Short name T353
Test name
Test status
Simulation time 3189934992 ps
CPU time 4.67 seconds
Started Aug 12 04:43:54 PM PDT 24
Finished Aug 12 04:43:59 PM PDT 24
Peak memory 219192 kb
Host smart-a2cc7db1-4061-4f0e-b33b-2307a389ce3f
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +i2c_bad_addr_pct=50 +cdc_instrumentation_enabled=1 +UVM_
NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2932251660 -assert nopostproc
+UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_target_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.
vdb -cm_log /dev/null -cm_name 26.i2c_target_bad_addr.2932251660
Directory /workspace/26.i2c_target_bad_addr/latest

Test location /workspace/coverage/default/26.i2c_target_fifo_reset_acq.107437760
Short name T1137
Test name
Test status
Simulation time 110575359 ps
CPU time 0.88 seconds
Started Aug 12 04:43:56 PM PDT 24
Finished Aug 12 04:43:57 PM PDT 24
Peak memory 205224 kb
Host smart-2b4bc197-7873-4dbd-a675-c5f5375ec369
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=107437760 -assert nopostproc +UVM_TESTNAME=i2c_base
_test +UVM_TEST_SEQ=i2c_target_fifo_reset_acq_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /
dev/null -cm_name 26.i2c_target_fifo_reset_acq.107437760
Directory /workspace/26.i2c_target_fifo_reset_acq/latest

Test location /workspace/coverage/default/26.i2c_target_fifo_reset_tx.3563220992
Short name T1276
Test name
Test status
Simulation time 261581034 ps
CPU time 0.81 seconds
Started Aug 12 04:43:53 PM PDT 24
Finished Aug 12 04:43:54 PM PDT 24
Peak memory 205372 kb
Host smart-372e241e-d5e5-4110-8454-2b8614876b68
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3563220992 -assert nopostproc +UVM_TESTNAME=i2c_bas
e_test +UVM_TEST_SEQ=i2c_target_fifo_reset_tx_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /
dev/null -cm_name 26.i2c_target_fifo_reset_tx.3563220992
Directory /workspace/26.i2c_target_fifo_reset_tx/latest

Test location /workspace/coverage/default/26.i2c_target_fifo_watermarks_acq.1213666837
Short name T392
Test name
Test status
Simulation time 4238409913 ps
CPU time 2.27 seconds
Started Aug 12 04:43:58 PM PDT 24
Finished Aug 12 04:44:00 PM PDT 24
Peak memory 205500 kb
Host smart-0efd27c8-42f6-4653-a28a-38a66e216b65
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1213666837 -assert nopostproc +UVM_TESTNAME=i2c_bas
e_test +UVM_TEST_SEQ=i2c_target_fifo_watermarks_acq_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm
_log /dev/null -cm_name 26.i2c_target_fifo_watermarks_acq.1213666837
Directory /workspace/26.i2c_target_fifo_watermarks_acq/latest

Test location /workspace/coverage/default/26.i2c_target_fifo_watermarks_tx.3951484052
Short name T1670
Test name
Test status
Simulation time 447121291 ps
CPU time 1.43 seconds
Started Aug 12 04:43:52 PM PDT 24
Finished Aug 12 04:43:54 PM PDT 24
Peak memory 205260 kb
Host smart-e6d87905-410c-47b9-a635-75fd9ffdadf0
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3951484052 -assert nopostproc +UVM_TESTNAME=i2c_bas
e_test +UVM_TEST_SEQ=i2c_target_fifo_watermarks_tx_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_
log /dev/null -cm_name 26.i2c_target_fifo_watermarks_tx.3951484052
Directory /workspace/26.i2c_target_fifo_watermarks_tx/latest

Test location /workspace/coverage/default/26.i2c_target_intr_smoke.3907669193
Short name T716
Test name
Test status
Simulation time 3405807884 ps
CPU time 4.36 seconds
Started Aug 12 04:43:53 PM PDT 24
Finished Aug 12 04:43:58 PM PDT 24
Peak memory 218732 kb
Host smart-fdc72d1f-d96f-42fe-b516-cc414a961125
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=200_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VER
BOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3907669193 -assert nopostproc +UVM_TESTNAME=i2c_ba
se_test +UVM_TEST_SEQ=i2c_target_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/nul
l -cm_name 26.i2c_target_intr_smoke.3907669193
Directory /workspace/26.i2c_target_intr_smoke/latest

Test location /workspace/coverage/default/26.i2c_target_intr_stress_wr.893450358
Short name T931
Test name
Test status
Simulation time 17104555505 ps
CPU time 89.25 seconds
Started Aug 12 04:43:56 PM PDT 24
Finished Aug 12 04:45:25 PM PDT 24
Peak memory 1323372 kb
Host smart-7885c09b-e5cb-440b-a641-da4276395073
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=600_000_000 +use_intr_handler=1 +slow_acq=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNO
TES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=893450358 -assert nopostproc +UVM_TEST
NAME=i2c_base_test +UVM_TEST_SEQ=i2c_target_stress_wr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -
cm_log /dev/null -cm_name 26.i2c_target_intr_stress_wr.893450358
Directory /workspace/26.i2c_target_intr_stress_wr/latest

Test location /workspace/coverage/default/26.i2c_target_nack_acqfull.593546079
Short name T871
Test name
Test status
Simulation time 2127632907 ps
CPU time 2.96 seconds
Started Aug 12 04:43:53 PM PDT 24
Finished Aug 12 04:43:56 PM PDT 24
Peak memory 213692 kb
Host smart-15d80f8a-b57c-48a1-9b7e-608a2a627f52
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=593546079 -assert nopostproc +UVM_TESTNAME=i2c_base
_test +UVM_TEST_SEQ=i2c_target_nack_acqfull_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /de
v/null -cm_name 26.i2c_target_nack_acqfull.593546079
Directory /workspace/26.i2c_target_nack_acqfull/latest

Test location /workspace/coverage/default/26.i2c_target_nack_acqfull_addr.641755718
Short name T929
Test name
Test status
Simulation time 4400789954 ps
CPU time 2.57 seconds
Started Aug 12 04:43:56 PM PDT 24
Finished Aug 12 04:43:58 PM PDT 24
Peak memory 205524 kb
Host smart-520f4d47-ce54-4818-9594-bc7923bd5e4f
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=641755718 -assert nopostproc +UVM_TESTNAME=i2c_base
_test +UVM_TEST_SEQ=i2c_target_nack_acqfull_addr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_lo
g /dev/null -cm_name 26.i2c_target_nack_acqfull_addr.641755718
Directory /workspace/26.i2c_target_nack_acqfull_addr/latest

Test location /workspace/coverage/default/26.i2c_target_perf.2796058944
Short name T377
Test name
Test status
Simulation time 2015212543 ps
CPU time 7.69 seconds
Started Aug 12 04:43:52 PM PDT 24
Finished Aug 12 04:44:00 PM PDT 24
Peak memory 229948 kb
Host smart-25d143ad-face-4d84-9be4-7e63ab04e7fc
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2796058944 -assert nopostproc +UVM_TESTNAME=i2c_bas
e_test +UVM_TEST_SEQ=i2c_target_perf_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null
-cm_name 26.i2c_target_perf.2796058944
Directory /workspace/26.i2c_target_perf/latest

Test location /workspace/coverage/default/26.i2c_target_smbus_maxlen.4244286475
Short name T523
Test name
Test status
Simulation time 594907266 ps
CPU time 2.56 seconds
Started Aug 12 04:43:56 PM PDT 24
Finished Aug 12 04:43:58 PM PDT 24
Peak memory 205144 kb
Host smart-617d7375-6e66-4d0d-8fc3-c4c4309d5380
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4244286475 -assert nopostproc +UVM_TESTNAME=i2c_bas
e_test +UVM_TEST_SEQ=i2c_target_smbus_maxlen_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /d
ev/null -cm_name 26.i2c_target_smbus_maxlen.4244286475
Directory /workspace/26.i2c_target_smbus_maxlen/latest

Test location /workspace/coverage/default/26.i2c_target_smoke.4070938300
Short name T307
Test name
Test status
Simulation time 1091501014 ps
CPU time 17.82 seconds
Started Aug 12 04:43:54 PM PDT 24
Finished Aug 12 04:44:12 PM PDT 24
Peak memory 218080 kb
Host smart-8864f20d-d9d1-4ade-8dd8-7fc9d61d0235
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=100_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licq
ueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4070938300 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SE
Q=i2c_target_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.i2c_ta
rget_smoke.4070938300
Directory /workspace/26.i2c_target_smoke/latest

Test location /workspace/coverage/default/26.i2c_target_stress_all.1569066794
Short name T435
Test name
Test status
Simulation time 34978919727 ps
CPU time 64.04 seconds
Started Aug 12 04:43:58 PM PDT 24
Finished Aug 12 04:45:02 PM PDT 24
Peak memory 712832 kb
Host smart-8607af25-c207-4b81-87b7-0b23d85dbb8d
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=300_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VER
BOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1569066794 -assert nopostproc +UVM_TESTNAME=i2c_ba
se_test +UVM_TEST_SEQ=i2c_target_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /de
v/null -cm_name 26.i2c_target_stress_all.1569066794
Directory /workspace/26.i2c_target_stress_all/latest

Test location /workspace/coverage/default/26.i2c_target_stress_rd.1755296549
Short name T877
Test name
Test status
Simulation time 1249994957 ps
CPU time 24.42 seconds
Started Aug 12 04:43:56 PM PDT 24
Finished Aug 12 04:44:20 PM PDT 24
Peak memory 229920 kb
Host smart-883248dd-7ad8-4840-98ae-82d5b3cf24f2
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=100_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licq
ueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1755296549 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SE
Q=i2c_target_stress_rd_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.i2
c_target_stress_rd.1755296549
Directory /workspace/26.i2c_target_stress_rd/latest

Test location /workspace/coverage/default/26.i2c_target_stress_wr.937457638
Short name T70
Test name
Test status
Simulation time 61347110069 ps
CPU time 826.26 seconds
Started Aug 12 04:43:51 PM PDT 24
Finished Aug 12 04:57:37 PM PDT 24
Peak memory 5185600 kb
Host smart-eb61db3d-b3be-4382-82e0-e6ea1b1da848
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=600_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licq
ueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=937457638 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ
=i2c_target_stress_wr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.i2c
_target_stress_wr.937457638
Directory /workspace/26.i2c_target_stress_wr/latest

Test location /workspace/coverage/default/26.i2c_target_stretch.3571279573
Short name T1723
Test name
Test status
Simulation time 4760402539 ps
CPU time 69.48 seconds
Started Aug 12 04:43:51 PM PDT 24
Finished Aug 12 04:45:01 PM PDT 24
Peak memory 913704 kb
Host smart-57142300-b718-4e39-b4a4-99d2e548c5f5
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=400_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licq
ueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3571279573 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SE
Q=i2c_target_stretch_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.i2c_
target_stretch.3571279573
Directory /workspace/26.i2c_target_stretch/latest

Test location /workspace/coverage/default/26.i2c_target_timeout.1370458451
Short name T1440
Test name
Test status
Simulation time 4133954491 ps
CPU time 6.72 seconds
Started Aug 12 04:43:53 PM PDT 24
Finished Aug 12 04:43:59 PM PDT 24
Peak memory 213788 kb
Host smart-36d98772-15c0-445d-bd45-f1dfe9bf4d15
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=50_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1370458451 -assert nopostproc +UVM_TESTNAME=i2c_bas
e_test +UVM_TEST_SEQ=i2c_target_timeout_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/nu
ll -cm_name 26.i2c_target_timeout.1370458451
Directory /workspace/26.i2c_target_timeout/latest

Test location /workspace/coverage/default/26.i2c_target_tx_stretch_ctrl.1373741171
Short name T1508
Test name
Test status
Simulation time 175973752 ps
CPU time 2.96 seconds
Started Aug 12 04:43:58 PM PDT 24
Finished Aug 12 04:44:01 PM PDT 24
Peak memory 205496 kb
Host smart-9ff9a119-607b-4279-a055-efb5150edb39
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1373741171 -assert nopostproc +UVM_TESTNAME=i2c_bas
e_test +UVM_TEST_SEQ=i2c_target_tx_stretch_ctrl_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log
/dev/null -cm_name 26.i2c_target_tx_stretch_ctrl.1373741171
Directory /workspace/26.i2c_target_tx_stretch_ctrl/latest

Test location /workspace/coverage/default/27.i2c_alert_test.3325981638
Short name T126
Test name
Test status
Simulation time 23595832 ps
CPU time 0.62 seconds
Started Aug 12 04:44:09 PM PDT 24
Finished Aug 12 04:44:10 PM PDT 24
Peak memory 204408 kb
Host smart-551f5467-9706-47a9-a9ae-dfb1c87c7028
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3325981638 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_common_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.i2c_alert_test.3325981638
Directory /workspace/27.i2c_alert_test/latest

Test location /workspace/coverage/default/27.i2c_host_error_intr.3604760696
Short name T470
Test name
Test status
Simulation time 92891020 ps
CPU time 1.56 seconds
Started Aug 12 04:44:03 PM PDT 24
Finished Aug 12 04:44:04 PM PDT 24
Peak memory 213460 kb
Host smart-39a02667-f98b-4384-8c68-e82ad6e8ee4f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3604760696 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_error_intr_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.i2c_host_error_intr.3604760696
Directory /workspace/27.i2c_host_error_intr/latest

Test location /workspace/coverage/default/27.i2c_host_fifo_fmt_empty.3011321183
Short name T1047
Test name
Test status
Simulation time 1162664442 ps
CPU time 5.4 seconds
Started Aug 12 04:44:00 PM PDT 24
Finished Aug 12 04:44:06 PM PDT 24
Peak memory 261368 kb
Host smart-8598e6da-0543-47be-b712-88e4a25b632e
User root
Command /workspace/default/simv +test_timeout_ns=10_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3011321183 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_fifo_fmt_em
pty_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.i2c_host_fifo_fmt_emp
ty.3011321183
Directory /workspace/27.i2c_host_fifo_fmt_empty/latest

Test location /workspace/coverage/default/27.i2c_host_fifo_full.341518587
Short name T686
Test name
Test status
Simulation time 3582945791 ps
CPU time 88.31 seconds
Started Aug 12 04:44:03 PM PDT 24
Finished Aug 12 04:45:31 PM PDT 24
Peak memory 480564 kb
Host smart-999ed543-b9d1-4036-8e8d-de3ad0d6e1c8
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=341518587 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_fifo_full_vseq +en_cov=1 -cm line+cond+f
sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.i2c_host_fifo_full.341518587
Directory /workspace/27.i2c_host_fifo_full/latest

Test location /workspace/coverage/default/27.i2c_host_fifo_overflow.774757384
Short name T1000
Test name
Test status
Simulation time 1563048117 ps
CPU time 51.38 seconds
Started Aug 12 04:43:59 PM PDT 24
Finished Aug 12 04:44:51 PM PDT 24
Peak memory 592384 kb
Host smart-5fbb48b9-c44e-4bfe-b99b-b1c745db3b74
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=774757384 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_fifo_overflow_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.i2c_host_fifo_overflow.774757384
Directory /workspace/27.i2c_host_fifo_overflow/latest

Test location /workspace/coverage/default/27.i2c_host_fifo_reset_fmt.634070240
Short name T252
Test name
Test status
Simulation time 186064303 ps
CPU time 1.43 seconds
Started Aug 12 04:44:00 PM PDT 24
Finished Aug 12 04:44:02 PM PDT 24
Peak memory 205056 kb
Host smart-5dd48adf-5f59-40ce-8558-e57bc0814734
User root
Command /workspace/default/simv +test_timeout_ns=10_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=634070240 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_fifo_reset_f
mt_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.i2c_host_fifo_reset_fm
t.634070240
Directory /workspace/27.i2c_host_fifo_reset_fmt/latest

Test location /workspace/coverage/default/27.i2c_host_fifo_reset_rx.2792162030
Short name T1380
Test name
Test status
Simulation time 1008943168 ps
CPU time 7.17 seconds
Started Aug 12 04:44:01 PM PDT 24
Finished Aug 12 04:44:09 PM PDT 24
Peak memory 253980 kb
Host smart-c8635c67-03b5-424a-a69a-f35a1d00374d
User root
Command /workspace/default/simv +test_timeout_ns=10_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2792162030 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_fifo_reset_
rx_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.i2c_host_fifo_reset_rx
.2792162030
Directory /workspace/27.i2c_host_fifo_reset_rx/latest

Test location /workspace/coverage/default/27.i2c_host_fifo_watermark.3414947121
Short name T609
Test name
Test status
Simulation time 10610283954 ps
CPU time 144.03 seconds
Started Aug 12 04:44:03 PM PDT 24
Finished Aug 12 04:46:28 PM PDT 24
Peak memory 659832 kb
Host smart-f6d730fc-ea7f-445c-a92d-e044873c81a2
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3414947121 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_fifo_watermark_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.i2c_host_fifo_watermark.3414947121
Directory /workspace/27.i2c_host_fifo_watermark/latest

Test location /workspace/coverage/default/27.i2c_host_may_nack.3876118808
Short name T264
Test name
Test status
Simulation time 538161247 ps
CPU time 4.27 seconds
Started Aug 12 04:44:00 PM PDT 24
Finished Aug 12 04:44:05 PM PDT 24
Peak memory 205260 kb
Host smart-4139a98c-8f18-4f57-b69e-c11074614e35
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3876118808 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_may_nack_vseq +en_cov=1 -cm line+cond+f
sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.i2c_host_may_nack.3876118808
Directory /workspace/27.i2c_host_may_nack/latest

Test location /workspace/coverage/default/27.i2c_host_override.4006293942
Short name T1594
Test name
Test status
Simulation time 21104419 ps
CPU time 0.74 seconds
Started Aug 12 04:44:02 PM PDT 24
Finished Aug 12 04:44:02 PM PDT 24
Peak memory 204996 kb
Host smart-8eb0904d-b9bc-4148-aac6-51d2165195fa
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4006293942 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_override_vseq +en_cov=1 -cm line+cond+f
sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.i2c_host_override.4006293942
Directory /workspace/27.i2c_host_override/latest

Test location /workspace/coverage/default/27.i2c_host_perf.2365337111
Short name T623
Test name
Test status
Simulation time 3115637849 ps
CPU time 20.57 seconds
Started Aug 12 04:43:59 PM PDT 24
Finished Aug 12 04:44:20 PM PDT 24
Peak memory 218520 kb
Host smart-32450f31-59fa-4cff-a54d-c6beb77f85a1
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2365337111 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_perf_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.i2c_host_perf.2365337111
Directory /workspace/27.i2c_host_perf/latest

Test location /workspace/coverage/default/27.i2c_host_perf_precise.3899961704
Short name T1746
Test name
Test status
Simulation time 42687634 ps
CPU time 1.43 seconds
Started Aug 12 04:44:00 PM PDT 24
Finished Aug 12 04:44:02 PM PDT 24
Peak memory 224808 kb
Host smart-25531a8d-89f5-4c03-a46e-50443e137cc5
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3899961704 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_perf_precise_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.i2c_host_perf_precise.3899961704
Directory /workspace/27.i2c_host_perf_precise/latest

Test location /workspace/coverage/default/27.i2c_host_smoke.3080510827
Short name T1328
Test name
Test status
Simulation time 6380991072 ps
CPU time 25.31 seconds
Started Aug 12 04:44:01 PM PDT 24
Finished Aug 12 04:44:26 PM PDT 24
Peak memory 335016 kb
Host smart-e7aa6999-afa5-4c04-b951-e9e33951fc27
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3080510827 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_smoke_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.i2c_host_smoke.3080510827
Directory /workspace/27.i2c_host_smoke/latest

Test location /workspace/coverage/default/27.i2c_host_stretch_timeout.2106153962
Short name T461
Test name
Test status
Simulation time 1192112997 ps
CPU time 9.93 seconds
Started Aug 12 04:44:03 PM PDT 24
Finished Aug 12 04:44:13 PM PDT 24
Peak memory 219848 kb
Host smart-6f964b23-ba4e-4bc4-9b86-d82e93cf1a60
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2106153962 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_stretch_timeout_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.i2c_host_stretch_timeout.2106153962
Directory /workspace/27.i2c_host_stretch_timeout/latest

Test location /workspace/coverage/default/27.i2c_target_bad_addr.4180118304
Short name T1297
Test name
Test status
Simulation time 3250664714 ps
CPU time 4.43 seconds
Started Aug 12 04:44:01 PM PDT 24
Finished Aug 12 04:44:05 PM PDT 24
Peak memory 213808 kb
Host smart-94834256-5455-4093-8990-768356188c09
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +i2c_bad_addr_pct=50 +cdc_instrumentation_enabled=1 +UVM_
NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4180118304 -assert nopostproc
+UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_target_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.
vdb -cm_log /dev/null -cm_name 27.i2c_target_bad_addr.4180118304
Directory /workspace/27.i2c_target_bad_addr/latest

Test location /workspace/coverage/default/27.i2c_target_fifo_reset_acq.3537977205
Short name T465
Test name
Test status
Simulation time 173922137 ps
CPU time 1.12 seconds
Started Aug 12 04:44:01 PM PDT 24
Finished Aug 12 04:44:02 PM PDT 24
Peak memory 205292 kb
Host smart-945a4779-43a6-45cd-a405-418505a4cd10
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3537977205 -assert nopostproc +UVM_TESTNAME=i2c_bas
e_test +UVM_TEST_SEQ=i2c_target_fifo_reset_acq_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log
/dev/null -cm_name 27.i2c_target_fifo_reset_acq.3537977205
Directory /workspace/27.i2c_target_fifo_reset_acq/latest

Test location /workspace/coverage/default/27.i2c_target_fifo_reset_tx.3492177583
Short name T736
Test name
Test status
Simulation time 166466649 ps
CPU time 1.28 seconds
Started Aug 12 04:44:01 PM PDT 24
Finished Aug 12 04:44:02 PM PDT 24
Peak memory 213912 kb
Host smart-1071d482-9acd-47ff-8706-1af49ae5a229
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3492177583 -assert nopostproc +UVM_TESTNAME=i2c_bas
e_test +UVM_TEST_SEQ=i2c_target_fifo_reset_tx_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /
dev/null -cm_name 27.i2c_target_fifo_reset_tx.3492177583
Directory /workspace/27.i2c_target_fifo_reset_tx/latest

Test location /workspace/coverage/default/27.i2c_target_fifo_watermarks_acq.2796720411
Short name T1280
Test name
Test status
Simulation time 321416517 ps
CPU time 2.3 seconds
Started Aug 12 04:44:01 PM PDT 24
Finished Aug 12 04:44:04 PM PDT 24
Peak memory 205584 kb
Host smart-a10703ac-57b4-4dfc-a7f5-75171ff0f91e
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2796720411 -assert nopostproc +UVM_TESTNAME=i2c_bas
e_test +UVM_TEST_SEQ=i2c_target_fifo_watermarks_acq_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm
_log /dev/null -cm_name 27.i2c_target_fifo_watermarks_acq.2796720411
Directory /workspace/27.i2c_target_fifo_watermarks_acq/latest

Test location /workspace/coverage/default/27.i2c_target_fifo_watermarks_tx.3227799119
Short name T899
Test name
Test status
Simulation time 250163356 ps
CPU time 1.5 seconds
Started Aug 12 04:44:00 PM PDT 24
Finished Aug 12 04:44:02 PM PDT 24
Peak memory 205276 kb
Host smart-edc67f29-99af-40bf-b83c-799978c9b6ef
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3227799119 -assert nopostproc +UVM_TESTNAME=i2c_bas
e_test +UVM_TEST_SEQ=i2c_target_fifo_watermarks_tx_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_
log /dev/null -cm_name 27.i2c_target_fifo_watermarks_tx.3227799119
Directory /workspace/27.i2c_target_fifo_watermarks_tx/latest

Test location /workspace/coverage/default/27.i2c_target_intr_smoke.3399795287
Short name T1578
Test name
Test status
Simulation time 861376072 ps
CPU time 5.43 seconds
Started Aug 12 04:44:03 PM PDT 24
Finished Aug 12 04:44:08 PM PDT 24
Peak memory 218808 kb
Host smart-db4faee8-fba4-440d-adba-10cd4f212220
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=200_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VER
BOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3399795287 -assert nopostproc +UVM_TESTNAME=i2c_ba
se_test +UVM_TEST_SEQ=i2c_target_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/nul
l -cm_name 27.i2c_target_intr_smoke.3399795287
Directory /workspace/27.i2c_target_intr_smoke/latest

Test location /workspace/coverage/default/27.i2c_target_intr_stress_wr.602826893
Short name T1295
Test name
Test status
Simulation time 17522596018 ps
CPU time 223.13 seconds
Started Aug 12 04:44:01 PM PDT 24
Finished Aug 12 04:47:44 PM PDT 24
Peak memory 2677276 kb
Host smart-b916acb9-9b0f-4690-a701-11c45f092191
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=600_000_000 +use_intr_handler=1 +slow_acq=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNO
TES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=602826893 -assert nopostproc +UVM_TEST
NAME=i2c_base_test +UVM_TEST_SEQ=i2c_target_stress_wr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -
cm_log /dev/null -cm_name 27.i2c_target_intr_stress_wr.602826893
Directory /workspace/27.i2c_target_intr_stress_wr/latest

Test location /workspace/coverage/default/27.i2c_target_nack_acqfull.3836731026
Short name T595
Test name
Test status
Simulation time 1799151793 ps
CPU time 2.79 seconds
Started Aug 12 04:44:00 PM PDT 24
Finished Aug 12 04:44:03 PM PDT 24
Peak memory 213740 kb
Host smart-78ca5c03-e8f8-4ff7-9d98-b87460129d70
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3836731026 -assert nopostproc +UVM_TESTNAME=i2c_bas
e_test +UVM_TEST_SEQ=i2c_target_nack_acqfull_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /d
ev/null -cm_name 27.i2c_target_nack_acqfull.3836731026
Directory /workspace/27.i2c_target_nack_acqfull/latest

Test location /workspace/coverage/default/27.i2c_target_nack_acqfull_addr.2380244223
Short name T1709
Test name
Test status
Simulation time 1131331704 ps
CPU time 3.07 seconds
Started Aug 12 04:44:12 PM PDT 24
Finished Aug 12 04:44:15 PM PDT 24
Peak memory 205512 kb
Host smart-eea1c01d-ccea-4a50-8f5b-e8c468672646
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2380244223 -assert nopostproc +UVM_TESTNAME=i2c_bas
e_test +UVM_TEST_SEQ=i2c_target_nack_acqfull_addr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_l
og /dev/null -cm_name 27.i2c_target_nack_acqfull_addr.2380244223
Directory /workspace/27.i2c_target_nack_acqfull_addr/latest

Test location /workspace/coverage/default/27.i2c_target_nack_txstretch.2102392524
Short name T843
Test name
Test status
Simulation time 187742033 ps
CPU time 1.52 seconds
Started Aug 12 04:44:09 PM PDT 24
Finished Aug 12 04:44:10 PM PDT 24
Peak memory 222108 kb
Host smart-a44200d3-da46-453e-a6fe-343ba21de881
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2102392524 -assert nopostproc +UVM_TESTNAME=i2c_bas
e_test +UVM_TEST_SEQ=i2c_target_nack_txstretch_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log
/dev/null -cm_name 27.i2c_target_nack_txstretch.2102392524
Directory /workspace/27.i2c_target_nack_txstretch/latest

Test location /workspace/coverage/default/27.i2c_target_perf.914619883
Short name T1305
Test name
Test status
Simulation time 2682803885 ps
CPU time 4.77 seconds
Started Aug 12 04:44:00 PM PDT 24
Finished Aug 12 04:44:05 PM PDT 24
Peak memory 220644 kb
Host smart-5018f55c-f430-499d-a2b2-30c080754609
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=914619883 -assert nopostproc +UVM_TESTNAME=i2c_base
_test +UVM_TEST_SEQ=i2c_target_perf_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -
cm_name 27.i2c_target_perf.914619883
Directory /workspace/27.i2c_target_perf/latest

Test location /workspace/coverage/default/27.i2c_target_smbus_maxlen.691276594
Short name T1283
Test name
Test status
Simulation time 4871626910 ps
CPU time 2.22 seconds
Started Aug 12 04:44:05 PM PDT 24
Finished Aug 12 04:44:07 PM PDT 24
Peak memory 205280 kb
Host smart-8b489d61-a562-4889-990c-468ae4e1d88d
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=691276594 -assert nopostproc +UVM_TESTNAME=i2c_base
_test +UVM_TEST_SEQ=i2c_target_smbus_maxlen_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /de
v/null -cm_name 27.i2c_target_smbus_maxlen.691276594
Directory /workspace/27.i2c_target_smbus_maxlen/latest

Test location /workspace/coverage/default/27.i2c_target_smoke.3464419635
Short name T89
Test name
Test status
Simulation time 11931136922 ps
CPU time 40.45 seconds
Started Aug 12 04:44:01 PM PDT 24
Finished Aug 12 04:44:42 PM PDT 24
Peak memory 222056 kb
Host smart-9cb00e10-262a-4829-821f-5af939e14c7b
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=100_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licq
ueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3464419635 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SE
Q=i2c_target_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.i2c_ta
rget_smoke.3464419635
Directory /workspace/27.i2c_target_smoke/latest

Test location /workspace/coverage/default/27.i2c_target_stress_all.128017183
Short name T1064
Test name
Test status
Simulation time 69842110303 ps
CPU time 33.18 seconds
Started Aug 12 04:43:59 PM PDT 24
Finished Aug 12 04:44:32 PM PDT 24
Peak memory 238944 kb
Host smart-ad58a8a8-933e-4233-b9aa-7795f0539cb5
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=300_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VER
BOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=128017183 -assert nopostproc +UVM_TESTNAME=i2c_bas
e_test +UVM_TEST_SEQ=i2c_target_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev
/null -cm_name 27.i2c_target_stress_all.128017183
Directory /workspace/27.i2c_target_stress_all/latest

Test location /workspace/coverage/default/27.i2c_target_stress_rd.1789948544
Short name T1339
Test name
Test status
Simulation time 6613487123 ps
CPU time 73.5 seconds
Started Aug 12 04:44:03 PM PDT 24
Finished Aug 12 04:45:16 PM PDT 24
Peak memory 218536 kb
Host smart-882f30e5-f1d0-4076-b1ed-c8eb7f4d27ef
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=100_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licq
ueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1789948544 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SE
Q=i2c_target_stress_rd_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.i2
c_target_stress_rd.1789948544
Directory /workspace/27.i2c_target_stress_rd/latest

Test location /workspace/coverage/default/27.i2c_target_stress_wr.1765146527
Short name T1550
Test name
Test status
Simulation time 54686094184 ps
CPU time 557.21 seconds
Started Aug 12 04:44:00 PM PDT 24
Finished Aug 12 04:53:18 PM PDT 24
Peak memory 4335156 kb
Host smart-d85b0540-db4b-44f7-a2e0-321d13123ae6
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=600_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licq
ueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1765146527 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SE
Q=i2c_target_stress_wr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.i2
c_target_stress_wr.1765146527
Directory /workspace/27.i2c_target_stress_wr/latest

Test location /workspace/coverage/default/27.i2c_target_stretch.3124335156
Short name T200
Test name
Test status
Simulation time 1420898169 ps
CPU time 1.63 seconds
Started Aug 12 04:44:02 PM PDT 24
Finished Aug 12 04:44:03 PM PDT 24
Peak memory 205364 kb
Host smart-3784aaa5-ba44-400c-96fd-c16b73b3206e
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=400_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licq
ueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3124335156 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SE
Q=i2c_target_stretch_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.i2c_
target_stretch.3124335156
Directory /workspace/27.i2c_target_stretch/latest

Test location /workspace/coverage/default/27.i2c_target_timeout.1400529546
Short name T1686
Test name
Test status
Simulation time 4995262607 ps
CPU time 7.57 seconds
Started Aug 12 04:44:01 PM PDT 24
Finished Aug 12 04:44:08 PM PDT 24
Peak memory 221944 kb
Host smart-f925dfbe-f121-4508-97da-4fe1d29be05c
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=50_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1400529546 -assert nopostproc +UVM_TESTNAME=i2c_bas
e_test +UVM_TEST_SEQ=i2c_target_timeout_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/nu
ll -cm_name 27.i2c_target_timeout.1400529546
Directory /workspace/27.i2c_target_timeout/latest

Test location /workspace/coverage/default/27.i2c_target_tx_stretch_ctrl.1667669906
Short name T358
Test name
Test status
Simulation time 54555590 ps
CPU time 1.32 seconds
Started Aug 12 04:44:00 PM PDT 24
Finished Aug 12 04:44:01 PM PDT 24
Peak memory 205464 kb
Host smart-39d606e0-35c0-4665-8840-ea597da91477
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1667669906 -assert nopostproc +UVM_TESTNAME=i2c_bas
e_test +UVM_TEST_SEQ=i2c_target_tx_stretch_ctrl_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log
/dev/null -cm_name 27.i2c_target_tx_stretch_ctrl.1667669906
Directory /workspace/27.i2c_target_tx_stretch_ctrl/latest

Test location /workspace/coverage/default/28.i2c_alert_test.3688191686
Short name T1629
Test name
Test status
Simulation time 37313343 ps
CPU time 0.64 seconds
Started Aug 12 04:44:11 PM PDT 24
Finished Aug 12 04:44:12 PM PDT 24
Peak memory 204432 kb
Host smart-ebbf3a7c-66bf-419b-9183-c644b6d837e7
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3688191686 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_common_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.i2c_alert_test.3688191686
Directory /workspace/28.i2c_alert_test/latest

Test location /workspace/coverage/default/28.i2c_host_error_intr.2012274139
Short name T418
Test name
Test status
Simulation time 164021979 ps
CPU time 1.5 seconds
Started Aug 12 04:44:09 PM PDT 24
Finished Aug 12 04:44:11 PM PDT 24
Peak memory 213520 kb
Host smart-3ff800d7-34b2-4f54-8576-7b890c50b40a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2012274139 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_error_intr_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.i2c_host_error_intr.2012274139
Directory /workspace/28.i2c_host_error_intr/latest

Test location /workspace/coverage/default/28.i2c_host_fifo_fmt_empty.666633491
Short name T30
Test name
Test status
Simulation time 413842228 ps
CPU time 22.07 seconds
Started Aug 12 04:44:11 PM PDT 24
Finished Aug 12 04:44:33 PM PDT 24
Peak memory 293416 kb
Host smart-4473bd49-2fb5-4d97-9ae4-74a1de394d92
User root
Command /workspace/default/simv +test_timeout_ns=10_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=666633491 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_fifo_fmt_emp
ty_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.i2c_host_fifo_fmt_empt
y.666633491
Directory /workspace/28.i2c_host_fifo_fmt_empty/latest

Test location /workspace/coverage/default/28.i2c_host_fifo_full.3362921163
Short name T25
Test name
Test status
Simulation time 11940052632 ps
CPU time 94.39 seconds
Started Aug 12 04:44:11 PM PDT 24
Finished Aug 12 04:45:46 PM PDT 24
Peak memory 724936 kb
Host smart-4f2d4934-2d40-42e6-a011-c7babcb4b786
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3362921163 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_fifo_full_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.i2c_host_fifo_full.3362921163
Directory /workspace/28.i2c_host_fifo_full/latest

Test location /workspace/coverage/default/28.i2c_host_fifo_overflow.1717001333
Short name T889
Test name
Test status
Simulation time 7272687681 ps
CPU time 61.91 seconds
Started Aug 12 04:44:09 PM PDT 24
Finished Aug 12 04:45:11 PM PDT 24
Peak memory 642592 kb
Host smart-c414e167-2749-4e35-9568-04aeb5c04b9f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1717001333 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_fifo_overflow_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.i2c_host_fifo_overflow.1717001333
Directory /workspace/28.i2c_host_fifo_overflow/latest

Test location /workspace/coverage/default/28.i2c_host_fifo_reset_fmt.1335935757
Short name T1543
Test name
Test status
Simulation time 80970775 ps
CPU time 0.89 seconds
Started Aug 12 04:44:11 PM PDT 24
Finished Aug 12 04:44:12 PM PDT 24
Peak memory 204928 kb
Host smart-085f0bbc-afd6-46b4-bc2b-f6fcc79d6d9d
User root
Command /workspace/default/simv +test_timeout_ns=10_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1335935757 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_fifo_reset_
fmt_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.i2c_host_fifo_reset_f
mt.1335935757
Directory /workspace/28.i2c_host_fifo_reset_fmt/latest

Test location /workspace/coverage/default/28.i2c_host_fifo_reset_rx.3704255516
Short name T473
Test name
Test status
Simulation time 476750326 ps
CPU time 4.83 seconds
Started Aug 12 04:44:08 PM PDT 24
Finished Aug 12 04:44:13 PM PDT 24
Peak memory 205296 kb
Host smart-b49410ed-509f-4679-9607-3d468dfe11df
User root
Command /workspace/default/simv +test_timeout_ns=10_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3704255516 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_fifo_reset_
rx_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.i2c_host_fifo_reset_rx
.3704255516
Directory /workspace/28.i2c_host_fifo_reset_rx/latest

Test location /workspace/coverage/default/28.i2c_host_fifo_watermark.2603847447
Short name T584
Test name
Test status
Simulation time 3424446392 ps
CPU time 90.48 seconds
Started Aug 12 04:44:08 PM PDT 24
Finished Aug 12 04:45:39 PM PDT 24
Peak memory 1022772 kb
Host smart-4bfbf2f5-9916-4095-acee-a8e427f6f991
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2603847447 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_fifo_watermark_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.i2c_host_fifo_watermark.2603847447
Directory /workspace/28.i2c_host_fifo_watermark/latest

Test location /workspace/coverage/default/28.i2c_host_may_nack.1436758677
Short name T269
Test name
Test status
Simulation time 406978561 ps
CPU time 17.49 seconds
Started Aug 12 04:44:10 PM PDT 24
Finished Aug 12 04:44:28 PM PDT 24
Peak memory 205224 kb
Host smart-d629598f-83af-41a9-be46-41d495e66a72
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1436758677 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_may_nack_vseq +en_cov=1 -cm line+cond+f
sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.i2c_host_may_nack.1436758677
Directory /workspace/28.i2c_host_may_nack/latest

Test location /workspace/coverage/default/28.i2c_host_mode_toggle.2482693716
Short name T283
Test name
Test status
Simulation time 148068571 ps
CPU time 1.91 seconds
Started Aug 12 04:44:11 PM PDT 24
Finished Aug 12 04:44:13 PM PDT 24
Peak memory 212876 kb
Host smart-c49d18ef-d363-4fc3-82a8-afa8d9b40166
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2482693716 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_mode_toggle_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.i2c_host_mode_toggle.2482693716
Directory /workspace/28.i2c_host_mode_toggle/latest

Test location /workspace/coverage/default/28.i2c_host_override.13258565
Short name T153
Test name
Test status
Simulation time 54311561 ps
CPU time 0.72 seconds
Started Aug 12 04:44:12 PM PDT 24
Finished Aug 12 04:44:13 PM PDT 24
Peak memory 204904 kb
Host smart-fe0578d3-6659-49e9-bf37-9dcb838ecc68
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=13258565 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_override_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.i2c_host_override.13258565
Directory /workspace/28.i2c_host_override/latest

Test location /workspace/coverage/default/28.i2c_host_perf.449181970
Short name T1041
Test name
Test status
Simulation time 31256259504 ps
CPU time 95.6 seconds
Started Aug 12 04:44:12 PM PDT 24
Finished Aug 12 04:45:48 PM PDT 24
Peak memory 253868 kb
Host smart-72ada4e9-72df-466b-837e-616ed0905247
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=449181970 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_perf_vseq +en_cov=1 -cm line+cond+fsm+tg
l+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.i2c_host_perf.449181970
Directory /workspace/28.i2c_host_perf/latest

Test location /workspace/coverage/default/28.i2c_host_perf_precise.2924914372
Short name T150
Test name
Test status
Simulation time 165427777 ps
CPU time 7.11 seconds
Started Aug 12 04:44:11 PM PDT 24
Finished Aug 12 04:44:18 PM PDT 24
Peak memory 205224 kb
Host smart-9969358e-ae2f-48e8-8276-283ea63ab5cb
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2924914372 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_perf_precise_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.i2c_host_perf_precise.2924914372
Directory /workspace/28.i2c_host_perf_precise/latest

Test location /workspace/coverage/default/28.i2c_host_smoke.2343794673
Short name T1734
Test name
Test status
Simulation time 2579247636 ps
CPU time 55.2 seconds
Started Aug 12 04:44:14 PM PDT 24
Finished Aug 12 04:45:09 PM PDT 24
Peak memory 294640 kb
Host smart-657f8a14-629f-4707-994c-1d3178ea12b0
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2343794673 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_smoke_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.i2c_host_smoke.2343794673
Directory /workspace/28.i2c_host_smoke/latest

Test location /workspace/coverage/default/28.i2c_host_stress_all.1793547599
Short name T553
Test name
Test status
Simulation time 12451953886 ps
CPU time 978.3 seconds
Started Aug 12 04:44:11 PM PDT 24
Finished Aug 12 05:00:30 PM PDT 24
Peak memory 1828332 kb
Host smart-cd912114-d18b-4000-9c09-faf1c96146af
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1793547599 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_stress_all_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.i2c_host_stress_all.1793547599
Directory /workspace/28.i2c_host_stress_all/latest

Test location /workspace/coverage/default/28.i2c_host_stretch_timeout.2552269845
Short name T15
Test name
Test status
Simulation time 3662498737 ps
CPU time 10.95 seconds
Started Aug 12 04:44:07 PM PDT 24
Finished Aug 12 04:44:18 PM PDT 24
Peak memory 221392 kb
Host smart-60dc96de-3350-488e-a32e-e74b823cd810
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2552269845 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_stretch_timeout_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.i2c_host_stretch_timeout.2552269845
Directory /workspace/28.i2c_host_stretch_timeout/latest

Test location /workspace/coverage/default/28.i2c_target_bad_addr.3664162729
Short name T63
Test name
Test status
Simulation time 3807033290 ps
CPU time 6.1 seconds
Started Aug 12 04:44:09 PM PDT 24
Finished Aug 12 04:44:15 PM PDT 24
Peak memory 219708 kb
Host smart-ad761d50-ca95-44f4-b650-c0e79c88a70a
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +i2c_bad_addr_pct=50 +cdc_instrumentation_enabled=1 +UVM_
NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3664162729 -assert nopostproc
+UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_target_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.
vdb -cm_log /dev/null -cm_name 28.i2c_target_bad_addr.3664162729
Directory /workspace/28.i2c_target_bad_addr/latest

Test location /workspace/coverage/default/28.i2c_target_fifo_reset_acq.2342269303
Short name T357
Test name
Test status
Simulation time 428992932 ps
CPU time 1.14 seconds
Started Aug 12 04:44:09 PM PDT 24
Finished Aug 12 04:44:10 PM PDT 24
Peak memory 205324 kb
Host smart-02b7d82c-c060-49c9-b318-fb328e5c505a
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2342269303 -assert nopostproc +UVM_TESTNAME=i2c_bas
e_test +UVM_TEST_SEQ=i2c_target_fifo_reset_acq_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log
/dev/null -cm_name 28.i2c_target_fifo_reset_acq.2342269303
Directory /workspace/28.i2c_target_fifo_reset_acq/latest

Test location /workspace/coverage/default/28.i2c_target_fifo_reset_tx.3676757836
Short name T567
Test name
Test status
Simulation time 328461360 ps
CPU time 1.26 seconds
Started Aug 12 04:44:10 PM PDT 24
Finished Aug 12 04:44:11 PM PDT 24
Peak memory 205292 kb
Host smart-e43edbfe-e165-4ac7-b0ac-fb22ea529d3f
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3676757836 -assert nopostproc +UVM_TESTNAME=i2c_bas
e_test +UVM_TEST_SEQ=i2c_target_fifo_reset_tx_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /
dev/null -cm_name 28.i2c_target_fifo_reset_tx.3676757836
Directory /workspace/28.i2c_target_fifo_reset_tx/latest

Test location /workspace/coverage/default/28.i2c_target_fifo_watermarks_acq.397077326
Short name T96
Test name
Test status
Simulation time 1136264044 ps
CPU time 1.73 seconds
Started Aug 12 04:44:11 PM PDT 24
Finished Aug 12 04:44:13 PM PDT 24
Peak memory 205272 kb
Host smart-b1967ba3-5391-4501-8f76-d06be68e0cdf
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=397077326 -assert nopostproc +UVM_TESTNAME=i2c_base
_test +UVM_TEST_SEQ=i2c_target_fifo_watermarks_acq_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_
log /dev/null -cm_name 28.i2c_target_fifo_watermarks_acq.397077326
Directory /workspace/28.i2c_target_fifo_watermarks_acq/latest

Test location /workspace/coverage/default/28.i2c_target_fifo_watermarks_tx.1390378924
Short name T660
Test name
Test status
Simulation time 645437830 ps
CPU time 1.36 seconds
Started Aug 12 04:44:10 PM PDT 24
Finished Aug 12 04:44:11 PM PDT 24
Peak memory 205252 kb
Host smart-96122afb-b200-4c92-bff0-10d3278b84a8
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1390378924 -assert nopostproc +UVM_TESTNAME=i2c_bas
e_test +UVM_TEST_SEQ=i2c_target_fifo_watermarks_tx_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_
log /dev/null -cm_name 28.i2c_target_fifo_watermarks_tx.1390378924
Directory /workspace/28.i2c_target_fifo_watermarks_tx/latest

Test location /workspace/coverage/default/28.i2c_target_intr_smoke.2248146620
Short name T811
Test name
Test status
Simulation time 3522240652 ps
CPU time 4.65 seconds
Started Aug 12 04:44:10 PM PDT 24
Finished Aug 12 04:44:15 PM PDT 24
Peak memory 221872 kb
Host smart-27e48e3f-90a3-4c76-af90-2b5bfbee0635
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=200_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VER
BOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2248146620 -assert nopostproc +UVM_TESTNAME=i2c_ba
se_test +UVM_TEST_SEQ=i2c_target_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/nul
l -cm_name 28.i2c_target_intr_smoke.2248146620
Directory /workspace/28.i2c_target_intr_smoke/latest

Test location /workspace/coverage/default/28.i2c_target_intr_stress_wr.2615144231
Short name T1744
Test name
Test status
Simulation time 18224717302 ps
CPU time 44.07 seconds
Started Aug 12 04:44:09 PM PDT 24
Finished Aug 12 04:44:54 PM PDT 24
Peak memory 761508 kb
Host smart-6a2b9ee6-58d5-430d-a978-57f1ce77494a
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=600_000_000 +use_intr_handler=1 +slow_acq=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNO
TES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2615144231 -assert nopostproc +UVM_TES
TNAME=i2c_base_test +UVM_TEST_SEQ=i2c_target_stress_wr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb
-cm_log /dev/null -cm_name 28.i2c_target_intr_stress_wr.2615144231
Directory /workspace/28.i2c_target_intr_stress_wr/latest

Test location /workspace/coverage/default/28.i2c_target_nack_acqfull.3193602948
Short name T960
Test name
Test status
Simulation time 591734639 ps
CPU time 2.97 seconds
Started Aug 12 04:44:10 PM PDT 24
Finished Aug 12 04:44:13 PM PDT 24
Peak memory 213636 kb
Host smart-91f68520-9b1b-4af0-a47d-b2d554d671aa
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3193602948 -assert nopostproc +UVM_TESTNAME=i2c_bas
e_test +UVM_TEST_SEQ=i2c_target_nack_acqfull_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /d
ev/null -cm_name 28.i2c_target_nack_acqfull.3193602948
Directory /workspace/28.i2c_target_nack_acqfull/latest

Test location /workspace/coverage/default/28.i2c_target_nack_acqfull_addr.1909671295
Short name T1149
Test name
Test status
Simulation time 1967338844 ps
CPU time 2.79 seconds
Started Aug 12 04:44:10 PM PDT 24
Finished Aug 12 04:44:13 PM PDT 24
Peak memory 205496 kb
Host smart-cbc62c89-ad66-4a77-8677-8ba5cff1dbf6
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1909671295 -assert nopostproc +UVM_TESTNAME=i2c_bas
e_test +UVM_TEST_SEQ=i2c_target_nack_acqfull_addr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_l
og /dev/null -cm_name 28.i2c_target_nack_acqfull_addr.1909671295
Directory /workspace/28.i2c_target_nack_acqfull_addr/latest

Test location /workspace/coverage/default/28.i2c_target_nack_txstretch.3719537887
Short name T50
Test name
Test status
Simulation time 519577478 ps
CPU time 1.51 seconds
Started Aug 12 04:44:08 PM PDT 24
Finished Aug 12 04:44:10 PM PDT 24
Peak memory 222288 kb
Host smart-bc44f113-2c82-406a-b027-bf4e993d8621
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3719537887 -assert nopostproc +UVM_TESTNAME=i2c_bas
e_test +UVM_TEST_SEQ=i2c_target_nack_txstretch_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log
/dev/null -cm_name 28.i2c_target_nack_txstretch.3719537887
Directory /workspace/28.i2c_target_nack_txstretch/latest

Test location /workspace/coverage/default/28.i2c_target_perf.250519873
Short name T44
Test name
Test status
Simulation time 9103596156 ps
CPU time 5.83 seconds
Started Aug 12 04:44:11 PM PDT 24
Finished Aug 12 04:44:17 PM PDT 24
Peak memory 221188 kb
Host smart-a56abff7-a73c-46ab-9731-f7c179d93078
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=250519873 -assert nopostproc +UVM_TESTNAME=i2c_base
_test +UVM_TEST_SEQ=i2c_target_perf_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -
cm_name 28.i2c_target_perf.250519873
Directory /workspace/28.i2c_target_perf/latest

Test location /workspace/coverage/default/28.i2c_target_smbus_maxlen.2962521603
Short name T1063
Test name
Test status
Simulation time 841239403 ps
CPU time 2.1 seconds
Started Aug 12 04:44:09 PM PDT 24
Finished Aug 12 04:44:12 PM PDT 24
Peak memory 205364 kb
Host smart-f01c8788-e5e6-4f7a-bd81-fe102575cd9e
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2962521603 -assert nopostproc +UVM_TESTNAME=i2c_bas
e_test +UVM_TEST_SEQ=i2c_target_smbus_maxlen_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /d
ev/null -cm_name 28.i2c_target_smbus_maxlen.2962521603
Directory /workspace/28.i2c_target_smbus_maxlen/latest

Test location /workspace/coverage/default/28.i2c_target_smoke.4250357671
Short name T73
Test name
Test status
Simulation time 2700606137 ps
CPU time 12.1 seconds
Started Aug 12 04:44:09 PM PDT 24
Finished Aug 12 04:44:21 PM PDT 24
Peak memory 221860 kb
Host smart-0ba7c623-4d9c-4269-9eaa-6e958af32e94
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=100_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licq
ueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4250357671 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SE
Q=i2c_target_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.i2c_ta
rget_smoke.4250357671
Directory /workspace/28.i2c_target_smoke/latest

Test location /workspace/coverage/default/28.i2c_target_stress_all.3385276036
Short name T957
Test name
Test status
Simulation time 33035085762 ps
CPU time 278.6 seconds
Started Aug 12 04:44:11 PM PDT 24
Finished Aug 12 04:48:49 PM PDT 24
Peak memory 1794508 kb
Host smart-8c861ddd-24f2-42cc-9bda-9acf99490333
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=300_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VER
BOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3385276036 -assert nopostproc +UVM_TESTNAME=i2c_ba
se_test +UVM_TEST_SEQ=i2c_target_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /de
v/null -cm_name 28.i2c_target_stress_all.3385276036
Directory /workspace/28.i2c_target_stress_all/latest

Test location /workspace/coverage/default/28.i2c_target_stress_rd.1111762623
Short name T1203
Test name
Test status
Simulation time 1857227645 ps
CPU time 34.28 seconds
Started Aug 12 04:44:11 PM PDT 24
Finished Aug 12 04:44:45 PM PDT 24
Peak memory 232980 kb
Host smart-1aff2189-0ef1-4cb9-8102-3836481c3ae2
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=100_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licq
ueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1111762623 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SE
Q=i2c_target_stress_rd_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.i2
c_target_stress_rd.1111762623
Directory /workspace/28.i2c_target_stress_rd/latest

Test location /workspace/coverage/default/28.i2c_target_stress_wr.4017690507
Short name T316
Test name
Test status
Simulation time 65597624008 ps
CPU time 540.54 seconds
Started Aug 12 04:44:10 PM PDT 24
Finished Aug 12 04:53:11 PM PDT 24
Peak memory 4100116 kb
Host smart-1e934f25-05af-427d-9824-8272e508d2b7
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=600_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licq
ueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4017690507 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SE
Q=i2c_target_stress_wr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.i2
c_target_stress_wr.4017690507
Directory /workspace/28.i2c_target_stress_wr/latest

Test location /workspace/coverage/default/28.i2c_target_stretch.768162504
Short name T1545
Test name
Test status
Simulation time 240391454 ps
CPU time 1.45 seconds
Started Aug 12 04:44:08 PM PDT 24
Finished Aug 12 04:44:10 PM PDT 24
Peak memory 205556 kb
Host smart-ce8c88f1-6395-413c-8763-a0514fec0e34
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=400_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licq
ueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=768162504 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ
=i2c_target_stretch_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.i2c_t
arget_stretch.768162504
Directory /workspace/28.i2c_target_stretch/latest

Test location /workspace/coverage/default/28.i2c_target_timeout.1463601743
Short name T361
Test name
Test status
Simulation time 1236509725 ps
CPU time 6.84 seconds
Started Aug 12 04:44:12 PM PDT 24
Finished Aug 12 04:44:19 PM PDT 24
Peak memory 213712 kb
Host smart-da3ecab5-c149-46b4-9255-6e5938240636
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=50_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1463601743 -assert nopostproc +UVM_TESTNAME=i2c_bas
e_test +UVM_TEST_SEQ=i2c_target_timeout_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/nu
ll -cm_name 28.i2c_target_timeout.1463601743
Directory /workspace/28.i2c_target_timeout/latest

Test location /workspace/coverage/default/28.i2c_target_tx_stretch_ctrl.4059567290
Short name T2
Test name
Test status
Simulation time 162813565 ps
CPU time 2.3 seconds
Started Aug 12 04:44:11 PM PDT 24
Finished Aug 12 04:44:13 PM PDT 24
Peak memory 205500 kb
Host smart-2727a2bd-d370-4a84-ba99-22c64b67aeaf
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4059567290 -assert nopostproc +UVM_TESTNAME=i2c_bas
e_test +UVM_TEST_SEQ=i2c_target_tx_stretch_ctrl_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log
/dev/null -cm_name 28.i2c_target_tx_stretch_ctrl.4059567290
Directory /workspace/28.i2c_target_tx_stretch_ctrl/latest

Test location /workspace/coverage/default/29.i2c_alert_test.1173931161
Short name T1637
Test name
Test status
Simulation time 29160774 ps
CPU time 0.63 seconds
Started Aug 12 04:44:21 PM PDT 24
Finished Aug 12 04:44:22 PM PDT 24
Peak memory 204504 kb
Host smart-bcefd381-8acb-4a3e-af30-e501e239bcb7
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1173931161 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_common_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.i2c_alert_test.1173931161
Directory /workspace/29.i2c_alert_test/latest

Test location /workspace/coverage/default/29.i2c_host_error_intr.237620017
Short name T1410
Test name
Test status
Simulation time 116163606 ps
CPU time 1.62 seconds
Started Aug 12 04:44:21 PM PDT 24
Finished Aug 12 04:44:23 PM PDT 24
Peak memory 213584 kb
Host smart-cdbf66c4-3c85-4cbf-b81a-2c1bc373eaa4
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=237620017 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_error_intr_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.i2c_host_error_intr.237620017
Directory /workspace/29.i2c_host_error_intr/latest

Test location /workspace/coverage/default/29.i2c_host_fifo_fmt_empty.3323992115
Short name T796
Test name
Test status
Simulation time 1180853140 ps
CPU time 5.32 seconds
Started Aug 12 04:44:21 PM PDT 24
Finished Aug 12 04:44:27 PM PDT 24
Peak memory 267284 kb
Host smart-a4f5dfe0-15fc-48b0-97f4-bf8c93280290
User root
Command /workspace/default/simv +test_timeout_ns=10_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3323992115 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_fifo_fmt_em
pty_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.i2c_host_fifo_fmt_emp
ty.3323992115
Directory /workspace/29.i2c_host_fifo_fmt_empty/latest

Test location /workspace/coverage/default/29.i2c_host_fifo_full.2126340717
Short name T564
Test name
Test status
Simulation time 18014228333 ps
CPU time 135.43 seconds
Started Aug 12 04:44:20 PM PDT 24
Finished Aug 12 04:46:36 PM PDT 24
Peak memory 626528 kb
Host smart-4eea87cb-d663-4cba-96a0-1c979e57e44a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2126340717 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_fifo_full_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.i2c_host_fifo_full.2126340717
Directory /workspace/29.i2c_host_fifo_full/latest

Test location /workspace/coverage/default/29.i2c_host_fifo_overflow.3216218284
Short name T915
Test name
Test status
Simulation time 2905000270 ps
CPU time 130.09 seconds
Started Aug 12 04:44:20 PM PDT 24
Finished Aug 12 04:46:30 PM PDT 24
Peak memory 669372 kb
Host smart-dd0df2d8-e885-48e9-87e0-33eefd6bff2f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3216218284 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_fifo_overflow_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.i2c_host_fifo_overflow.3216218284
Directory /workspace/29.i2c_host_fifo_overflow/latest

Test location /workspace/coverage/default/29.i2c_host_fifo_reset_fmt.3022938685
Short name T740
Test name
Test status
Simulation time 520576359 ps
CPU time 1.23 seconds
Started Aug 12 04:44:20 PM PDT 24
Finished Aug 12 04:44:21 PM PDT 24
Peak memory 205160 kb
Host smart-77e7f390-2110-4bff-af31-888ac31b9852
User root
Command /workspace/default/simv +test_timeout_ns=10_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3022938685 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_fifo_reset_
fmt_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.i2c_host_fifo_reset_f
mt.3022938685
Directory /workspace/29.i2c_host_fifo_reset_fmt/latest

Test location /workspace/coverage/default/29.i2c_host_fifo_reset_rx.265425199
Short name T1144
Test name
Test status
Simulation time 193017310 ps
CPU time 5.69 seconds
Started Aug 12 04:44:22 PM PDT 24
Finished Aug 12 04:44:28 PM PDT 24
Peak memory 240820 kb
Host smart-e9e5fdda-be95-46bd-bae7-76225ba87005
User root
Command /workspace/default/simv +test_timeout_ns=10_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=265425199 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_fifo_reset_r
x_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.i2c_host_fifo_reset_rx.
265425199
Directory /workspace/29.i2c_host_fifo_reset_rx/latest

Test location /workspace/coverage/default/29.i2c_host_fifo_watermark.2720851793
Short name T1548
Test name
Test status
Simulation time 7759839919 ps
CPU time 157.02 seconds
Started Aug 12 04:44:18 PM PDT 24
Finished Aug 12 04:46:56 PM PDT 24
Peak memory 1471880 kb
Host smart-eed88f68-1eca-4b16-9867-a457b012e7ed
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2720851793 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_fifo_watermark_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.i2c_host_fifo_watermark.2720851793
Directory /workspace/29.i2c_host_fifo_watermark/latest

Test location /workspace/coverage/default/29.i2c_host_may_nack.2470222791
Short name T1102
Test name
Test status
Simulation time 496637170 ps
CPU time 6.99 seconds
Started Aug 12 04:44:22 PM PDT 24
Finished Aug 12 04:44:29 PM PDT 24
Peak memory 205228 kb
Host smart-d8f6aaa7-e86d-42b3-ac08-37c6d5c66ca2
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2470222791 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_may_nack_vseq +en_cov=1 -cm line+cond+f
sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.i2c_host_may_nack.2470222791
Directory /workspace/29.i2c_host_may_nack/latest

Test location /workspace/coverage/default/29.i2c_host_override.1751722607
Short name T560
Test name
Test status
Simulation time 62691663 ps
CPU time 0.72 seconds
Started Aug 12 04:44:18 PM PDT 24
Finished Aug 12 04:44:19 PM PDT 24
Peak memory 205000 kb
Host smart-86b9b395-669c-4f06-9180-0338aaed5eff
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1751722607 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_override_vseq +en_cov=1 -cm line+cond+f
sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.i2c_host_override.1751722607
Directory /workspace/29.i2c_host_override/latest

Test location /workspace/coverage/default/29.i2c_host_perf.3078530923
Short name T628
Test name
Test status
Simulation time 28089719863 ps
CPU time 378.41 seconds
Started Aug 12 04:44:18 PM PDT 24
Finished Aug 12 04:50:37 PM PDT 24
Peak memory 730656 kb
Host smart-90ff1557-6bf9-47e1-bb13-9d4569f1d0bf
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3078530923 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_perf_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.i2c_host_perf.3078530923
Directory /workspace/29.i2c_host_perf/latest

Test location /workspace/coverage/default/29.i2c_host_perf_precise.198379839
Short name T484
Test name
Test status
Simulation time 6025214868 ps
CPU time 72.7 seconds
Started Aug 12 04:44:20 PM PDT 24
Finished Aug 12 04:45:33 PM PDT 24
Peak memory 205216 kb
Host smart-cf0c3969-447b-46c4-8ac8-874b64c96224
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=198379839 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_perf_precise_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.i2c_host_perf_precise.198379839
Directory /workspace/29.i2c_host_perf_precise/latest

Test location /workspace/coverage/default/29.i2c_host_smoke.3845388152
Short name T1067
Test name
Test status
Simulation time 6484805216 ps
CPU time 21.74 seconds
Started Aug 12 04:44:11 PM PDT 24
Finished Aug 12 04:44:33 PM PDT 24
Peak memory 304312 kb
Host smart-bb5c5217-2d84-4670-bf41-620bb2effa0d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3845388152 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_smoke_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.i2c_host_smoke.3845388152
Directory /workspace/29.i2c_host_smoke/latest

Test location /workspace/coverage/default/29.i2c_host_stretch_timeout.1746945304
Short name T665
Test name
Test status
Simulation time 1675836132 ps
CPU time 7.18 seconds
Started Aug 12 04:44:18 PM PDT 24
Finished Aug 12 04:44:26 PM PDT 24
Peak memory 215372 kb
Host smart-bd313f2f-e50f-4c46-b1bd-7dd28a8896f4
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1746945304 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_stretch_timeout_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.i2c_host_stretch_timeout.1746945304
Directory /workspace/29.i2c_host_stretch_timeout/latest

Test location /workspace/coverage/default/29.i2c_target_bad_addr.2678361353
Short name T1321
Test name
Test status
Simulation time 2680507656 ps
CPU time 3.82 seconds
Started Aug 12 04:44:22 PM PDT 24
Finished Aug 12 04:44:25 PM PDT 24
Peak memory 213712 kb
Host smart-07300265-77c4-4fd5-987e-5dc33d030708
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +i2c_bad_addr_pct=50 +cdc_instrumentation_enabled=1 +UVM_
NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2678361353 -assert nopostproc
+UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_target_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.
vdb -cm_log /dev/null -cm_name 29.i2c_target_bad_addr.2678361353
Directory /workspace/29.i2c_target_bad_addr/latest

Test location /workspace/coverage/default/29.i2c_target_fifo_reset_acq.1456669491
Short name T1187
Test name
Test status
Simulation time 161716612 ps
CPU time 1.06 seconds
Started Aug 12 04:44:20 PM PDT 24
Finished Aug 12 04:44:21 PM PDT 24
Peak memory 205276 kb
Host smart-dd58296a-a105-4eaf-8f54-34f5b5bc7601
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1456669491 -assert nopostproc +UVM_TESTNAME=i2c_bas
e_test +UVM_TEST_SEQ=i2c_target_fifo_reset_acq_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log
/dev/null -cm_name 29.i2c_target_fifo_reset_acq.1456669491
Directory /workspace/29.i2c_target_fifo_reset_acq/latest

Test location /workspace/coverage/default/29.i2c_target_fifo_reset_tx.527954142
Short name T103
Test name
Test status
Simulation time 374943714 ps
CPU time 1.05 seconds
Started Aug 12 04:44:21 PM PDT 24
Finished Aug 12 04:44:22 PM PDT 24
Peak memory 205256 kb
Host smart-05a08bc8-a1f3-4cca-a48e-ad31d13c274f
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=527954142 -assert nopostproc +UVM_TESTNAME=i2c_base
_test +UVM_TEST_SEQ=i2c_target_fifo_reset_tx_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /d
ev/null -cm_name 29.i2c_target_fifo_reset_tx.527954142
Directory /workspace/29.i2c_target_fifo_reset_tx/latest

Test location /workspace/coverage/default/29.i2c_target_fifo_watermarks_acq.325986702
Short name T1128
Test name
Test status
Simulation time 1437454519 ps
CPU time 2.11 seconds
Started Aug 12 04:44:20 PM PDT 24
Finished Aug 12 04:44:22 PM PDT 24
Peak memory 205236 kb
Host smart-0d3e4cde-c86e-4881-9166-5b1cf5588df4
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=325986702 -assert nopostproc +UVM_TESTNAME=i2c_base
_test +UVM_TEST_SEQ=i2c_target_fifo_watermarks_acq_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_
log /dev/null -cm_name 29.i2c_target_fifo_watermarks_acq.325986702
Directory /workspace/29.i2c_target_fifo_watermarks_acq/latest

Test location /workspace/coverage/default/29.i2c_target_fifo_watermarks_tx.1158950534
Short name T160
Test name
Test status
Simulation time 131822398 ps
CPU time 1.13 seconds
Started Aug 12 04:44:21 PM PDT 24
Finished Aug 12 04:44:22 PM PDT 24
Peak memory 205376 kb
Host smart-590c9bc5-0298-4355-bb25-def82e6c370e
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1158950534 -assert nopostproc +UVM_TESTNAME=i2c_bas
e_test +UVM_TEST_SEQ=i2c_target_fifo_watermarks_tx_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_
log /dev/null -cm_name 29.i2c_target_fifo_watermarks_tx.1158950534
Directory /workspace/29.i2c_target_fifo_watermarks_tx/latest

Test location /workspace/coverage/default/29.i2c_target_intr_smoke.2969663787
Short name T1122
Test name
Test status
Simulation time 814089274 ps
CPU time 5.29 seconds
Started Aug 12 04:44:20 PM PDT 24
Finished Aug 12 04:44:25 PM PDT 24
Peak memory 213548 kb
Host smart-1feeb5be-fe8e-4e53-b150-e95c69644427
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=200_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VER
BOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2969663787 -assert nopostproc +UVM_TESTNAME=i2c_ba
se_test +UVM_TEST_SEQ=i2c_target_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/nul
l -cm_name 29.i2c_target_intr_smoke.2969663787
Directory /workspace/29.i2c_target_intr_smoke/latest

Test location /workspace/coverage/default/29.i2c_target_intr_stress_wr.1858053409
Short name T1095
Test name
Test status
Simulation time 5045476687 ps
CPU time 6.28 seconds
Started Aug 12 04:44:21 PM PDT 24
Finished Aug 12 04:44:27 PM PDT 24
Peak memory 205624 kb
Host smart-7ff124eb-5c2b-455c-ad9b-e852c85007c0
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=600_000_000 +use_intr_handler=1 +slow_acq=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNO
TES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1858053409 -assert nopostproc +UVM_TES
TNAME=i2c_base_test +UVM_TEST_SEQ=i2c_target_stress_wr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb
-cm_log /dev/null -cm_name 29.i2c_target_intr_stress_wr.1858053409
Directory /workspace/29.i2c_target_intr_stress_wr/latest

Test location /workspace/coverage/default/29.i2c_target_nack_acqfull.3828028707
Short name T168
Test name
Test status
Simulation time 2864525862 ps
CPU time 2.51 seconds
Started Aug 12 04:44:20 PM PDT 24
Finished Aug 12 04:44:23 PM PDT 24
Peak memory 213744 kb
Host smart-21bce7c6-c366-49a6-acd4-0071a3f004be
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3828028707 -assert nopostproc +UVM_TESTNAME=i2c_bas
e_test +UVM_TEST_SEQ=i2c_target_nack_acqfull_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /d
ev/null -cm_name 29.i2c_target_nack_acqfull.3828028707
Directory /workspace/29.i2c_target_nack_acqfull/latest

Test location /workspace/coverage/default/29.i2c_target_nack_acqfull_addr.2831256598
Short name T72
Test name
Test status
Simulation time 804867298 ps
CPU time 2.53 seconds
Started Aug 12 04:44:19 PM PDT 24
Finished Aug 12 04:44:21 PM PDT 24
Peak memory 205540 kb
Host smart-b8083ba0-1136-4bd1-a3c3-fd48052d3e5d
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2831256598 -assert nopostproc +UVM_TESTNAME=i2c_bas
e_test +UVM_TEST_SEQ=i2c_target_nack_acqfull_addr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_l
og /dev/null -cm_name 29.i2c_target_nack_acqfull_addr.2831256598
Directory /workspace/29.i2c_target_nack_acqfull_addr/latest

Test location /workspace/coverage/default/29.i2c_target_nack_txstretch.3913840732
Short name T530
Test name
Test status
Simulation time 132823094 ps
CPU time 1.4 seconds
Started Aug 12 04:44:19 PM PDT 24
Finished Aug 12 04:44:21 PM PDT 24
Peak memory 222360 kb
Host smart-28bf2b0a-e47f-4d3b-9b2c-b1ea7ed6c5b2
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3913840732 -assert nopostproc +UVM_TESTNAME=i2c_bas
e_test +UVM_TEST_SEQ=i2c_target_nack_txstretch_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log
/dev/null -cm_name 29.i2c_target_nack_txstretch.3913840732
Directory /workspace/29.i2c_target_nack_txstretch/latest

Test location /workspace/coverage/default/29.i2c_target_perf.934969784
Short name T898
Test name
Test status
Simulation time 1838778210 ps
CPU time 6.13 seconds
Started Aug 12 04:44:18 PM PDT 24
Finished Aug 12 04:44:24 PM PDT 24
Peak memory 213600 kb
Host smart-6c5cf8d9-c2f6-475c-82fb-e7d50fab7a8f
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=934969784 -assert nopostproc +UVM_TESTNAME=i2c_base
_test +UVM_TEST_SEQ=i2c_target_perf_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -
cm_name 29.i2c_target_perf.934969784
Directory /workspace/29.i2c_target_perf/latest

Test location /workspace/coverage/default/29.i2c_target_smbus_maxlen.577649395
Short name T434
Test name
Test status
Simulation time 552559814 ps
CPU time 2.63 seconds
Started Aug 12 04:44:21 PM PDT 24
Finished Aug 12 04:44:23 PM PDT 24
Peak memory 205284 kb
Host smart-28dcb7ab-321c-4560-a987-e503e55eaece
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=577649395 -assert nopostproc +UVM_TESTNAME=i2c_base
_test +UVM_TEST_SEQ=i2c_target_smbus_maxlen_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /de
v/null -cm_name 29.i2c_target_smbus_maxlen.577649395
Directory /workspace/29.i2c_target_smbus_maxlen/latest

Test location /workspace/coverage/default/29.i2c_target_smoke.2420825404
Short name T1424
Test name
Test status
Simulation time 995994221 ps
CPU time 15.36 seconds
Started Aug 12 04:44:18 PM PDT 24
Finished Aug 12 04:44:33 PM PDT 24
Peak memory 213776 kb
Host smart-b54b25f7-7e16-4a1a-89a8-5c949968dad4
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=100_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licq
ueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2420825404 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SE
Q=i2c_target_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.i2c_ta
rget_smoke.2420825404
Directory /workspace/29.i2c_target_smoke/latest

Test location /workspace/coverage/default/29.i2c_target_stress_all.2968752696
Short name T1403
Test name
Test status
Simulation time 99517011749 ps
CPU time 55.57 seconds
Started Aug 12 04:44:21 PM PDT 24
Finished Aug 12 04:45:16 PM PDT 24
Peak memory 303036 kb
Host smart-e4fd4abc-9f59-447a-acce-ffa8b766e5bb
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=300_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VER
BOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2968752696 -assert nopostproc +UVM_TESTNAME=i2c_ba
se_test +UVM_TEST_SEQ=i2c_target_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /de
v/null -cm_name 29.i2c_target_stress_all.2968752696
Directory /workspace/29.i2c_target_stress_all/latest

Test location /workspace/coverage/default/29.i2c_target_stress_rd.4155692528
Short name T1420
Test name
Test status
Simulation time 5474668784 ps
CPU time 60.23 seconds
Started Aug 12 04:44:20 PM PDT 24
Finished Aug 12 04:45:20 PM PDT 24
Peak memory 213924 kb
Host smart-59dd164a-b799-43d8-99b7-6e616ecb9900
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=100_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licq
ueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4155692528 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SE
Q=i2c_target_stress_rd_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.i2
c_target_stress_rd.4155692528
Directory /workspace/29.i2c_target_stress_rd/latest

Test location /workspace/coverage/default/29.i2c_target_stress_wr.2089279626
Short name T1171
Test name
Test status
Simulation time 25721032358 ps
CPU time 105.18 seconds
Started Aug 12 04:44:21 PM PDT 24
Finished Aug 12 04:46:06 PM PDT 24
Peak memory 1582648 kb
Host smart-a573cd53-3c0b-4573-9bf1-a8b9c910a28e
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=600_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licq
ueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2089279626 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SE
Q=i2c_target_stress_wr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.i2
c_target_stress_wr.2089279626
Directory /workspace/29.i2c_target_stress_wr/latest

Test location /workspace/coverage/default/29.i2c_target_stretch.3683936676
Short name T1350
Test name
Test status
Simulation time 2140552228 ps
CPU time 45.15 seconds
Started Aug 12 04:44:22 PM PDT 24
Finished Aug 12 04:45:08 PM PDT 24
Peak memory 426796 kb
Host smart-0a04726a-741e-457c-8c4c-e9057608cf4e
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=400_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licq
ueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3683936676 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SE
Q=i2c_target_stretch_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.i2c_
target_stretch.3683936676
Directory /workspace/29.i2c_target_stretch/latest

Test location /workspace/coverage/default/29.i2c_target_timeout.428039656
Short name T999
Test name
Test status
Simulation time 6516078632 ps
CPU time 8.21 seconds
Started Aug 12 04:44:19 PM PDT 24
Finished Aug 12 04:44:27 PM PDT 24
Peak memory 221688 kb
Host smart-f5245fef-a885-4d8a-a3a2-3172fe266752
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=50_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=428039656 -assert nopostproc +UVM_TESTNAME=i2c_base
_test +UVM_TEST_SEQ=i2c_target_timeout_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/nul
l -cm_name 29.i2c_target_timeout.428039656
Directory /workspace/29.i2c_target_timeout/latest

Test location /workspace/coverage/default/29.i2c_target_tx_stretch_ctrl.2563969894
Short name T836
Test name
Test status
Simulation time 640839028 ps
CPU time 8.44 seconds
Started Aug 12 04:44:21 PM PDT 24
Finished Aug 12 04:44:30 PM PDT 24
Peak memory 205516 kb
Host smart-c18bbdf4-0f1b-4ba7-86a1-b6ad716b2da9
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2563969894 -assert nopostproc +UVM_TESTNAME=i2c_bas
e_test +UVM_TEST_SEQ=i2c_target_tx_stretch_ctrl_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log
/dev/null -cm_name 29.i2c_target_tx_stretch_ctrl.2563969894
Directory /workspace/29.i2c_target_tx_stretch_ctrl/latest

Test location /workspace/coverage/default/3.i2c_alert_test.333433242
Short name T1031
Test name
Test status
Simulation time 79092487 ps
CPU time 0.62 seconds
Started Aug 12 04:41:04 PM PDT 24
Finished Aug 12 04:41:04 PM PDT 24
Peak memory 204452 kb
Host smart-ced87203-5d42-4b97-9b21-bfaaf5b647c8
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=333433242 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_common_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.i2c_alert_test.333433242
Directory /workspace/3.i2c_alert_test/latest

Test location /workspace/coverage/default/3.i2c_host_error_intr.610632274
Short name T1668
Test name
Test status
Simulation time 481145359 ps
CPU time 1.99 seconds
Started Aug 12 04:41:05 PM PDT 24
Finished Aug 12 04:41:07 PM PDT 24
Peak memory 213564 kb
Host smart-0d03dfd9-7be9-4609-83ad-28736f1da059
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=610632274 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_error_intr_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.i2c_host_error_intr.610632274
Directory /workspace/3.i2c_host_error_intr/latest

Test location /workspace/coverage/default/3.i2c_host_fifo_fmt_empty.425234335
Short name T514
Test name
Test status
Simulation time 1411256798 ps
CPU time 17.57 seconds
Started Aug 12 04:41:00 PM PDT 24
Finished Aug 12 04:41:18 PM PDT 24
Peak memory 278640 kb
Host smart-d046a527-2079-4c34-97fa-f444f8e1f4a4
User root
Command /workspace/default/simv +test_timeout_ns=10_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=425234335 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_fifo_fmt_emp
ty_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.i2c_host_fifo_fmt_empty
.425234335
Directory /workspace/3.i2c_host_fifo_fmt_empty/latest

Test location /workspace/coverage/default/3.i2c_host_fifo_full.3366589051
Short name T794
Test name
Test status
Simulation time 3181046809 ps
CPU time 213.78 seconds
Started Aug 12 04:41:01 PM PDT 24
Finished Aug 12 04:44:35 PM PDT 24
Peak memory 589696 kb
Host smart-a407865e-72dd-43e7-a62f-000c1dbd0d2b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3366589051 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_fifo_full_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.i2c_host_fifo_full.3366589051
Directory /workspace/3.i2c_host_fifo_full/latest

Test location /workspace/coverage/default/3.i2c_host_fifo_overflow.1364999428
Short name T783
Test name
Test status
Simulation time 2580773522 ps
CPU time 190.32 seconds
Started Aug 12 04:40:55 PM PDT 24
Finished Aug 12 04:44:05 PM PDT 24
Peak memory 767784 kb
Host smart-9298cf1c-a5de-434d-b5ff-54cb3784d911
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1364999428 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_fifo_overflow_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.i2c_host_fifo_overflow.1364999428
Directory /workspace/3.i2c_host_fifo_overflow/latest

Test location /workspace/coverage/default/3.i2c_host_fifo_reset_fmt.1039331035
Short name T1167
Test name
Test status
Simulation time 145094918 ps
CPU time 1.29 seconds
Started Aug 12 04:40:54 PM PDT 24
Finished Aug 12 04:40:56 PM PDT 24
Peak memory 204912 kb
Host smart-7f4d2e49-9b51-4bac-a730-6b7c95b7b0e9
User root
Command /workspace/default/simv +test_timeout_ns=10_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1039331035 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_fifo_reset_
fmt_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.i2c_host_fifo_reset_fm
t.1039331035
Directory /workspace/3.i2c_host_fifo_reset_fmt/latest

Test location /workspace/coverage/default/3.i2c_host_fifo_reset_rx.1282541593
Short name T918
Test name
Test status
Simulation time 648864800 ps
CPU time 3.95 seconds
Started Aug 12 04:41:01 PM PDT 24
Finished Aug 12 04:41:05 PM PDT 24
Peak memory 205216 kb
Host smart-cedff689-707e-4d60-a3d9-6dd205f1f602
User root
Command /workspace/default/simv +test_timeout_ns=10_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1282541593 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_fifo_reset_
rx_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.i2c_host_fifo_reset_rx.
1282541593
Directory /workspace/3.i2c_host_fifo_reset_rx/latest

Test location /workspace/coverage/default/3.i2c_host_fifo_watermark.4122159623
Short name T739
Test name
Test status
Simulation time 7945405634 ps
CPU time 91.63 seconds
Started Aug 12 04:40:59 PM PDT 24
Finished Aug 12 04:42:31 PM PDT 24
Peak memory 985536 kb
Host smart-7c89d4d8-f253-4128-944c-20023ae0a62e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4122159623 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_fifo_watermark_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.i2c_host_fifo_watermark.4122159623
Directory /workspace/3.i2c_host_fifo_watermark/latest

Test location /workspace/coverage/default/3.i2c_host_may_nack.2392839069
Short name T23
Test name
Test status
Simulation time 1153165456 ps
CPU time 4.43 seconds
Started Aug 12 04:41:07 PM PDT 24
Finished Aug 12 04:41:12 PM PDT 24
Peak memory 205004 kb
Host smart-12a46159-c343-40b4-94dd-eef69ad3fd50
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2392839069 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_may_nack_vseq +en_cov=1 -cm line+cond+f
sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.i2c_host_may_nack.2392839069
Directory /workspace/3.i2c_host_may_nack/latest

Test location /workspace/coverage/default/3.i2c_host_mode_toggle.2068103781
Short name T76
Test name
Test status
Simulation time 85624877 ps
CPU time 1.25 seconds
Started Aug 12 04:41:06 PM PDT 24
Finished Aug 12 04:41:07 PM PDT 24
Peak memory 213444 kb
Host smart-0ae6c0cf-9651-4c2d-bed9-a2bfd33b5235
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2068103781 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_mode_toggle_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.i2c_host_mode_toggle.2068103781
Directory /workspace/3.i2c_host_mode_toggle/latest

Test location /workspace/coverage/default/3.i2c_host_override.4196421193
Short name T745
Test name
Test status
Simulation time 90098990 ps
CPU time 0.68 seconds
Started Aug 12 04:41:00 PM PDT 24
Finished Aug 12 04:41:01 PM PDT 24
Peak memory 204892 kb
Host smart-a11580b2-9ddf-4c49-9a5d-24e08608c069
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4196421193 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_override_vseq +en_cov=1 -cm line+cond+f
sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.i2c_host_override.4196421193
Directory /workspace/3.i2c_host_override/latest

Test location /workspace/coverage/default/3.i2c_host_perf.157554358
Short name T1184
Test name
Test status
Simulation time 7207661365 ps
CPU time 228.09 seconds
Started Aug 12 04:41:09 PM PDT 24
Finished Aug 12 04:44:57 PM PDT 24
Peak memory 1614716 kb
Host smart-9bfcc396-7a91-49e8-a9d0-85778ee820d1
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=157554358 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_perf_vseq +en_cov=1 -cm line+cond+fsm+tg
l+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.i2c_host_perf.157554358
Directory /workspace/3.i2c_host_perf/latest

Test location /workspace/coverage/default/3.i2c_host_perf_precise.873181203
Short name T1332
Test name
Test status
Simulation time 612729055 ps
CPU time 2.33 seconds
Started Aug 12 04:41:03 PM PDT 24
Finished Aug 12 04:41:06 PM PDT 24
Peak memory 205120 kb
Host smart-9de0bcee-209f-42b1-84c2-bd1a08d612fa
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=873181203 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_perf_precise_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.i2c_host_perf_precise.873181203
Directory /workspace/3.i2c_host_perf_precise/latest

Test location /workspace/coverage/default/3.i2c_host_smoke.2664308639
Short name T1433
Test name
Test status
Simulation time 6634897052 ps
CPU time 29.1 seconds
Started Aug 12 04:40:54 PM PDT 24
Finished Aug 12 04:41:23 PM PDT 24
Peak memory 294404 kb
Host smart-53b155c4-de05-44a4-aa99-f59a96045709
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2664308639 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_smoke_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.i2c_host_smoke.2664308639
Directory /workspace/3.i2c_host_smoke/latest

Test location /workspace/coverage/default/3.i2c_host_stretch_timeout.1794399342
Short name T317
Test name
Test status
Simulation time 3186810823 ps
CPU time 9.51 seconds
Started Aug 12 04:41:03 PM PDT 24
Finished Aug 12 04:41:13 PM PDT 24
Peak memory 213488 kb
Host smart-e6f44007-ae2e-4aa7-8bd6-bc2815cbcd1c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1794399342 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_stretch_timeout_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.i2c_host_stretch_timeout.1794399342
Directory /workspace/3.i2c_host_stretch_timeout/latest

Test location /workspace/coverage/default/3.i2c_sec_cm.1581640886
Short name T197
Test name
Test status
Simulation time 195966824 ps
CPU time 0.87 seconds
Started Aug 12 04:41:02 PM PDT 24
Finished Aug 12 04:41:03 PM PDT 24
Peak memory 223308 kb
Host smart-9ff1db2b-4654-406d-aee8-3770b6992591
User root
Command /workspace/default/simv +run_sec_cm_fi +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1581640886 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_common_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.i2c_sec_cm.1581640886
Directory /workspace/3.i2c_sec_cm/latest

Test location /workspace/coverage/default/3.i2c_target_bad_addr.2324689488
Short name T933
Test name
Test status
Simulation time 3417908654 ps
CPU time 5.37 seconds
Started Aug 12 04:41:03 PM PDT 24
Finished Aug 12 04:41:09 PM PDT 24
Peak memory 213976 kb
Host smart-1e3b471e-99fd-4f17-b366-45408176c0d3
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +i2c_bad_addr_pct=50 +cdc_instrumentation_enabled=1 +UVM_
NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2324689488 -assert nopostproc
+UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_target_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.
vdb -cm_log /dev/null -cm_name 3.i2c_target_bad_addr.2324689488
Directory /workspace/3.i2c_target_bad_addr/latest

Test location /workspace/coverage/default/3.i2c_target_fifo_reset_acq.1930432550
Short name T74
Test name
Test status
Simulation time 614757746 ps
CPU time 1.33 seconds
Started Aug 12 04:41:04 PM PDT 24
Finished Aug 12 04:41:06 PM PDT 24
Peak memory 205444 kb
Host smart-1e3682e0-0aca-4bfd-9948-2e2c070a7d7e
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1930432550 -assert nopostproc +UVM_TESTNAME=i2c_bas
e_test +UVM_TEST_SEQ=i2c_target_fifo_reset_acq_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log
/dev/null -cm_name 3.i2c_target_fifo_reset_acq.1930432550
Directory /workspace/3.i2c_target_fifo_reset_acq/latest

Test location /workspace/coverage/default/3.i2c_target_fifo_reset_tx.330707319
Short name T1579
Test name
Test status
Simulation time 323498904 ps
CPU time 1.79 seconds
Started Aug 12 04:41:03 PM PDT 24
Finished Aug 12 04:41:05 PM PDT 24
Peak memory 221640 kb
Host smart-f5fcc3d5-c064-4030-a25a-3c7370e2cabd
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=330707319 -assert nopostproc +UVM_TESTNAME=i2c_base
_test +UVM_TEST_SEQ=i2c_target_fifo_reset_tx_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /d
ev/null -cm_name 3.i2c_target_fifo_reset_tx.330707319
Directory /workspace/3.i2c_target_fifo_reset_tx/latest

Test location /workspace/coverage/default/3.i2c_target_fifo_watermarks_acq.2132412189
Short name T1337
Test name
Test status
Simulation time 765911513 ps
CPU time 1.78 seconds
Started Aug 12 04:41:04 PM PDT 24
Finished Aug 12 04:41:06 PM PDT 24
Peak memory 205208 kb
Host smart-c3e5d986-5298-4545-b0fd-78623ed38ea1
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2132412189 -assert nopostproc +UVM_TESTNAME=i2c_bas
e_test +UVM_TEST_SEQ=i2c_target_fifo_watermarks_acq_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm
_log /dev/null -cm_name 3.i2c_target_fifo_watermarks_acq.2132412189
Directory /workspace/3.i2c_target_fifo_watermarks_acq/latest

Test location /workspace/coverage/default/3.i2c_target_fifo_watermarks_tx.2574742342
Short name T746
Test name
Test status
Simulation time 121076196 ps
CPU time 1.3 seconds
Started Aug 12 04:41:09 PM PDT 24
Finished Aug 12 04:41:10 PM PDT 24
Peak memory 205204 kb
Host smart-b2994604-58c0-4b50-815b-d9b38419821d
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2574742342 -assert nopostproc +UVM_TESTNAME=i2c_bas
e_test +UVM_TEST_SEQ=i2c_target_fifo_watermarks_tx_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_
log /dev/null -cm_name 3.i2c_target_fifo_watermarks_tx.2574742342
Directory /workspace/3.i2c_target_fifo_watermarks_tx/latest

Test location /workspace/coverage/default/3.i2c_target_intr_smoke.1281653220
Short name T1116
Test name
Test status
Simulation time 958574217 ps
CPU time 4.95 seconds
Started Aug 12 04:41:02 PM PDT 24
Finished Aug 12 04:41:07 PM PDT 24
Peak memory 221732 kb
Host smart-2181be71-81c6-4126-9225-4f8b59949718
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=200_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VER
BOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1281653220 -assert nopostproc +UVM_TESTNAME=i2c_ba
se_test +UVM_TEST_SEQ=i2c_target_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/nul
l -cm_name 3.i2c_target_intr_smoke.1281653220
Directory /workspace/3.i2c_target_intr_smoke/latest

Test location /workspace/coverage/default/3.i2c_target_intr_stress_wr.3296320158
Short name T1704
Test name
Test status
Simulation time 5656581023 ps
CPU time 7.68 seconds
Started Aug 12 04:41:09 PM PDT 24
Finished Aug 12 04:41:16 PM PDT 24
Peak memory 205580 kb
Host smart-ef41c774-4ef3-4a95-b42e-d5beeeaec1ae
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=600_000_000 +use_intr_handler=1 +slow_acq=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNO
TES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3296320158 -assert nopostproc +UVM_TES
TNAME=i2c_base_test +UVM_TEST_SEQ=i2c_target_stress_wr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb
-cm_log /dev/null -cm_name 3.i2c_target_intr_stress_wr.3296320158
Directory /workspace/3.i2c_target_intr_stress_wr/latest

Test location /workspace/coverage/default/3.i2c_target_nack_acqfull.3376277028
Short name T1107
Test name
Test status
Simulation time 531773234 ps
CPU time 3.07 seconds
Started Aug 12 04:41:02 PM PDT 24
Finished Aug 12 04:41:05 PM PDT 24
Peak memory 213656 kb
Host smart-37671f78-ac7d-4240-9ef3-7530bd7208df
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3376277028 -assert nopostproc +UVM_TESTNAME=i2c_bas
e_test +UVM_TEST_SEQ=i2c_target_nack_acqfull_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /d
ev/null -cm_name 3.i2c_target_nack_acqfull.3376277028
Directory /workspace/3.i2c_target_nack_acqfull/latest

Test location /workspace/coverage/default/3.i2c_target_nack_acqfull_addr.598352049
Short name T1707
Test name
Test status
Simulation time 522876396 ps
CPU time 2.51 seconds
Started Aug 12 04:41:03 PM PDT 24
Finished Aug 12 04:41:05 PM PDT 24
Peak memory 205488 kb
Host smart-105e704e-ace0-4459-823c-51f675b81b89
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=598352049 -assert nopostproc +UVM_TESTNAME=i2c_base
_test +UVM_TEST_SEQ=i2c_target_nack_acqfull_addr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_lo
g /dev/null -cm_name 3.i2c_target_nack_acqfull_addr.598352049
Directory /workspace/3.i2c_target_nack_acqfull_addr/latest

Test location /workspace/coverage/default/3.i2c_target_nack_txstretch.2257753629
Short name T608
Test name
Test status
Simulation time 1185826043 ps
CPU time 1.53 seconds
Started Aug 12 04:41:09 PM PDT 24
Finished Aug 12 04:41:10 PM PDT 24
Peak memory 223084 kb
Host smart-d0dc4cec-bbcc-493e-bf6b-bc1d6a513738
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2257753629 -assert nopostproc +UVM_TESTNAME=i2c_bas
e_test +UVM_TEST_SEQ=i2c_target_nack_txstretch_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log
/dev/null -cm_name 3.i2c_target_nack_txstretch.2257753629
Directory /workspace/3.i2c_target_nack_txstretch/latest

Test location /workspace/coverage/default/3.i2c_target_perf.40986876
Short name T872
Test name
Test status
Simulation time 436876888 ps
CPU time 3.6 seconds
Started Aug 12 04:41:04 PM PDT 24
Finished Aug 12 04:41:08 PM PDT 24
Peak memory 217472 kb
Host smart-ea5f8894-965c-4326-bac6-cdbaafd5768c
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=40986876 -assert nopostproc +UVM_TESTNAME=i2c_base_
test +UVM_TEST_SEQ=i2c_target_perf_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -c
m_name 3.i2c_target_perf.40986876
Directory /workspace/3.i2c_target_perf/latest

Test location /workspace/coverage/default/3.i2c_target_smbus_maxlen.2165269201
Short name T1157
Test name
Test status
Simulation time 470746703 ps
CPU time 2.25 seconds
Started Aug 12 04:41:05 PM PDT 24
Finished Aug 12 04:41:07 PM PDT 24
Peak memory 205212 kb
Host smart-691f8e3e-f175-42d8-b2b1-c9b4eb779ffe
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2165269201 -assert nopostproc +UVM_TESTNAME=i2c_bas
e_test +UVM_TEST_SEQ=i2c_target_smbus_maxlen_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /d
ev/null -cm_name 3.i2c_target_smbus_maxlen.2165269201
Directory /workspace/3.i2c_target_smbus_maxlen/latest

Test location /workspace/coverage/default/3.i2c_target_smoke.1027037138
Short name T1205
Test name
Test status
Simulation time 3354522912 ps
CPU time 12.83 seconds
Started Aug 12 04:41:08 PM PDT 24
Finished Aug 12 04:41:21 PM PDT 24
Peak memory 213768 kb
Host smart-1de98627-adcd-4804-8a7d-0ae689e2cbba
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=100_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licq
ueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1027037138 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SE
Q=i2c_target_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.i2c_tar
get_smoke.1027037138
Directory /workspace/3.i2c_target_smoke/latest

Test location /workspace/coverage/default/3.i2c_target_stress_all.1629419107
Short name T641
Test name
Test status
Simulation time 9541410814 ps
CPU time 27.86 seconds
Started Aug 12 04:41:05 PM PDT 24
Finished Aug 12 04:41:33 PM PDT 24
Peak memory 264280 kb
Host smart-f5c980e3-8807-49d5-b2eb-6ae319fcb5ee
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=300_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VER
BOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1629419107 -assert nopostproc +UVM_TESTNAME=i2c_ba
se_test +UVM_TEST_SEQ=i2c_target_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /de
v/null -cm_name 3.i2c_target_stress_all.1629419107
Directory /workspace/3.i2c_target_stress_all/latest

Test location /workspace/coverage/default/3.i2c_target_stress_rd.903627192
Short name T282
Test name
Test status
Simulation time 1303861881 ps
CPU time 55.8 seconds
Started Aug 12 04:41:04 PM PDT 24
Finished Aug 12 04:42:00 PM PDT 24
Peak memory 216776 kb
Host smart-a6d121f8-86b1-46ae-aef2-d8ef9218fd3e
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=100_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licq
ueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=903627192 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ
=i2c_target_stress_rd_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.i2c_
target_stress_rd.903627192
Directory /workspace/3.i2c_target_stress_rd/latest

Test location /workspace/coverage/default/3.i2c_target_stress_wr.1017638053
Short name T1568
Test name
Test status
Simulation time 49167098918 ps
CPU time 1228.87 seconds
Started Aug 12 04:41:07 PM PDT 24
Finished Aug 12 05:01:36 PM PDT 24
Peak memory 7251292 kb
Host smart-9c4b4609-134a-4213-a48f-9faf9f2ced49
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=600_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licq
ueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1017638053 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SE
Q=i2c_target_stress_wr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.i2c
_target_stress_wr.1017638053
Directory /workspace/3.i2c_target_stress_wr/latest

Test location /workspace/coverage/default/3.i2c_target_stretch.421984348
Short name T1703
Test name
Test status
Simulation time 2955105013 ps
CPU time 2.57 seconds
Started Aug 12 04:41:08 PM PDT 24
Finished Aug 12 04:41:10 PM PDT 24
Peak memory 229944 kb
Host smart-a1de50a8-c8fc-4e19-94af-4056f2e41f9d
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=400_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licq
ueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=421984348 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ
=i2c_target_stretch_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.i2c_ta
rget_stretch.421984348
Directory /workspace/3.i2c_target_stretch/latest

Test location /workspace/coverage/default/3.i2c_target_timeout.2526181048
Short name T98
Test name
Test status
Simulation time 1350971592 ps
CPU time 6.97 seconds
Started Aug 12 04:41:08 PM PDT 24
Finished Aug 12 04:41:15 PM PDT 24
Peak memory 221864 kb
Host smart-7b98a47a-5736-4536-9e74-4d6145781502
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=50_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2526181048 -assert nopostproc +UVM_TESTNAME=i2c_bas
e_test +UVM_TEST_SEQ=i2c_target_timeout_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/nu
ll -cm_name 3.i2c_target_timeout.2526181048
Directory /workspace/3.i2c_target_timeout/latest

Test location /workspace/coverage/default/3.i2c_target_tx_stretch_ctrl.2992465440
Short name T767
Test name
Test status
Simulation time 233911812 ps
CPU time 3.71 seconds
Started Aug 12 04:41:02 PM PDT 24
Finished Aug 12 04:41:06 PM PDT 24
Peak memory 205504 kb
Host smart-a9cdbec3-182f-4dc2-bd11-c430f2125e76
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2992465440 -assert nopostproc +UVM_TESTNAME=i2c_bas
e_test +UVM_TEST_SEQ=i2c_target_tx_stretch_ctrl_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log
/dev/null -cm_name 3.i2c_target_tx_stretch_ctrl.2992465440
Directory /workspace/3.i2c_target_tx_stretch_ctrl/latest

Test location /workspace/coverage/default/30.i2c_alert_test.422956640
Short name T1006
Test name
Test status
Simulation time 16052325 ps
CPU time 0.67 seconds
Started Aug 12 04:44:27 PM PDT 24
Finished Aug 12 04:44:28 PM PDT 24
Peak memory 204408 kb
Host smart-f9477054-1b3e-463f-91a8-3a58c7de665f
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=422956640 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_common_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.i2c_alert_test.422956640
Directory /workspace/30.i2c_alert_test/latest

Test location /workspace/coverage/default/30.i2c_host_error_intr.2223612738
Short name T1379
Test name
Test status
Simulation time 199818174 ps
CPU time 1.95 seconds
Started Aug 12 04:44:26 PM PDT 24
Finished Aug 12 04:44:28 PM PDT 24
Peak memory 213500 kb
Host smart-b2860874-e7ce-4a7d-a114-cb22169c45a7
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2223612738 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_error_intr_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.i2c_host_error_intr.2223612738
Directory /workspace/30.i2c_host_error_intr/latest

Test location /workspace/coverage/default/30.i2c_host_fifo_fmt_empty.992107950
Short name T1685
Test name
Test status
Simulation time 1230609673 ps
CPU time 5.41 seconds
Started Aug 12 04:44:27 PM PDT 24
Finished Aug 12 04:44:32 PM PDT 24
Peak memory 257188 kb
Host smart-9786e9fc-b289-4d9c-b62f-32376aa70ed7
User root
Command /workspace/default/simv +test_timeout_ns=10_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=992107950 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_fifo_fmt_emp
ty_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.i2c_host_fifo_fmt_empt
y.992107950
Directory /workspace/30.i2c_host_fifo_fmt_empty/latest

Test location /workspace/coverage/default/30.i2c_host_fifo_full.298089567
Short name T166
Test name
Test status
Simulation time 2154032397 ps
CPU time 149.51 seconds
Started Aug 12 04:44:26 PM PDT 24
Finished Aug 12 04:46:56 PM PDT 24
Peak memory 675584 kb
Host smart-add9062f-9e64-4c7c-b7bd-484af84cc249
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=298089567 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_fifo_full_vseq +en_cov=1 -cm line+cond+f
sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.i2c_host_fifo_full.298089567
Directory /workspace/30.i2c_host_fifo_full/latest

Test location /workspace/coverage/default/30.i2c_host_fifo_overflow.3024531582
Short name T1625
Test name
Test status
Simulation time 5320712339 ps
CPU time 78.75 seconds
Started Aug 12 04:44:26 PM PDT 24
Finished Aug 12 04:45:45 PM PDT 24
Peak memory 443528 kb
Host smart-567746d6-f530-45db-9b78-5c5588d804ca
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3024531582 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_fifo_overflow_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.i2c_host_fifo_overflow.3024531582
Directory /workspace/30.i2c_host_fifo_overflow/latest

Test location /workspace/coverage/default/30.i2c_host_fifo_reset_fmt.1241073897
Short name T750
Test name
Test status
Simulation time 260747222 ps
CPU time 0.85 seconds
Started Aug 12 04:44:29 PM PDT 24
Finished Aug 12 04:44:30 PM PDT 24
Peak memory 205040 kb
Host smart-9e893d0d-d938-43bb-a67e-23e0c0f9217c
User root
Command /workspace/default/simv +test_timeout_ns=10_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1241073897 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_fifo_reset_
fmt_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.i2c_host_fifo_reset_f
mt.1241073897
Directory /workspace/30.i2c_host_fifo_reset_fmt/latest

Test location /workspace/coverage/default/30.i2c_host_fifo_reset_rx.3126444246
Short name T162
Test name
Test status
Simulation time 491487703 ps
CPU time 6.93 seconds
Started Aug 12 04:44:27 PM PDT 24
Finished Aug 12 04:44:34 PM PDT 24
Peak memory 252020 kb
Host smart-1d9c9a6a-dd7f-4a79-a832-4872da2fb750
User root
Command /workspace/default/simv +test_timeout_ns=10_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3126444246 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_fifo_reset_
rx_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.i2c_host_fifo_reset_rx
.3126444246
Directory /workspace/30.i2c_host_fifo_reset_rx/latest

Test location /workspace/coverage/default/30.i2c_host_fifo_watermark.1409253431
Short name T1025
Test name
Test status
Simulation time 19903320883 ps
CPU time 152.54 seconds
Started Aug 12 04:44:28 PM PDT 24
Finished Aug 12 04:47:01 PM PDT 24
Peak memory 1537412 kb
Host smart-e4c2f16f-2c3c-41bd-8918-88ea6ae8a417
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1409253431 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_fifo_watermark_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.i2c_host_fifo_watermark.1409253431
Directory /workspace/30.i2c_host_fifo_watermark/latest

Test location /workspace/coverage/default/30.i2c_host_may_nack.3106755243
Short name T1640
Test name
Test status
Simulation time 452028976 ps
CPU time 6.72 seconds
Started Aug 12 04:44:36 PM PDT 24
Finished Aug 12 04:44:43 PM PDT 24
Peak memory 205248 kb
Host smart-9a2bb690-fcb6-46bf-844e-0ef58fca3af1
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3106755243 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_may_nack_vseq +en_cov=1 -cm line+cond+f
sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.i2c_host_may_nack.3106755243
Directory /workspace/30.i2c_host_may_nack/latest

Test location /workspace/coverage/default/30.i2c_host_override.671944107
Short name T1698
Test name
Test status
Simulation time 45932706 ps
CPU time 0.66 seconds
Started Aug 12 04:44:21 PM PDT 24
Finished Aug 12 04:44:22 PM PDT 24
Peak memory 204920 kb
Host smart-bf19adca-435d-4ff0-a616-7dd8791c309b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=671944107 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_override_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.i2c_host_override.671944107
Directory /workspace/30.i2c_host_override/latest

Test location /workspace/coverage/default/30.i2c_host_perf.1165609203
Short name T479
Test name
Test status
Simulation time 19133011838 ps
CPU time 130.22 seconds
Started Aug 12 04:44:32 PM PDT 24
Finished Aug 12 04:46:43 PM PDT 24
Peak memory 230940 kb
Host smart-063a52e2-e526-4c45-8579-173ce7e85f60
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1165609203 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_perf_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.i2c_host_perf.1165609203
Directory /workspace/30.i2c_host_perf/latest

Test location /workspace/coverage/default/30.i2c_host_perf_precise.1407010820
Short name T1411
Test name
Test status
Simulation time 24637844350 ps
CPU time 233.38 seconds
Started Aug 12 04:44:28 PM PDT 24
Finished Aug 12 04:48:21 PM PDT 24
Peak memory 205236 kb
Host smart-779af77f-f7db-46fa-be68-bda44f46af00
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1407010820 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_perf_precise_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.i2c_host_perf_precise.1407010820
Directory /workspace/30.i2c_host_perf_precise/latest

Test location /workspace/coverage/default/30.i2c_host_smoke.963798338
Short name T300
Test name
Test status
Simulation time 4431940376 ps
CPU time 40.36 seconds
Started Aug 12 04:44:18 PM PDT 24
Finished Aug 12 04:44:58 PM PDT 24
Peak memory 344556 kb
Host smart-e3b8fbe8-e856-4b75-a6cc-04c95863d4fc
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=963798338 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_smoke_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.i2c_host_smoke.963798338
Directory /workspace/30.i2c_host_smoke/latest

Test location /workspace/coverage/default/30.i2c_host_stretch_timeout.1395904743
Short name T760
Test name
Test status
Simulation time 669220764 ps
CPU time 11.15 seconds
Started Aug 12 04:44:36 PM PDT 24
Finished Aug 12 04:44:48 PM PDT 24
Peak memory 221500 kb
Host smart-3d7fd0d1-c19f-45b8-9dd6-d1ea05387640
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1395904743 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_stretch_timeout_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.i2c_host_stretch_timeout.1395904743
Directory /workspace/30.i2c_host_stretch_timeout/latest

Test location /workspace/coverage/default/30.i2c_target_bad_addr.2648046687
Short name T1247
Test name
Test status
Simulation time 765527936 ps
CPU time 4.71 seconds
Started Aug 12 04:44:28 PM PDT 24
Finished Aug 12 04:44:33 PM PDT 24
Peak memory 213736 kb
Host smart-2527010f-372f-4004-8f3f-20f801218c8f
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +i2c_bad_addr_pct=50 +cdc_instrumentation_enabled=1 +UVM_
NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2648046687 -assert nopostproc
+UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_target_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.
vdb -cm_log /dev/null -cm_name 30.i2c_target_bad_addr.2648046687
Directory /workspace/30.i2c_target_bad_addr/latest

Test location /workspace/coverage/default/30.i2c_target_fifo_reset_acq.3179327536
Short name T375
Test name
Test status
Simulation time 100082037 ps
CPU time 0.71 seconds
Started Aug 12 04:44:27 PM PDT 24
Finished Aug 12 04:44:28 PM PDT 24
Peak memory 205280 kb
Host smart-3c005693-3660-4bc2-bd00-f7c3e51e8cfe
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3179327536 -assert nopostproc +UVM_TESTNAME=i2c_bas
e_test +UVM_TEST_SEQ=i2c_target_fifo_reset_acq_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log
/dev/null -cm_name 30.i2c_target_fifo_reset_acq.3179327536
Directory /workspace/30.i2c_target_fifo_reset_acq/latest

Test location /workspace/coverage/default/30.i2c_target_fifo_reset_tx.34111276
Short name T1303
Test name
Test status
Simulation time 313627644 ps
CPU time 1.25 seconds
Started Aug 12 04:44:28 PM PDT 24
Finished Aug 12 04:44:30 PM PDT 24
Peak memory 205284 kb
Host smart-04f4f469-e3fc-477c-b5e9-fe44c2ed0ee3
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=34111276 -assert nopostproc +UVM_TESTNAME=i2c_base_
test +UVM_TEST_SEQ=i2c_target_fifo_reset_tx_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /de
v/null -cm_name 30.i2c_target_fifo_reset_tx.34111276
Directory /workspace/30.i2c_target_fifo_reset_tx/latest

Test location /workspace/coverage/default/30.i2c_target_fifo_watermarks_acq.1429435515
Short name T1727
Test name
Test status
Simulation time 339914894 ps
CPU time 2.07 seconds
Started Aug 12 04:44:28 PM PDT 24
Finished Aug 12 04:44:30 PM PDT 24
Peak memory 205216 kb
Host smart-d100fdba-1836-4fad-bc78-c93eb8bb9250
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1429435515 -assert nopostproc +UVM_TESTNAME=i2c_bas
e_test +UVM_TEST_SEQ=i2c_target_fifo_watermarks_acq_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm
_log /dev/null -cm_name 30.i2c_target_fifo_watermarks_acq.1429435515
Directory /workspace/30.i2c_target_fifo_watermarks_acq/latest

Test location /workspace/coverage/default/30.i2c_target_fifo_watermarks_tx.3146380346
Short name T1079
Test name
Test status
Simulation time 323652283 ps
CPU time 1.26 seconds
Started Aug 12 04:44:32 PM PDT 24
Finished Aug 12 04:44:33 PM PDT 24
Peak memory 205292 kb
Host smart-d12f39c1-9309-42d6-8795-17b6af4fa843
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3146380346 -assert nopostproc +UVM_TESTNAME=i2c_bas
e_test +UVM_TEST_SEQ=i2c_target_fifo_watermarks_tx_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_
log /dev/null -cm_name 30.i2c_target_fifo_watermarks_tx.3146380346
Directory /workspace/30.i2c_target_fifo_watermarks_tx/latest

Test location /workspace/coverage/default/30.i2c_target_intr_smoke.2955557387
Short name T642
Test name
Test status
Simulation time 2465389018 ps
CPU time 7.53 seconds
Started Aug 12 04:44:29 PM PDT 24
Finished Aug 12 04:44:37 PM PDT 24
Peak memory 221916 kb
Host smart-c21853df-a928-4345-a04c-472150395863
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=200_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VER
BOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2955557387 -assert nopostproc +UVM_TESTNAME=i2c_ba
se_test +UVM_TEST_SEQ=i2c_target_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/nul
l -cm_name 30.i2c_target_intr_smoke.2955557387
Directory /workspace/30.i2c_target_intr_smoke/latest

Test location /workspace/coverage/default/30.i2c_target_intr_stress_wr.2051444525
Short name T1445
Test name
Test status
Simulation time 21899321542 ps
CPU time 67.73 seconds
Started Aug 12 04:44:27 PM PDT 24
Finished Aug 12 04:45:35 PM PDT 24
Peak memory 913284 kb
Host smart-302f9018-144c-4d94-9382-00e8cb306fd5
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=600_000_000 +use_intr_handler=1 +slow_acq=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNO
TES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2051444525 -assert nopostproc +UVM_TES
TNAME=i2c_base_test +UVM_TEST_SEQ=i2c_target_stress_wr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb
-cm_log /dev/null -cm_name 30.i2c_target_intr_stress_wr.2051444525
Directory /workspace/30.i2c_target_intr_stress_wr/latest

Test location /workspace/coverage/default/30.i2c_target_nack_acqfull.2248529176
Short name T944
Test name
Test status
Simulation time 453838315 ps
CPU time 2.58 seconds
Started Aug 12 04:44:31 PM PDT 24
Finished Aug 12 04:44:34 PM PDT 24
Peak memory 213764 kb
Host smart-1bfd9168-2621-4e63-9f66-ffdc5157967c
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2248529176 -assert nopostproc +UVM_TESTNAME=i2c_bas
e_test +UVM_TEST_SEQ=i2c_target_nack_acqfull_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /d
ev/null -cm_name 30.i2c_target_nack_acqfull.2248529176
Directory /workspace/30.i2c_target_nack_acqfull/latest

Test location /workspace/coverage/default/30.i2c_target_nack_acqfull_addr.2089126387
Short name T1207
Test name
Test status
Simulation time 445605333 ps
CPU time 2.45 seconds
Started Aug 12 04:44:28 PM PDT 24
Finished Aug 12 04:44:30 PM PDT 24
Peak memory 205472 kb
Host smart-65e65df9-1ba7-4707-9edf-cc6ed22604d2
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2089126387 -assert nopostproc +UVM_TESTNAME=i2c_bas
e_test +UVM_TEST_SEQ=i2c_target_nack_acqfull_addr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_l
og /dev/null -cm_name 30.i2c_target_nack_acqfull_addr.2089126387
Directory /workspace/30.i2c_target_nack_acqfull_addr/latest

Test location /workspace/coverage/default/30.i2c_target_perf.3688764426
Short name T770
Test name
Test status
Simulation time 1192732655 ps
CPU time 9.31 seconds
Started Aug 12 04:44:31 PM PDT 24
Finished Aug 12 04:44:40 PM PDT 24
Peak memory 236196 kb
Host smart-a4c4a999-bedb-4a68-9f25-08027bd49550
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3688764426 -assert nopostproc +UVM_TESTNAME=i2c_bas
e_test +UVM_TEST_SEQ=i2c_target_perf_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null
-cm_name 30.i2c_target_perf.3688764426
Directory /workspace/30.i2c_target_perf/latest

Test location /workspace/coverage/default/30.i2c_target_smbus_maxlen.1651294893
Short name T1143
Test name
Test status
Simulation time 1895118393 ps
CPU time 2.39 seconds
Started Aug 12 04:44:31 PM PDT 24
Finished Aug 12 04:44:34 PM PDT 24
Peak memory 205288 kb
Host smart-d8b63dc0-4df9-4c9b-b248-507c6711ee12
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1651294893 -assert nopostproc +UVM_TESTNAME=i2c_bas
e_test +UVM_TEST_SEQ=i2c_target_smbus_maxlen_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /d
ev/null -cm_name 30.i2c_target_smbus_maxlen.1651294893
Directory /workspace/30.i2c_target_smbus_maxlen/latest

Test location /workspace/coverage/default/30.i2c_target_smoke.2941584178
Short name T205
Test name
Test status
Simulation time 685475811 ps
CPU time 22.88 seconds
Started Aug 12 04:44:27 PM PDT 24
Finished Aug 12 04:44:50 PM PDT 24
Peak memory 213752 kb
Host smart-b10631c9-4026-4b9d-9f5d-3903708669a5
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=100_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licq
ueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2941584178 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SE
Q=i2c_target_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.i2c_ta
rget_smoke.2941584178
Directory /workspace/30.i2c_target_smoke/latest

Test location /workspace/coverage/default/30.i2c_target_stress_all.725372607
Short name T303
Test name
Test status
Simulation time 42050284279 ps
CPU time 533 seconds
Started Aug 12 04:44:29 PM PDT 24
Finished Aug 12 04:53:22 PM PDT 24
Peak memory 3511516 kb
Host smart-432434de-5508-4b0a-9d62-14ecf6b7194c
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=300_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VER
BOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=725372607 -assert nopostproc +UVM_TESTNAME=i2c_bas
e_test +UVM_TEST_SEQ=i2c_target_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev
/null -cm_name 30.i2c_target_stress_all.725372607
Directory /workspace/30.i2c_target_stress_all/latest

Test location /workspace/coverage/default/30.i2c_target_stress_rd.4274458847
Short name T227
Test name
Test status
Simulation time 1122812714 ps
CPU time 12.17 seconds
Started Aug 12 04:44:27 PM PDT 24
Finished Aug 12 04:44:39 PM PDT 24
Peak memory 213708 kb
Host smart-5ec54b64-6682-40ad-a123-31c9eb411f85
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=100_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licq
ueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4274458847 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SE
Q=i2c_target_stress_rd_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.i2
c_target_stress_rd.4274458847
Directory /workspace/30.i2c_target_stress_rd/latest

Test location /workspace/coverage/default/30.i2c_target_stress_wr.3348665701
Short name T55
Test name
Test status
Simulation time 63932046020 ps
CPU time 3145.95 seconds
Started Aug 12 04:44:36 PM PDT 24
Finished Aug 12 05:37:03 PM PDT 24
Peak memory 11186452 kb
Host smart-82f57947-36b5-414d-9cda-b2aff1ce4ad5
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=600_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licq
ueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3348665701 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SE
Q=i2c_target_stress_wr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.i2
c_target_stress_wr.3348665701
Directory /workspace/30.i2c_target_stress_wr/latest

Test location /workspace/coverage/default/30.i2c_target_timeout.1888214998
Short name T397
Test name
Test status
Simulation time 10480731805 ps
CPU time 6.33 seconds
Started Aug 12 04:44:26 PM PDT 24
Finished Aug 12 04:44:32 PM PDT 24
Peak memory 219160 kb
Host smart-653727eb-e98a-4246-8e3b-bcc6c15e700a
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=50_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1888214998 -assert nopostproc +UVM_TESTNAME=i2c_bas
e_test +UVM_TEST_SEQ=i2c_target_timeout_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/nu
ll -cm_name 30.i2c_target_timeout.1888214998
Directory /workspace/30.i2c_target_timeout/latest

Test location /workspace/coverage/default/30.i2c_target_tx_stretch_ctrl.4275391954
Short name T1349
Test name
Test status
Simulation time 243600089 ps
CPU time 3.67 seconds
Started Aug 12 04:44:31 PM PDT 24
Finished Aug 12 04:44:35 PM PDT 24
Peak memory 205460 kb
Host smart-d422afee-044a-44d8-87aa-d542c1de48e0
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4275391954 -assert nopostproc +UVM_TESTNAME=i2c_bas
e_test +UVM_TEST_SEQ=i2c_target_tx_stretch_ctrl_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log
/dev/null -cm_name 30.i2c_target_tx_stretch_ctrl.4275391954
Directory /workspace/30.i2c_target_tx_stretch_ctrl/latest

Test location /workspace/coverage/default/31.i2c_alert_test.1286064400
Short name T491
Test name
Test status
Simulation time 18460458 ps
CPU time 0.63 seconds
Started Aug 12 04:44:42 PM PDT 24
Finished Aug 12 04:44:43 PM PDT 24
Peak memory 204472 kb
Host smart-502d7c42-1bdb-4ff5-b885-f825f7557385
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1286064400 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_common_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.i2c_alert_test.1286064400
Directory /workspace/31.i2c_alert_test/latest

Test location /workspace/coverage/default/31.i2c_host_fifo_fmt_empty.2394972489
Short name T687
Test name
Test status
Simulation time 918191915 ps
CPU time 26.37 seconds
Started Aug 12 04:44:31 PM PDT 24
Finished Aug 12 04:44:58 PM PDT 24
Peak memory 312428 kb
Host smart-27a29b9f-864c-4d7a-bb86-c467c1922006
User root
Command /workspace/default/simv +test_timeout_ns=10_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2394972489 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_fifo_fmt_em
pty_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.i2c_host_fifo_fmt_emp
ty.2394972489
Directory /workspace/31.i2c_host_fifo_fmt_empty/latest

Test location /workspace/coverage/default/31.i2c_host_fifo_full.3213039381
Short name T774
Test name
Test status
Simulation time 2347590230 ps
CPU time 111.55 seconds
Started Aug 12 04:44:27 PM PDT 24
Finished Aug 12 04:46:19 PM PDT 24
Peak memory 237692 kb
Host smart-5051c63f-966f-4b35-b33f-26b4bf9aba26
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3213039381 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_fifo_full_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.i2c_host_fifo_full.3213039381
Directory /workspace/31.i2c_host_fifo_full/latest

Test location /workspace/coverage/default/31.i2c_host_fifo_overflow.3416446808
Short name T727
Test name
Test status
Simulation time 3955455003 ps
CPU time 49.48 seconds
Started Aug 12 04:44:32 PM PDT 24
Finished Aug 12 04:45:22 PM PDT 24
Peak memory 537260 kb
Host smart-b5cb1cb4-3d96-4e27-ad86-ddba430d59a4
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3416446808 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_fifo_overflow_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.i2c_host_fifo_overflow.3416446808
Directory /workspace/31.i2c_host_fifo_overflow/latest

Test location /workspace/coverage/default/31.i2c_host_fifo_reset_fmt.2891207121
Short name T600
Test name
Test status
Simulation time 444338986 ps
CPU time 1.15 seconds
Started Aug 12 04:44:31 PM PDT 24
Finished Aug 12 04:44:32 PM PDT 24
Peak memory 204952 kb
Host smart-a8265544-8502-4f15-b285-4720d479ea08
User root
Command /workspace/default/simv +test_timeout_ns=10_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2891207121 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_fifo_reset_
fmt_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.i2c_host_fifo_reset_f
mt.2891207121
Directory /workspace/31.i2c_host_fifo_reset_fmt/latest

Test location /workspace/coverage/default/31.i2c_host_fifo_reset_rx.1462248621
Short name T1720
Test name
Test status
Simulation time 997678884 ps
CPU time 10.4 seconds
Started Aug 12 04:44:26 PM PDT 24
Finished Aug 12 04:44:37 PM PDT 24
Peak memory 239660 kb
Host smart-0aa0674d-8908-4a01-a26d-ed3e0283a13f
User root
Command /workspace/default/simv +test_timeout_ns=10_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1462248621 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_fifo_reset_
rx_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.i2c_host_fifo_reset_rx
.1462248621
Directory /workspace/31.i2c_host_fifo_reset_rx/latest

Test location /workspace/coverage/default/31.i2c_host_fifo_watermark.3285561883
Short name T1712
Test name
Test status
Simulation time 6751522439 ps
CPU time 211.56 seconds
Started Aug 12 04:44:31 PM PDT 24
Finished Aug 12 04:48:03 PM PDT 24
Peak memory 1014824 kb
Host smart-9a3124ed-6e76-4473-ae82-d25a04ee03d3
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3285561883 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_fifo_watermark_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.i2c_host_fifo_watermark.3285561883
Directory /workspace/31.i2c_host_fifo_watermark/latest

Test location /workspace/coverage/default/31.i2c_host_may_nack.2769551743
Short name T1647
Test name
Test status
Simulation time 2086799735 ps
CPU time 8.8 seconds
Started Aug 12 04:44:37 PM PDT 24
Finished Aug 12 04:44:46 PM PDT 24
Peak memory 205160 kb
Host smart-a375efda-fe3f-4309-b940-528388993c69
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2769551743 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_may_nack_vseq +en_cov=1 -cm line+cond+f
sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.i2c_host_may_nack.2769551743
Directory /workspace/31.i2c_host_may_nack/latest

Test location /workspace/coverage/default/31.i2c_host_override.2430204009
Short name T427
Test name
Test status
Simulation time 91371259 ps
CPU time 0.69 seconds
Started Aug 12 04:44:27 PM PDT 24
Finished Aug 12 04:44:27 PM PDT 24
Peak memory 204892 kb
Host smart-0b6c0e00-7229-4b4c-81cb-ea5172085088
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2430204009 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_override_vseq +en_cov=1 -cm line+cond+f
sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.i2c_host_override.2430204009
Directory /workspace/31.i2c_host_override/latest

Test location /workspace/coverage/default/31.i2c_host_perf.3700087700
Short name T352
Test name
Test status
Simulation time 229363755 ps
CPU time 3.03 seconds
Started Aug 12 04:44:27 PM PDT 24
Finished Aug 12 04:44:30 PM PDT 24
Peak memory 229804 kb
Host smart-554444c1-3a5a-441a-8960-407e56da84c3
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3700087700 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_perf_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.i2c_host_perf.3700087700
Directory /workspace/31.i2c_host_perf/latest

Test location /workspace/coverage/default/31.i2c_host_perf_precise.2684426040
Short name T742
Test name
Test status
Simulation time 1418853997 ps
CPU time 12.45 seconds
Started Aug 12 04:44:31 PM PDT 24
Finished Aug 12 04:44:44 PM PDT 24
Peak memory 338668 kb
Host smart-e55298c9-ed1f-484c-805d-4958fb66aeec
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2684426040 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_perf_precise_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.i2c_host_perf_precise.2684426040
Directory /workspace/31.i2c_host_perf_precise/latest

Test location /workspace/coverage/default/31.i2c_host_smoke.929614984
Short name T884
Test name
Test status
Simulation time 1380740701 ps
CPU time 62.31 seconds
Started Aug 12 04:44:28 PM PDT 24
Finished Aug 12 04:45:30 PM PDT 24
Peak memory 329812 kb
Host smart-1ccba2c3-1780-4bd0-ad4c-41ef7ef69119
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=929614984 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_smoke_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.i2c_host_smoke.929614984
Directory /workspace/31.i2c_host_smoke/latest

Test location /workspace/coverage/default/31.i2c_host_stress_all.403756877
Short name T137
Test name
Test status
Simulation time 15607899936 ps
CPU time 234.93 seconds
Started Aug 12 04:44:30 PM PDT 24
Finished Aug 12 04:48:25 PM PDT 24
Peak memory 1047628 kb
Host smart-0080bb21-8484-4d74-b57d-934cbea3127a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=403756877 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_stress_all_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.i2c_host_stress_all.403756877
Directory /workspace/31.i2c_host_stress_all/latest

Test location /workspace/coverage/default/31.i2c_host_stretch_timeout.2095888668
Short name T873
Test name
Test status
Simulation time 5087043464 ps
CPU time 38.09 seconds
Started Aug 12 04:44:29 PM PDT 24
Finished Aug 12 04:45:07 PM PDT 24
Peak memory 214500 kb
Host smart-96b76c0c-cf08-4623-885a-36751e92ef1b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2095888668 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_stretch_timeout_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.i2c_host_stretch_timeout.2095888668
Directory /workspace/31.i2c_host_stretch_timeout/latest

Test location /workspace/coverage/default/31.i2c_target_bad_addr.1262866747
Short name T65
Test name
Test status
Simulation time 1673944591 ps
CPU time 4.75 seconds
Started Aug 12 04:44:36 PM PDT 24
Finished Aug 12 04:44:41 PM PDT 24
Peak memory 209536 kb
Host smart-9bc76fba-86f6-4589-8d89-e0a71b25c6d9
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +i2c_bad_addr_pct=50 +cdc_instrumentation_enabled=1 +UVM_
NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1262866747 -assert nopostproc
+UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_target_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.
vdb -cm_log /dev/null -cm_name 31.i2c_target_bad_addr.1262866747
Directory /workspace/31.i2c_target_bad_addr/latest

Test location /workspace/coverage/default/31.i2c_target_fifo_reset_acq.4088140298
Short name T1002
Test name
Test status
Simulation time 284130052 ps
CPU time 1.01 seconds
Started Aug 12 04:44:32 PM PDT 24
Finished Aug 12 04:44:33 PM PDT 24
Peak memory 205256 kb
Host smart-5811a914-c3c2-43f4-9252-d84635a3c99e
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4088140298 -assert nopostproc +UVM_TESTNAME=i2c_bas
e_test +UVM_TEST_SEQ=i2c_target_fifo_reset_acq_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log
/dev/null -cm_name 31.i2c_target_fifo_reset_acq.4088140298
Directory /workspace/31.i2c_target_fifo_reset_acq/latest

Test location /workspace/coverage/default/31.i2c_target_fifo_reset_tx.47147612
Short name T1481
Test name
Test status
Simulation time 749096297 ps
CPU time 1.09 seconds
Started Aug 12 04:44:36 PM PDT 24
Finished Aug 12 04:44:37 PM PDT 24
Peak memory 213708 kb
Host smart-abba417c-325e-4478-95b0-1f19826481e9
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=47147612 -assert nopostproc +UVM_TESTNAME=i2c_base_
test +UVM_TEST_SEQ=i2c_target_fifo_reset_tx_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /de
v/null -cm_name 31.i2c_target_fifo_reset_tx.47147612
Directory /workspace/31.i2c_target_fifo_reset_tx/latest

Test location /workspace/coverage/default/31.i2c_target_fifo_watermarks_acq.3065322889
Short name T838
Test name
Test status
Simulation time 404807524 ps
CPU time 2.27 seconds
Started Aug 12 04:44:33 PM PDT 24
Finished Aug 12 04:44:36 PM PDT 24
Peak memory 205356 kb
Host smart-17bf7626-7fef-4698-9b39-1953632c94de
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3065322889 -assert nopostproc +UVM_TESTNAME=i2c_bas
e_test +UVM_TEST_SEQ=i2c_target_fifo_watermarks_acq_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm
_log /dev/null -cm_name 31.i2c_target_fifo_watermarks_acq.3065322889
Directory /workspace/31.i2c_target_fifo_watermarks_acq/latest

Test location /workspace/coverage/default/31.i2c_target_fifo_watermarks_tx.1713469509
Short name T1687
Test name
Test status
Simulation time 765655724 ps
CPU time 1.19 seconds
Started Aug 12 04:44:35 PM PDT 24
Finished Aug 12 04:44:36 PM PDT 24
Peak memory 205344 kb
Host smart-d7f87c93-eea8-47c6-ac9d-68f17e03970e
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1713469509 -assert nopostproc +UVM_TESTNAME=i2c_bas
e_test +UVM_TEST_SEQ=i2c_target_fifo_watermarks_tx_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_
log /dev/null -cm_name 31.i2c_target_fifo_watermarks_tx.1713469509
Directory /workspace/31.i2c_target_fifo_watermarks_tx/latest

Test location /workspace/coverage/default/31.i2c_target_intr_smoke.559139008
Short name T766
Test name
Test status
Simulation time 1825513615 ps
CPU time 4.76 seconds
Started Aug 12 04:44:28 PM PDT 24
Finished Aug 12 04:44:33 PM PDT 24
Peak memory 221880 kb
Host smart-3be58911-92c7-4189-a696-562cc8ab1982
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=200_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VER
BOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=559139008 -assert nopostproc +UVM_TESTNAME=i2c_bas
e_test +UVM_TEST_SEQ=i2c_target_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null
-cm_name 31.i2c_target_intr_smoke.559139008
Directory /workspace/31.i2c_target_intr_smoke/latest

Test location /workspace/coverage/default/31.i2c_target_intr_stress_wr.2487948985
Short name T614
Test name
Test status
Simulation time 562736671 ps
CPU time 1.97 seconds
Started Aug 12 04:44:31 PM PDT 24
Finished Aug 12 04:44:33 PM PDT 24
Peak memory 205208 kb
Host smart-01532133-f845-4ead-9e04-856141c814c9
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=600_000_000 +use_intr_handler=1 +slow_acq=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNO
TES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2487948985 -assert nopostproc +UVM_TES
TNAME=i2c_base_test +UVM_TEST_SEQ=i2c_target_stress_wr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb
-cm_log /dev/null -cm_name 31.i2c_target_intr_stress_wr.2487948985
Directory /workspace/31.i2c_target_intr_stress_wr/latest

Test location /workspace/coverage/default/31.i2c_target_nack_acqfull.344648326
Short name T1435
Test name
Test status
Simulation time 1642915906 ps
CPU time 2.51 seconds
Started Aug 12 04:44:37 PM PDT 24
Finished Aug 12 04:44:39 PM PDT 24
Peak memory 213768 kb
Host smart-4372354e-d44b-4a57-b2af-fb3ddf134346
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=344648326 -assert nopostproc +UVM_TESTNAME=i2c_base
_test +UVM_TEST_SEQ=i2c_target_nack_acqfull_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /de
v/null -cm_name 31.i2c_target_nack_acqfull.344648326
Directory /workspace/31.i2c_target_nack_acqfull/latest

Test location /workspace/coverage/default/31.i2c_target_nack_acqfull_addr.914165118
Short name T1434
Test name
Test status
Simulation time 487479539 ps
CPU time 2.55 seconds
Started Aug 12 04:44:43 PM PDT 24
Finished Aug 12 04:44:45 PM PDT 24
Peak memory 205476 kb
Host smart-ff72db4c-9373-434d-9094-38a21f514934
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=914165118 -assert nopostproc +UVM_TESTNAME=i2c_base
_test +UVM_TEST_SEQ=i2c_target_nack_acqfull_addr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_lo
g /dev/null -cm_name 31.i2c_target_nack_acqfull_addr.914165118
Directory /workspace/31.i2c_target_nack_acqfull_addr/latest

Test location /workspace/coverage/default/31.i2c_target_nack_txstretch.2918885711
Short name T581
Test name
Test status
Simulation time 947536718 ps
CPU time 1.32 seconds
Started Aug 12 04:44:35 PM PDT 24
Finished Aug 12 04:44:36 PM PDT 24
Peak memory 222000 kb
Host smart-1b02743c-a44a-4c4c-a2b1-dcc57ae54e6e
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2918885711 -assert nopostproc +UVM_TESTNAME=i2c_bas
e_test +UVM_TEST_SEQ=i2c_target_nack_txstretch_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log
/dev/null -cm_name 31.i2c_target_nack_txstretch.2918885711
Directory /workspace/31.i2c_target_nack_txstretch/latest

Test location /workspace/coverage/default/31.i2c_target_perf.3431250438
Short name T1717
Test name
Test status
Simulation time 2723919914 ps
CPU time 5.71 seconds
Started Aug 12 04:44:32 PM PDT 24
Finished Aug 12 04:44:38 PM PDT 24
Peak memory 211436 kb
Host smart-41e6eab0-e1ba-41f4-9853-a872a0a75979
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3431250438 -assert nopostproc +UVM_TESTNAME=i2c_bas
e_test +UVM_TEST_SEQ=i2c_target_perf_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null
-cm_name 31.i2c_target_perf.3431250438
Directory /workspace/31.i2c_target_perf/latest

Test location /workspace/coverage/default/31.i2c_target_smbus_maxlen.954541999
Short name T310
Test name
Test status
Simulation time 1815594030 ps
CPU time 2.3 seconds
Started Aug 12 04:44:34 PM PDT 24
Finished Aug 12 04:44:36 PM PDT 24
Peak memory 205296 kb
Host smart-a1d8aa31-dc77-4dd1-9948-52591541a383
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=954541999 -assert nopostproc +UVM_TESTNAME=i2c_base
_test +UVM_TEST_SEQ=i2c_target_smbus_maxlen_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /de
v/null -cm_name 31.i2c_target_smbus_maxlen.954541999
Directory /workspace/31.i2c_target_smbus_maxlen/latest

Test location /workspace/coverage/default/31.i2c_target_smoke.1008816705
Short name T93
Test name
Test status
Simulation time 11407825697 ps
CPU time 8.6 seconds
Started Aug 12 04:44:31 PM PDT 24
Finished Aug 12 04:44:40 PM PDT 24
Peak memory 213724 kb
Host smart-75ff1db3-2c9b-4611-bda6-e6c697020ab2
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=100_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licq
ueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1008816705 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SE
Q=i2c_target_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.i2c_ta
rget_smoke.1008816705
Directory /workspace/31.i2c_target_smoke/latest

Test location /workspace/coverage/default/31.i2c_target_stress_all.3793350914
Short name T819
Test name
Test status
Simulation time 36213971590 ps
CPU time 1093.23 seconds
Started Aug 12 04:44:31 PM PDT 24
Finished Aug 12 05:02:45 PM PDT 24
Peak memory 5173112 kb
Host smart-7e9aef6a-cd7b-4b9b-91e2-33c145a5c3d8
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=300_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VER
BOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3793350914 -assert nopostproc +UVM_TESTNAME=i2c_ba
se_test +UVM_TEST_SEQ=i2c_target_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /de
v/null -cm_name 31.i2c_target_stress_all.3793350914
Directory /workspace/31.i2c_target_stress_all/latest

Test location /workspace/coverage/default/31.i2c_target_stress_rd.2179543978
Short name T875
Test name
Test status
Simulation time 298476318 ps
CPU time 4.83 seconds
Started Aug 12 04:44:31 PM PDT 24
Finished Aug 12 04:44:36 PM PDT 24
Peak memory 205464 kb
Host smart-282e4c37-973d-4d64-a830-5c117287b7af
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=100_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licq
ueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2179543978 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SE
Q=i2c_target_stress_rd_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.i2
c_target_stress_rd.2179543978
Directory /workspace/31.i2c_target_stress_rd/latest

Test location /workspace/coverage/default/31.i2c_target_stress_wr.4224703278
Short name T527
Test name
Test status
Simulation time 56956193170 ps
CPU time 1881.27 seconds
Started Aug 12 04:44:32 PM PDT 24
Finished Aug 12 05:15:54 PM PDT 24
Peak memory 9172764 kb
Host smart-c1ead027-8b7b-464e-a303-75956d2f7fd1
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=600_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licq
ueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4224703278 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SE
Q=i2c_target_stress_wr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.i2
c_target_stress_wr.4224703278
Directory /workspace/31.i2c_target_stress_wr/latest

Test location /workspace/coverage/default/31.i2c_target_stretch.701294337
Short name T1085
Test name
Test status
Simulation time 3125262202 ps
CPU time 19.51 seconds
Started Aug 12 04:44:27 PM PDT 24
Finished Aug 12 04:44:46 PM PDT 24
Peak memory 351084 kb
Host smart-02d41ed6-4cdd-46b8-93aa-2353cc723a0b
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=400_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licq
ueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=701294337 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ
=i2c_target_stretch_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.i2c_t
arget_stretch.701294337
Directory /workspace/31.i2c_target_stretch/latest

Test location /workspace/coverage/default/31.i2c_target_timeout.3069579495
Short name T1317
Test name
Test status
Simulation time 1363342632 ps
CPU time 6.88 seconds
Started Aug 12 04:44:31 PM PDT 24
Finished Aug 12 04:44:38 PM PDT 24
Peak memory 231424 kb
Host smart-820b1110-3f72-44f7-8b54-1fde3b268cd9
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=50_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3069579495 -assert nopostproc +UVM_TESTNAME=i2c_bas
e_test +UVM_TEST_SEQ=i2c_target_timeout_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/nu
ll -cm_name 31.i2c_target_timeout.3069579495
Directory /workspace/31.i2c_target_timeout/latest

Test location /workspace/coverage/default/31.i2c_target_tx_stretch_ctrl.3291257822
Short name T867
Test name
Test status
Simulation time 154260442 ps
CPU time 2.09 seconds
Started Aug 12 04:44:32 PM PDT 24
Finished Aug 12 04:44:35 PM PDT 24
Peak memory 205360 kb
Host smart-1c0fdf57-e4f8-4322-9a0b-704188c37f57
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3291257822 -assert nopostproc +UVM_TESTNAME=i2c_bas
e_test +UVM_TEST_SEQ=i2c_target_tx_stretch_ctrl_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log
/dev/null -cm_name 31.i2c_target_tx_stretch_ctrl.3291257822
Directory /workspace/31.i2c_target_tx_stretch_ctrl/latest

Test location /workspace/coverage/default/32.i2c_alert_test.3224793266
Short name T802
Test name
Test status
Simulation time 18772497 ps
CPU time 0.65 seconds
Started Aug 12 04:44:44 PM PDT 24
Finished Aug 12 04:44:45 PM PDT 24
Peak memory 204468 kb
Host smart-3fe87226-d3a0-41bd-bd12-5b908b7c188c
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3224793266 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_common_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.i2c_alert_test.3224793266
Directory /workspace/32.i2c_alert_test/latest

Test location /workspace/coverage/default/32.i2c_host_error_intr.3072764768
Short name T575
Test name
Test status
Simulation time 179569943 ps
CPU time 2.83 seconds
Started Aug 12 04:44:38 PM PDT 24
Finished Aug 12 04:44:41 PM PDT 24
Peak memory 213516 kb
Host smart-b60da2a7-f135-4230-9379-e3fcefc33cf4
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3072764768 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_error_intr_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.i2c_host_error_intr.3072764768
Directory /workspace/32.i2c_host_error_intr/latest

Test location /workspace/coverage/default/32.i2c_host_fifo_fmt_empty.1445442732
Short name T953
Test name
Test status
Simulation time 1739903065 ps
CPU time 16.21 seconds
Started Aug 12 04:44:42 PM PDT 24
Finished Aug 12 04:44:58 PM PDT 24
Peak memory 273944 kb
Host smart-27905137-3bb3-4cd5-a1d9-397f8ed52a40
User root
Command /workspace/default/simv +test_timeout_ns=10_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1445442732 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_fifo_fmt_em
pty_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.i2c_host_fifo_fmt_emp
ty.1445442732
Directory /workspace/32.i2c_host_fifo_fmt_empty/latest

Test location /workspace/coverage/default/32.i2c_host_fifo_full.3666377648
Short name T40
Test name
Test status
Simulation time 3219046445 ps
CPU time 97.09 seconds
Started Aug 12 04:44:42 PM PDT 24
Finished Aug 12 04:46:19 PM PDT 24
Peak memory 449080 kb
Host smart-53aa6153-330b-4063-9b59-951af0cfcdc0
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3666377648 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_fifo_full_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.i2c_host_fifo_full.3666377648
Directory /workspace/32.i2c_host_fifo_full/latest

Test location /workspace/coverage/default/32.i2c_host_fifo_overflow.414615287
Short name T1656
Test name
Test status
Simulation time 3387414040 ps
CPU time 121.33 seconds
Started Aug 12 04:44:37 PM PDT 24
Finished Aug 12 04:46:39 PM PDT 24
Peak memory 612192 kb
Host smart-558a5ae4-2425-4636-8a3e-12104dd4cd9d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=414615287 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_fifo_overflow_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.i2c_host_fifo_overflow.414615287
Directory /workspace/32.i2c_host_fifo_overflow/latest

Test location /workspace/coverage/default/32.i2c_host_fifo_reset_fmt.1378952880
Short name T130
Test name
Test status
Simulation time 100418089 ps
CPU time 1.24 seconds
Started Aug 12 04:44:35 PM PDT 24
Finished Aug 12 04:44:36 PM PDT 24
Peak memory 205180 kb
Host smart-4ab96cd6-7425-40b9-be0f-870ecbafbe14
User root
Command /workspace/default/simv +test_timeout_ns=10_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1378952880 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_fifo_reset_
fmt_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.i2c_host_fifo_reset_f
mt.1378952880
Directory /workspace/32.i2c_host_fifo_reset_fmt/latest

Test location /workspace/coverage/default/32.i2c_host_fifo_reset_rx.2723404893
Short name T248
Test name
Test status
Simulation time 126176470 ps
CPU time 7.53 seconds
Started Aug 12 04:44:36 PM PDT 24
Finished Aug 12 04:44:44 PM PDT 24
Peak memory 226028 kb
Host smart-69dffed1-6717-439d-a80b-7e3ad54814be
User root
Command /workspace/default/simv +test_timeout_ns=10_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2723404893 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_fifo_reset_
rx_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.i2c_host_fifo_reset_rx
.2723404893
Directory /workspace/32.i2c_host_fifo_reset_rx/latest

Test location /workspace/coverage/default/32.i2c_host_fifo_watermark.1583284632
Short name T1648
Test name
Test status
Simulation time 13461713119 ps
CPU time 203.77 seconds
Started Aug 12 04:44:42 PM PDT 24
Finished Aug 12 04:48:06 PM PDT 24
Peak memory 977368 kb
Host smart-37041141-271a-422c-9e9b-a28b12b704d0
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1583284632 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_fifo_watermark_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.i2c_host_fifo_watermark.1583284632
Directory /workspace/32.i2c_host_fifo_watermark/latest

Test location /workspace/coverage/default/32.i2c_host_may_nack.2185261888
Short name T1301
Test name
Test status
Simulation time 331002845 ps
CPU time 6.98 seconds
Started Aug 12 04:44:36 PM PDT 24
Finished Aug 12 04:44:43 PM PDT 24
Peak memory 205284 kb
Host smart-676ccd46-6e06-4a71-a4d2-e57790f0e2da
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2185261888 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_may_nack_vseq +en_cov=1 -cm line+cond+f
sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.i2c_host_may_nack.2185261888
Directory /workspace/32.i2c_host_may_nack/latest

Test location /workspace/coverage/default/32.i2c_host_override.4230850887
Short name T1310
Test name
Test status
Simulation time 41878600 ps
CPU time 0.69 seconds
Started Aug 12 04:44:39 PM PDT 24
Finished Aug 12 04:44:40 PM PDT 24
Peak memory 204888 kb
Host smart-e4ce5d37-db3f-4428-9648-aade8a9208c9
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4230850887 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_override_vseq +en_cov=1 -cm line+cond+f
sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.i2c_host_override.4230850887
Directory /workspace/32.i2c_host_override/latest

Test location /workspace/coverage/default/32.i2c_host_perf.3298954421
Short name T1112
Test name
Test status
Simulation time 3677804790 ps
CPU time 10.87 seconds
Started Aug 12 04:44:42 PM PDT 24
Finished Aug 12 04:44:53 PM PDT 24
Peak memory 213776 kb
Host smart-01ff6228-3aa7-4ab7-a241-ccde87be642e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3298954421 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_perf_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.i2c_host_perf.3298954421
Directory /workspace/32.i2c_host_perf/latest

Test location /workspace/coverage/default/32.i2c_host_perf_precise.801721756
Short name T713
Test name
Test status
Simulation time 94716161 ps
CPU time 1.2 seconds
Started Aug 12 04:44:36 PM PDT 24
Finished Aug 12 04:44:38 PM PDT 24
Peak memory 205564 kb
Host smart-e1b4c552-f18a-4aec-a74c-5c55f8063aef
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=801721756 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_perf_precise_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.i2c_host_perf_precise.801721756
Directory /workspace/32.i2c_host_perf_precise/latest

Test location /workspace/coverage/default/32.i2c_host_smoke.2461238038
Short name T457
Test name
Test status
Simulation time 3497815897 ps
CPU time 62.14 seconds
Started Aug 12 04:44:35 PM PDT 24
Finished Aug 12 04:45:37 PM PDT 24
Peak memory 351368 kb
Host smart-9725bf75-f35f-4096-8909-f2e305072856
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2461238038 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_smoke_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.i2c_host_smoke.2461238038
Directory /workspace/32.i2c_host_smoke/latest

Test location /workspace/coverage/default/32.i2c_host_stretch_timeout.1462654987
Short name T1367
Test name
Test status
Simulation time 460961918 ps
CPU time 20.49 seconds
Started Aug 12 04:44:38 PM PDT 24
Finished Aug 12 04:44:59 PM PDT 24
Peak memory 213444 kb
Host smart-c4995ddc-38fc-4576-97bd-e13691f18a6f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1462654987 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_stretch_timeout_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.i2c_host_stretch_timeout.1462654987
Directory /workspace/32.i2c_host_stretch_timeout/latest

Test location /workspace/coverage/default/32.i2c_target_bad_addr.2652924072
Short name T1688
Test name
Test status
Simulation time 2941015140 ps
CPU time 6.58 seconds
Started Aug 12 04:44:36 PM PDT 24
Finished Aug 12 04:44:43 PM PDT 24
Peak memory 215696 kb
Host smart-381d5e62-53a4-469e-aefd-6798ba9e22a6
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +i2c_bad_addr_pct=50 +cdc_instrumentation_enabled=1 +UVM_
NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2652924072 -assert nopostproc
+UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_target_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.
vdb -cm_log /dev/null -cm_name 32.i2c_target_bad_addr.2652924072
Directory /workspace/32.i2c_target_bad_addr/latest

Test location /workspace/coverage/default/32.i2c_target_fifo_reset_acq.2618892615
Short name T977
Test name
Test status
Simulation time 210099393 ps
CPU time 0.97 seconds
Started Aug 12 04:44:38 PM PDT 24
Finished Aug 12 04:44:39 PM PDT 24
Peak memory 205288 kb
Host smart-48016fe5-6281-4fae-a13c-8c37dd93e267
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2618892615 -assert nopostproc +UVM_TESTNAME=i2c_bas
e_test +UVM_TEST_SEQ=i2c_target_fifo_reset_acq_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log
/dev/null -cm_name 32.i2c_target_fifo_reset_acq.2618892615
Directory /workspace/32.i2c_target_fifo_reset_acq/latest

Test location /workspace/coverage/default/32.i2c_target_fifo_reset_tx.1916420653
Short name T1416
Test name
Test status
Simulation time 773358229 ps
CPU time 1.53 seconds
Started Aug 12 04:44:43 PM PDT 24
Finished Aug 12 04:44:45 PM PDT 24
Peak memory 205468 kb
Host smart-cbfc52b3-5bba-4c79-909e-0987fa7d9fca
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1916420653 -assert nopostproc +UVM_TESTNAME=i2c_bas
e_test +UVM_TEST_SEQ=i2c_target_fifo_reset_tx_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /
dev/null -cm_name 32.i2c_target_fifo_reset_tx.1916420653
Directory /workspace/32.i2c_target_fifo_reset_tx/latest

Test location /workspace/coverage/default/32.i2c_target_fifo_watermarks_acq.441993878
Short name T591
Test name
Test status
Simulation time 1190979724 ps
CPU time 1.9 seconds
Started Aug 12 04:44:37 PM PDT 24
Finished Aug 12 04:44:40 PM PDT 24
Peak memory 205220 kb
Host smart-accfbf04-1e7d-4b8f-a3e6-5040a5d3681e
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=441993878 -assert nopostproc +UVM_TESTNAME=i2c_base
_test +UVM_TEST_SEQ=i2c_target_fifo_watermarks_acq_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_
log /dev/null -cm_name 32.i2c_target_fifo_watermarks_acq.441993878
Directory /workspace/32.i2c_target_fifo_watermarks_acq/latest

Test location /workspace/coverage/default/32.i2c_target_fifo_watermarks_tx.4291182630
Short name T45
Test name
Test status
Simulation time 777881793 ps
CPU time 0.92 seconds
Started Aug 12 04:44:42 PM PDT 24
Finished Aug 12 04:44:43 PM PDT 24
Peak memory 205204 kb
Host smart-015447d2-e1aa-4cab-bcd3-d54c1ebeab09
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4291182630 -assert nopostproc +UVM_TESTNAME=i2c_bas
e_test +UVM_TEST_SEQ=i2c_target_fifo_watermarks_tx_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_
log /dev/null -cm_name 32.i2c_target_fifo_watermarks_tx.4291182630
Directory /workspace/32.i2c_target_fifo_watermarks_tx/latest

Test location /workspace/coverage/default/32.i2c_target_intr_smoke.3637181400
Short name T928
Test name
Test status
Simulation time 1464557402 ps
CPU time 4.93 seconds
Started Aug 12 04:44:37 PM PDT 24
Finished Aug 12 04:44:42 PM PDT 24
Peak memory 213712 kb
Host smart-aff280cd-e99a-4969-b493-325ab332db21
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=200_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VER
BOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3637181400 -assert nopostproc +UVM_TESTNAME=i2c_ba
se_test +UVM_TEST_SEQ=i2c_target_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/nul
l -cm_name 32.i2c_target_intr_smoke.3637181400
Directory /workspace/32.i2c_target_intr_smoke/latest

Test location /workspace/coverage/default/32.i2c_target_intr_stress_wr.3895650803
Short name T522
Test name
Test status
Simulation time 3328219988 ps
CPU time 4.97 seconds
Started Aug 12 04:44:43 PM PDT 24
Finished Aug 12 04:44:49 PM PDT 24
Peak memory 310180 kb
Host smart-f4619c1f-bcf1-4656-b974-0fc4855912a8
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=600_000_000 +use_intr_handler=1 +slow_acq=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNO
TES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3895650803 -assert nopostproc +UVM_TES
TNAME=i2c_base_test +UVM_TEST_SEQ=i2c_target_stress_wr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb
-cm_log /dev/null -cm_name 32.i2c_target_intr_stress_wr.3895650803
Directory /workspace/32.i2c_target_intr_stress_wr/latest

Test location /workspace/coverage/default/32.i2c_target_nack_acqfull.2935398036
Short name T900
Test name
Test status
Simulation time 528068199 ps
CPU time 2.89 seconds
Started Aug 12 04:44:42 PM PDT 24
Finished Aug 12 04:44:45 PM PDT 24
Peak memory 213648 kb
Host smart-ebc22550-035e-4b7c-9c88-999ca825c188
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2935398036 -assert nopostproc +UVM_TESTNAME=i2c_bas
e_test +UVM_TEST_SEQ=i2c_target_nack_acqfull_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /d
ev/null -cm_name 32.i2c_target_nack_acqfull.2935398036
Directory /workspace/32.i2c_target_nack_acqfull/latest

Test location /workspace/coverage/default/32.i2c_target_nack_acqfull_addr.859842312
Short name T647
Test name
Test status
Simulation time 486495017 ps
CPU time 2.66 seconds
Started Aug 12 04:44:45 PM PDT 24
Finished Aug 12 04:44:48 PM PDT 24
Peak memory 206268 kb
Host smart-77a0f77a-b222-49c6-8162-e81dbc671439
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=859842312 -assert nopostproc +UVM_TESTNAME=i2c_base
_test +UVM_TEST_SEQ=i2c_target_nack_acqfull_addr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_lo
g /dev/null -cm_name 32.i2c_target_nack_acqfull_addr.859842312
Directory /workspace/32.i2c_target_nack_acqfull_addr/latest

Test location /workspace/coverage/default/32.i2c_target_nack_txstretch.3640528565
Short name T654
Test name
Test status
Simulation time 1044203858 ps
CPU time 1.34 seconds
Started Aug 12 04:44:43 PM PDT 24
Finished Aug 12 04:44:45 PM PDT 24
Peak memory 222304 kb
Host smart-09fd6481-1505-471b-b5c9-f4e04f8b67fe
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3640528565 -assert nopostproc +UVM_TESTNAME=i2c_bas
e_test +UVM_TEST_SEQ=i2c_target_nack_txstretch_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log
/dev/null -cm_name 32.i2c_target_nack_txstretch.3640528565
Directory /workspace/32.i2c_target_nack_txstretch/latest

Test location /workspace/coverage/default/32.i2c_target_perf.576269983
Short name T1506
Test name
Test status
Simulation time 816198527 ps
CPU time 5.9 seconds
Started Aug 12 04:44:38 PM PDT 24
Finished Aug 12 04:44:44 PM PDT 24
Peak memory 230072 kb
Host smart-03ef91c6-173c-45db-8c67-30e8c2b3e4ae
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=576269983 -assert nopostproc +UVM_TESTNAME=i2c_base
_test +UVM_TEST_SEQ=i2c_target_perf_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -
cm_name 32.i2c_target_perf.576269983
Directory /workspace/32.i2c_target_perf/latest

Test location /workspace/coverage/default/32.i2c_target_smbus_maxlen.3565711839
Short name T615
Test name
Test status
Simulation time 2439420195 ps
CPU time 2.21 seconds
Started Aug 12 04:44:38 PM PDT 24
Finished Aug 12 04:44:40 PM PDT 24
Peak memory 205292 kb
Host smart-8b0325e2-1214-4614-bf70-9956dade0117
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3565711839 -assert nopostproc +UVM_TESTNAME=i2c_bas
e_test +UVM_TEST_SEQ=i2c_target_smbus_maxlen_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /d
ev/null -cm_name 32.i2c_target_smbus_maxlen.3565711839
Directory /workspace/32.i2c_target_smbus_maxlen/latest

Test location /workspace/coverage/default/32.i2c_target_smoke.3974688644
Short name T1401
Test name
Test status
Simulation time 1471472139 ps
CPU time 42.81 seconds
Started Aug 12 04:44:36 PM PDT 24
Finished Aug 12 04:45:19 PM PDT 24
Peak memory 213700 kb
Host smart-b49e48e8-3779-4c6a-9d33-2716043e0ee0
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=100_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licq
ueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3974688644 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SE
Q=i2c_target_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.i2c_ta
rget_smoke.3974688644
Directory /workspace/32.i2c_target_smoke/latest

Test location /workspace/coverage/default/32.i2c_target_stress_all.4097149673
Short name T1140
Test name
Test status
Simulation time 60835771322 ps
CPU time 319 seconds
Started Aug 12 04:44:36 PM PDT 24
Finished Aug 12 04:49:56 PM PDT 24
Peak memory 1591128 kb
Host smart-71052b41-9f19-41d0-a64a-547115d3aeff
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=300_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VER
BOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4097149673 -assert nopostproc +UVM_TESTNAME=i2c_ba
se_test +UVM_TEST_SEQ=i2c_target_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /de
v/null -cm_name 32.i2c_target_stress_all.4097149673
Directory /workspace/32.i2c_target_stress_all/latest

Test location /workspace/coverage/default/32.i2c_target_stress_rd.1107025230
Short name T1719
Test name
Test status
Simulation time 10696075274 ps
CPU time 26.4 seconds
Started Aug 12 04:44:35 PM PDT 24
Finished Aug 12 04:45:02 PM PDT 24
Peak memory 222416 kb
Host smart-ea575036-fa27-48ca-b319-1d0785ed6747
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=100_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licq
ueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1107025230 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SE
Q=i2c_target_stress_rd_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.i2
c_target_stress_rd.1107025230
Directory /workspace/32.i2c_target_stress_rd/latest

Test location /workspace/coverage/default/32.i2c_target_stress_wr.3834647297
Short name T173
Test name
Test status
Simulation time 12134398252 ps
CPU time 7.84 seconds
Started Aug 12 04:44:33 PM PDT 24
Finished Aug 12 04:44:41 PM PDT 24
Peak memory 205520 kb
Host smart-1cb79f87-0afe-4006-9dfa-2edbe01a62dd
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=600_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licq
ueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3834647297 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SE
Q=i2c_target_stress_wr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.i2
c_target_stress_wr.3834647297
Directory /workspace/32.i2c_target_stress_wr/latest

Test location /workspace/coverage/default/32.i2c_target_stretch.758378671
Short name T1658
Test name
Test status
Simulation time 1267956083 ps
CPU time 21.07 seconds
Started Aug 12 04:44:36 PM PDT 24
Finished Aug 12 04:44:57 PM PDT 24
Peak memory 462688 kb
Host smart-93880019-b4b8-41ec-a448-ea817f3d5503
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=400_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licq
ueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=758378671 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ
=i2c_target_stretch_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.i2c_t
arget_stretch.758378671
Directory /workspace/32.i2c_target_stretch/latest

Test location /workspace/coverage/default/32.i2c_target_timeout.2831704449
Short name T323
Test name
Test status
Simulation time 2269863179 ps
CPU time 7.03 seconds
Started Aug 12 04:44:34 PM PDT 24
Finished Aug 12 04:44:41 PM PDT 24
Peak memory 221868 kb
Host smart-da1dfc8c-be05-43b3-80e3-184579b0d77e
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=50_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2831704449 -assert nopostproc +UVM_TESTNAME=i2c_bas
e_test +UVM_TEST_SEQ=i2c_target_timeout_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/nu
ll -cm_name 32.i2c_target_timeout.2831704449
Directory /workspace/32.i2c_target_timeout/latest

Test location /workspace/coverage/default/32.i2c_target_tx_stretch_ctrl.1588428235
Short name T1208
Test name
Test status
Simulation time 82155325 ps
CPU time 2.04 seconds
Started Aug 12 04:44:38 PM PDT 24
Finished Aug 12 04:44:40 PM PDT 24
Peak memory 205484 kb
Host smart-649dc18f-372f-499b-b3ab-08f22516890f
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1588428235 -assert nopostproc +UVM_TESTNAME=i2c_bas
e_test +UVM_TEST_SEQ=i2c_target_tx_stretch_ctrl_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log
/dev/null -cm_name 32.i2c_target_tx_stretch_ctrl.1588428235
Directory /workspace/32.i2c_target_tx_stretch_ctrl/latest

Test location /workspace/coverage/default/33.i2c_alert_test.2016212939
Short name T1352
Test name
Test status
Simulation time 41490289 ps
CPU time 0.65 seconds
Started Aug 12 04:44:52 PM PDT 24
Finished Aug 12 04:44:53 PM PDT 24
Peak memory 204408 kb
Host smart-0fb04816-395a-4111-89f8-722d2ab5c22c
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2016212939 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_common_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.i2c_alert_test.2016212939
Directory /workspace/33.i2c_alert_test/latest

Test location /workspace/coverage/default/33.i2c_host_error_intr.4272125567
Short name T793
Test name
Test status
Simulation time 974505919 ps
CPU time 8.14 seconds
Started Aug 12 04:44:43 PM PDT 24
Finished Aug 12 04:44:52 PM PDT 24
Peak memory 238092 kb
Host smart-efeacc08-3805-44e7-9658-ec31334501d7
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4272125567 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_error_intr_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.i2c_host_error_intr.4272125567
Directory /workspace/33.i2c_host_error_intr/latest

Test location /workspace/coverage/default/33.i2c_host_fifo_fmt_empty.3126471296
Short name T99
Test name
Test status
Simulation time 1552236877 ps
CPU time 14.49 seconds
Started Aug 12 04:44:43 PM PDT 24
Finished Aug 12 04:44:58 PM PDT 24
Peak memory 262892 kb
Host smart-9fb44b63-d414-408d-8602-08673c79d844
User root
Command /workspace/default/simv +test_timeout_ns=10_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3126471296 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_fifo_fmt_em
pty_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.i2c_host_fifo_fmt_emp
ty.3126471296
Directory /workspace/33.i2c_host_fifo_fmt_empty/latest

Test location /workspace/coverage/default/33.i2c_host_fifo_full.2446631096
Short name T679
Test name
Test status
Simulation time 2900190226 ps
CPU time 186.98 seconds
Started Aug 12 04:44:43 PM PDT 24
Finished Aug 12 04:47:51 PM PDT 24
Peak memory 543276 kb
Host smart-bf9c8086-4301-4754-9149-44ac90face70
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2446631096 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_fifo_full_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.i2c_host_fifo_full.2446631096
Directory /workspace/33.i2c_host_fifo_full/latest

Test location /workspace/coverage/default/33.i2c_host_fifo_overflow.3535528929
Short name T404
Test name
Test status
Simulation time 8241861041 ps
CPU time 84.93 seconds
Started Aug 12 04:44:44 PM PDT 24
Finished Aug 12 04:46:09 PM PDT 24
Peak memory 768668 kb
Host smart-3d0fcd9a-9aea-4ea2-b763-cd075e4bc8ee
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3535528929 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_fifo_overflow_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.i2c_host_fifo_overflow.3535528929
Directory /workspace/33.i2c_host_fifo_overflow/latest

Test location /workspace/coverage/default/33.i2c_host_fifo_reset_fmt.994350972
Short name T1391
Test name
Test status
Simulation time 556883610 ps
CPU time 1.04 seconds
Started Aug 12 04:44:45 PM PDT 24
Finished Aug 12 04:44:46 PM PDT 24
Peak memory 204972 kb
Host smart-d2ab6204-2d26-4c17-85bd-e6f50a7493c3
User root
Command /workspace/default/simv +test_timeout_ns=10_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=994350972 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_fifo_reset_f
mt_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.i2c_host_fifo_reset_fm
t.994350972
Directory /workspace/33.i2c_host_fifo_reset_fmt/latest

Test location /workspace/coverage/default/33.i2c_host_fifo_reset_rx.2062740057
Short name T632
Test name
Test status
Simulation time 160379323 ps
CPU time 8.54 seconds
Started Aug 12 04:44:45 PM PDT 24
Finished Aug 12 04:44:54 PM PDT 24
Peak memory 232992 kb
Host smart-11b7ebd4-63da-4339-b10b-b9e39890b8a7
User root
Command /workspace/default/simv +test_timeout_ns=10_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2062740057 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_fifo_reset_
rx_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.i2c_host_fifo_reset_rx
.2062740057
Directory /workspace/33.i2c_host_fifo_reset_rx/latest

Test location /workspace/coverage/default/33.i2c_host_fifo_watermark.1997399885
Short name T123
Test name
Test status
Simulation time 3118562114 ps
CPU time 66.26 seconds
Started Aug 12 04:44:44 PM PDT 24
Finished Aug 12 04:45:51 PM PDT 24
Peak memory 957012 kb
Host smart-4c98def5-d7c5-4e97-87be-1f485d127803
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1997399885 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_fifo_watermark_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.i2c_host_fifo_watermark.1997399885
Directory /workspace/33.i2c_host_fifo_watermark/latest

Test location /workspace/coverage/default/33.i2c_host_override.806660668
Short name T152
Test name
Test status
Simulation time 20561494 ps
CPU time 0.72 seconds
Started Aug 12 04:44:43 PM PDT 24
Finished Aug 12 04:44:44 PM PDT 24
Peak memory 204920 kb
Host smart-ce0a30f6-4d49-4a7d-a60b-377e2e9ff33d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=806660668 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_override_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.i2c_host_override.806660668
Directory /workspace/33.i2c_host_override/latest

Test location /workspace/coverage/default/33.i2c_host_perf.3191886883
Short name T1188
Test name
Test status
Simulation time 6944165941 ps
CPU time 87.08 seconds
Started Aug 12 04:44:43 PM PDT 24
Finished Aug 12 04:46:10 PM PDT 24
Peak memory 566844 kb
Host smart-73974956-c44d-4841-91ad-ed0b6101aaf5
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3191886883 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_perf_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.i2c_host_perf.3191886883
Directory /workspace/33.i2c_host_perf/latest

Test location /workspace/coverage/default/33.i2c_host_perf_precise.2403672226
Short name T652
Test name
Test status
Simulation time 91268036 ps
CPU time 1.66 seconds
Started Aug 12 04:44:47 PM PDT 24
Finished Aug 12 04:44:49 PM PDT 24
Peak memory 205940 kb
Host smart-282a6295-c050-46a3-9601-1a1086d45edb
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2403672226 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_perf_precise_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.i2c_host_perf_precise.2403672226
Directory /workspace/33.i2c_host_perf_precise/latest

Test location /workspace/coverage/default/33.i2c_host_smoke.1368868717
Short name T610
Test name
Test status
Simulation time 26341644846 ps
CPU time 94.77 seconds
Started Aug 12 04:44:43 PM PDT 24
Finished Aug 12 04:46:18 PM PDT 24
Peak memory 376580 kb
Host smart-4c9ec9b3-377c-46d9-b5af-519d7512df3b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1368868717 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_smoke_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.i2c_host_smoke.1368868717
Directory /workspace/33.i2c_host_smoke/latest

Test location /workspace/coverage/default/33.i2c_host_stretch_timeout.98846991
Short name T313
Test name
Test status
Simulation time 988990975 ps
CPU time 14.48 seconds
Started Aug 12 04:44:45 PM PDT 24
Finished Aug 12 04:45:00 PM PDT 24
Peak memory 229644 kb
Host smart-3d5a5d31-72cc-456b-804d-a82e621b59c7
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=98846991 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_stretch_timeout_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.i2c_host_stretch_timeout.98846991
Directory /workspace/33.i2c_host_stretch_timeout/latest

Test location /workspace/coverage/default/33.i2c_target_bad_addr.233920767
Short name T1565
Test name
Test status
Simulation time 1391203282 ps
CPU time 4.93 seconds
Started Aug 12 04:44:44 PM PDT 24
Finished Aug 12 04:44:49 PM PDT 24
Peak memory 209616 kb
Host smart-6fcd0bff-a4d2-4a3c-b19d-d5d50d27aca3
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +i2c_bad_addr_pct=50 +cdc_instrumentation_enabled=1 +UVM_
NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=233920767 -assert nopostproc +
UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_target_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.v
db -cm_log /dev/null -cm_name 33.i2c_target_bad_addr.233920767
Directory /workspace/33.i2c_target_bad_addr/latest

Test location /workspace/coverage/default/33.i2c_target_fifo_reset_acq.3644708166
Short name T348
Test name
Test status
Simulation time 1076628300 ps
CPU time 1.61 seconds
Started Aug 12 04:44:42 PM PDT 24
Finished Aug 12 04:44:44 PM PDT 24
Peak memory 205480 kb
Host smart-f74dc0e4-78f7-4def-8393-60fdbdd19e84
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3644708166 -assert nopostproc +UVM_TESTNAME=i2c_bas
e_test +UVM_TEST_SEQ=i2c_target_fifo_reset_acq_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log
/dev/null -cm_name 33.i2c_target_fifo_reset_acq.3644708166
Directory /workspace/33.i2c_target_fifo_reset_acq/latest

Test location /workspace/coverage/default/33.i2c_target_fifo_reset_tx.4003819787
Short name T1072
Test name
Test status
Simulation time 639422028 ps
CPU time 0.92 seconds
Started Aug 12 04:44:42 PM PDT 24
Finished Aug 12 04:44:43 PM PDT 24
Peak memory 205372 kb
Host smart-6f802665-533a-4c6e-9fca-e52866249ea2
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4003819787 -assert nopostproc +UVM_TESTNAME=i2c_bas
e_test +UVM_TEST_SEQ=i2c_target_fifo_reset_tx_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /
dev/null -cm_name 33.i2c_target_fifo_reset_tx.4003819787
Directory /workspace/33.i2c_target_fifo_reset_tx/latest

Test location /workspace/coverage/default/33.i2c_target_fifo_watermarks_acq.3094828512
Short name T1449
Test name
Test status
Simulation time 7378618951 ps
CPU time 2.88 seconds
Started Aug 12 04:44:42 PM PDT 24
Finished Aug 12 04:44:45 PM PDT 24
Peak memory 205496 kb
Host smart-36a2b943-78cb-495c-9168-cc206988f71f
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3094828512 -assert nopostproc +UVM_TESTNAME=i2c_bas
e_test +UVM_TEST_SEQ=i2c_target_fifo_watermarks_acq_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm
_log /dev/null -cm_name 33.i2c_target_fifo_watermarks_acq.3094828512
Directory /workspace/33.i2c_target_fifo_watermarks_acq/latest

Test location /workspace/coverage/default/33.i2c_target_fifo_watermarks_tx.4186870577
Short name T775
Test name
Test status
Simulation time 69285978 ps
CPU time 0.88 seconds
Started Aug 12 04:44:43 PM PDT 24
Finished Aug 12 04:44:44 PM PDT 24
Peak memory 205296 kb
Host smart-1f8404de-dfe4-4726-bb76-2bc6f78d0afa
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4186870577 -assert nopostproc +UVM_TESTNAME=i2c_bas
e_test +UVM_TEST_SEQ=i2c_target_fifo_watermarks_tx_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_
log /dev/null -cm_name 33.i2c_target_fifo_watermarks_tx.4186870577
Directory /workspace/33.i2c_target_fifo_watermarks_tx/latest

Test location /workspace/coverage/default/33.i2c_target_hrst.1093352037
Short name T185
Test name
Test status
Simulation time 696972985 ps
CPU time 2.32 seconds
Started Aug 12 04:44:43 PM PDT 24
Finished Aug 12 04:44:46 PM PDT 24
Peak memory 213748 kb
Host smart-1ce75d3a-c09f-4af3-a325-63714bdc9cca
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1093352037 -assert nopostproc +UVM_TESTNAME=i2c_bas
e_test +UVM_TEST_SEQ=i2c_target_hrst_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null
-cm_name 33.i2c_target_hrst.1093352037
Directory /workspace/33.i2c_target_hrst/latest

Test location /workspace/coverage/default/33.i2c_target_intr_smoke.2537197932
Short name T420
Test name
Test status
Simulation time 1368659012 ps
CPU time 7.2 seconds
Started Aug 12 04:44:48 PM PDT 24
Finished Aug 12 04:44:55 PM PDT 24
Peak memory 213692 kb
Host smart-03441bfb-0899-47c1-a0b8-080e09385ee9
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=200_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VER
BOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2537197932 -assert nopostproc +UVM_TESTNAME=i2c_ba
se_test +UVM_TEST_SEQ=i2c_target_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/nul
l -cm_name 33.i2c_target_intr_smoke.2537197932
Directory /workspace/33.i2c_target_intr_smoke/latest

Test location /workspace/coverage/default/33.i2c_target_intr_stress_wr.2114651100
Short name T1715
Test name
Test status
Simulation time 29177325083 ps
CPU time 44.43 seconds
Started Aug 12 04:44:44 PM PDT 24
Finished Aug 12 04:45:29 PM PDT 24
Peak memory 909024 kb
Host smart-7e34ee45-fc33-4f55-aa9a-ef5ba3289446
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=600_000_000 +use_intr_handler=1 +slow_acq=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNO
TES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2114651100 -assert nopostproc +UVM_TES
TNAME=i2c_base_test +UVM_TEST_SEQ=i2c_target_stress_wr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb
-cm_log /dev/null -cm_name 33.i2c_target_intr_stress_wr.2114651100
Directory /workspace/33.i2c_target_intr_stress_wr/latest

Test location /workspace/coverage/default/33.i2c_target_nack_acqfull.1274330177
Short name T68
Test name
Test status
Simulation time 473089402 ps
CPU time 3.04 seconds
Started Aug 12 04:44:51 PM PDT 24
Finished Aug 12 04:44:54 PM PDT 24
Peak memory 213740 kb
Host smart-4eecfe62-2142-40dd-a87e-5e3af307d941
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1274330177 -assert nopostproc +UVM_TESTNAME=i2c_bas
e_test +UVM_TEST_SEQ=i2c_target_nack_acqfull_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /d
ev/null -cm_name 33.i2c_target_nack_acqfull.1274330177
Directory /workspace/33.i2c_target_nack_acqfull/latest

Test location /workspace/coverage/default/33.i2c_target_nack_acqfull_addr.2792798774
Short name T846
Test name
Test status
Simulation time 2114385299 ps
CPU time 2.36 seconds
Started Aug 12 04:44:51 PM PDT 24
Finished Aug 12 04:44:54 PM PDT 24
Peak memory 205468 kb
Host smart-d3032110-909c-4d03-afb5-a748e4d2ed58
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2792798774 -assert nopostproc +UVM_TESTNAME=i2c_bas
e_test +UVM_TEST_SEQ=i2c_target_nack_acqfull_addr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_l
og /dev/null -cm_name 33.i2c_target_nack_acqfull_addr.2792798774
Directory /workspace/33.i2c_target_nack_acqfull_addr/latest

Test location /workspace/coverage/default/33.i2c_target_perf.3282745824
Short name T1322
Test name
Test status
Simulation time 800716864 ps
CPU time 5.8 seconds
Started Aug 12 04:44:44 PM PDT 24
Finished Aug 12 04:44:50 PM PDT 24
Peak memory 217080 kb
Host smart-e0be9a1b-3f5a-409a-a5a8-d80eb5560f3f
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3282745824 -assert nopostproc +UVM_TESTNAME=i2c_bas
e_test +UVM_TEST_SEQ=i2c_target_perf_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null
-cm_name 33.i2c_target_perf.3282745824
Directory /workspace/33.i2c_target_perf/latest

Test location /workspace/coverage/default/33.i2c_target_smbus_maxlen.3583761247
Short name T758
Test name
Test status
Simulation time 2435098652 ps
CPU time 2.19 seconds
Started Aug 12 04:44:42 PM PDT 24
Finished Aug 12 04:44:45 PM PDT 24
Peak memory 205292 kb
Host smart-1ba747f2-1a84-4179-9e36-bddae58486e2
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3583761247 -assert nopostproc +UVM_TESTNAME=i2c_bas
e_test +UVM_TEST_SEQ=i2c_target_smbus_maxlen_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /d
ev/null -cm_name 33.i2c_target_smbus_maxlen.3583761247
Directory /workspace/33.i2c_target_smbus_maxlen/latest

Test location /workspace/coverage/default/33.i2c_target_smoke.198499307
Short name T923
Test name
Test status
Simulation time 4281846603 ps
CPU time 15.73 seconds
Started Aug 12 04:44:47 PM PDT 24
Finished Aug 12 04:45:03 PM PDT 24
Peak memory 213820 kb
Host smart-40c50ed3-a5e1-49d1-9d18-fd318ef7d2f9
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=100_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licq
ueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=198499307 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ
=i2c_target_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.i2c_tar
get_smoke.198499307
Directory /workspace/33.i2c_target_smoke/latest

Test location /workspace/coverage/default/33.i2c_target_stress_all.3259510551
Short name T1216
Test name
Test status
Simulation time 43105049683 ps
CPU time 814.23 seconds
Started Aug 12 04:44:41 PM PDT 24
Finished Aug 12 04:58:15 PM PDT 24
Peak memory 4158640 kb
Host smart-0e4b43ac-41a8-4d28-9ba6-27bc1d322980
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=300_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VER
BOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3259510551 -assert nopostproc +UVM_TESTNAME=i2c_ba
se_test +UVM_TEST_SEQ=i2c_target_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /de
v/null -cm_name 33.i2c_target_stress_all.3259510551
Directory /workspace/33.i2c_target_stress_all/latest

Test location /workspace/coverage/default/33.i2c_target_stress_rd.433598054
Short name T1562
Test name
Test status
Simulation time 1510329905 ps
CPU time 61.25 seconds
Started Aug 12 04:44:42 PM PDT 24
Finished Aug 12 04:45:44 PM PDT 24
Peak memory 218180 kb
Host smart-7505e642-2ed2-44b7-a39c-5ffef8819003
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=100_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licq
ueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=433598054 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ
=i2c_target_stress_rd_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.i2c
_target_stress_rd.433598054
Directory /workspace/33.i2c_target_stress_rd/latest

Test location /workspace/coverage/default/33.i2c_target_stress_wr.2903997231
Short name T494
Test name
Test status
Simulation time 16474877322 ps
CPU time 24.79 seconds
Started Aug 12 04:44:43 PM PDT 24
Finished Aug 12 04:45:08 PM PDT 24
Peak memory 205540 kb
Host smart-c01c2c8d-888c-4cdb-9b34-5be906cf5a48
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=600_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licq
ueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2903997231 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SE
Q=i2c_target_stress_wr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.i2
c_target_stress_wr.2903997231
Directory /workspace/33.i2c_target_stress_wr/latest

Test location /workspace/coverage/default/33.i2c_target_timeout.4121221504
Short name T512
Test name
Test status
Simulation time 13154618845 ps
CPU time 6.82 seconds
Started Aug 12 04:44:46 PM PDT 24
Finished Aug 12 04:44:53 PM PDT 24
Peak memory 218392 kb
Host smart-d8156149-9fb2-4af5-8278-dbfceb96a81b
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=50_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4121221504 -assert nopostproc +UVM_TESTNAME=i2c_bas
e_test +UVM_TEST_SEQ=i2c_target_timeout_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/nu
ll -cm_name 33.i2c_target_timeout.4121221504
Directory /workspace/33.i2c_target_timeout/latest

Test location /workspace/coverage/default/33.i2c_target_tx_stretch_ctrl.3126210189
Short name T1017
Test name
Test status
Simulation time 77009370 ps
CPU time 1.74 seconds
Started Aug 12 04:44:43 PM PDT 24
Finished Aug 12 04:44:45 PM PDT 24
Peak memory 205476 kb
Host smart-f58a81a7-ea47-44c3-9320-e5c187ea5b06
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3126210189 -assert nopostproc +UVM_TESTNAME=i2c_bas
e_test +UVM_TEST_SEQ=i2c_target_tx_stretch_ctrl_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log
/dev/null -cm_name 33.i2c_target_tx_stretch_ctrl.3126210189
Directory /workspace/33.i2c_target_tx_stretch_ctrl/latest

Test location /workspace/coverage/default/34.i2c_alert_test.3601463010
Short name T934
Test name
Test status
Simulation time 30429763 ps
CPU time 0.63 seconds
Started Aug 12 04:45:02 PM PDT 24
Finished Aug 12 04:45:03 PM PDT 24
Peak memory 204428 kb
Host smart-98b86070-9d66-4cd7-b66e-a59faba041c8
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3601463010 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_common_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.i2c_alert_test.3601463010
Directory /workspace/34.i2c_alert_test/latest

Test location /workspace/coverage/default/34.i2c_host_error_intr.559869750
Short name T723
Test name
Test status
Simulation time 1159198056 ps
CPU time 4.73 seconds
Started Aug 12 04:44:51 PM PDT 24
Finished Aug 12 04:44:56 PM PDT 24
Peak memory 265680 kb
Host smart-273aa22d-de94-4c3b-b0a4-db0531698140
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=559869750 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_error_intr_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.i2c_host_error_intr.559869750
Directory /workspace/34.i2c_host_error_intr/latest

Test location /workspace/coverage/default/34.i2c_host_fifo_fmt_empty.1315139919
Short name T936
Test name
Test status
Simulation time 547019808 ps
CPU time 5.44 seconds
Started Aug 12 04:44:55 PM PDT 24
Finished Aug 12 04:45:01 PM PDT 24
Peak memory 260336 kb
Host smart-725f5d3c-caee-42f9-9652-145ba1f3073a
User root
Command /workspace/default/simv +test_timeout_ns=10_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1315139919 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_fifo_fmt_em
pty_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.i2c_host_fifo_fmt_emp
ty.1315139919
Directory /workspace/34.i2c_host_fifo_fmt_empty/latest

Test location /workspace/coverage/default/34.i2c_host_fifo_full.188050919
Short name T786
Test name
Test status
Simulation time 4386755727 ps
CPU time 54.12 seconds
Started Aug 12 04:44:52 PM PDT 24
Finished Aug 12 04:45:46 PM PDT 24
Peak memory 386456 kb
Host smart-4add5047-b450-44d0-90bc-ea07d7322655
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=188050919 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_fifo_full_vseq +en_cov=1 -cm line+cond+f
sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.i2c_host_fifo_full.188050919
Directory /workspace/34.i2c_host_fifo_full/latest

Test location /workspace/coverage/default/34.i2c_host_fifo_overflow.715345411
Short name T596
Test name
Test status
Simulation time 1519334157 ps
CPU time 48.55 seconds
Started Aug 12 04:44:52 PM PDT 24
Finished Aug 12 04:45:41 PM PDT 24
Peak memory 581092 kb
Host smart-1669dd0d-ec44-420a-be00-44fcbb2bfa7e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=715345411 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_fifo_overflow_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.i2c_host_fifo_overflow.715345411
Directory /workspace/34.i2c_host_fifo_overflow/latest

Test location /workspace/coverage/default/34.i2c_host_fifo_reset_fmt.821248702
Short name T1560
Test name
Test status
Simulation time 289893726 ps
CPU time 1.22 seconds
Started Aug 12 04:44:51 PM PDT 24
Finished Aug 12 04:44:53 PM PDT 24
Peak memory 205220 kb
Host smart-c2fe7c53-fa1f-4839-9564-fd43a795567a
User root
Command /workspace/default/simv +test_timeout_ns=10_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=821248702 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_fifo_reset_f
mt_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.i2c_host_fifo_reset_fm
t.821248702
Directory /workspace/34.i2c_host_fifo_reset_fmt/latest

Test location /workspace/coverage/default/34.i2c_host_fifo_reset_rx.4015686081
Short name T471
Test name
Test status
Simulation time 1418838812 ps
CPU time 7.59 seconds
Started Aug 12 04:44:52 PM PDT 24
Finished Aug 12 04:44:59 PM PDT 24
Peak memory 205188 kb
Host smart-4a76b170-aaf0-4cfa-a499-29a65d1f2993
User root
Command /workspace/default/simv +test_timeout_ns=10_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4015686081 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_fifo_reset_
rx_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.i2c_host_fifo_reset_rx
.4015686081
Directory /workspace/34.i2c_host_fifo_reset_rx/latest

Test location /workspace/coverage/default/34.i2c_host_fifo_watermark.1156146870
Short name T119
Test name
Test status
Simulation time 9306269327 ps
CPU time 105.47 seconds
Started Aug 12 04:44:51 PM PDT 24
Finished Aug 12 04:46:36 PM PDT 24
Peak memory 1280048 kb
Host smart-a5f82289-bc2a-4846-a2d5-1ade578ebc27
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1156146870 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_fifo_watermark_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.i2c_host_fifo_watermark.1156146870
Directory /workspace/34.i2c_host_fifo_watermark/latest

Test location /workspace/coverage/default/34.i2c_host_may_nack.450498807
Short name T1461
Test name
Test status
Simulation time 472949383 ps
CPU time 7.93 seconds
Started Aug 12 04:44:58 PM PDT 24
Finished Aug 12 04:45:06 PM PDT 24
Peak memory 205300 kb
Host smart-ce415af0-0428-4094-905f-4b5f1e2b4676
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=450498807 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_may_nack_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.i2c_host_may_nack.450498807
Directory /workspace/34.i2c_host_may_nack/latest

Test location /workspace/coverage/default/34.i2c_host_override.2121414926
Short name T1664
Test name
Test status
Simulation time 29555652 ps
CPU time 0.71 seconds
Started Aug 12 04:44:49 PM PDT 24
Finished Aug 12 04:44:50 PM PDT 24
Peak memory 204900 kb
Host smart-b9dda461-b941-4fb2-a15f-e2b517544ee3
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2121414926 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_override_vseq +en_cov=1 -cm line+cond+f
sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.i2c_host_override.2121414926
Directory /workspace/34.i2c_host_override/latest

Test location /workspace/coverage/default/34.i2c_host_perf.3713196872
Short name T1675
Test name
Test status
Simulation time 4919859134 ps
CPU time 39.38 seconds
Started Aug 12 04:44:49 PM PDT 24
Finished Aug 12 04:45:28 PM PDT 24
Peak memory 494016 kb
Host smart-64da2779-fca2-4111-93a0-685292f25093
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3713196872 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_perf_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.i2c_host_perf.3713196872
Directory /workspace/34.i2c_host_perf/latest

Test location /workspace/coverage/default/34.i2c_host_perf_precise.4264659263
Short name T474
Test name
Test status
Simulation time 175847566 ps
CPU time 7.41 seconds
Started Aug 12 04:44:55 PM PDT 24
Finished Aug 12 04:45:03 PM PDT 24
Peak memory 227484 kb
Host smart-95a4c4b3-f3be-4132-afea-e22bfec9a5bc
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4264659263 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_perf_precise_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.i2c_host_perf_precise.4264659263
Directory /workspace/34.i2c_host_perf_precise/latest

Test location /workspace/coverage/default/34.i2c_host_smoke.968243996
Short name T1185
Test name
Test status
Simulation time 5220316957 ps
CPU time 19.9 seconds
Started Aug 12 04:44:51 PM PDT 24
Finished Aug 12 04:45:11 PM PDT 24
Peak memory 326988 kb
Host smart-e5581096-0ff2-4926-b91c-30e07af631ca
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=968243996 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_smoke_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.i2c_host_smoke.968243996
Directory /workspace/34.i2c_host_smoke/latest

Test location /workspace/coverage/default/34.i2c_host_stress_all.15101934
Short name T136
Test name
Test status
Simulation time 46061520162 ps
CPU time 1008.33 seconds
Started Aug 12 04:44:51 PM PDT 24
Finished Aug 12 05:01:40 PM PDT 24
Peak memory 2715652 kb
Host smart-b72d8018-1910-49ed-b5ba-a5c9845f249e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=15101934 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_stress_all_vseq +en_cov=1 -cm line+cond+f
sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.i2c_host_stress_all.15101934
Directory /workspace/34.i2c_host_stress_all/latest

Test location /workspace/coverage/default/34.i2c_host_stretch_timeout.3310393562
Short name T1288
Test name
Test status
Simulation time 553357256 ps
CPU time 24.87 seconds
Started Aug 12 04:44:55 PM PDT 24
Finished Aug 12 04:45:21 PM PDT 24
Peak memory 213292 kb
Host smart-237ebf06-d6b0-4bca-a853-da435113d77d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3310393562 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_stretch_timeout_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.i2c_host_stretch_timeout.3310393562
Directory /workspace/34.i2c_host_stretch_timeout/latest

Test location /workspace/coverage/default/34.i2c_target_bad_addr.2358006360
Short name T395
Test name
Test status
Simulation time 1649916464 ps
CPU time 5.23 seconds
Started Aug 12 04:44:51 PM PDT 24
Finished Aug 12 04:44:56 PM PDT 24
Peak memory 213680 kb
Host smart-3193970d-be4e-4f78-a2bf-45f233fc838d
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +i2c_bad_addr_pct=50 +cdc_instrumentation_enabled=1 +UVM_
NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2358006360 -assert nopostproc
+UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_target_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.
vdb -cm_log /dev/null -cm_name 34.i2c_target_bad_addr.2358006360
Directory /workspace/34.i2c_target_bad_addr/latest

Test location /workspace/coverage/default/34.i2c_target_fifo_reset_acq.2212649646
Short name T389
Test name
Test status
Simulation time 259646322 ps
CPU time 1.56 seconds
Started Aug 12 04:44:52 PM PDT 24
Finished Aug 12 04:44:53 PM PDT 24
Peak memory 205440 kb
Host smart-adefb6bf-4e67-44b4-81e4-52f76ffecc84
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2212649646 -assert nopostproc +UVM_TESTNAME=i2c_bas
e_test +UVM_TEST_SEQ=i2c_target_fifo_reset_acq_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log
/dev/null -cm_name 34.i2c_target_fifo_reset_acq.2212649646
Directory /workspace/34.i2c_target_fifo_reset_acq/latest

Test location /workspace/coverage/default/34.i2c_target_fifo_reset_tx.954009417
Short name T734
Test name
Test status
Simulation time 355728218 ps
CPU time 1.3 seconds
Started Aug 12 04:44:52 PM PDT 24
Finished Aug 12 04:44:53 PM PDT 24
Peak memory 206252 kb
Host smart-abfba1af-d677-4c2f-b10f-72ce4d9c3ef1
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=954009417 -assert nopostproc +UVM_TESTNAME=i2c_base
_test +UVM_TEST_SEQ=i2c_target_fifo_reset_tx_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /d
ev/null -cm_name 34.i2c_target_fifo_reset_tx.954009417
Directory /workspace/34.i2c_target_fifo_reset_tx/latest

Test location /workspace/coverage/default/34.i2c_target_fifo_watermarks_acq.305542447
Short name T1230
Test name
Test status
Simulation time 360077650 ps
CPU time 2.43 seconds
Started Aug 12 04:44:59 PM PDT 24
Finished Aug 12 04:45:02 PM PDT 24
Peak memory 205568 kb
Host smart-fd1bb37b-d500-41bb-a2e0-d98362e80277
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=305542447 -assert nopostproc +UVM_TESTNAME=i2c_base
_test +UVM_TEST_SEQ=i2c_target_fifo_watermarks_acq_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_
log /dev/null -cm_name 34.i2c_target_fifo_watermarks_acq.305542447
Directory /workspace/34.i2c_target_fifo_watermarks_acq/latest

Test location /workspace/coverage/default/34.i2c_target_fifo_watermarks_tx.3760955862
Short name T822
Test name
Test status
Simulation time 132069289 ps
CPU time 1.39 seconds
Started Aug 12 04:44:59 PM PDT 24
Finished Aug 12 04:45:01 PM PDT 24
Peak memory 205288 kb
Host smart-faab8f0e-e417-4bcb-9d1f-d2b6643b3432
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3760955862 -assert nopostproc +UVM_TESTNAME=i2c_bas
e_test +UVM_TEST_SEQ=i2c_target_fifo_watermarks_tx_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_
log /dev/null -cm_name 34.i2c_target_fifo_watermarks_tx.3760955862
Directory /workspace/34.i2c_target_fifo_watermarks_tx/latest

Test location /workspace/coverage/default/34.i2c_target_intr_smoke.2469666372
Short name T749
Test name
Test status
Simulation time 5737825084 ps
CPU time 6.68 seconds
Started Aug 12 04:44:50 PM PDT 24
Finished Aug 12 04:44:57 PM PDT 24
Peak memory 221828 kb
Host smart-05c9bb01-9499-4698-b823-c9926316d5f9
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=200_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VER
BOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2469666372 -assert nopostproc +UVM_TESTNAME=i2c_ba
se_test +UVM_TEST_SEQ=i2c_target_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/nul
l -cm_name 34.i2c_target_intr_smoke.2469666372
Directory /workspace/34.i2c_target_intr_smoke/latest

Test location /workspace/coverage/default/34.i2c_target_intr_stress_wr.1523124573
Short name T691
Test name
Test status
Simulation time 4165693738 ps
CPU time 9.02 seconds
Started Aug 12 04:44:49 PM PDT 24
Finished Aug 12 04:44:58 PM PDT 24
Peak memory 205424 kb
Host smart-4e27892d-ab1e-46ce-b4b4-c1ec86a6b10f
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=600_000_000 +use_intr_handler=1 +slow_acq=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNO
TES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1523124573 -assert nopostproc +UVM_TES
TNAME=i2c_base_test +UVM_TEST_SEQ=i2c_target_stress_wr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb
-cm_log /dev/null -cm_name 34.i2c_target_intr_stress_wr.1523124573
Directory /workspace/34.i2c_target_intr_stress_wr/latest

Test location /workspace/coverage/default/34.i2c_target_nack_acqfull.1831438491
Short name T737
Test name
Test status
Simulation time 398514513 ps
CPU time 2.69 seconds
Started Aug 12 04:44:57 PM PDT 24
Finished Aug 12 04:45:00 PM PDT 24
Peak memory 213712 kb
Host smart-d3ea8b7f-f6cd-4ddb-93bf-6d4e4f40fd85
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1831438491 -assert nopostproc +UVM_TESTNAME=i2c_bas
e_test +UVM_TEST_SEQ=i2c_target_nack_acqfull_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /d
ev/null -cm_name 34.i2c_target_nack_acqfull.1831438491
Directory /workspace/34.i2c_target_nack_acqfull/latest

Test location /workspace/coverage/default/34.i2c_target_nack_acqfull_addr.3952656760
Short name T707
Test name
Test status
Simulation time 1029632667 ps
CPU time 2.53 seconds
Started Aug 12 04:44:59 PM PDT 24
Finished Aug 12 04:45:02 PM PDT 24
Peak memory 205508 kb
Host smart-90613137-11da-4d38-8c17-6a10e42f7b37
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3952656760 -assert nopostproc +UVM_TESTNAME=i2c_bas
e_test +UVM_TEST_SEQ=i2c_target_nack_acqfull_addr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_l
og /dev/null -cm_name 34.i2c_target_nack_acqfull_addr.3952656760
Directory /workspace/34.i2c_target_nack_acqfull_addr/latest

Test location /workspace/coverage/default/34.i2c_target_nack_txstretch.73189597
Short name T132
Test name
Test status
Simulation time 159192091 ps
CPU time 1.39 seconds
Started Aug 12 04:44:58 PM PDT 24
Finished Aug 12 04:45:00 PM PDT 24
Peak memory 222176 kb
Host smart-1440a342-94b7-4075-b650-f6f55ac43b1b
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=73189597 -assert nopostproc +UVM_TESTNAME=i2c_base_
test +UVM_TEST_SEQ=i2c_target_nack_txstretch_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /d
ev/null -cm_name 34.i2c_target_nack_txstretch.73189597
Directory /workspace/34.i2c_target_nack_txstretch/latest

Test location /workspace/coverage/default/34.i2c_target_perf.3630509594
Short name T893
Test name
Test status
Simulation time 626075258 ps
CPU time 4.2 seconds
Started Aug 12 04:44:50 PM PDT 24
Finished Aug 12 04:44:54 PM PDT 24
Peak memory 213640 kb
Host smart-1e9e45b4-ac67-4dbc-90c1-3e193585515e
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3630509594 -assert nopostproc +UVM_TESTNAME=i2c_bas
e_test +UVM_TEST_SEQ=i2c_target_perf_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null
-cm_name 34.i2c_target_perf.3630509594
Directory /workspace/34.i2c_target_perf/latest

Test location /workspace/coverage/default/34.i2c_target_smbus_maxlen.2826534888
Short name T1733
Test name
Test status
Simulation time 1868623027 ps
CPU time 2.25 seconds
Started Aug 12 04:44:58 PM PDT 24
Finished Aug 12 04:45:01 PM PDT 24
Peak memory 204620 kb
Host smart-5f4e8773-9059-4283-9652-4be59192bb11
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2826534888 -assert nopostproc +UVM_TESTNAME=i2c_bas
e_test +UVM_TEST_SEQ=i2c_target_smbus_maxlen_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /d
ev/null -cm_name 34.i2c_target_smbus_maxlen.2826534888
Directory /workspace/34.i2c_target_smbus_maxlen/latest

Test location /workspace/coverage/default/34.i2c_target_smoke.89091840
Short name T355
Test name
Test status
Simulation time 18423955380 ps
CPU time 43.12 seconds
Started Aug 12 04:44:51 PM PDT 24
Finished Aug 12 04:45:35 PM PDT 24
Peak memory 213828 kb
Host smart-d85d9289-bce0-4bdb-9989-1456e7d03327
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=100_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licq
ueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=89091840 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=
i2c_target_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.i2c_targ
et_smoke.89091840
Directory /workspace/34.i2c_target_smoke/latest

Test location /workspace/coverage/default/34.i2c_target_stress_all.2256744562
Short name T1553
Test name
Test status
Simulation time 31929196454 ps
CPU time 395.13 seconds
Started Aug 12 04:44:55 PM PDT 24
Finished Aug 12 04:51:31 PM PDT 24
Peak memory 2854900 kb
Host smart-ac0dee45-42f3-44a6-b7ad-bf356f433e43
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=300_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VER
BOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2256744562 -assert nopostproc +UVM_TESTNAME=i2c_ba
se_test +UVM_TEST_SEQ=i2c_target_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /de
v/null -cm_name 34.i2c_target_stress_all.2256744562
Directory /workspace/34.i2c_target_stress_all/latest

Test location /workspace/coverage/default/34.i2c_target_stress_rd.1533235495
Short name T1285
Test name
Test status
Simulation time 9444490900 ps
CPU time 23.86 seconds
Started Aug 12 04:44:51 PM PDT 24
Finished Aug 12 04:45:15 PM PDT 24
Peak memory 230108 kb
Host smart-48646f01-fe1a-45fc-bf95-ac3ffadc8c05
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=100_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licq
ueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1533235495 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SE
Q=i2c_target_stress_rd_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.i2
c_target_stress_rd.1533235495
Directory /workspace/34.i2c_target_stress_rd/latest

Test location /workspace/coverage/default/34.i2c_target_stress_wr.722491375
Short name T881
Test name
Test status
Simulation time 10818887898 ps
CPU time 6.21 seconds
Started Aug 12 04:44:50 PM PDT 24
Finished Aug 12 04:44:57 PM PDT 24
Peak memory 205592 kb
Host smart-0516719f-f359-450b-b475-eff45ce946fa
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=600_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licq
ueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=722491375 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ
=i2c_target_stress_wr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.i2c
_target_stress_wr.722491375
Directory /workspace/34.i2c_target_stress_wr/latest

Test location /workspace/coverage/default/34.i2c_target_timeout.3100277679
Short name T1569
Test name
Test status
Simulation time 1745305673 ps
CPU time 8.76 seconds
Started Aug 12 04:44:51 PM PDT 24
Finished Aug 12 04:45:00 PM PDT 24
Peak memory 230056 kb
Host smart-db52eb01-3f16-4cf9-bf0b-4d9b5f0cf7ff
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=50_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3100277679 -assert nopostproc +UVM_TESTNAME=i2c_bas
e_test +UVM_TEST_SEQ=i2c_target_timeout_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/nu
ll -cm_name 34.i2c_target_timeout.3100277679
Directory /workspace/34.i2c_target_timeout/latest

Test location /workspace/coverage/default/34.i2c_target_tx_stretch_ctrl.363608208
Short name T580
Test name
Test status
Simulation time 2001146507 ps
CPU time 22.58 seconds
Started Aug 12 04:45:02 PM PDT 24
Finished Aug 12 04:45:25 PM PDT 24
Peak memory 205548 kb
Host smart-94928473-f835-4b32-b65b-83bfaa240c31
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=363608208 -assert nopostproc +UVM_TESTNAME=i2c_base
_test +UVM_TEST_SEQ=i2c_target_tx_stretch_ctrl_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log
/dev/null -cm_name 34.i2c_target_tx_stretch_ctrl.363608208
Directory /workspace/34.i2c_target_tx_stretch_ctrl/latest

Test location /workspace/coverage/default/35.i2c_alert_test.356338000
Short name T1164
Test name
Test status
Simulation time 18922253 ps
CPU time 0.61 seconds
Started Aug 12 04:45:05 PM PDT 24
Finished Aug 12 04:45:05 PM PDT 24
Peak memory 204328 kb
Host smart-4075602f-a596-452c-9bfa-91bd8c0854e5
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=356338000 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_common_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.i2c_alert_test.356338000
Directory /workspace/35.i2c_alert_test/latest

Test location /workspace/coverage/default/35.i2c_host_error_intr.3997793101
Short name T792
Test name
Test status
Simulation time 175823335 ps
CPU time 1.72 seconds
Started Aug 12 04:44:57 PM PDT 24
Finished Aug 12 04:44:59 PM PDT 24
Peak memory 213472 kb
Host smart-d648ad3a-5ea5-4e49-88e3-0ee4cad49bf3
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3997793101 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_error_intr_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.i2c_host_error_intr.3997793101
Directory /workspace/35.i2c_host_error_intr/latest

Test location /workspace/coverage/default/35.i2c_host_fifo_fmt_empty.3529823195
Short name T711
Test name
Test status
Simulation time 456381889 ps
CPU time 8.01 seconds
Started Aug 12 04:44:58 PM PDT 24
Finished Aug 12 04:45:06 PM PDT 24
Peak memory 284996 kb
Host smart-b02b92de-52e0-4eee-9627-c0f8f7163c3f
User root
Command /workspace/default/simv +test_timeout_ns=10_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3529823195 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_fifo_fmt_em
pty_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.i2c_host_fifo_fmt_emp
ty.3529823195
Directory /workspace/35.i2c_host_fifo_fmt_empty/latest

Test location /workspace/coverage/default/35.i2c_host_fifo_full.4228699081
Short name T1485
Test name
Test status
Simulation time 6033997842 ps
CPU time 108.49 seconds
Started Aug 12 04:44:58 PM PDT 24
Finished Aug 12 04:46:47 PM PDT 24
Peak memory 711528 kb
Host smart-00f1fecb-07a7-4f8a-b265-7104943635c7
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4228699081 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_fifo_full_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.i2c_host_fifo_full.4228699081
Directory /workspace/35.i2c_host_fifo_full/latest

Test location /workspace/coverage/default/35.i2c_host_fifo_overflow.1616901727
Short name T1265
Test name
Test status
Simulation time 4795930631 ps
CPU time 181.52 seconds
Started Aug 12 04:45:04 PM PDT 24
Finished Aug 12 04:48:05 PM PDT 24
Peak memory 793172 kb
Host smart-0ad96192-7af0-4d35-b9aa-7cf8c037fb19
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1616901727 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_fifo_overflow_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.i2c_host_fifo_overflow.1616901727
Directory /workspace/35.i2c_host_fifo_overflow/latest

Test location /workspace/coverage/default/35.i2c_host_fifo_reset_fmt.1598671387
Short name T33
Test name
Test status
Simulation time 261817983 ps
CPU time 1.22 seconds
Started Aug 12 04:44:58 PM PDT 24
Finished Aug 12 04:45:00 PM PDT 24
Peak memory 204312 kb
Host smart-61f5d4f4-d3a1-4e16-a666-5fcf205137aa
User root
Command /workspace/default/simv +test_timeout_ns=10_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1598671387 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_fifo_reset_
fmt_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.i2c_host_fifo_reset_f
mt.1598671387
Directory /workspace/35.i2c_host_fifo_reset_fmt/latest

Test location /workspace/coverage/default/35.i2c_host_fifo_reset_rx.2504357286
Short name T498
Test name
Test status
Simulation time 100738714 ps
CPU time 2.49 seconds
Started Aug 12 04:44:58 PM PDT 24
Finished Aug 12 04:45:01 PM PDT 24
Peak memory 205216 kb
Host smart-30ab4415-7461-40e6-826b-ec596b17397f
User root
Command /workspace/default/simv +test_timeout_ns=10_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2504357286 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_fifo_reset_
rx_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.i2c_host_fifo_reset_rx
.2504357286
Directory /workspace/35.i2c_host_fifo_reset_rx/latest

Test location /workspace/coverage/default/35.i2c_host_fifo_watermark.992696053
Short name T533
Test name
Test status
Simulation time 43858671947 ps
CPU time 168.05 seconds
Started Aug 12 04:44:57 PM PDT 24
Finished Aug 12 04:47:45 PM PDT 24
Peak memory 1512208 kb
Host smart-87e52123-e9b5-4fdd-a5b8-66f657983f25
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=992696053 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_fifo_watermark_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.i2c_host_fifo_watermark.992696053
Directory /workspace/35.i2c_host_fifo_watermark/latest

Test location /workspace/coverage/default/35.i2c_host_may_nack.2203362938
Short name T263
Test name
Test status
Simulation time 1369011316 ps
CPU time 4.86 seconds
Started Aug 12 04:45:05 PM PDT 24
Finished Aug 12 04:45:09 PM PDT 24
Peak memory 205140 kb
Host smart-97979840-418f-497f-9b73-c11e93b11642
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2203362938 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_may_nack_vseq +en_cov=1 -cm line+cond+f
sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.i2c_host_may_nack.2203362938
Directory /workspace/35.i2c_host_may_nack/latest

Test location /workspace/coverage/default/35.i2c_host_mode_toggle.4054544189
Short name T77
Test name
Test status
Simulation time 162931566 ps
CPU time 4.82 seconds
Started Aug 12 04:45:04 PM PDT 24
Finished Aug 12 04:45:09 PM PDT 24
Peak memory 230240 kb
Host smart-310a6237-82ec-447b-a75c-51b7852774a6
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4054544189 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_mode_toggle_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.i2c_host_mode_toggle.4054544189
Directory /workspace/35.i2c_host_mode_toggle/latest

Test location /workspace/coverage/default/35.i2c_host_override.453705445
Short name T81
Test name
Test status
Simulation time 83604688 ps
CPU time 0.68 seconds
Started Aug 12 04:44:58 PM PDT 24
Finished Aug 12 04:44:59 PM PDT 24
Peak memory 205020 kb
Host smart-39fa6739-e467-4b3b-94d8-b9ae074d4248
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=453705445 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_override_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.i2c_host_override.453705445
Directory /workspace/35.i2c_host_override/latest

Test location /workspace/coverage/default/35.i2c_host_perf.4211124044
Short name T1012
Test name
Test status
Simulation time 5866624244 ps
CPU time 22.73 seconds
Started Aug 12 04:45:05 PM PDT 24
Finished Aug 12 04:45:28 PM PDT 24
Peak memory 205632 kb
Host smart-d16a5f2f-9c80-44fb-9893-b0908abe619a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4211124044 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_perf_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.i2c_host_perf.4211124044
Directory /workspace/35.i2c_host_perf/latest

Test location /workspace/coverage/default/35.i2c_host_perf_precise.1079931137
Short name T1396
Test name
Test status
Simulation time 1356636136 ps
CPU time 4.76 seconds
Started Aug 12 04:44:58 PM PDT 24
Finished Aug 12 04:45:02 PM PDT 24
Peak memory 213392 kb
Host smart-22ccfe41-cbe4-4d0c-836b-d839bb2c2e33
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1079931137 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_perf_precise_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.i2c_host_perf_precise.1079931137
Directory /workspace/35.i2c_host_perf_precise/latest

Test location /workspace/coverage/default/35.i2c_host_smoke.331124384
Short name T1141
Test name
Test status
Simulation time 4655527097 ps
CPU time 20.85 seconds
Started Aug 12 04:44:58 PM PDT 24
Finished Aug 12 04:45:19 PM PDT 24
Peak memory 304180 kb
Host smart-5d0feadb-c3d3-48e1-a224-63e44627cac0
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=331124384 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_smoke_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.i2c_host_smoke.331124384
Directory /workspace/35.i2c_host_smoke/latest

Test location /workspace/coverage/default/35.i2c_host_stress_all.938343628
Short name T188
Test name
Test status
Simulation time 27521310857 ps
CPU time 196.87 seconds
Started Aug 12 04:44:58 PM PDT 24
Finished Aug 12 04:48:15 PM PDT 24
Peak memory 947764 kb
Host smart-1b2b932f-1220-4017-b0fb-21a4bbd4d7a4
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=938343628 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_stress_all_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.i2c_host_stress_all.938343628
Directory /workspace/35.i2c_host_stress_all/latest

Test location /workspace/coverage/default/35.i2c_host_stretch_timeout.1711394397
Short name T1408
Test name
Test status
Simulation time 807966832 ps
CPU time 14.52 seconds
Started Aug 12 04:44:59 PM PDT 24
Finished Aug 12 04:45:14 PM PDT 24
Peak memory 221608 kb
Host smart-0c5b4153-8bd2-4a89-9c35-2541326e2a91
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1711394397 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_stretch_timeout_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.i2c_host_stretch_timeout.1711394397
Directory /workspace/35.i2c_host_stretch_timeout/latest

Test location /workspace/coverage/default/35.i2c_target_bad_addr.4072881866
Short name T302
Test name
Test status
Simulation time 902189802 ps
CPU time 4.28 seconds
Started Aug 12 04:45:07 PM PDT 24
Finished Aug 12 04:45:11 PM PDT 24
Peak memory 219420 kb
Host smart-ff4d94d5-fede-4d18-9175-9b229ef6e814
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +i2c_bad_addr_pct=50 +cdc_instrumentation_enabled=1 +UVM_
NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4072881866 -assert nopostproc
+UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_target_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.
vdb -cm_log /dev/null -cm_name 35.i2c_target_bad_addr.4072881866
Directory /workspace/35.i2c_target_bad_addr/latest

Test location /workspace/coverage/default/35.i2c_target_fifo_reset_acq.2330353577
Short name T1489
Test name
Test status
Simulation time 354813382 ps
CPU time 1.28 seconds
Started Aug 12 04:45:02 PM PDT 24
Finished Aug 12 04:45:04 PM PDT 24
Peak memory 205236 kb
Host smart-b7c37230-dfb6-49b4-b70c-eed5456995a8
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2330353577 -assert nopostproc +UVM_TESTNAME=i2c_bas
e_test +UVM_TEST_SEQ=i2c_target_fifo_reset_acq_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log
/dev/null -cm_name 35.i2c_target_fifo_reset_acq.2330353577
Directory /workspace/35.i2c_target_fifo_reset_acq/latest

Test location /workspace/coverage/default/35.i2c_target_fifo_reset_tx.902281360
Short name T1586
Test name
Test status
Simulation time 174747777 ps
CPU time 1.17 seconds
Started Aug 12 04:44:56 PM PDT 24
Finished Aug 12 04:44:58 PM PDT 24
Peak memory 205400 kb
Host smart-79f520e1-7a30-4ffb-985f-d29066dcfa75
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=902281360 -assert nopostproc +UVM_TESTNAME=i2c_base
_test +UVM_TEST_SEQ=i2c_target_fifo_reset_tx_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /d
ev/null -cm_name 35.i2c_target_fifo_reset_tx.902281360
Directory /workspace/35.i2c_target_fifo_reset_tx/latest

Test location /workspace/coverage/default/35.i2c_target_fifo_watermarks_acq.1921218614
Short name T324
Test name
Test status
Simulation time 842910326 ps
CPU time 2.21 seconds
Started Aug 12 04:45:06 PM PDT 24
Finished Aug 12 04:45:08 PM PDT 24
Peak memory 205332 kb
Host smart-29ba6d45-8e31-4bce-b1c1-7ec32318fc1d
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1921218614 -assert nopostproc +UVM_TESTNAME=i2c_bas
e_test +UVM_TEST_SEQ=i2c_target_fifo_watermarks_acq_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm
_log /dev/null -cm_name 35.i2c_target_fifo_watermarks_acq.1921218614
Directory /workspace/35.i2c_target_fifo_watermarks_acq/latest

Test location /workspace/coverage/default/35.i2c_target_fifo_watermarks_tx.834485749
Short name T1178
Test name
Test status
Simulation time 198910978 ps
CPU time 1.28 seconds
Started Aug 12 04:45:04 PM PDT 24
Finished Aug 12 04:45:06 PM PDT 24
Peak memory 205268 kb
Host smart-fef7b808-3391-4828-bf60-5542c805b343
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=834485749 -assert nopostproc +UVM_TESTNAME=i2c_base
_test +UVM_TEST_SEQ=i2c_target_fifo_watermarks_tx_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_l
og /dev/null -cm_name 35.i2c_target_fifo_watermarks_tx.834485749
Directory /workspace/35.i2c_target_fifo_watermarks_tx/latest

Test location /workspace/coverage/default/35.i2c_target_intr_smoke.385263029
Short name T1081
Test name
Test status
Simulation time 1159666171 ps
CPU time 6.16 seconds
Started Aug 12 04:44:59 PM PDT 24
Finished Aug 12 04:45:05 PM PDT 24
Peak memory 219372 kb
Host smart-ea6ea5af-7c57-4e7e-9db4-49bb5bb0c32f
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=200_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VER
BOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=385263029 -assert nopostproc +UVM_TESTNAME=i2c_bas
e_test +UVM_TEST_SEQ=i2c_target_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null
-cm_name 35.i2c_target_intr_smoke.385263029
Directory /workspace/35.i2c_target_intr_smoke/latest

Test location /workspace/coverage/default/35.i2c_target_intr_stress_wr.2377117052
Short name T1246
Test name
Test status
Simulation time 4710405076 ps
CPU time 20.62 seconds
Started Aug 12 04:45:00 PM PDT 24
Finished Aug 12 04:45:21 PM PDT 24
Peak memory 722836 kb
Host smart-30db7835-5504-4d38-99fa-525ae17f813e
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=600_000_000 +use_intr_handler=1 +slow_acq=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNO
TES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2377117052 -assert nopostproc +UVM_TES
TNAME=i2c_base_test +UVM_TEST_SEQ=i2c_target_stress_wr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb
-cm_log /dev/null -cm_name 35.i2c_target_intr_stress_wr.2377117052
Directory /workspace/35.i2c_target_intr_stress_wr/latest

Test location /workspace/coverage/default/35.i2c_target_nack_acqfull.3081820320
Short name T773
Test name
Test status
Simulation time 515611504 ps
CPU time 2.88 seconds
Started Aug 12 04:45:05 PM PDT 24
Finished Aug 12 04:45:08 PM PDT 24
Peak memory 213688 kb
Host smart-afc9e274-0855-47ae-aea3-11a755228645
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3081820320 -assert nopostproc +UVM_TESTNAME=i2c_bas
e_test +UVM_TEST_SEQ=i2c_target_nack_acqfull_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /d
ev/null -cm_name 35.i2c_target_nack_acqfull.3081820320
Directory /workspace/35.i2c_target_nack_acqfull/latest

Test location /workspace/coverage/default/35.i2c_target_nack_acqfull_addr.3343351094
Short name T1071
Test name
Test status
Simulation time 928178809 ps
CPU time 2.62 seconds
Started Aug 12 04:45:05 PM PDT 24
Finished Aug 12 04:45:08 PM PDT 24
Peak memory 205636 kb
Host smart-d86725fa-f8ca-476f-8b6d-3461e3e88a98
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3343351094 -assert nopostproc +UVM_TESTNAME=i2c_bas
e_test +UVM_TEST_SEQ=i2c_target_nack_acqfull_addr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_l
og /dev/null -cm_name 35.i2c_target_nack_acqfull_addr.3343351094
Directory /workspace/35.i2c_target_nack_acqfull_addr/latest

Test location /workspace/coverage/default/35.i2c_target_nack_txstretch.3449846497
Short name T1168
Test name
Test status
Simulation time 279770236 ps
CPU time 1.38 seconds
Started Aug 12 04:45:04 PM PDT 24
Finished Aug 12 04:45:06 PM PDT 24
Peak memory 222156 kb
Host smart-11b42366-e2c0-4d81-9075-517875fcaf58
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3449846497 -assert nopostproc +UVM_TESTNAME=i2c_bas
e_test +UVM_TEST_SEQ=i2c_target_nack_txstretch_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log
/dev/null -cm_name 35.i2c_target_nack_txstretch.3449846497
Directory /workspace/35.i2c_target_nack_txstretch/latest

Test location /workspace/coverage/default/35.i2c_target_perf.1117368045
Short name T670
Test name
Test status
Simulation time 463826528 ps
CPU time 3.38 seconds
Started Aug 12 04:45:05 PM PDT 24
Finished Aug 12 04:45:09 PM PDT 24
Peak memory 213668 kb
Host smart-65cfd806-007e-4cc9-9715-a46182a6e857
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1117368045 -assert nopostproc +UVM_TESTNAME=i2c_bas
e_test +UVM_TEST_SEQ=i2c_target_perf_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null
-cm_name 35.i2c_target_perf.1117368045
Directory /workspace/35.i2c_target_perf/latest

Test location /workspace/coverage/default/35.i2c_target_smbus_maxlen.3738845622
Short name T466
Test name
Test status
Simulation time 432089425 ps
CPU time 2.22 seconds
Started Aug 12 04:45:04 PM PDT 24
Finished Aug 12 04:45:07 PM PDT 24
Peak memory 205200 kb
Host smart-8a772d62-338d-40f8-8fa7-e379905545ce
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3738845622 -assert nopostproc +UVM_TESTNAME=i2c_bas
e_test +UVM_TEST_SEQ=i2c_target_smbus_maxlen_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /d
ev/null -cm_name 35.i2c_target_smbus_maxlen.3738845622
Directory /workspace/35.i2c_target_smbus_maxlen/latest

Test location /workspace/coverage/default/35.i2c_target_smoke.880162924
Short name T1076
Test name
Test status
Simulation time 5471200366 ps
CPU time 16.55 seconds
Started Aug 12 04:44:58 PM PDT 24
Finished Aug 12 04:45:15 PM PDT 24
Peak memory 219920 kb
Host smart-d7be0333-b672-4e15-977e-d7f7ebf0e4e5
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=100_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licq
ueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=880162924 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ
=i2c_target_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.i2c_tar
get_smoke.880162924
Directory /workspace/35.i2c_target_smoke/latest

Test location /workspace/coverage/default/35.i2c_target_stress_all.3625290972
Short name T301
Test name
Test status
Simulation time 15168088527 ps
CPU time 52.85 seconds
Started Aug 12 04:45:05 PM PDT 24
Finished Aug 12 04:45:58 PM PDT 24
Peak memory 304384 kb
Host smart-ed0a029e-04d9-44db-abb0-46c32b886ad6
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=300_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VER
BOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3625290972 -assert nopostproc +UVM_TESTNAME=i2c_ba
se_test +UVM_TEST_SEQ=i2c_target_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /de
v/null -cm_name 35.i2c_target_stress_all.3625290972
Directory /workspace/35.i2c_target_stress_all/latest

Test location /workspace/coverage/default/35.i2c_target_stress_rd.544468458
Short name T989
Test name
Test status
Simulation time 5612796556 ps
CPU time 55.53 seconds
Started Aug 12 04:45:02 PM PDT 24
Finished Aug 12 04:45:57 PM PDT 24
Peak memory 215980 kb
Host smart-71f4104b-6a94-49d2-846f-24cacf4ad17c
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=100_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licq
ueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=544468458 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ
=i2c_target_stress_rd_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.i2c
_target_stress_rd.544468458
Directory /workspace/35.i2c_target_stress_rd/latest

Test location /workspace/coverage/default/35.i2c_target_stress_wr.2763911952
Short name T1735
Test name
Test status
Simulation time 63319702433 ps
CPU time 2260.55 seconds
Started Aug 12 04:44:57 PM PDT 24
Finished Aug 12 05:22:38 PM PDT 24
Peak memory 10505272 kb
Host smart-59b8bf70-f773-4094-892c-6d4a09194791
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=600_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licq
ueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2763911952 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SE
Q=i2c_target_stress_wr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.i2
c_target_stress_wr.2763911952
Directory /workspace/35.i2c_target_stress_wr/latest

Test location /workspace/coverage/default/35.i2c_target_stretch.4154715040
Short name T1478
Test name
Test status
Simulation time 339335285 ps
CPU time 4.33 seconds
Started Aug 12 04:44:59 PM PDT 24
Finished Aug 12 04:45:03 PM PDT 24
Peak memory 241932 kb
Host smart-21809fe2-9f98-4a2a-be3b-45a50383f95b
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=400_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licq
ueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4154715040 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SE
Q=i2c_target_stretch_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.i2c_
target_stretch.4154715040
Directory /workspace/35.i2c_target_stretch/latest

Test location /workspace/coverage/default/35.i2c_target_timeout.3644501184
Short name T1536
Test name
Test status
Simulation time 1235869766 ps
CPU time 7.18 seconds
Started Aug 12 04:45:02 PM PDT 24
Finished Aug 12 04:45:10 PM PDT 24
Peak memory 230040 kb
Host smart-deb7ea50-feb6-4939-8421-5f201dcd2a29
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=50_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3644501184 -assert nopostproc +UVM_TESTNAME=i2c_bas
e_test +UVM_TEST_SEQ=i2c_target_timeout_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/nu
ll -cm_name 35.i2c_target_timeout.3644501184
Directory /workspace/35.i2c_target_timeout/latest

Test location /workspace/coverage/default/35.i2c_target_tx_stretch_ctrl.1806556020
Short name T1421
Test name
Test status
Simulation time 182928932 ps
CPU time 3.13 seconds
Started Aug 12 04:45:03 PM PDT 24
Finished Aug 12 04:45:06 PM PDT 24
Peak memory 205376 kb
Host smart-61cdc20a-1c66-4940-93cc-5771d85b34a2
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1806556020 -assert nopostproc +UVM_TESTNAME=i2c_bas
e_test +UVM_TEST_SEQ=i2c_target_tx_stretch_ctrl_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log
/dev/null -cm_name 35.i2c_target_tx_stretch_ctrl.1806556020
Directory /workspace/35.i2c_target_tx_stretch_ctrl/latest

Test location /workspace/coverage/default/36.i2c_alert_test.4238212821
Short name T1422
Test name
Test status
Simulation time 24174934 ps
CPU time 0.65 seconds
Started Aug 12 04:45:20 PM PDT 24
Finished Aug 12 04:45:21 PM PDT 24
Peak memory 204500 kb
Host smart-1d39d817-ab69-4217-9704-3b864c4ae508
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4238212821 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_common_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.i2c_alert_test.4238212821
Directory /workspace/36.i2c_alert_test/latest

Test location /workspace/coverage/default/36.i2c_host_error_intr.3071642747
Short name T28
Test name
Test status
Simulation time 57304812 ps
CPU time 1.33 seconds
Started Aug 12 04:45:17 PM PDT 24
Finished Aug 12 04:45:18 PM PDT 24
Peak memory 213492 kb
Host smart-c54868ed-9889-4d62-83a5-e21142d1486d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3071642747 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_error_intr_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.i2c_host_error_intr.3071642747
Directory /workspace/36.i2c_host_error_intr/latest

Test location /workspace/coverage/default/36.i2c_host_fifo_fmt_empty.2232869533
Short name T1003
Test name
Test status
Simulation time 2944714838 ps
CPU time 16.94 seconds
Started Aug 12 04:45:06 PM PDT 24
Finished Aug 12 04:45:23 PM PDT 24
Peak memory 275224 kb
Host smart-617cb0a1-783a-4d66-8356-66764f3fa7cb
User root
Command /workspace/default/simv +test_timeout_ns=10_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2232869533 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_fifo_fmt_em
pty_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.i2c_host_fifo_fmt_emp
ty.2232869533
Directory /workspace/36.i2c_host_fifo_fmt_empty/latest

Test location /workspace/coverage/default/36.i2c_host_fifo_full.378191730
Short name T606
Test name
Test status
Simulation time 3314052840 ps
CPU time 225.66 seconds
Started Aug 12 04:45:03 PM PDT 24
Finished Aug 12 04:48:49 PM PDT 24
Peak memory 772096 kb
Host smart-7e2c1671-b1d6-4746-b48d-750388f831d4
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=378191730 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_fifo_full_vseq +en_cov=1 -cm line+cond+f
sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.i2c_host_fifo_full.378191730
Directory /workspace/36.i2c_host_fifo_full/latest

Test location /workspace/coverage/default/36.i2c_host_fifo_overflow.3517208452
Short name T1213
Test name
Test status
Simulation time 10492335023 ps
CPU time 104.88 seconds
Started Aug 12 04:45:07 PM PDT 24
Finished Aug 12 04:46:52 PM PDT 24
Peak memory 541192 kb
Host smart-3c36f4d6-1576-425f-a282-69b713eb77f9
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3517208452 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_fifo_overflow_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.i2c_host_fifo_overflow.3517208452
Directory /workspace/36.i2c_host_fifo_overflow/latest

Test location /workspace/coverage/default/36.i2c_host_fifo_reset_fmt.4238146482
Short name T1551
Test name
Test status
Simulation time 188917973 ps
CPU time 0.99 seconds
Started Aug 12 04:45:06 PM PDT 24
Finished Aug 12 04:45:07 PM PDT 24
Peak memory 204984 kb
Host smart-9305cd3c-bd07-4b2b-b27a-5cc17f188c61
User root
Command /workspace/default/simv +test_timeout_ns=10_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4238146482 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_fifo_reset_
fmt_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.i2c_host_fifo_reset_f
mt.4238146482
Directory /workspace/36.i2c_host_fifo_reset_fmt/latest

Test location /workspace/coverage/default/36.i2c_host_fifo_reset_rx.275221486
Short name T1086
Test name
Test status
Simulation time 783871304 ps
CPU time 7.59 seconds
Started Aug 12 04:45:05 PM PDT 24
Finished Aug 12 04:45:13 PM PDT 24
Peak memory 205204 kb
Host smart-289bfc35-d39d-46d8-a990-bf60aafd2ce1
User root
Command /workspace/default/simv +test_timeout_ns=10_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=275221486 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_fifo_reset_r
x_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.i2c_host_fifo_reset_rx.
275221486
Directory /workspace/36.i2c_host_fifo_reset_rx/latest

Test location /workspace/coverage/default/36.i2c_host_fifo_watermark.1923019394
Short name T1078
Test name
Test status
Simulation time 5607138557 ps
CPU time 181.51 seconds
Started Aug 12 04:45:05 PM PDT 24
Finished Aug 12 04:48:07 PM PDT 24
Peak memory 1539404 kb
Host smart-5c889d9e-e7a3-46c0-8706-7df60d3c33a2
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1923019394 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_fifo_watermark_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.i2c_host_fifo_watermark.1923019394
Directory /workspace/36.i2c_host_fifo_watermark/latest

Test location /workspace/coverage/default/36.i2c_host_may_nack.243995154
Short name T260
Test name
Test status
Simulation time 4546278551 ps
CPU time 11.31 seconds
Started Aug 12 04:45:19 PM PDT 24
Finished Aug 12 04:45:30 PM PDT 24
Peak memory 205244 kb
Host smart-0c47f881-e7ac-4e98-9872-7cb56168f1b5
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=243995154 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_may_nack_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.i2c_host_may_nack.243995154
Directory /workspace/36.i2c_host_may_nack/latest

Test location /workspace/coverage/default/36.i2c_host_override.1252462483
Short name T338
Test name
Test status
Simulation time 29597562 ps
CPU time 0.68 seconds
Started Aug 12 04:45:06 PM PDT 24
Finished Aug 12 04:45:07 PM PDT 24
Peak memory 205032 kb
Host smart-4828b4cd-7797-4a9a-a7e7-a50e90f980fd
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1252462483 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_override_vseq +en_cov=1 -cm line+cond+f
sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.i2c_host_override.1252462483
Directory /workspace/36.i2c_host_override/latest

Test location /workspace/coverage/default/36.i2c_host_perf.3310840425
Short name T1643
Test name
Test status
Simulation time 2755431519 ps
CPU time 8.62 seconds
Started Aug 12 04:45:04 PM PDT 24
Finished Aug 12 04:45:13 PM PDT 24
Peak memory 255120 kb
Host smart-27aec153-be8c-4831-a38c-c193beee4eb7
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3310840425 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_perf_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.i2c_host_perf.3310840425
Directory /workspace/36.i2c_host_perf/latest

Test location /workspace/coverage/default/36.i2c_host_perf_precise.666151121
Short name T927
Test name
Test status
Simulation time 131921521 ps
CPU time 5.55 seconds
Started Aug 12 04:45:04 PM PDT 24
Finished Aug 12 04:45:10 PM PDT 24
Peak memory 205832 kb
Host smart-7a75fe90-b0e2-4553-9b72-280a759c39d8
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=666151121 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_perf_precise_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.i2c_host_perf_precise.666151121
Directory /workspace/36.i2c_host_perf_precise/latest

Test location /workspace/coverage/default/36.i2c_host_smoke.1767144641
Short name T481
Test name
Test status
Simulation time 1738237689 ps
CPU time 23.66 seconds
Started Aug 12 04:45:03 PM PDT 24
Finished Aug 12 04:45:27 PM PDT 24
Peak memory 290668 kb
Host smart-cadb4177-3b7f-4ea6-8659-7fb7a33d4644
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1767144641 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_smoke_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.i2c_host_smoke.1767144641
Directory /workspace/36.i2c_host_smoke/latest

Test location /workspace/coverage/default/36.i2c_host_stretch_timeout.2147214684
Short name T394
Test name
Test status
Simulation time 2724664791 ps
CPU time 13.47 seconds
Started Aug 12 04:45:13 PM PDT 24
Finished Aug 12 04:45:26 PM PDT 24
Peak memory 216412 kb
Host smart-b70afc7e-1fa2-4154-958c-2335bffc364e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2147214684 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_stretch_timeout_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.i2c_host_stretch_timeout.2147214684
Directory /workspace/36.i2c_host_stretch_timeout/latest

Test location /workspace/coverage/default/36.i2c_target_bad_addr.2908400024
Short name T720
Test name
Test status
Simulation time 1088201445 ps
CPU time 3.21 seconds
Started Aug 12 04:45:19 PM PDT 24
Finished Aug 12 04:45:22 PM PDT 24
Peak memory 213636 kb
Host smart-e8639c6e-5f95-4b13-ae46-7e8b41ad087c
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +i2c_bad_addr_pct=50 +cdc_instrumentation_enabled=1 +UVM_
NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2908400024 -assert nopostproc
+UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_target_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.
vdb -cm_log /dev/null -cm_name 36.i2c_target_bad_addr.2908400024
Directory /workspace/36.i2c_target_bad_addr/latest

Test location /workspace/coverage/default/36.i2c_target_fifo_reset_acq.465302908
Short name T966
Test name
Test status
Simulation time 165750008 ps
CPU time 1.04 seconds
Started Aug 12 04:45:18 PM PDT 24
Finished Aug 12 04:45:20 PM PDT 24
Peak memory 205260 kb
Host smart-8e1ec2f0-c7f9-41f9-b316-687d7c04f36e
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=465302908 -assert nopostproc +UVM_TESTNAME=i2c_base
_test +UVM_TEST_SEQ=i2c_target_fifo_reset_acq_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /
dev/null -cm_name 36.i2c_target_fifo_reset_acq.465302908
Directory /workspace/36.i2c_target_fifo_reset_acq/latest

Test location /workspace/coverage/default/36.i2c_target_fifo_reset_tx.2308739091
Short name T351
Test name
Test status
Simulation time 1405834528 ps
CPU time 1.14 seconds
Started Aug 12 04:45:17 PM PDT 24
Finished Aug 12 04:45:18 PM PDT 24
Peak memory 205496 kb
Host smart-60772c9d-af99-4a57-8b90-a9f7b1c05fb0
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2308739091 -assert nopostproc +UVM_TESTNAME=i2c_bas
e_test +UVM_TEST_SEQ=i2c_target_fifo_reset_tx_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /
dev/null -cm_name 36.i2c_target_fifo_reset_tx.2308739091
Directory /workspace/36.i2c_target_fifo_reset_tx/latest

Test location /workspace/coverage/default/36.i2c_target_fifo_watermarks_acq.4022918741
Short name T951
Test name
Test status
Simulation time 1619608050 ps
CPU time 2.65 seconds
Started Aug 12 04:45:13 PM PDT 24
Finished Aug 12 04:45:15 PM PDT 24
Peak memory 205400 kb
Host smart-efec90cd-6410-4a95-b0e8-5fb5f716c43c
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4022918741 -assert nopostproc +UVM_TESTNAME=i2c_bas
e_test +UVM_TEST_SEQ=i2c_target_fifo_watermarks_acq_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm
_log /dev/null -cm_name 36.i2c_target_fifo_watermarks_acq.4022918741
Directory /workspace/36.i2c_target_fifo_watermarks_acq/latest

Test location /workspace/coverage/default/36.i2c_target_fifo_watermarks_tx.664237232
Short name T1684
Test name
Test status
Simulation time 780733765 ps
CPU time 1.8 seconds
Started Aug 12 04:45:20 PM PDT 24
Finished Aug 12 04:45:22 PM PDT 24
Peak memory 205548 kb
Host smart-5b29ce64-cf69-43a2-ad7a-d10109f1f4fd
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=664237232 -assert nopostproc +UVM_TESTNAME=i2c_base
_test +UVM_TEST_SEQ=i2c_target_fifo_watermarks_tx_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_l
og /dev/null -cm_name 36.i2c_target_fifo_watermarks_tx.664237232
Directory /workspace/36.i2c_target_fifo_watermarks_tx/latest

Test location /workspace/coverage/default/36.i2c_target_hrst.1572839850
Short name T607
Test name
Test status
Simulation time 984634169 ps
CPU time 1.85 seconds
Started Aug 12 04:45:17 PM PDT 24
Finished Aug 12 04:45:19 PM PDT 24
Peak memory 213624 kb
Host smart-17fbec0c-7a23-48c4-915e-8e52bb30939d
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1572839850 -assert nopostproc +UVM_TESTNAME=i2c_bas
e_test +UVM_TEST_SEQ=i2c_target_hrst_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null
-cm_name 36.i2c_target_hrst.1572839850
Directory /workspace/36.i2c_target_hrst/latest

Test location /workspace/coverage/default/36.i2c_target_intr_smoke.1217181613
Short name T1581
Test name
Test status
Simulation time 10101373719 ps
CPU time 6.31 seconds
Started Aug 12 04:45:18 PM PDT 24
Finished Aug 12 04:45:25 PM PDT 24
Peak memory 218412 kb
Host smart-da08ca67-99d1-4923-b0ab-799023ba5036
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=200_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VER
BOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1217181613 -assert nopostproc +UVM_TESTNAME=i2c_ba
se_test +UVM_TEST_SEQ=i2c_target_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/nul
l -cm_name 36.i2c_target_intr_smoke.1217181613
Directory /workspace/36.i2c_target_intr_smoke/latest

Test location /workspace/coverage/default/36.i2c_target_intr_stress_wr.207143093
Short name T1165
Test name
Test status
Simulation time 2308024223 ps
CPU time 7.8 seconds
Started Aug 12 04:45:16 PM PDT 24
Finished Aug 12 04:45:24 PM PDT 24
Peak memory 420440 kb
Host smart-5c5307a9-bae4-4389-b4dd-1e988eb66cf1
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=600_000_000 +use_intr_handler=1 +slow_acq=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNO
TES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=207143093 -assert nopostproc +UVM_TEST
NAME=i2c_base_test +UVM_TEST_SEQ=i2c_target_stress_wr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -
cm_log /dev/null -cm_name 36.i2c_target_intr_stress_wr.207143093
Directory /workspace/36.i2c_target_intr_stress_wr/latest

Test location /workspace/coverage/default/36.i2c_target_nack_acqfull.3393523716
Short name T1160
Test name
Test status
Simulation time 2283785691 ps
CPU time 2.91 seconds
Started Aug 12 04:45:14 PM PDT 24
Finished Aug 12 04:45:17 PM PDT 24
Peak memory 213716 kb
Host smart-406a1fcd-b75a-4587-b93b-0933933a6055
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3393523716 -assert nopostproc +UVM_TESTNAME=i2c_bas
e_test +UVM_TEST_SEQ=i2c_target_nack_acqfull_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /d
ev/null -cm_name 36.i2c_target_nack_acqfull.3393523716
Directory /workspace/36.i2c_target_nack_acqfull/latest

Test location /workspace/coverage/default/36.i2c_target_nack_acqfull_addr.2711031557
Short name T1311
Test name
Test status
Simulation time 2052116672 ps
CPU time 2.39 seconds
Started Aug 12 04:45:18 PM PDT 24
Finished Aug 12 04:45:21 PM PDT 24
Peak memory 205452 kb
Host smart-4094edb3-4fae-42f4-b25e-593ccee03b80
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2711031557 -assert nopostproc +UVM_TESTNAME=i2c_bas
e_test +UVM_TEST_SEQ=i2c_target_nack_acqfull_addr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_l
og /dev/null -cm_name 36.i2c_target_nack_acqfull_addr.2711031557
Directory /workspace/36.i2c_target_nack_acqfull_addr/latest

Test location /workspace/coverage/default/36.i2c_target_nack_txstretch.1245052088
Short name T178
Test name
Test status
Simulation time 918388279 ps
CPU time 1.32 seconds
Started Aug 12 04:45:14 PM PDT 24
Finished Aug 12 04:45:15 PM PDT 24
Peak memory 221928 kb
Host smart-541571e0-b741-4231-a16e-d65e7a17545f
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1245052088 -assert nopostproc +UVM_TESTNAME=i2c_bas
e_test +UVM_TEST_SEQ=i2c_target_nack_txstretch_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log
/dev/null -cm_name 36.i2c_target_nack_txstretch.1245052088
Directory /workspace/36.i2c_target_nack_txstretch/latest

Test location /workspace/coverage/default/36.i2c_target_perf.4148569036
Short name T1005
Test name
Test status
Simulation time 824787006 ps
CPU time 5.43 seconds
Started Aug 12 04:45:14 PM PDT 24
Finished Aug 12 04:45:19 PM PDT 24
Peak memory 215760 kb
Host smart-156edd38-1231-441d-b6fd-0f528d99fba3
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4148569036 -assert nopostproc +UVM_TESTNAME=i2c_bas
e_test +UVM_TEST_SEQ=i2c_target_perf_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null
-cm_name 36.i2c_target_perf.4148569036
Directory /workspace/36.i2c_target_perf/latest

Test location /workspace/coverage/default/36.i2c_target_smbus_maxlen.4142398920
Short name T1225
Test name
Test status
Simulation time 2132456865 ps
CPU time 2.48 seconds
Started Aug 12 04:45:16 PM PDT 24
Finished Aug 12 04:45:18 PM PDT 24
Peak memory 205240 kb
Host smart-7702c399-6e7b-4dde-928f-703531c19727
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4142398920 -assert nopostproc +UVM_TESTNAME=i2c_bas
e_test +UVM_TEST_SEQ=i2c_target_smbus_maxlen_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /d
ev/null -cm_name 36.i2c_target_smbus_maxlen.4142398920
Directory /workspace/36.i2c_target_smbus_maxlen/latest

Test location /workspace/coverage/default/36.i2c_target_smoke.4285934050
Short name T1176
Test name
Test status
Simulation time 1601020270 ps
CPU time 25.87 seconds
Started Aug 12 04:45:13 PM PDT 24
Finished Aug 12 04:45:39 PM PDT 24
Peak memory 217124 kb
Host smart-aefe3223-34c7-453d-bbba-b3a1c77edd08
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=100_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licq
ueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4285934050 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SE
Q=i2c_target_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.i2c_ta
rget_smoke.4285934050
Directory /workspace/36.i2c_target_smoke/latest

Test location /workspace/coverage/default/36.i2c_target_stress_all.3669852109
Short name T159
Test name
Test status
Simulation time 12798777151 ps
CPU time 52.43 seconds
Started Aug 12 04:45:18 PM PDT 24
Finished Aug 12 04:46:10 PM PDT 24
Peak memory 349912 kb
Host smart-90723a7a-e9f6-4299-9b46-af8330b8d1a2
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=300_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VER
BOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3669852109 -assert nopostproc +UVM_TESTNAME=i2c_ba
se_test +UVM_TEST_SEQ=i2c_target_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /de
v/null -cm_name 36.i2c_target_stress_all.3669852109
Directory /workspace/36.i2c_target_stress_all/latest

Test location /workspace/coverage/default/36.i2c_target_stress_rd.3812920580
Short name T1544
Test name
Test status
Simulation time 9213351454 ps
CPU time 7.84 seconds
Started Aug 12 04:45:13 PM PDT 24
Finished Aug 12 04:45:21 PM PDT 24
Peak memory 211040 kb
Host smart-7b3b8877-f893-422a-94fb-4f3090a722b4
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=100_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licq
ueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3812920580 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SE
Q=i2c_target_stress_rd_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.i2
c_target_stress_rd.3812920580
Directory /workspace/36.i2c_target_stress_rd/latest

Test location /workspace/coverage/default/36.i2c_target_stress_wr.565244511
Short name T1363
Test name
Test status
Simulation time 11650773176 ps
CPU time 4.42 seconds
Started Aug 12 04:45:18 PM PDT 24
Finished Aug 12 04:45:22 PM PDT 24
Peak memory 205596 kb
Host smart-fc64d02b-c1ff-4b86-8a5c-dcedefc8b5b5
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=600_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licq
ueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=565244511 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ
=i2c_target_stress_wr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.i2c
_target_stress_wr.565244511
Directory /workspace/36.i2c_target_stress_wr/latest

Test location /workspace/coverage/default/36.i2c_target_stretch.3697972864
Short name T651
Test name
Test status
Simulation time 4331477728 ps
CPU time 235.92 seconds
Started Aug 12 04:45:13 PM PDT 24
Finished Aug 12 04:49:09 PM PDT 24
Peak memory 1136708 kb
Host smart-6bfaf2f3-7a8f-46c7-b0cd-8ba164026164
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=400_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licq
ueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3697972864 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SE
Q=i2c_target_stretch_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.i2c_
target_stretch.3697972864
Directory /workspace/36.i2c_target_stretch/latest

Test location /workspace/coverage/default/36.i2c_target_timeout.1057883794
Short name T1174
Test name
Test status
Simulation time 3292436303 ps
CPU time 6.75 seconds
Started Aug 12 04:45:19 PM PDT 24
Finished Aug 12 04:45:26 PM PDT 24
Peak memory 221876 kb
Host smart-5e1a261b-060d-4452-a95b-5bf4974754cf
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=50_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1057883794 -assert nopostproc +UVM_TESTNAME=i2c_bas
e_test +UVM_TEST_SEQ=i2c_target_timeout_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/nu
ll -cm_name 36.i2c_target_timeout.1057883794
Directory /workspace/36.i2c_target_timeout/latest

Test location /workspace/coverage/default/36.i2c_target_tx_stretch_ctrl.1064872003
Short name T1229
Test name
Test status
Simulation time 166627933 ps
CPU time 2.94 seconds
Started Aug 12 04:45:17 PM PDT 24
Finished Aug 12 04:45:20 PM PDT 24
Peak memory 206148 kb
Host smart-13de233f-139a-4db4-b71d-19597c7bf862
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1064872003 -assert nopostproc +UVM_TESTNAME=i2c_bas
e_test +UVM_TEST_SEQ=i2c_target_tx_stretch_ctrl_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log
/dev/null -cm_name 36.i2c_target_tx_stretch_ctrl.1064872003
Directory /workspace/36.i2c_target_tx_stretch_ctrl/latest

Test location /workspace/coverage/default/37.i2c_alert_test.159936458
Short name T480
Test name
Test status
Simulation time 18944770 ps
CPU time 0.64 seconds
Started Aug 12 04:45:20 PM PDT 24
Finished Aug 12 04:45:21 PM PDT 24
Peak memory 204480 kb
Host smart-6fc604ea-74da-470b-98bd-7285f575b96d
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=159936458 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_common_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.i2c_alert_test.159936458
Directory /workspace/37.i2c_alert_test/latest

Test location /workspace/coverage/default/37.i2c_host_error_intr.4232161953
Short name T1251
Test name
Test status
Simulation time 1152886738 ps
CPU time 3.36 seconds
Started Aug 12 04:45:18 PM PDT 24
Finished Aug 12 04:45:21 PM PDT 24
Peak memory 227548 kb
Host smart-0dffba45-bce0-4e3c-b0f2-1893a61f5f3b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4232161953 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_error_intr_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.i2c_host_error_intr.4232161953
Directory /workspace/37.i2c_host_error_intr/latest

Test location /workspace/coverage/default/37.i2c_host_fifo_fmt_empty.3452987017
Short name T1692
Test name
Test status
Simulation time 522406535 ps
CPU time 5.58 seconds
Started Aug 12 04:45:16 PM PDT 24
Finished Aug 12 04:45:22 PM PDT 24
Peak memory 258360 kb
Host smart-f47a5b87-e475-467c-bfd1-61130f154b21
User root
Command /workspace/default/simv +test_timeout_ns=10_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3452987017 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_fifo_fmt_em
pty_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.i2c_host_fifo_fmt_emp
ty.3452987017
Directory /workspace/37.i2c_host_fifo_fmt_empty/latest

Test location /workspace/coverage/default/37.i2c_host_fifo_full.2185564490
Short name T1353
Test name
Test status
Simulation time 3130320431 ps
CPU time 83.9 seconds
Started Aug 12 04:45:19 PM PDT 24
Finished Aug 12 04:46:43 PM PDT 24
Peak memory 485492 kb
Host smart-f5326397-a275-4b4b-b966-4651d93f5409
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2185564490 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_fifo_full_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.i2c_host_fifo_full.2185564490
Directory /workspace/37.i2c_host_fifo_full/latest

Test location /workspace/coverage/default/37.i2c_host_fifo_overflow.497219669
Short name T645
Test name
Test status
Simulation time 6322775125 ps
CPU time 122.72 seconds
Started Aug 12 04:45:14 PM PDT 24
Finished Aug 12 04:47:17 PM PDT 24
Peak memory 604824 kb
Host smart-9a280d8d-6a89-404e-a8e4-c61346bad9b1
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=497219669 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_fifo_overflow_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.i2c_host_fifo_overflow.497219669
Directory /workspace/37.i2c_host_fifo_overflow/latest

Test location /workspace/coverage/default/37.i2c_host_fifo_reset_fmt.2528911883
Short name T1642
Test name
Test status
Simulation time 348598620 ps
CPU time 1.13 seconds
Started Aug 12 04:45:19 PM PDT 24
Finished Aug 12 04:45:20 PM PDT 24
Peak memory 205064 kb
Host smart-43330d79-9439-4ae4-b735-ca6adaec237b
User root
Command /workspace/default/simv +test_timeout_ns=10_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2528911883 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_fifo_reset_
fmt_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.i2c_host_fifo_reset_f
mt.2528911883
Directory /workspace/37.i2c_host_fifo_reset_fmt/latest

Test location /workspace/coverage/default/37.i2c_host_fifo_reset_rx.2998488251
Short name T169
Test name
Test status
Simulation time 186330854 ps
CPU time 3.72 seconds
Started Aug 12 04:45:18 PM PDT 24
Finished Aug 12 04:45:22 PM PDT 24
Peak memory 205340 kb
Host smart-f8cdcb26-0c60-4fe7-a9ac-a825edba8ff5
User root
Command /workspace/default/simv +test_timeout_ns=10_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2998488251 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_fifo_reset_
rx_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.i2c_host_fifo_reset_rx
.2998488251
Directory /workspace/37.i2c_host_fifo_reset_rx/latest

Test location /workspace/coverage/default/37.i2c_host_fifo_watermark.1957009158
Short name T437
Test name
Test status
Simulation time 20826250972 ps
CPU time 387.52 seconds
Started Aug 12 04:45:14 PM PDT 24
Finished Aug 12 04:51:42 PM PDT 24
Peak memory 1481084 kb
Host smart-2e597a5a-6da0-48a4-8c0a-6b0c41af3a63
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1957009158 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_fifo_watermark_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.i2c_host_fifo_watermark.1957009158
Directory /workspace/37.i2c_host_fifo_watermark/latest

Test location /workspace/coverage/default/37.i2c_host_may_nack.223607157
Short name T265
Test name
Test status
Simulation time 1814766094 ps
CPU time 18.64 seconds
Started Aug 12 04:45:21 PM PDT 24
Finished Aug 12 04:45:40 PM PDT 24
Peak memory 205164 kb
Host smart-203116b7-3e7f-4bec-9e46-34fbdaa6272b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=223607157 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_may_nack_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.i2c_host_may_nack.223607157
Directory /workspace/37.i2c_host_may_nack/latest

Test location /workspace/coverage/default/37.i2c_host_mode_toggle.3118029022
Short name T12
Test name
Test status
Simulation time 94403955 ps
CPU time 1.6 seconds
Started Aug 12 04:45:22 PM PDT 24
Finished Aug 12 04:45:24 PM PDT 24
Peak memory 213456 kb
Host smart-c480324a-ef03-4c9c-a884-e38e9ad8707b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3118029022 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_mode_toggle_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.i2c_host_mode_toggle.3118029022
Directory /workspace/37.i2c_host_mode_toggle/latest

Test location /workspace/coverage/default/37.i2c_host_override.1399205544
Short name T1439
Test name
Test status
Simulation time 27053027 ps
CPU time 0.66 seconds
Started Aug 12 04:45:14 PM PDT 24
Finished Aug 12 04:45:15 PM PDT 24
Peak memory 205000 kb
Host smart-a7594913-623d-43cd-84f5-a0883d5e73eb
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1399205544 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_override_vseq +en_cov=1 -cm line+cond+f
sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.i2c_host_override.1399205544
Directory /workspace/37.i2c_host_override/latest

Test location /workspace/coverage/default/37.i2c_host_perf.423300100
Short name T246
Test name
Test status
Simulation time 48571083784 ps
CPU time 839.73 seconds
Started Aug 12 04:45:18 PM PDT 24
Finished Aug 12 04:59:18 PM PDT 24
Peak memory 226924 kb
Host smart-31f593a5-dd7e-43fd-82f4-faef313caa45
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=423300100 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_perf_vseq +en_cov=1 -cm line+cond+fsm+tg
l+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.i2c_host_perf.423300100
Directory /workspace/37.i2c_host_perf/latest

Test location /workspace/coverage/default/37.i2c_host_perf_precise.744950832
Short name T1161
Test name
Test status
Simulation time 865788603 ps
CPU time 10.1 seconds
Started Aug 12 04:45:14 PM PDT 24
Finished Aug 12 04:45:25 PM PDT 24
Peak memory 213504 kb
Host smart-81275fea-07a8-4806-8bdd-ced06e0ae47b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=744950832 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_perf_precise_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.i2c_host_perf_precise.744950832
Directory /workspace/37.i2c_host_perf_precise/latest

Test location /workspace/coverage/default/37.i2c_host_smoke.3072675494
Short name T524
Test name
Test status
Simulation time 2664358581 ps
CPU time 22.19 seconds
Started Aug 12 04:45:15 PM PDT 24
Finished Aug 12 04:45:37 PM PDT 24
Peak memory 316432 kb
Host smart-81026d8a-4d65-4135-afa8-e463726771c2
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3072675494 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_smoke_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.i2c_host_smoke.3072675494
Directory /workspace/37.i2c_host_smoke/latest

Test location /workspace/coverage/default/37.i2c_host_stretch_timeout.1310221574
Short name T1731
Test name
Test status
Simulation time 661470402 ps
CPU time 26.85 seconds
Started Aug 12 04:45:14 PM PDT 24
Finished Aug 12 04:45:41 PM PDT 24
Peak memory 213344 kb
Host smart-263cb63a-21b4-45ad-b49f-b33a3eb47358
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1310221574 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_stretch_timeout_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.i2c_host_stretch_timeout.1310221574
Directory /workspace/37.i2c_host_stretch_timeout/latest

Test location /workspace/coverage/default/37.i2c_target_bad_addr.1196039869
Short name T496
Test name
Test status
Simulation time 776267998 ps
CPU time 4.42 seconds
Started Aug 12 04:45:25 PM PDT 24
Finished Aug 12 04:45:30 PM PDT 24
Peak memory 218992 kb
Host smart-75ba1d54-bac5-47e5-9aa5-fd1b251d585b
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +i2c_bad_addr_pct=50 +cdc_instrumentation_enabled=1 +UVM_
NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1196039869 -assert nopostproc
+UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_target_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.
vdb -cm_log /dev/null -cm_name 37.i2c_target_bad_addr.1196039869
Directory /workspace/37.i2c_target_bad_addr/latest

Test location /workspace/coverage/default/37.i2c_target_fifo_reset_acq.501990390
Short name T1256
Test name
Test status
Simulation time 425228293 ps
CPU time 1.71 seconds
Started Aug 12 04:45:27 PM PDT 24
Finished Aug 12 04:45:29 PM PDT 24
Peak memory 207644 kb
Host smart-ac019da4-ce71-4de4-8d5a-61d2a5bf5e55
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=501990390 -assert nopostproc +UVM_TESTNAME=i2c_base
_test +UVM_TEST_SEQ=i2c_target_fifo_reset_acq_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /
dev/null -cm_name 37.i2c_target_fifo_reset_acq.501990390
Directory /workspace/37.i2c_target_fifo_reset_acq/latest

Test location /workspace/coverage/default/37.i2c_target_fifo_reset_tx.2013774531
Short name T1022
Test name
Test status
Simulation time 228378027 ps
CPU time 1.28 seconds
Started Aug 12 04:45:25 PM PDT 24
Finished Aug 12 04:45:27 PM PDT 24
Peak memory 205196 kb
Host smart-179d836f-df19-42c9-80d6-42c75f4ce528
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2013774531 -assert nopostproc +UVM_TESTNAME=i2c_bas
e_test +UVM_TEST_SEQ=i2c_target_fifo_reset_tx_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /
dev/null -cm_name 37.i2c_target_fifo_reset_tx.2013774531
Directory /workspace/37.i2c_target_fifo_reset_tx/latest

Test location /workspace/coverage/default/37.i2c_target_fifo_watermarks_acq.3545556890
Short name T912
Test name
Test status
Simulation time 560951588 ps
CPU time 3.28 seconds
Started Aug 12 04:45:24 PM PDT 24
Finished Aug 12 04:45:27 PM PDT 24
Peak memory 205456 kb
Host smart-8dcdb2e4-77e7-40ff-ad08-1b1ac895aef2
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3545556890 -assert nopostproc +UVM_TESTNAME=i2c_bas
e_test +UVM_TEST_SEQ=i2c_target_fifo_watermarks_acq_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm
_log /dev/null -cm_name 37.i2c_target_fifo_watermarks_acq.3545556890
Directory /workspace/37.i2c_target_fifo_watermarks_acq/latest

Test location /workspace/coverage/default/37.i2c_target_fifo_watermarks_tx.2921218828
Short name T980
Test name
Test status
Simulation time 320023324 ps
CPU time 1.44 seconds
Started Aug 12 04:45:28 PM PDT 24
Finished Aug 12 04:45:29 PM PDT 24
Peak memory 205328 kb
Host smart-a405a71b-ee5f-41fb-96c8-2cc42d58810c
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2921218828 -assert nopostproc +UVM_TESTNAME=i2c_bas
e_test +UVM_TEST_SEQ=i2c_target_fifo_watermarks_tx_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_
log /dev/null -cm_name 37.i2c_target_fifo_watermarks_tx.2921218828
Directory /workspace/37.i2c_target_fifo_watermarks_tx/latest

Test location /workspace/coverage/default/37.i2c_target_intr_smoke.2958931119
Short name T305
Test name
Test status
Simulation time 6374937241 ps
CPU time 10.08 seconds
Started Aug 12 04:45:22 PM PDT 24
Finished Aug 12 04:45:32 PM PDT 24
Peak memory 233868 kb
Host smart-6f4eddc6-8a77-406f-bbd1-a548c8eaba22
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=200_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VER
BOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2958931119 -assert nopostproc +UVM_TESTNAME=i2c_ba
se_test +UVM_TEST_SEQ=i2c_target_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/nul
l -cm_name 37.i2c_target_intr_smoke.2958931119
Directory /workspace/37.i2c_target_intr_smoke/latest

Test location /workspace/coverage/default/37.i2c_target_intr_stress_wr.455624481
Short name T565
Test name
Test status
Simulation time 1290691051 ps
CPU time 1.89 seconds
Started Aug 12 04:45:24 PM PDT 24
Finished Aug 12 04:45:26 PM PDT 24
Peak memory 205360 kb
Host smart-2d0329c6-5897-44c0-8350-3d031db66f5a
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=600_000_000 +use_intr_handler=1 +slow_acq=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNO
TES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=455624481 -assert nopostproc +UVM_TEST
NAME=i2c_base_test +UVM_TEST_SEQ=i2c_target_stress_wr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -
cm_log /dev/null -cm_name 37.i2c_target_intr_stress_wr.455624481
Directory /workspace/37.i2c_target_intr_stress_wr/latest

Test location /workspace/coverage/default/37.i2c_target_nack_acqfull.3366139790
Short name T1222
Test name
Test status
Simulation time 560506955 ps
CPU time 2.77 seconds
Started Aug 12 04:45:25 PM PDT 24
Finished Aug 12 04:45:27 PM PDT 24
Peak memory 213596 kb
Host smart-7556c512-f4ac-4a70-99bd-74a4c14dcc48
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3366139790 -assert nopostproc +UVM_TESTNAME=i2c_bas
e_test +UVM_TEST_SEQ=i2c_target_nack_acqfull_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /d
ev/null -cm_name 37.i2c_target_nack_acqfull.3366139790
Directory /workspace/37.i2c_target_nack_acqfull/latest

Test location /workspace/coverage/default/37.i2c_target_nack_acqfull_addr.2236558336
Short name T1488
Test name
Test status
Simulation time 1041206145 ps
CPU time 2.5 seconds
Started Aug 12 04:45:24 PM PDT 24
Finished Aug 12 04:45:27 PM PDT 24
Peak memory 205468 kb
Host smart-dffb2868-6745-4322-9697-b3670b61c35a
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2236558336 -assert nopostproc +UVM_TESTNAME=i2c_bas
e_test +UVM_TEST_SEQ=i2c_target_nack_acqfull_addr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_l
og /dev/null -cm_name 37.i2c_target_nack_acqfull_addr.2236558336
Directory /workspace/37.i2c_target_nack_acqfull_addr/latest

Test location /workspace/coverage/default/37.i2c_target_nack_txstretch.864110642
Short name T1224
Test name
Test status
Simulation time 623376199 ps
CPU time 1.44 seconds
Started Aug 12 04:45:21 PM PDT 24
Finished Aug 12 04:45:23 PM PDT 24
Peak memory 222180 kb
Host smart-f571db3e-0aad-49d1-a3e6-745779ee5ae0
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=864110642 -assert nopostproc +UVM_TESTNAME=i2c_base
_test +UVM_TEST_SEQ=i2c_target_nack_txstretch_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /
dev/null -cm_name 37.i2c_target_nack_txstretch.864110642
Directory /workspace/37.i2c_target_nack_txstretch/latest

Test location /workspace/coverage/default/37.i2c_target_perf.3228089378
Short name T1609
Test name
Test status
Simulation time 8060098962 ps
CPU time 5.27 seconds
Started Aug 12 04:45:23 PM PDT 24
Finished Aug 12 04:45:28 PM PDT 24
Peak memory 221860 kb
Host smart-a5bcfa64-9453-4c58-8812-c5c7a0ebf3b7
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3228089378 -assert nopostproc +UVM_TESTNAME=i2c_bas
e_test +UVM_TEST_SEQ=i2c_target_perf_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null
-cm_name 37.i2c_target_perf.3228089378
Directory /workspace/37.i2c_target_perf/latest

Test location /workspace/coverage/default/37.i2c_target_smbus_maxlen.2892615057
Short name T787
Test name
Test status
Simulation time 418418788 ps
CPU time 2.42 seconds
Started Aug 12 04:45:20 PM PDT 24
Finished Aug 12 04:45:23 PM PDT 24
Peak memory 205248 kb
Host smart-9e135ead-1031-451a-9f89-0ed30c26fdcc
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2892615057 -assert nopostproc +UVM_TESTNAME=i2c_bas
e_test +UVM_TEST_SEQ=i2c_target_smbus_maxlen_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /d
ev/null -cm_name 37.i2c_target_smbus_maxlen.2892615057
Directory /workspace/37.i2c_target_smbus_maxlen/latest

Test location /workspace/coverage/default/37.i2c_target_smoke.3997313402
Short name T688
Test name
Test status
Simulation time 16940468650 ps
CPU time 35.33 seconds
Started Aug 12 04:45:22 PM PDT 24
Finished Aug 12 04:45:57 PM PDT 24
Peak memory 221868 kb
Host smart-6bfe63bc-5dd9-4316-8d1e-8ec8259299d7
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=100_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licq
ueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3997313402 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SE
Q=i2c_target_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.i2c_ta
rget_smoke.3997313402
Directory /workspace/37.i2c_target_smoke/latest

Test location /workspace/coverage/default/37.i2c_target_stress_all.1685090370
Short name T508
Test name
Test status
Simulation time 65512938681 ps
CPU time 242.51 seconds
Started Aug 12 04:45:22 PM PDT 24
Finished Aug 12 04:49:25 PM PDT 24
Peak memory 2101016 kb
Host smart-a6c660fb-c833-4934-a3cf-ba7854a4d6c2
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=300_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VER
BOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1685090370 -assert nopostproc +UVM_TESTNAME=i2c_ba
se_test +UVM_TEST_SEQ=i2c_target_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /de
v/null -cm_name 37.i2c_target_stress_all.1685090370
Directory /workspace/37.i2c_target_stress_all/latest

Test location /workspace/coverage/default/37.i2c_target_stress_rd.47791936
Short name T1476
Test name
Test status
Simulation time 1123860796 ps
CPU time 51.07 seconds
Started Aug 12 04:45:22 PM PDT 24
Finished Aug 12 04:46:14 PM PDT 24
Peak memory 221816 kb
Host smart-3b59a8a1-128c-4166-909f-681d3f8aa98f
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=100_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licq
ueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=47791936 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=
i2c_target_stress_rd_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.i2c_
target_stress_rd.47791936
Directory /workspace/37.i2c_target_stress_rd/latest

Test location /workspace/coverage/default/37.i2c_target_stress_wr.385925838
Short name T1730
Test name
Test status
Simulation time 54666409119 ps
CPU time 531.33 seconds
Started Aug 12 04:45:20 PM PDT 24
Finished Aug 12 04:54:11 PM PDT 24
Peak memory 3762688 kb
Host smart-b0175c27-f004-4b68-9a80-fba37059ae2d
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=600_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licq
ueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=385925838 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ
=i2c_target_stress_wr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.i2c
_target_stress_wr.385925838
Directory /workspace/37.i2c_target_stress_wr/latest

Test location /workspace/coverage/default/37.i2c_target_stretch.4183101568
Short name T1344
Test name
Test status
Simulation time 1299822305 ps
CPU time 25.96 seconds
Started Aug 12 04:45:27 PM PDT 24
Finished Aug 12 04:45:53 PM PDT 24
Peak memory 324356 kb
Host smart-b087e7d2-6e3a-494a-ac3b-910f1193e2bd
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=400_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licq
ueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4183101568 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SE
Q=i2c_target_stretch_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.i2c_
target_stretch.4183101568
Directory /workspace/37.i2c_target_stretch/latest

Test location /workspace/coverage/default/37.i2c_target_timeout.2932292830
Short name T1577
Test name
Test status
Simulation time 12387801290 ps
CPU time 6.98 seconds
Started Aug 12 04:45:23 PM PDT 24
Finished Aug 12 04:45:30 PM PDT 24
Peak memory 230016 kb
Host smart-956d0f45-c4db-443f-a0aa-2acedf7e941b
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=50_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2932292830 -assert nopostproc +UVM_TESTNAME=i2c_bas
e_test +UVM_TEST_SEQ=i2c_target_timeout_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/nu
ll -cm_name 37.i2c_target_timeout.2932292830
Directory /workspace/37.i2c_target_timeout/latest

Test location /workspace/coverage/default/37.i2c_target_tx_stretch_ctrl.3741426746
Short name T1689
Test name
Test status
Simulation time 284946466 ps
CPU time 3.87 seconds
Started Aug 12 04:45:21 PM PDT 24
Finished Aug 12 04:45:25 PM PDT 24
Peak memory 205444 kb
Host smart-fb800a68-8b3f-4d81-b3e9-e9b6704d6471
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3741426746 -assert nopostproc +UVM_TESTNAME=i2c_bas
e_test +UVM_TEST_SEQ=i2c_target_tx_stretch_ctrl_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log
/dev/null -cm_name 37.i2c_target_tx_stretch_ctrl.3741426746
Directory /workspace/37.i2c_target_tx_stretch_ctrl/latest

Test location /workspace/coverage/default/38.i2c_alert_test.3704568619
Short name T621
Test name
Test status
Simulation time 64257520 ps
CPU time 0.64 seconds
Started Aug 12 04:45:29 PM PDT 24
Finished Aug 12 04:45:30 PM PDT 24
Peak memory 204452 kb
Host smart-639f58ff-2eec-4636-b8ae-d2941eb3a059
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3704568619 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_common_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.i2c_alert_test.3704568619
Directory /workspace/38.i2c_alert_test/latest

Test location /workspace/coverage/default/38.i2c_host_error_intr.172257703
Short name T1597
Test name
Test status
Simulation time 68032528 ps
CPU time 1.57 seconds
Started Aug 12 04:45:21 PM PDT 24
Finished Aug 12 04:45:22 PM PDT 24
Peak memory 213544 kb
Host smart-1ed28445-9a2c-4250-a2d5-6d0e90b039cf
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=172257703 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_error_intr_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.i2c_host_error_intr.172257703
Directory /workspace/38.i2c_host_error_intr/latest

Test location /workspace/coverage/default/38.i2c_host_fifo_fmt_empty.886735506
Short name T908
Test name
Test status
Simulation time 275459841 ps
CPU time 14.18 seconds
Started Aug 12 04:45:32 PM PDT 24
Finished Aug 12 04:45:46 PM PDT 24
Peak memory 260392 kb
Host smart-7ff22250-6dcb-4e90-805f-c7c0610eaf57
User root
Command /workspace/default/simv +test_timeout_ns=10_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=886735506 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_fifo_fmt_emp
ty_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.i2c_host_fifo_fmt_empt
y.886735506
Directory /workspace/38.i2c_host_fifo_fmt_empty/latest

Test location /workspace/coverage/default/38.i2c_host_fifo_full.2578496515
Short name T1711
Test name
Test status
Simulation time 5290709788 ps
CPU time 92.96 seconds
Started Aug 12 04:45:22 PM PDT 24
Finished Aug 12 04:46:55 PM PDT 24
Peak memory 440668 kb
Host smart-e9ea9221-711b-4e0a-bf5e-1010156cb394
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2578496515 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_fifo_full_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.i2c_host_fifo_full.2578496515
Directory /workspace/38.i2c_host_fifo_full/latest

Test location /workspace/coverage/default/38.i2c_host_fifo_overflow.269901467
Short name T440
Test name
Test status
Simulation time 18716684055 ps
CPU time 70 seconds
Started Aug 12 04:45:26 PM PDT 24
Finished Aug 12 04:46:37 PM PDT 24
Peak memory 768932 kb
Host smart-4d86e72b-03de-442a-b592-667782928c6f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=269901467 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_fifo_overflow_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.i2c_host_fifo_overflow.269901467
Directory /workspace/38.i2c_host_fifo_overflow/latest

Test location /workspace/coverage/default/38.i2c_host_fifo_reset_fmt.2805129665
Short name T631
Test name
Test status
Simulation time 88630924 ps
CPU time 0.96 seconds
Started Aug 12 04:45:23 PM PDT 24
Finished Aug 12 04:45:24 PM PDT 24
Peak memory 204916 kb
Host smart-113f13a8-65bf-4d7f-aa29-a12efd254130
User root
Command /workspace/default/simv +test_timeout_ns=10_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2805129665 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_fifo_reset_
fmt_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.i2c_host_fifo_reset_f
mt.2805129665
Directory /workspace/38.i2c_host_fifo_reset_fmt/latest

Test location /workspace/coverage/default/38.i2c_host_fifo_reset_rx.559338527
Short name T1713
Test name
Test status
Simulation time 133061170 ps
CPU time 3.28 seconds
Started Aug 12 04:45:32 PM PDT 24
Finished Aug 12 04:45:36 PM PDT 24
Peak memory 223436 kb
Host smart-cec3f258-aca3-459a-9db5-a7c19c2a33b8
User root
Command /workspace/default/simv +test_timeout_ns=10_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=559338527 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_fifo_reset_r
x_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.i2c_host_fifo_reset_rx.
559338527
Directory /workspace/38.i2c_host_fifo_reset_rx/latest

Test location /workspace/coverage/default/38.i2c_host_fifo_watermark.1418334707
Short name T85
Test name
Test status
Simulation time 2436476799 ps
CPU time 137.97 seconds
Started Aug 12 04:45:25 PM PDT 24
Finished Aug 12 04:47:43 PM PDT 24
Peak memory 712332 kb
Host smart-b326a9de-6057-44b4-839e-c055b4d57a61
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1418334707 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_fifo_watermark_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.i2c_host_fifo_watermark.1418334707
Directory /workspace/38.i2c_host_fifo_watermark/latest

Test location /workspace/coverage/default/38.i2c_host_may_nack.3929944420
Short name T1329
Test name
Test status
Simulation time 2252855148 ps
CPU time 5.67 seconds
Started Aug 12 04:45:30 PM PDT 24
Finished Aug 12 04:45:35 PM PDT 24
Peak memory 205368 kb
Host smart-3a13aaea-dbc8-4436-ab7a-32fcbd6ff3ec
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3929944420 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_may_nack_vseq +en_cov=1 -cm line+cond+f
sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.i2c_host_may_nack.3929944420
Directory /workspace/38.i2c_host_may_nack/latest

Test location /workspace/coverage/default/38.i2c_host_mode_toggle.2382766624
Short name T1510
Test name
Test status
Simulation time 285462528 ps
CPU time 5.43 seconds
Started Aug 12 04:45:34 PM PDT 24
Finished Aug 12 04:45:40 PM PDT 24
Peak memory 205188 kb
Host smart-e6e68082-449d-4caa-8312-f47990c3c1cb
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2382766624 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_mode_toggle_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.i2c_host_mode_toggle.2382766624
Directory /workspace/38.i2c_host_mode_toggle/latest

Test location /workspace/coverage/default/38.i2c_host_override.1750513337
Short name T689
Test name
Test status
Simulation time 20173233 ps
CPU time 0.66 seconds
Started Aug 12 04:45:22 PM PDT 24
Finished Aug 12 04:45:23 PM PDT 24
Peak memory 204908 kb
Host smart-92c69ecc-1c6d-4877-9468-bc930fb5de46
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1750513337 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_override_vseq +en_cov=1 -cm line+cond+f
sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.i2c_host_override.1750513337
Directory /workspace/38.i2c_host_override/latest

Test location /workspace/coverage/default/38.i2c_host_perf.1860120756
Short name T1721
Test name
Test status
Simulation time 12447533292 ps
CPU time 107.31 seconds
Started Aug 12 04:45:23 PM PDT 24
Finished Aug 12 04:47:11 PM PDT 24
Peak memory 667052 kb
Host smart-fd73b411-beca-47fa-9100-cb54381f5b08
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1860120756 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_perf_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.i2c_host_perf.1860120756
Directory /workspace/38.i2c_host_perf/latest

Test location /workspace/coverage/default/38.i2c_host_perf_precise.3022499932
Short name T1718
Test name
Test status
Simulation time 62491985 ps
CPU time 3.11 seconds
Started Aug 12 04:45:20 PM PDT 24
Finished Aug 12 04:45:23 PM PDT 24
Peak memory 205280 kb
Host smart-121dcad3-372d-4a9f-b799-170eaf528fab
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3022499932 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_perf_precise_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.i2c_host_perf_precise.3022499932
Directory /workspace/38.i2c_host_perf_precise/latest

Test location /workspace/coverage/default/38.i2c_host_smoke.1310201250
Short name T568
Test name
Test status
Simulation time 1689968354 ps
CPU time 26.92 seconds
Started Aug 12 04:45:23 PM PDT 24
Finished Aug 12 04:45:50 PM PDT 24
Peak memory 332284 kb
Host smart-df65b5c2-3ebb-4533-b5c8-2c70b0861cc2
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1310201250 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_smoke_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.i2c_host_smoke.1310201250
Directory /workspace/38.i2c_host_smoke/latest

Test location /workspace/coverage/default/38.i2c_host_stretch_timeout.4282133664
Short name T1243
Test name
Test status
Simulation time 771972960 ps
CPU time 10.59 seconds
Started Aug 12 04:45:23 PM PDT 24
Finished Aug 12 04:45:34 PM PDT 24
Peak memory 221412 kb
Host smart-147e465c-2abc-4987-b2b2-7bfd38e1de7a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4282133664 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_stretch_timeout_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.i2c_host_stretch_timeout.4282133664
Directory /workspace/38.i2c_host_stretch_timeout/latest

Test location /workspace/coverage/default/38.i2c_target_bad_addr.1942065527
Short name T818
Test name
Test status
Simulation time 4002665742 ps
CPU time 5.08 seconds
Started Aug 12 04:45:28 PM PDT 24
Finished Aug 12 04:45:33 PM PDT 24
Peak memory 214276 kb
Host smart-4c23c51c-a8c3-4d96-911f-878651bca109
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +i2c_bad_addr_pct=50 +cdc_instrumentation_enabled=1 +UVM_
NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1942065527 -assert nopostproc
+UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_target_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.
vdb -cm_log /dev/null -cm_name 38.i2c_target_bad_addr.1942065527
Directory /workspace/38.i2c_target_bad_addr/latest

Test location /workspace/coverage/default/38.i2c_target_fifo_reset_acq.1886745378
Short name T1044
Test name
Test status
Simulation time 222918052 ps
CPU time 0.76 seconds
Started Aug 12 04:45:20 PM PDT 24
Finished Aug 12 04:45:21 PM PDT 24
Peak memory 205276 kb
Host smart-1d506265-2b20-4741-8e5e-eb7be86e8f81
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1886745378 -assert nopostproc +UVM_TESTNAME=i2c_bas
e_test +UVM_TEST_SEQ=i2c_target_fifo_reset_acq_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log
/dev/null -cm_name 38.i2c_target_fifo_reset_acq.1886745378
Directory /workspace/38.i2c_target_fifo_reset_acq/latest

Test location /workspace/coverage/default/38.i2c_target_fifo_reset_tx.1470733645
Short name T330
Test name
Test status
Simulation time 642737238 ps
CPU time 1.24 seconds
Started Aug 12 04:45:29 PM PDT 24
Finished Aug 12 04:45:31 PM PDT 24
Peak memory 205284 kb
Host smart-5beab4e1-f8e3-44e2-aca8-7e706d53f56e
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1470733645 -assert nopostproc +UVM_TESTNAME=i2c_bas
e_test +UVM_TEST_SEQ=i2c_target_fifo_reset_tx_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /
dev/null -cm_name 38.i2c_target_fifo_reset_tx.1470733645
Directory /workspace/38.i2c_target_fifo_reset_tx/latest

Test location /workspace/coverage/default/38.i2c_target_fifo_watermarks_acq.857562162
Short name T1127
Test name
Test status
Simulation time 377822189 ps
CPU time 2.33 seconds
Started Aug 12 04:45:30 PM PDT 24
Finished Aug 12 04:45:33 PM PDT 24
Peak memory 205428 kb
Host smart-da661476-3876-460f-b8ee-bbbc16e0d4f2
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=857562162 -assert nopostproc +UVM_TESTNAME=i2c_base
_test +UVM_TEST_SEQ=i2c_target_fifo_watermarks_acq_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_
log /dev/null -cm_name 38.i2c_target_fifo_watermarks_acq.857562162
Directory /workspace/38.i2c_target_fifo_watermarks_acq/latest

Test location /workspace/coverage/default/38.i2c_target_fifo_watermarks_tx.3485366129
Short name T1083
Test name
Test status
Simulation time 139201872 ps
CPU time 1.28 seconds
Started Aug 12 04:45:27 PM PDT 24
Finished Aug 12 04:45:29 PM PDT 24
Peak memory 205280 kb
Host smart-7928f90a-f680-4bdf-8740-3d6d28282bde
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3485366129 -assert nopostproc +UVM_TESTNAME=i2c_bas
e_test +UVM_TEST_SEQ=i2c_target_fifo_watermarks_tx_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_
log /dev/null -cm_name 38.i2c_target_fifo_watermarks_tx.3485366129
Directory /workspace/38.i2c_target_fifo_watermarks_tx/latest

Test location /workspace/coverage/default/38.i2c_target_hrst.2861551113
Short name T1330
Test name
Test status
Simulation time 850937482 ps
CPU time 1.65 seconds
Started Aug 12 04:45:29 PM PDT 24
Finished Aug 12 04:45:31 PM PDT 24
Peak memory 213720 kb
Host smart-6f33da59-0c77-4ad7-9350-fc819ee13c08
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2861551113 -assert nopostproc +UVM_TESTNAME=i2c_bas
e_test +UVM_TEST_SEQ=i2c_target_hrst_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null
-cm_name 38.i2c_target_hrst.2861551113
Directory /workspace/38.i2c_target_hrst/latest

Test location /workspace/coverage/default/38.i2c_target_intr_smoke.4211954604
Short name T906
Test name
Test status
Simulation time 3950024352 ps
CPU time 5.79 seconds
Started Aug 12 04:45:32 PM PDT 24
Finished Aug 12 04:45:38 PM PDT 24
Peak memory 221952 kb
Host smart-dce508c5-c2c4-4286-8c65-ca3a1e442133
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=200_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VER
BOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4211954604 -assert nopostproc +UVM_TESTNAME=i2c_ba
se_test +UVM_TEST_SEQ=i2c_target_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/nul
l -cm_name 38.i2c_target_intr_smoke.4211954604
Directory /workspace/38.i2c_target_intr_smoke/latest

Test location /workspace/coverage/default/38.i2c_target_intr_stress_wr.3541271439
Short name T950
Test name
Test status
Simulation time 11798348030 ps
CPU time 75.04 seconds
Started Aug 12 04:45:20 PM PDT 24
Finished Aug 12 04:46:35 PM PDT 24
Peak memory 1317720 kb
Host smart-7f54e3f2-b74e-4bfc-b7da-1ba11cd488df
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=600_000_000 +use_intr_handler=1 +slow_acq=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNO
TES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3541271439 -assert nopostproc +UVM_TES
TNAME=i2c_base_test +UVM_TEST_SEQ=i2c_target_stress_wr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb
-cm_log /dev/null -cm_name 38.i2c_target_intr_stress_wr.3541271439
Directory /workspace/38.i2c_target_intr_stress_wr/latest

Test location /workspace/coverage/default/38.i2c_target_nack_acqfull.4230404700
Short name T1115
Test name
Test status
Simulation time 2111023768 ps
CPU time 2.99 seconds
Started Aug 12 04:45:30 PM PDT 24
Finished Aug 12 04:45:34 PM PDT 24
Peak memory 213748 kb
Host smart-1a404419-e1b7-4d03-9958-7679514d509e
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4230404700 -assert nopostproc +UVM_TESTNAME=i2c_bas
e_test +UVM_TEST_SEQ=i2c_target_nack_acqfull_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /d
ev/null -cm_name 38.i2c_target_nack_acqfull.4230404700
Directory /workspace/38.i2c_target_nack_acqfull/latest

Test location /workspace/coverage/default/38.i2c_target_nack_acqfull_addr.2381466753
Short name T53
Test name
Test status
Simulation time 2935967441 ps
CPU time 2.91 seconds
Started Aug 12 04:45:31 PM PDT 24
Finished Aug 12 04:45:34 PM PDT 24
Peak memory 205624 kb
Host smart-7f349a76-b1aa-4841-a3ed-28687c3d0091
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2381466753 -assert nopostproc +UVM_TESTNAME=i2c_bas
e_test +UVM_TEST_SEQ=i2c_target_nack_acqfull_addr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_l
og /dev/null -cm_name 38.i2c_target_nack_acqfull_addr.2381466753
Directory /workspace/38.i2c_target_nack_acqfull_addr/latest

Test location /workspace/coverage/default/38.i2c_target_nack_txstretch.922554387
Short name T1100
Test name
Test status
Simulation time 137272026 ps
CPU time 1.59 seconds
Started Aug 12 04:45:30 PM PDT 24
Finished Aug 12 04:45:32 PM PDT 24
Peak memory 222472 kb
Host smart-094046a5-920b-43be-a011-cf3f3a9d45e5
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=922554387 -assert nopostproc +UVM_TESTNAME=i2c_base
_test +UVM_TEST_SEQ=i2c_target_nack_txstretch_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /
dev/null -cm_name 38.i2c_target_nack_txstretch.922554387
Directory /workspace/38.i2c_target_nack_txstretch/latest

Test location /workspace/coverage/default/38.i2c_target_perf.3182774233
Short name T675
Test name
Test status
Simulation time 2758569795 ps
CPU time 7.3 seconds
Started Aug 12 04:45:28 PM PDT 24
Finished Aug 12 04:45:35 PM PDT 24
Peak memory 221900 kb
Host smart-46706041-4693-4a38-be22-84496e881e4b
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3182774233 -assert nopostproc +UVM_TESTNAME=i2c_bas
e_test +UVM_TEST_SEQ=i2c_target_perf_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null
-cm_name 38.i2c_target_perf.3182774233
Directory /workspace/38.i2c_target_perf/latest

Test location /workspace/coverage/default/38.i2c_target_smbus_maxlen.3179519831
Short name T1009
Test name
Test status
Simulation time 531821129 ps
CPU time 2.14 seconds
Started Aug 12 04:45:27 PM PDT 24
Finished Aug 12 04:45:29 PM PDT 24
Peak memory 205240 kb
Host smart-116bfa7e-4c68-4d48-a22f-fbc983e9dfce
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3179519831 -assert nopostproc +UVM_TESTNAME=i2c_bas
e_test +UVM_TEST_SEQ=i2c_target_smbus_maxlen_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /d
ev/null -cm_name 38.i2c_target_smbus_maxlen.3179519831
Directory /workspace/38.i2c_target_smbus_maxlen/latest

Test location /workspace/coverage/default/38.i2c_target_smoke.1854702081
Short name T86
Test name
Test status
Simulation time 1886771661 ps
CPU time 28.48 seconds
Started Aug 12 04:45:19 PM PDT 24
Finished Aug 12 04:45:48 PM PDT 24
Peak memory 221872 kb
Host smart-89368823-b078-450f-a23d-38300b3568db
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=100_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licq
ueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1854702081 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SE
Q=i2c_target_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.i2c_ta
rget_smoke.1854702081
Directory /workspace/38.i2c_target_smoke/latest

Test location /workspace/coverage/default/38.i2c_target_stress_all.3841658770
Short name T947
Test name
Test status
Simulation time 10541684861 ps
CPU time 29.61 seconds
Started Aug 12 04:45:27 PM PDT 24
Finished Aug 12 04:45:57 PM PDT 24
Peak memory 231216 kb
Host smart-ce69984b-590f-4389-b97d-a3c02317a279
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=300_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VER
BOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3841658770 -assert nopostproc +UVM_TESTNAME=i2c_ba
se_test +UVM_TEST_SEQ=i2c_target_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /de
v/null -cm_name 38.i2c_target_stress_all.3841658770
Directory /workspace/38.i2c_target_stress_all/latest

Test location /workspace/coverage/default/38.i2c_target_stress_rd.198143115
Short name T1361
Test name
Test status
Simulation time 1381217376 ps
CPU time 5.63 seconds
Started Aug 12 04:45:32 PM PDT 24
Finished Aug 12 04:45:38 PM PDT 24
Peak memory 207180 kb
Host smart-6165a882-5116-47d2-88d8-ecaa8d28b34d
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=100_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licq
ueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=198143115 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ
=i2c_target_stress_rd_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.i2c
_target_stress_rd.198143115
Directory /workspace/38.i2c_target_stress_rd/latest

Test location /workspace/coverage/default/38.i2c_target_stress_wr.3809281821
Short name T1066
Test name
Test status
Simulation time 57388557887 ps
CPU time 1855.23 seconds
Started Aug 12 04:45:22 PM PDT 24
Finished Aug 12 05:16:18 PM PDT 24
Peak memory 9159428 kb
Host smart-0006bbac-994a-4d94-a0a5-e3fdd2253925
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=600_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licq
ueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3809281821 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SE
Q=i2c_target_stress_wr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.i2
c_target_stress_wr.3809281821
Directory /workspace/38.i2c_target_stress_wr/latest

Test location /workspace/coverage/default/38.i2c_target_stretch.4098539703
Short name T1033
Test name
Test status
Simulation time 2705303370 ps
CPU time 53.32 seconds
Started Aug 12 04:45:28 PM PDT 24
Finished Aug 12 04:46:22 PM PDT 24
Peak memory 804668 kb
Host smart-0b9a5e8b-d867-46e3-9c64-3bb5b511defc
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=400_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licq
ueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4098539703 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SE
Q=i2c_target_stretch_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.i2c_
target_stretch.4098539703
Directory /workspace/38.i2c_target_stretch/latest

Test location /workspace/coverage/default/38.i2c_target_timeout.1500773625
Short name T1150
Test name
Test status
Simulation time 2819336770 ps
CPU time 6.89 seconds
Started Aug 12 04:45:25 PM PDT 24
Finished Aug 12 04:45:32 PM PDT 24
Peak memory 213768 kb
Host smart-eaa8dfb3-9d46-4ff8-b854-c1161a536a8b
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=50_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1500773625 -assert nopostproc +UVM_TESTNAME=i2c_bas
e_test +UVM_TEST_SEQ=i2c_target_timeout_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/nu
ll -cm_name 38.i2c_target_timeout.1500773625
Directory /workspace/38.i2c_target_timeout/latest

Test location /workspace/coverage/default/38.i2c_target_tx_stretch_ctrl.2992179309
Short name T904
Test name
Test status
Simulation time 496201633 ps
CPU time 6.95 seconds
Started Aug 12 04:45:34 PM PDT 24
Finished Aug 12 04:45:41 PM PDT 24
Peak memory 206544 kb
Host smart-9ba2e355-01e8-4531-8b7f-dc7c227ace14
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2992179309 -assert nopostproc +UVM_TESTNAME=i2c_bas
e_test +UVM_TEST_SEQ=i2c_target_tx_stretch_ctrl_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log
/dev/null -cm_name 38.i2c_target_tx_stretch_ctrl.2992179309
Directory /workspace/38.i2c_target_tx_stretch_ctrl/latest

Test location /workspace/coverage/default/39.i2c_alert_test.1764106029
Short name T1503
Test name
Test status
Simulation time 34733571 ps
CPU time 0.66 seconds
Started Aug 12 04:45:37 PM PDT 24
Finished Aug 12 04:45:38 PM PDT 24
Peak memory 204516 kb
Host smart-1382ac4e-ac25-4e78-a225-9c358cf5d04c
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1764106029 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_common_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.i2c_alert_test.1764106029
Directory /workspace/39.i2c_alert_test/latest

Test location /workspace/coverage/default/39.i2c_host_error_intr.3150473086
Short name T1055
Test name
Test status
Simulation time 1673964090 ps
CPU time 4.8 seconds
Started Aug 12 04:45:27 PM PDT 24
Finished Aug 12 04:45:32 PM PDT 24
Peak memory 214500 kb
Host smart-36c4f9ef-38e0-42cb-8029-73920351ff66
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3150473086 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_error_intr_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.i2c_host_error_intr.3150473086
Directory /workspace/39.i2c_host_error_intr/latest

Test location /workspace/coverage/default/39.i2c_host_fifo_fmt_empty.1335173926
Short name T1515
Test name
Test status
Simulation time 280870153 ps
CPU time 15.43 seconds
Started Aug 12 04:45:29 PM PDT 24
Finished Aug 12 04:45:45 PM PDT 24
Peak memory 265548 kb
Host smart-8ea6cb88-3b79-42b4-8c48-2090fa0fad86
User root
Command /workspace/default/simv +test_timeout_ns=10_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1335173926 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_fifo_fmt_em
pty_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.i2c_host_fifo_fmt_emp
ty.1335173926
Directory /workspace/39.i2c_host_fifo_fmt_empty/latest

Test location /workspace/coverage/default/39.i2c_host_fifo_full.289511843
Short name T39
Test name
Test status
Simulation time 1759969461 ps
CPU time 45.93 seconds
Started Aug 12 04:45:27 PM PDT 24
Finished Aug 12 04:46:13 PM PDT 24
Peak memory 433204 kb
Host smart-a99e1ff7-a569-4a5a-bbbd-82984ec6a28a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=289511843 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_fifo_full_vseq +en_cov=1 -cm line+cond+f
sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.i2c_host_fifo_full.289511843
Directory /workspace/39.i2c_host_fifo_full/latest

Test location /workspace/coverage/default/39.i2c_host_fifo_overflow.2218396531
Short name T1043
Test name
Test status
Simulation time 6959233203 ps
CPU time 43.78 seconds
Started Aug 12 04:45:28 PM PDT 24
Finished Aug 12 04:46:12 PM PDT 24
Peak memory 506684 kb
Host smart-ca15bf8c-8049-4678-bcd3-d0817f096f94
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2218396531 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_fifo_overflow_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.i2c_host_fifo_overflow.2218396531
Directory /workspace/39.i2c_host_fifo_overflow/latest

Test location /workspace/coverage/default/39.i2c_host_fifo_reset_fmt.3924655003
Short name T669
Test name
Test status
Simulation time 144484182 ps
CPU time 1.02 seconds
Started Aug 12 04:45:28 PM PDT 24
Finished Aug 12 04:45:29 PM PDT 24
Peak memory 205064 kb
Host smart-689750b2-8c89-499a-8e67-cdc695d4f3a7
User root
Command /workspace/default/simv +test_timeout_ns=10_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3924655003 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_fifo_reset_
fmt_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.i2c_host_fifo_reset_f
mt.3924655003
Directory /workspace/39.i2c_host_fifo_reset_fmt/latest

Test location /workspace/coverage/default/39.i2c_host_fifo_reset_rx.375432736
Short name T781
Test name
Test status
Simulation time 168227708 ps
CPU time 3.23 seconds
Started Aug 12 04:45:30 PM PDT 24
Finished Aug 12 04:45:33 PM PDT 24
Peak memory 205196 kb
Host smart-9f137b91-0474-4e36-a26c-e951b0e093fc
User root
Command /workspace/default/simv +test_timeout_ns=10_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=375432736 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_fifo_reset_r
x_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.i2c_host_fifo_reset_rx.
375432736
Directory /workspace/39.i2c_host_fifo_reset_rx/latest

Test location /workspace/coverage/default/39.i2c_host_fifo_watermark.1572781920
Short name T1120
Test name
Test status
Simulation time 3383993227 ps
CPU time 231.49 seconds
Started Aug 12 04:45:31 PM PDT 24
Finished Aug 12 04:49:22 PM PDT 24
Peak memory 1022716 kb
Host smart-3193ca9b-ba86-419c-8c34-daec1c01bcd5
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1572781920 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_fifo_watermark_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.i2c_host_fifo_watermark.1572781920
Directory /workspace/39.i2c_host_fifo_watermark/latest

Test location /workspace/coverage/default/39.i2c_host_may_nack.3131288511
Short name T292
Test name
Test status
Simulation time 612397243 ps
CPU time 9.4 seconds
Started Aug 12 04:45:39 PM PDT 24
Finished Aug 12 04:45:48 PM PDT 24
Peak memory 205192 kb
Host smart-6e40cf34-0ccb-492e-86a6-8c957bcbeefe
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3131288511 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_may_nack_vseq +en_cov=1 -cm line+cond+f
sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.i2c_host_may_nack.3131288511
Directory /workspace/39.i2c_host_may_nack/latest

Test location /workspace/coverage/default/39.i2c_host_override.3702832138
Short name T878
Test name
Test status
Simulation time 26262263 ps
CPU time 0.67 seconds
Started Aug 12 04:45:32 PM PDT 24
Finished Aug 12 04:45:32 PM PDT 24
Peak memory 204892 kb
Host smart-5a2b2667-536a-48bd-a46e-95b2e176a122
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3702832138 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_override_vseq +en_cov=1 -cm line+cond+f
sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.i2c_host_override.3702832138
Directory /workspace/39.i2c_host_override/latest

Test location /workspace/coverage/default/39.i2c_host_perf.3868540397
Short name T829
Test name
Test status
Simulation time 13498989876 ps
CPU time 161.51 seconds
Started Aug 12 04:45:28 PM PDT 24
Finished Aug 12 04:48:10 PM PDT 24
Peak memory 617940 kb
Host smart-a43c5d9d-39af-48a4-a1be-964047f79ff6
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3868540397 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_perf_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.i2c_host_perf.3868540397
Directory /workspace/39.i2c_host_perf/latest

Test location /workspace/coverage/default/39.i2c_host_perf_precise.2042482193
Short name T1105
Test name
Test status
Simulation time 222502005 ps
CPU time 9.25 seconds
Started Aug 12 04:45:29 PM PDT 24
Finished Aug 12 04:45:39 PM PDT 24
Peak memory 221388 kb
Host smart-9d4018a1-7837-4fef-9a0a-f484666bd6fb
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2042482193 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_perf_precise_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.i2c_host_perf_precise.2042482193
Directory /workspace/39.i2c_host_perf_precise/latest

Test location /workspace/coverage/default/39.i2c_host_smoke.3159145145
Short name T570
Test name
Test status
Simulation time 7142927083 ps
CPU time 86.88 seconds
Started Aug 12 04:45:30 PM PDT 24
Finished Aug 12 04:46:57 PM PDT 24
Peak memory 405668 kb
Host smart-e6500d7b-f79d-4b5a-8cdb-fd53737c0e78
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3159145145 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_smoke_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.i2c_host_smoke.3159145145
Directory /workspace/39.i2c_host_smoke/latest

Test location /workspace/coverage/default/39.i2c_host_stretch_timeout.2116648688
Short name T1580
Test name
Test status
Simulation time 1068086518 ps
CPU time 10.46 seconds
Started Aug 12 04:45:28 PM PDT 24
Finished Aug 12 04:45:39 PM PDT 24
Peak memory 220700 kb
Host smart-92216710-40bb-4fb4-bc05-4ab45f000a2f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2116648688 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_stretch_timeout_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.i2c_host_stretch_timeout.2116648688
Directory /workspace/39.i2c_host_stretch_timeout/latest

Test location /workspace/coverage/default/39.i2c_target_bad_addr.1055428779
Short name T416
Test name
Test status
Simulation time 897648452 ps
CPU time 4.83 seconds
Started Aug 12 04:45:37 PM PDT 24
Finished Aug 12 04:45:42 PM PDT 24
Peak memory 213648 kb
Host smart-ad2e08d1-c3f3-4548-940f-1aae80ea2651
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +i2c_bad_addr_pct=50 +cdc_instrumentation_enabled=1 +UVM_
NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1055428779 -assert nopostproc
+UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_target_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.
vdb -cm_log /dev/null -cm_name 39.i2c_target_bad_addr.1055428779
Directory /workspace/39.i2c_target_bad_addr/latest

Test location /workspace/coverage/default/39.i2c_target_fifo_reset_acq.3897839634
Short name T1335
Test name
Test status
Simulation time 196564609 ps
CPU time 0.8 seconds
Started Aug 12 04:45:37 PM PDT 24
Finished Aug 12 04:45:38 PM PDT 24
Peak memory 205220 kb
Host smart-d9a09e64-4501-4c0c-9536-4a721cdfe2c3
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3897839634 -assert nopostproc +UVM_TESTNAME=i2c_bas
e_test +UVM_TEST_SEQ=i2c_target_fifo_reset_acq_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log
/dev/null -cm_name 39.i2c_target_fifo_reset_acq.3897839634
Directory /workspace/39.i2c_target_fifo_reset_acq/latest

Test location /workspace/coverage/default/39.i2c_target_fifo_reset_tx.24307691
Short name T891
Test name
Test status
Simulation time 199001321 ps
CPU time 1.28 seconds
Started Aug 12 04:45:39 PM PDT 24
Finished Aug 12 04:45:41 PM PDT 24
Peak memory 205252 kb
Host smart-37a22afb-2968-401b-82d2-f8b0616ad386
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=24307691 -assert nopostproc +UVM_TESTNAME=i2c_base_
test +UVM_TEST_SEQ=i2c_target_fifo_reset_tx_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /de
v/null -cm_name 39.i2c_target_fifo_reset_tx.24307691
Directory /workspace/39.i2c_target_fifo_reset_tx/latest

Test location /workspace/coverage/default/39.i2c_target_fifo_watermarks_acq.3069099408
Short name T805
Test name
Test status
Simulation time 2940888069 ps
CPU time 2.69 seconds
Started Aug 12 04:45:36 PM PDT 24
Finished Aug 12 04:45:39 PM PDT 24
Peak memory 205548 kb
Host smart-09caa473-c7c9-4407-864d-54e6af292dea
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3069099408 -assert nopostproc +UVM_TESTNAME=i2c_bas
e_test +UVM_TEST_SEQ=i2c_target_fifo_watermarks_acq_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm
_log /dev/null -cm_name 39.i2c_target_fifo_watermarks_acq.3069099408
Directory /workspace/39.i2c_target_fifo_watermarks_acq/latest

Test location /workspace/coverage/default/39.i2c_target_fifo_watermarks_tx.1510674704
Short name T1564
Test name
Test status
Simulation time 151914342 ps
CPU time 1.47 seconds
Started Aug 12 04:45:35 PM PDT 24
Finished Aug 12 04:45:37 PM PDT 24
Peak memory 205264 kb
Host smart-714b3026-bad6-4f96-b558-c4c65d1341cb
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1510674704 -assert nopostproc +UVM_TESTNAME=i2c_bas
e_test +UVM_TEST_SEQ=i2c_target_fifo_watermarks_tx_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_
log /dev/null -cm_name 39.i2c_target_fifo_watermarks_tx.1510674704
Directory /workspace/39.i2c_target_fifo_watermarks_tx/latest

Test location /workspace/coverage/default/39.i2c_target_intr_smoke.2619369476
Short name T1011
Test name
Test status
Simulation time 3728848041 ps
CPU time 4.96 seconds
Started Aug 12 04:45:29 PM PDT 24
Finished Aug 12 04:45:34 PM PDT 24
Peak memory 218476 kb
Host smart-51b4b9b1-000a-4865-aa12-55c744e5d5a8
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=200_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VER
BOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2619369476 -assert nopostproc +UVM_TESTNAME=i2c_ba
se_test +UVM_TEST_SEQ=i2c_target_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/nul
l -cm_name 39.i2c_target_intr_smoke.2619369476
Directory /workspace/39.i2c_target_intr_smoke/latest

Test location /workspace/coverage/default/39.i2c_target_intr_stress_wr.2726631524
Short name T329
Test name
Test status
Simulation time 19664728233 ps
CPU time 45.45 seconds
Started Aug 12 04:45:34 PM PDT 24
Finished Aug 12 04:46:20 PM PDT 24
Peak memory 746136 kb
Host smart-87bcdbc1-e88e-4727-b584-b6fc13504786
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=600_000_000 +use_intr_handler=1 +slow_acq=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNO
TES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2726631524 -assert nopostproc +UVM_TES
TNAME=i2c_base_test +UVM_TEST_SEQ=i2c_target_stress_wr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb
-cm_log /dev/null -cm_name 39.i2c_target_intr_stress_wr.2726631524
Directory /workspace/39.i2c_target_intr_stress_wr/latest

Test location /workspace/coverage/default/39.i2c_target_nack_acqfull.808321796
Short name T922
Test name
Test status
Simulation time 1198314225 ps
CPU time 3.2 seconds
Started Aug 12 04:45:39 PM PDT 24
Finished Aug 12 04:45:42 PM PDT 24
Peak memory 213628 kb
Host smart-0aab6ad5-a014-471a-81b7-fc7859c46cd5
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=808321796 -assert nopostproc +UVM_TESTNAME=i2c_base
_test +UVM_TEST_SEQ=i2c_target_nack_acqfull_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /de
v/null -cm_name 39.i2c_target_nack_acqfull.808321796
Directory /workspace/39.i2c_target_nack_acqfull/latest

Test location /workspace/coverage/default/39.i2c_target_nack_acqfull_addr.3973345608
Short name T1655
Test name
Test status
Simulation time 6647612790 ps
CPU time 2.84 seconds
Started Aug 12 04:45:38 PM PDT 24
Finished Aug 12 04:45:41 PM PDT 24
Peak memory 205616 kb
Host smart-976fa9db-ae04-4fe5-b7a8-f604e6906885
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3973345608 -assert nopostproc +UVM_TESTNAME=i2c_bas
e_test +UVM_TEST_SEQ=i2c_target_nack_acqfull_addr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_l
og /dev/null -cm_name 39.i2c_target_nack_acqfull_addr.3973345608
Directory /workspace/39.i2c_target_nack_acqfull_addr/latest

Test location /workspace/coverage/default/39.i2c_target_nack_txstretch.2684461231
Short name T1307
Test name
Test status
Simulation time 576098083 ps
CPU time 1.32 seconds
Started Aug 12 04:45:37 PM PDT 24
Finished Aug 12 04:45:39 PM PDT 24
Peak memory 222272 kb
Host smart-e1c46614-e99c-4d23-8fc0-9eea0ac293d2
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2684461231 -assert nopostproc +UVM_TESTNAME=i2c_bas
e_test +UVM_TEST_SEQ=i2c_target_nack_txstretch_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log
/dev/null -cm_name 39.i2c_target_nack_txstretch.2684461231
Directory /workspace/39.i2c_target_nack_txstretch/latest

Test location /workspace/coverage/default/39.i2c_target_perf.1776507370
Short name T1491
Test name
Test status
Simulation time 720121245 ps
CPU time 5.37 seconds
Started Aug 12 04:45:36 PM PDT 24
Finished Aug 12 04:45:42 PM PDT 24
Peak memory 219060 kb
Host smart-c5ac52c8-58e4-48d7-a470-7c4618a4f3b4
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1776507370 -assert nopostproc +UVM_TESTNAME=i2c_bas
e_test +UVM_TEST_SEQ=i2c_target_perf_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null
-cm_name 39.i2c_target_perf.1776507370
Directory /workspace/39.i2c_target_perf/latest

Test location /workspace/coverage/default/39.i2c_target_smbus_maxlen.3470917435
Short name T1618
Test name
Test status
Simulation time 482187648 ps
CPU time 2.38 seconds
Started Aug 12 04:45:38 PM PDT 24
Finished Aug 12 04:45:41 PM PDT 24
Peak memory 205240 kb
Host smart-caf79045-26aa-44e5-a0d3-f1a55d7bfff0
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3470917435 -assert nopostproc +UVM_TESTNAME=i2c_bas
e_test +UVM_TEST_SEQ=i2c_target_smbus_maxlen_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /d
ev/null -cm_name 39.i2c_target_smbus_maxlen.3470917435
Directory /workspace/39.i2c_target_smbus_maxlen/latest

Test location /workspace/coverage/default/39.i2c_target_smoke.217586722
Short name T87
Test name
Test status
Simulation time 1195834527 ps
CPU time 36.41 seconds
Started Aug 12 04:45:27 PM PDT 24
Finished Aug 12 04:46:04 PM PDT 24
Peak memory 218196 kb
Host smart-9b551df6-77c6-44fc-8092-4ee0710f56e3
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=100_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licq
ueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=217586722 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ
=i2c_target_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.i2c_tar
get_smoke.217586722
Directory /workspace/39.i2c_target_smoke/latest

Test location /workspace/coverage/default/39.i2c_target_stress_all.1113287157
Short name T788
Test name
Test status
Simulation time 56335882634 ps
CPU time 621.49 seconds
Started Aug 12 04:45:37 PM PDT 24
Finished Aug 12 04:55:59 PM PDT 24
Peak memory 3868844 kb
Host smart-8fc09c81-ed73-48e0-8b7a-399bfd744726
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=300_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VER
BOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1113287157 -assert nopostproc +UVM_TESTNAME=i2c_ba
se_test +UVM_TEST_SEQ=i2c_target_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /de
v/null -cm_name 39.i2c_target_stress_all.1113287157
Directory /workspace/39.i2c_target_stress_all/latest

Test location /workspace/coverage/default/39.i2c_target_stress_rd.465814731
Short name T531
Test name
Test status
Simulation time 4941610400 ps
CPU time 57.4 seconds
Started Aug 12 04:45:31 PM PDT 24
Finished Aug 12 04:46:28 PM PDT 24
Peak memory 220196 kb
Host smart-8a2fb98e-cafe-4578-a10d-ffdc88604aaa
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=100_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licq
ueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=465814731 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ
=i2c_target_stress_rd_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.i2c
_target_stress_rd.465814731
Directory /workspace/39.i2c_target_stress_rd/latest

Test location /workspace/coverage/default/39.i2c_target_stress_wr.857890630
Short name T390
Test name
Test status
Simulation time 52973198649 ps
CPU time 177.15 seconds
Started Aug 12 04:45:29 PM PDT 24
Finished Aug 12 04:48:27 PM PDT 24
Peak memory 1968492 kb
Host smart-d7ed2144-c761-4b59-9ef7-4be1867baa0c
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=600_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licq
ueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=857890630 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ
=i2c_target_stress_wr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.i2c
_target_stress_wr.857890630
Directory /workspace/39.i2c_target_stress_wr/latest

Test location /workspace/coverage/default/39.i2c_target_stretch.344310889
Short name T325
Test name
Test status
Simulation time 4957450969 ps
CPU time 12.44 seconds
Started Aug 12 04:45:34 PM PDT 24
Finished Aug 12 04:45:47 PM PDT 24
Peak memory 387492 kb
Host smart-c6db5a24-47a6-44ba-83c8-7be2d13572a9
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=400_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licq
ueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=344310889 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ
=i2c_target_stretch_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.i2c_t
arget_stretch.344310889
Directory /workspace/39.i2c_target_stretch/latest

Test location /workspace/coverage/default/39.i2c_target_timeout.1437738868
Short name T731
Test name
Test status
Simulation time 1358077249 ps
CPU time 7.77 seconds
Started Aug 12 04:45:31 PM PDT 24
Finished Aug 12 04:45:39 PM PDT 24
Peak memory 229988 kb
Host smart-5df0adc7-a72a-4e0d-8fec-c8848efb2f2b
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=50_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1437738868 -assert nopostproc +UVM_TESTNAME=i2c_bas
e_test +UVM_TEST_SEQ=i2c_target_timeout_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/nu
ll -cm_name 39.i2c_target_timeout.1437738868
Directory /workspace/39.i2c_target_timeout/latest

Test location /workspace/coverage/default/39.i2c_target_tx_stretch_ctrl.825363643
Short name T456
Test name
Test status
Simulation time 152433108 ps
CPU time 2.52 seconds
Started Aug 12 04:45:38 PM PDT 24
Finished Aug 12 04:45:40 PM PDT 24
Peak memory 205436 kb
Host smart-b4ef1954-ce54-4e74-afc4-d52010562528
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=825363643 -assert nopostproc +UVM_TESTNAME=i2c_base
_test +UVM_TEST_SEQ=i2c_target_tx_stretch_ctrl_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log
/dev/null -cm_name 39.i2c_target_tx_stretch_ctrl.825363643
Directory /workspace/39.i2c_target_tx_stretch_ctrl/latest

Test location /workspace/coverage/default/4.i2c_alert_test.179305242
Short name T680
Test name
Test status
Simulation time 71173042 ps
CPU time 0.63 seconds
Started Aug 12 04:41:11 PM PDT 24
Finished Aug 12 04:41:12 PM PDT 24
Peak memory 204480 kb
Host smart-63362d57-1d58-4fad-8a6a-bf0abcd71354
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=179305242 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_common_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.i2c_alert_test.179305242
Directory /workspace/4.i2c_alert_test/latest

Test location /workspace/coverage/default/4.i2c_host_error_intr.3415208886
Short name T1046
Test name
Test status
Simulation time 259891394 ps
CPU time 3.58 seconds
Started Aug 12 04:41:07 PM PDT 24
Finished Aug 12 04:41:11 PM PDT 24
Peak memory 233868 kb
Host smart-d7f2e4c8-e310-45ad-860e-349fad8838dc
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3415208886 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_error_intr_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.i2c_host_error_intr.3415208886
Directory /workspace/4.i2c_host_error_intr/latest

Test location /workspace/coverage/default/4.i2c_host_fifo_fmt_empty.3596059911
Short name T578
Test name
Test status
Simulation time 2076821274 ps
CPU time 7.19 seconds
Started Aug 12 04:41:04 PM PDT 24
Finished Aug 12 04:41:11 PM PDT 24
Peak memory 263572 kb
Host smart-ee58bcc0-56e0-408c-9353-ea8a404d7b8f
User root
Command /workspace/default/simv +test_timeout_ns=10_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3596059911 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_fifo_fmt_em
pty_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.i2c_host_fifo_fmt_empt
y.3596059911
Directory /workspace/4.i2c_host_fifo_fmt_empty/latest

Test location /workspace/coverage/default/4.i2c_host_fifo_full.1041352768
Short name T495
Test name
Test status
Simulation time 8896314965 ps
CPU time 238.57 seconds
Started Aug 12 04:41:05 PM PDT 24
Finished Aug 12 04:45:03 PM PDT 24
Peak memory 634152 kb
Host smart-66d5e4b9-d435-4da6-ad29-effa09cfdec0
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1041352768 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_fifo_full_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.i2c_host_fifo_full.1041352768
Directory /workspace/4.i2c_host_fifo_full/latest

Test location /workspace/coverage/default/4.i2c_host_fifo_overflow.2950576812
Short name T890
Test name
Test status
Simulation time 5272379823 ps
CPU time 203.67 seconds
Started Aug 12 04:41:03 PM PDT 24
Finished Aug 12 04:44:27 PM PDT 24
Peak memory 836316 kb
Host smart-7ae92c4b-f5de-46bc-b572-73d604757ffb
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2950576812 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_fifo_overflow_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.i2c_host_fifo_overflow.2950576812
Directory /workspace/4.i2c_host_fifo_overflow/latest

Test location /workspace/coverage/default/4.i2c_host_fifo_reset_fmt.445188315
Short name T940
Test name
Test status
Simulation time 119903181 ps
CPU time 1.29 seconds
Started Aug 12 04:41:08 PM PDT 24
Finished Aug 12 04:41:10 PM PDT 24
Peak memory 205188 kb
Host smart-d01d4c71-448d-4f88-9f78-7d8d513851f5
User root
Command /workspace/default/simv +test_timeout_ns=10_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=445188315 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_fifo_reset_f
mt_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.i2c_host_fifo_reset_fmt
.445188315
Directory /workspace/4.i2c_host_fifo_reset_fmt/latest

Test location /workspace/coverage/default/4.i2c_host_fifo_reset_rx.1005491120
Short name T743
Test name
Test status
Simulation time 228822597 ps
CPU time 3.2 seconds
Started Aug 12 04:41:07 PM PDT 24
Finished Aug 12 04:41:10 PM PDT 24
Peak memory 220808 kb
Host smart-03cb64de-6c60-40fb-b8c1-b828f1dae5c5
User root
Command /workspace/default/simv +test_timeout_ns=10_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1005491120 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_fifo_reset_
rx_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.i2c_host_fifo_reset_rx.
1005491120
Directory /workspace/4.i2c_host_fifo_reset_rx/latest

Test location /workspace/coverage/default/4.i2c_host_fifo_watermark.926103474
Short name T1289
Test name
Test status
Simulation time 3468340295 ps
CPU time 76.44 seconds
Started Aug 12 04:41:06 PM PDT 24
Finished Aug 12 04:42:22 PM PDT 24
Peak memory 953424 kb
Host smart-b87ec0fe-66e2-4525-9142-eeccb08a023f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=926103474 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_fifo_watermark_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.i2c_host_fifo_watermark.926103474
Directory /workspace/4.i2c_host_fifo_watermark/latest

Test location /workspace/coverage/default/4.i2c_host_override.971296714
Short name T1714
Test name
Test status
Simulation time 30486917 ps
CPU time 0.74 seconds
Started Aug 12 04:41:08 PM PDT 24
Finished Aug 12 04:41:09 PM PDT 24
Peak memory 204944 kb
Host smart-9c61a7b4-5175-4e91-a802-7305e132de4b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=971296714 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_override_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.i2c_host_override.971296714
Directory /workspace/4.i2c_host_override/latest

Test location /workspace/coverage/default/4.i2c_host_perf.2999124315
Short name T1455
Test name
Test status
Simulation time 5770818335 ps
CPU time 89.7 seconds
Started Aug 12 04:41:05 PM PDT 24
Finished Aug 12 04:42:35 PM PDT 24
Peak memory 576264 kb
Host smart-a234911e-0e52-47bb-8901-71ff4a13f8f2
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2999124315 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_perf_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.i2c_host_perf.2999124315
Directory /workspace/4.i2c_host_perf/latest

Test location /workspace/coverage/default/4.i2c_host_perf_precise.2324247481
Short name T870
Test name
Test status
Simulation time 687639995 ps
CPU time 3.27 seconds
Started Aug 12 04:41:02 PM PDT 24
Finished Aug 12 04:41:06 PM PDT 24
Peak memory 205108 kb
Host smart-19265c76-c19e-4ca6-9ed0-6a7efa5cb7b6
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2324247481 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_perf_precise_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.i2c_host_perf_precise.2324247481
Directory /workspace/4.i2c_host_perf_precise/latest

Test location /workspace/coverage/default/4.i2c_host_smoke.2506547076
Short name T678
Test name
Test status
Simulation time 1587985118 ps
CPU time 29.88 seconds
Started Aug 12 04:41:05 PM PDT 24
Finished Aug 12 04:41:35 PM PDT 24
Peak memory 312344 kb
Host smart-8a7ba60c-acf5-40f6-b65d-c0b6b1782893
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2506547076 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_smoke_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.i2c_host_smoke.2506547076
Directory /workspace/4.i2c_host_smoke/latest

Test location /workspace/coverage/default/4.i2c_host_stress_all.3569826067
Short name T1320
Test name
Test status
Simulation time 66637073310 ps
CPU time 783.73 seconds
Started Aug 12 04:41:03 PM PDT 24
Finished Aug 12 04:54:07 PM PDT 24
Peak memory 2078832 kb
Host smart-4b1ae7e0-8cf3-45a5-bd74-77bb4587f6ff
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3569826067 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_stress_all_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.i2c_host_stress_all.3569826067
Directory /workspace/4.i2c_host_stress_all/latest

Test location /workspace/coverage/default/4.i2c_host_stretch_timeout.1075348707
Short name T965
Test name
Test status
Simulation time 5905717461 ps
CPU time 21.39 seconds
Started Aug 12 04:41:07 PM PDT 24
Finished Aug 12 04:41:29 PM PDT 24
Peak memory 231768 kb
Host smart-293d20af-1885-4841-b0b9-e10185cdcdec
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1075348707 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_stretch_timeout_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.i2c_host_stretch_timeout.1075348707
Directory /workspace/4.i2c_host_stretch_timeout/latest

Test location /workspace/coverage/default/4.i2c_sec_cm.1859951854
Short name T198
Test name
Test status
Simulation time 79895858 ps
CPU time 0.99 seconds
Started Aug 12 04:41:11 PM PDT 24
Finished Aug 12 04:41:12 PM PDT 24
Peak memory 223616 kb
Host smart-811efbcc-4276-4174-b4d9-884e0d9b2fd0
User root
Command /workspace/default/simv +run_sec_cm_fi +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1859951854 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_common_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.i2c_sec_cm.1859951854
Directory /workspace/4.i2c_sec_cm/latest

Test location /workspace/coverage/default/4.i2c_target_bad_addr.1813259111
Short name T779
Test name
Test status
Simulation time 2125311628 ps
CPU time 5.84 seconds
Started Aug 12 04:41:11 PM PDT 24
Finished Aug 12 04:41:17 PM PDT 24
Peak memory 213668 kb
Host smart-4cbe368d-e053-4e4a-aab0-fdd1457fb555
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +i2c_bad_addr_pct=50 +cdc_instrumentation_enabled=1 +UVM_
NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1813259111 -assert nopostproc
+UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_target_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.
vdb -cm_log /dev/null -cm_name 4.i2c_target_bad_addr.1813259111
Directory /workspace/4.i2c_target_bad_addr/latest

Test location /workspace/coverage/default/4.i2c_target_fifo_reset_acq.3463313118
Short name T383
Test name
Test status
Simulation time 144103708 ps
CPU time 1.06 seconds
Started Aug 12 04:41:11 PM PDT 24
Finished Aug 12 04:41:12 PM PDT 24
Peak memory 205264 kb
Host smart-3499c5ac-b419-4299-afc3-263e0f8a9035
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3463313118 -assert nopostproc +UVM_TESTNAME=i2c_bas
e_test +UVM_TEST_SEQ=i2c_target_fifo_reset_acq_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log
/dev/null -cm_name 4.i2c_target_fifo_reset_acq.3463313118
Directory /workspace/4.i2c_target_fifo_reset_acq/latest

Test location /workspace/coverage/default/4.i2c_target_fifo_reset_tx.2573710377
Short name T406
Test name
Test status
Simulation time 384477648 ps
CPU time 1.4 seconds
Started Aug 12 04:41:10 PM PDT 24
Finished Aug 12 04:41:11 PM PDT 24
Peak memory 205444 kb
Host smart-72cdfed5-66d4-4e49-b59b-da87383dc216
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2573710377 -assert nopostproc +UVM_TESTNAME=i2c_bas
e_test +UVM_TEST_SEQ=i2c_target_fifo_reset_tx_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /
dev/null -cm_name 4.i2c_target_fifo_reset_tx.2573710377
Directory /workspace/4.i2c_target_fifo_reset_tx/latest

Test location /workspace/coverage/default/4.i2c_target_fifo_watermarks_acq.470699268
Short name T322
Test name
Test status
Simulation time 2619905773 ps
CPU time 2.43 seconds
Started Aug 12 04:41:12 PM PDT 24
Finished Aug 12 04:41:15 PM PDT 24
Peak memory 205496 kb
Host smart-40144860-9ccd-4b7c-ab0a-9400cc9b8139
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=470699268 -assert nopostproc +UVM_TESTNAME=i2c_base
_test +UVM_TEST_SEQ=i2c_target_fifo_watermarks_acq_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_
log /dev/null -cm_name 4.i2c_target_fifo_watermarks_acq.470699268
Directory /workspace/4.i2c_target_fifo_watermarks_acq/latest

Test location /workspace/coverage/default/4.i2c_target_fifo_watermarks_tx.194811149
Short name T1454
Test name
Test status
Simulation time 448484738 ps
CPU time 1.12 seconds
Started Aug 12 04:41:19 PM PDT 24
Finished Aug 12 04:41:20 PM PDT 24
Peak memory 205252 kb
Host smart-0ddbca54-80f8-4e63-84e1-f04736ac0eaf
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=194811149 -assert nopostproc +UVM_TESTNAME=i2c_base
_test +UVM_TEST_SEQ=i2c_target_fifo_watermarks_tx_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_l
og /dev/null -cm_name 4.i2c_target_fifo_watermarks_tx.194811149
Directory /workspace/4.i2c_target_fifo_watermarks_tx/latest

Test location /workspace/coverage/default/4.i2c_target_intr_smoke.2188385388
Short name T385
Test name
Test status
Simulation time 1378446041 ps
CPU time 4.63 seconds
Started Aug 12 04:41:10 PM PDT 24
Finished Aug 12 04:41:15 PM PDT 24
Peak memory 217036 kb
Host smart-11195ecb-672c-4c7d-ad7b-28096b33bad8
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=200_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VER
BOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2188385388 -assert nopostproc +UVM_TESTNAME=i2c_ba
se_test +UVM_TEST_SEQ=i2c_target_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/nul
l -cm_name 4.i2c_target_intr_smoke.2188385388
Directory /workspace/4.i2c_target_intr_smoke/latest

Test location /workspace/coverage/default/4.i2c_target_intr_stress_wr.1244930001
Short name T1375
Test name
Test status
Simulation time 4897601009 ps
CPU time 48.32 seconds
Started Aug 12 04:41:13 PM PDT 24
Finished Aug 12 04:42:01 PM PDT 24
Peak memory 1337284 kb
Host smart-4ab817b0-190a-4503-a273-7a373bf2646e
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=600_000_000 +use_intr_handler=1 +slow_acq=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNO
TES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1244930001 -assert nopostproc +UVM_TES
TNAME=i2c_base_test +UVM_TEST_SEQ=i2c_target_stress_wr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb
-cm_log /dev/null -cm_name 4.i2c_target_intr_stress_wr.1244930001
Directory /workspace/4.i2c_target_intr_stress_wr/latest

Test location /workspace/coverage/default/4.i2c_target_nack_acqfull.1340495045
Short name T1631
Test name
Test status
Simulation time 1581607087 ps
CPU time 2.53 seconds
Started Aug 12 04:41:12 PM PDT 24
Finished Aug 12 04:41:15 PM PDT 24
Peak memory 213636 kb
Host smart-1c576924-87b7-4031-8c63-7e9acae0113b
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1340495045 -assert nopostproc +UVM_TESTNAME=i2c_bas
e_test +UVM_TEST_SEQ=i2c_target_nack_acqfull_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /d
ev/null -cm_name 4.i2c_target_nack_acqfull.1340495045
Directory /workspace/4.i2c_target_nack_acqfull/latest

Test location /workspace/coverage/default/4.i2c_target_nack_acqfull_addr.2872070053
Short name T919
Test name
Test status
Simulation time 597590814 ps
CPU time 2.96 seconds
Started Aug 12 04:41:11 PM PDT 24
Finished Aug 12 04:41:14 PM PDT 24
Peak memory 205928 kb
Host smart-0cdc31ed-7ec1-4ed9-b6b6-d7d2df4ecf39
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2872070053 -assert nopostproc +UVM_TESTNAME=i2c_bas
e_test +UVM_TEST_SEQ=i2c_target_nack_acqfull_addr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_l
og /dev/null -cm_name 4.i2c_target_nack_acqfull_addr.2872070053
Directory /workspace/4.i2c_target_nack_acqfull_addr/latest

Test location /workspace/coverage/default/4.i2c_target_nack_txstretch.1766321732
Short name T813
Test name
Test status
Simulation time 130193727 ps
CPU time 1.6 seconds
Started Aug 12 04:41:16 PM PDT 24
Finished Aug 12 04:41:18 PM PDT 24
Peak memory 222256 kb
Host smart-b183714e-e839-4fcb-8e3d-7cec619d0d18
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1766321732 -assert nopostproc +UVM_TESTNAME=i2c_bas
e_test +UVM_TEST_SEQ=i2c_target_nack_txstretch_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log
/dev/null -cm_name 4.i2c_target_nack_txstretch.1766321732
Directory /workspace/4.i2c_target_nack_txstretch/latest

Test location /workspace/coverage/default/4.i2c_target_perf.2467139079
Short name T1432
Test name
Test status
Simulation time 3934706887 ps
CPU time 5.65 seconds
Started Aug 12 04:41:18 PM PDT 24
Finished Aug 12 04:41:24 PM PDT 24
Peak memory 221868 kb
Host smart-ae132be9-779f-4910-bc9a-e1ea3841920b
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2467139079 -assert nopostproc +UVM_TESTNAME=i2c_bas
e_test +UVM_TEST_SEQ=i2c_target_perf_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null
-cm_name 4.i2c_target_perf.2467139079
Directory /workspace/4.i2c_target_perf/latest

Test location /workspace/coverage/default/4.i2c_target_smbus_maxlen.229364481
Short name T1130
Test name
Test status
Simulation time 8252544162 ps
CPU time 2.69 seconds
Started Aug 12 04:41:12 PM PDT 24
Finished Aug 12 04:41:14 PM PDT 24
Peak memory 205308 kb
Host smart-9eb2cbca-cf45-49dd-9a56-3fa6965cd86e
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=229364481 -assert nopostproc +UVM_TESTNAME=i2c_base
_test +UVM_TEST_SEQ=i2c_target_smbus_maxlen_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /de
v/null -cm_name 4.i2c_target_smbus_maxlen.229364481
Directory /workspace/4.i2c_target_smbus_maxlen/latest

Test location /workspace/coverage/default/4.i2c_target_stress_all.1020053564
Short name T1347
Test name
Test status
Simulation time 57056544173 ps
CPU time 1572.05 seconds
Started Aug 12 04:41:12 PM PDT 24
Finished Aug 12 05:07:24 PM PDT 24
Peak memory 6423256 kb
Host smart-eda33d99-04b4-467b-ba88-b236257194ce
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=300_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VER
BOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1020053564 -assert nopostproc +UVM_TESTNAME=i2c_ba
se_test +UVM_TEST_SEQ=i2c_target_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /de
v/null -cm_name 4.i2c_target_stress_all.1020053564
Directory /workspace/4.i2c_target_stress_all/latest

Test location /workspace/coverage/default/4.i2c_target_stress_rd.141081583
Short name T1134
Test name
Test status
Simulation time 1346104069 ps
CPU time 62.72 seconds
Started Aug 12 04:41:05 PM PDT 24
Finished Aug 12 04:42:08 PM PDT 24
Peak memory 214788 kb
Host smart-3c4a2060-aa5f-4f78-8e0e-e172ca2cf52a
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=100_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licq
ueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=141081583 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ
=i2c_target_stress_rd_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.i2c_
target_stress_rd.141081583
Directory /workspace/4.i2c_target_stress_rd/latest

Test location /workspace/coverage/default/4.i2c_target_stress_wr.1084390143
Short name T1745
Test name
Test status
Simulation time 13622198704 ps
CPU time 7.1 seconds
Started Aug 12 04:41:09 PM PDT 24
Finished Aug 12 04:41:16 PM PDT 24
Peak memory 205516 kb
Host smart-65ffeebb-111f-49af-b0f3-c3b8eb1bb5f7
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=600_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licq
ueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1084390143 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SE
Q=i2c_target_stress_wr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.i2c
_target_stress_wr.1084390143
Directory /workspace/4.i2c_target_stress_wr/latest

Test location /workspace/coverage/default/4.i2c_target_stretch.2795702942
Short name T444
Test name
Test status
Simulation time 1525331039 ps
CPU time 6.07 seconds
Started Aug 12 04:41:14 PM PDT 24
Finished Aug 12 04:41:20 PM PDT 24
Peak memory 254684 kb
Host smart-295f33da-b64a-4ab6-96a8-63850b5c2f19
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=400_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licq
ueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2795702942 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SE
Q=i2c_target_stretch_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.i2c_t
arget_stretch.2795702942
Directory /workspace/4.i2c_target_stretch/latest

Test location /workspace/coverage/default/4.i2c_target_timeout.1545365981
Short name T447
Test name
Test status
Simulation time 4162216759 ps
CPU time 7.87 seconds
Started Aug 12 04:41:12 PM PDT 24
Finished Aug 12 04:41:20 PM PDT 24
Peak memory 221920 kb
Host smart-6a513bef-ad37-4ead-a338-98997e8400c0
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=50_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1545365981 -assert nopostproc +UVM_TESTNAME=i2c_bas
e_test +UVM_TEST_SEQ=i2c_target_timeout_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/nu
ll -cm_name 4.i2c_target_timeout.1545365981
Directory /workspace/4.i2c_target_timeout/latest

Test location /workspace/coverage/default/4.i2c_target_tx_stretch_ctrl.1695605558
Short name T1635
Test name
Test status
Simulation time 139349103 ps
CPU time 2.92 seconds
Started Aug 12 04:41:13 PM PDT 24
Finished Aug 12 04:41:16 PM PDT 24
Peak memory 205388 kb
Host smart-39747c85-e81a-4edc-9228-98c5d8f7704a
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1695605558 -assert nopostproc +UVM_TESTNAME=i2c_bas
e_test +UVM_TEST_SEQ=i2c_target_tx_stretch_ctrl_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log
/dev/null -cm_name 4.i2c_target_tx_stretch_ctrl.1695605558
Directory /workspace/4.i2c_target_tx_stretch_ctrl/latest

Test location /workspace/coverage/default/40.i2c_alert_test.1946948694
Short name T845
Test name
Test status
Simulation time 16238109 ps
CPU time 0.65 seconds
Started Aug 12 04:45:49 PM PDT 24
Finished Aug 12 04:45:50 PM PDT 24
Peak memory 204556 kb
Host smart-005028e4-53fd-497f-9cde-c494e01591f7
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1946948694 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_common_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.i2c_alert_test.1946948694
Directory /workspace/40.i2c_alert_test/latest

Test location /workspace/coverage/default/40.i2c_host_error_intr.2265931573
Short name T832
Test name
Test status
Simulation time 2534712994 ps
CPU time 2.14 seconds
Started Aug 12 04:45:36 PM PDT 24
Finished Aug 12 04:45:39 PM PDT 24
Peak memory 213616 kb
Host smart-bdbce796-646e-4d0f-8c70-d02b51fe46a3
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2265931573 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_error_intr_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.i2c_host_error_intr.2265931573
Directory /workspace/40.i2c_host_error_intr/latest

Test location /workspace/coverage/default/40.i2c_host_fifo_fmt_empty.2891445881
Short name T1587
Test name
Test status
Simulation time 1955452969 ps
CPU time 21.58 seconds
Started Aug 12 04:45:38 PM PDT 24
Finished Aug 12 04:46:00 PM PDT 24
Peak memory 268332 kb
Host smart-6a79bb2b-bc74-46c5-9d63-0dcf9196a6cd
User root
Command /workspace/default/simv +test_timeout_ns=10_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2891445881 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_fifo_fmt_em
pty_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.i2c_host_fifo_fmt_emp
ty.2891445881
Directory /workspace/40.i2c_host_fifo_fmt_empty/latest

Test location /workspace/coverage/default/40.i2c_host_fifo_full.1000883899
Short name T559
Test name
Test status
Simulation time 6128856907 ps
CPU time 68.68 seconds
Started Aug 12 04:45:36 PM PDT 24
Finished Aug 12 04:46:45 PM PDT 24
Peak memory 462408 kb
Host smart-f3f92b87-8147-4eeb-99f6-a34ed34cda67
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1000883899 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_fifo_full_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.i2c_host_fifo_full.1000883899
Directory /workspace/40.i2c_host_fifo_full/latest

Test location /workspace/coverage/default/40.i2c_host_fifo_overflow.2154582653
Short name T1148
Test name
Test status
Simulation time 2661647314 ps
CPU time 198.21 seconds
Started Aug 12 04:45:42 PM PDT 24
Finished Aug 12 04:49:01 PM PDT 24
Peak memory 811288 kb
Host smart-41735bc0-afa4-4939-a947-0035c21112ba
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2154582653 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_fifo_overflow_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.i2c_host_fifo_overflow.2154582653
Directory /workspace/40.i2c_host_fifo_overflow/latest

Test location /workspace/coverage/default/40.i2c_host_fifo_reset_fmt.2276100
Short name T254
Test name
Test status
Simulation time 413596698 ps
CPU time 1.33 seconds
Started Aug 12 04:45:41 PM PDT 24
Finished Aug 12 04:45:43 PM PDT 24
Peak memory 205104 kb
Host smart-869914fd-bb8c-4bd2-aeef-c9dbdbc2fa9a
User root
Command /workspace/default/simv +test_timeout_ns=10_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2276100 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_fifo_reset_fmt
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.i2c_host_fifo_reset_fmt.2276100
Directory /workspace/40.i2c_host_fifo_reset_fmt/latest

Test location /workspace/coverage/default/40.i2c_host_fifo_reset_rx.843443165
Short name T452
Test name
Test status
Simulation time 1624221778 ps
CPU time 3.33 seconds
Started Aug 12 04:45:38 PM PDT 24
Finished Aug 12 04:45:42 PM PDT 24
Peak memory 205216 kb
Host smart-902eff8a-03de-49ef-b4ca-8535003167e7
User root
Command /workspace/default/simv +test_timeout_ns=10_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=843443165 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_fifo_reset_r
x_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.i2c_host_fifo_reset_rx.
843443165
Directory /workspace/40.i2c_host_fifo_reset_rx/latest

Test location /workspace/coverage/default/40.i2c_host_fifo_watermark.121780222
Short name T1277
Test name
Test status
Simulation time 25762579869 ps
CPU time 90.87 seconds
Started Aug 12 04:45:37 PM PDT 24
Finished Aug 12 04:47:08 PM PDT 24
Peak memory 1040108 kb
Host smart-933eb1a9-ad9f-4c93-8a02-2481320ef880
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=121780222 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_fifo_watermark_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.i2c_host_fifo_watermark.121780222
Directory /workspace/40.i2c_host_fifo_watermark/latest

Test location /workspace/coverage/default/40.i2c_host_may_nack.647887691
Short name T261
Test name
Test status
Simulation time 1596357401 ps
CPU time 16.46 seconds
Started Aug 12 04:45:45 PM PDT 24
Finished Aug 12 04:46:02 PM PDT 24
Peak memory 205216 kb
Host smart-fcc9e95b-5772-4b90-8ddd-6d49cd0807b2
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=647887691 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_may_nack_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.i2c_host_may_nack.647887691
Directory /workspace/40.i2c_host_may_nack/latest

Test location /workspace/coverage/default/40.i2c_host_mode_toggle.3000564242
Short name T657
Test name
Test status
Simulation time 230415510 ps
CPU time 1.78 seconds
Started Aug 12 04:46:05 PM PDT 24
Finished Aug 12 04:46:07 PM PDT 24
Peak memory 213420 kb
Host smart-d9460ea1-78db-45e9-94d5-6a25a41e4f8f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3000564242 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_mode_toggle_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.i2c_host_mode_toggle.3000564242
Directory /workspace/40.i2c_host_mode_toggle/latest

Test location /workspace/coverage/default/40.i2c_host_override.3427863610
Short name T80
Test name
Test status
Simulation time 18999888 ps
CPU time 0.68 seconds
Started Aug 12 04:45:36 PM PDT 24
Finished Aug 12 04:45:37 PM PDT 24
Peak memory 204884 kb
Host smart-1a508ff4-8e93-4d71-acbd-4426ff0876fc
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3427863610 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_override_vseq +en_cov=1 -cm line+cond+f
sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.i2c_host_override.3427863610
Directory /workspace/40.i2c_host_override/latest

Test location /workspace/coverage/default/40.i2c_host_perf.2929888877
Short name T1163
Test name
Test status
Simulation time 14290679342 ps
CPU time 137.2 seconds
Started Aug 12 04:45:39 PM PDT 24
Finished Aug 12 04:47:56 PM PDT 24
Peak memory 253792 kb
Host smart-ff8ae80c-a79a-4aa9-bcf6-c6cf01f2aee4
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2929888877 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_perf_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.i2c_host_perf.2929888877
Directory /workspace/40.i2c_host_perf/latest

Test location /workspace/coverage/default/40.i2c_host_perf_precise.3965064563
Short name T18
Test name
Test status
Simulation time 5879079249 ps
CPU time 59.51 seconds
Started Aug 12 04:45:39 PM PDT 24
Finished Aug 12 04:46:39 PM PDT 24
Peak memory 205188 kb
Host smart-bb7673a8-a79d-4836-8cf2-713623ee6b9c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3965064563 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_perf_precise_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.i2c_host_perf_precise.3965064563
Directory /workspace/40.i2c_host_perf_precise/latest

Test location /workspace/coverage/default/40.i2c_host_smoke.507072993
Short name T1221
Test name
Test status
Simulation time 2096756360 ps
CPU time 36.63 seconds
Started Aug 12 04:45:37 PM PDT 24
Finished Aug 12 04:46:14 PM PDT 24
Peak memory 437724 kb
Host smart-8906a19a-13a5-49ae-9bff-7d7f836edaf0
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=507072993 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_smoke_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.i2c_host_smoke.507072993
Directory /workspace/40.i2c_host_smoke/latest

Test location /workspace/coverage/default/40.i2c_host_stress_all.4130613034
Short name T1376
Test name
Test status
Simulation time 25190747171 ps
CPU time 1194.22 seconds
Started Aug 12 04:45:41 PM PDT 24
Finished Aug 12 05:05:35 PM PDT 24
Peak memory 3221484 kb
Host smart-bdca49ce-1636-4f96-a939-9570f84b1114
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4130613034 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_stress_all_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.i2c_host_stress_all.4130613034
Directory /workspace/40.i2c_host_stress_all/latest

Test location /workspace/coverage/default/40.i2c_host_stretch_timeout.3823592499
Short name T801
Test name
Test status
Simulation time 7383724631 ps
CPU time 15.3 seconds
Started Aug 12 04:45:37 PM PDT 24
Finished Aug 12 04:45:53 PM PDT 24
Peak memory 218880 kb
Host smart-af680e86-3fd7-485f-ba2c-5df49c381b57
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3823592499 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_stretch_timeout_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.i2c_host_stretch_timeout.3823592499
Directory /workspace/40.i2c_host_stretch_timeout/latest

Test location /workspace/coverage/default/40.i2c_target_bad_addr.3202773865
Short name T1197
Test name
Test status
Simulation time 5154003043 ps
CPU time 4.78 seconds
Started Aug 12 04:45:46 PM PDT 24
Finished Aug 12 04:45:51 PM PDT 24
Peak memory 213896 kb
Host smart-3047ad07-5c59-43bb-9107-acb45ba22970
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +i2c_bad_addr_pct=50 +cdc_instrumentation_enabled=1 +UVM_
NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3202773865 -assert nopostproc
+UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_target_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.
vdb -cm_log /dev/null -cm_name 40.i2c_target_bad_addr.3202773865
Directory /workspace/40.i2c_target_bad_addr/latest

Test location /workspace/coverage/default/40.i2c_target_fifo_reset_acq.3587823740
Short name T959
Test name
Test status
Simulation time 629154582 ps
CPU time 1.29 seconds
Started Aug 12 04:45:38 PM PDT 24
Finished Aug 12 04:45:40 PM PDT 24
Peak memory 205484 kb
Host smart-18f3fe54-287d-48c8-9e15-d8708ea25110
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3587823740 -assert nopostproc +UVM_TESTNAME=i2c_bas
e_test +UVM_TEST_SEQ=i2c_target_fifo_reset_acq_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log
/dev/null -cm_name 40.i2c_target_fifo_reset_acq.3587823740
Directory /workspace/40.i2c_target_fifo_reset_acq/latest

Test location /workspace/coverage/default/40.i2c_target_fifo_reset_tx.1399973580
Short name T986
Test name
Test status
Simulation time 215370067 ps
CPU time 0.94 seconds
Started Aug 12 04:45:38 PM PDT 24
Finished Aug 12 04:45:39 PM PDT 24
Peak memory 205268 kb
Host smart-ef1b2ba9-586c-4128-9dce-e1512af0f8ef
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1399973580 -assert nopostproc +UVM_TESTNAME=i2c_bas
e_test +UVM_TEST_SEQ=i2c_target_fifo_reset_tx_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /
dev/null -cm_name 40.i2c_target_fifo_reset_tx.1399973580
Directory /workspace/40.i2c_target_fifo_reset_tx/latest

Test location /workspace/coverage/default/40.i2c_target_fifo_watermarks_acq.1683369363
Short name T668
Test name
Test status
Simulation time 1468578009 ps
CPU time 2.95 seconds
Started Aug 12 04:45:46 PM PDT 24
Finished Aug 12 04:45:49 PM PDT 24
Peak memory 205440 kb
Host smart-f54910af-d329-4d30-a256-3e85ea60df64
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1683369363 -assert nopostproc +UVM_TESTNAME=i2c_bas
e_test +UVM_TEST_SEQ=i2c_target_fifo_watermarks_acq_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm
_log /dev/null -cm_name 40.i2c_target_fifo_watermarks_acq.1683369363
Directory /workspace/40.i2c_target_fifo_watermarks_acq/latest

Test location /workspace/coverage/default/40.i2c_target_fifo_watermarks_tx.4010002445
Short name T1556
Test name
Test status
Simulation time 261270818 ps
CPU time 1.25 seconds
Started Aug 12 04:45:50 PM PDT 24
Finished Aug 12 04:45:51 PM PDT 24
Peak memory 205376 kb
Host smart-2e8e5d14-dee8-4662-abf4-1fcaf7eefb5d
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4010002445 -assert nopostproc +UVM_TESTNAME=i2c_bas
e_test +UVM_TEST_SEQ=i2c_target_fifo_watermarks_tx_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_
log /dev/null -cm_name 40.i2c_target_fifo_watermarks_tx.4010002445
Directory /workspace/40.i2c_target_fifo_watermarks_tx/latest

Test location /workspace/coverage/default/40.i2c_target_intr_smoke.1595485190
Short name T853
Test name
Test status
Simulation time 1962977578 ps
CPU time 5.28 seconds
Started Aug 12 04:45:35 PM PDT 24
Finished Aug 12 04:45:41 PM PDT 24
Peak memory 221960 kb
Host smart-526979e4-bb4d-43f8-bd1c-8616ff0713cb
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=200_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VER
BOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1595485190 -assert nopostproc +UVM_TESTNAME=i2c_ba
se_test +UVM_TEST_SEQ=i2c_target_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/nul
l -cm_name 40.i2c_target_intr_smoke.1595485190
Directory /workspace/40.i2c_target_intr_smoke/latest

Test location /workspace/coverage/default/40.i2c_target_intr_stress_wr.3596533217
Short name T59
Test name
Test status
Simulation time 21282323021 ps
CPU time 9.31 seconds
Started Aug 12 04:45:36 PM PDT 24
Finished Aug 12 04:45:46 PM PDT 24
Peak memory 243128 kb
Host smart-a874bb92-0189-41ca-88e9-18c4dd6aa2f8
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=600_000_000 +use_intr_handler=1 +slow_acq=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNO
TES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3596533217 -assert nopostproc +UVM_TES
TNAME=i2c_base_test +UVM_TEST_SEQ=i2c_target_stress_wr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb
-cm_log /dev/null -cm_name 40.i2c_target_intr_stress_wr.3596533217
Directory /workspace/40.i2c_target_intr_stress_wr/latest

Test location /workspace/coverage/default/40.i2c_target_nack_acqfull.1345363205
Short name T1477
Test name
Test status
Simulation time 1101771482 ps
CPU time 3.14 seconds
Started Aug 12 04:45:51 PM PDT 24
Finished Aug 12 04:45:54 PM PDT 24
Peak memory 213112 kb
Host smart-c732d9dd-1537-4255-8aa4-a75420f7e95e
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1345363205 -assert nopostproc +UVM_TESTNAME=i2c_bas
e_test +UVM_TEST_SEQ=i2c_target_nack_acqfull_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /d
ev/null -cm_name 40.i2c_target_nack_acqfull.1345363205
Directory /workspace/40.i2c_target_nack_acqfull/latest

Test location /workspace/coverage/default/40.i2c_target_nack_acqfull_addr.533904582
Short name T170
Test name
Test status
Simulation time 1010139252 ps
CPU time 2.71 seconds
Started Aug 12 04:45:47 PM PDT 24
Finished Aug 12 04:45:50 PM PDT 24
Peak memory 205468 kb
Host smart-ad076575-7f69-43b9-8564-e7dd32322add
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=533904582 -assert nopostproc +UVM_TESTNAME=i2c_base
_test +UVM_TEST_SEQ=i2c_target_nack_acqfull_addr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_lo
g /dev/null -cm_name 40.i2c_target_nack_acqfull_addr.533904582
Directory /workspace/40.i2c_target_nack_acqfull_addr/latest

Test location /workspace/coverage/default/40.i2c_target_perf.2047045826
Short name T1262
Test name
Test status
Simulation time 2516848960 ps
CPU time 3.87 seconds
Started Aug 12 04:45:37 PM PDT 24
Finished Aug 12 04:45:41 PM PDT 24
Peak memory 220764 kb
Host smart-834c9377-5369-411c-a495-ea394766b85f
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2047045826 -assert nopostproc +UVM_TESTNAME=i2c_bas
e_test +UVM_TEST_SEQ=i2c_target_perf_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null
-cm_name 40.i2c_target_perf.2047045826
Directory /workspace/40.i2c_target_perf/latest

Test location /workspace/coverage/default/40.i2c_target_smbus_maxlen.2212346380
Short name T589
Test name
Test status
Simulation time 2562046089 ps
CPU time 2.11 seconds
Started Aug 12 04:45:48 PM PDT 24
Finished Aug 12 04:45:50 PM PDT 24
Peak memory 205296 kb
Host smart-01b8979c-c76a-4ff5-abac-41d0da87c7d1
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2212346380 -assert nopostproc +UVM_TESTNAME=i2c_bas
e_test +UVM_TEST_SEQ=i2c_target_smbus_maxlen_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /d
ev/null -cm_name 40.i2c_target_smbus_maxlen.2212346380
Directory /workspace/40.i2c_target_smbus_maxlen/latest

Test location /workspace/coverage/default/40.i2c_target_smoke.3749105042
Short name T488
Test name
Test status
Simulation time 1036841713 ps
CPU time 29.91 seconds
Started Aug 12 04:45:40 PM PDT 24
Finished Aug 12 04:46:10 PM PDT 24
Peak memory 213652 kb
Host smart-be6e3afd-89f0-49c9-b6a2-8c125ccf104a
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=100_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licq
ueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3749105042 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SE
Q=i2c_target_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.i2c_ta
rget_smoke.3749105042
Directory /workspace/40.i2c_target_smoke/latest

Test location /workspace/coverage/default/40.i2c_target_stress_all.4015098048
Short name T1450
Test name
Test status
Simulation time 41876478990 ps
CPU time 197.84 seconds
Started Aug 12 04:45:37 PM PDT 24
Finished Aug 12 04:48:55 PM PDT 24
Peak memory 1929144 kb
Host smart-ef2dcb8e-ee5a-428a-9b2d-50b8d26ff836
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=300_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VER
BOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4015098048 -assert nopostproc +UVM_TESTNAME=i2c_ba
se_test +UVM_TEST_SEQ=i2c_target_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /de
v/null -cm_name 40.i2c_target_stress_all.4015098048
Directory /workspace/40.i2c_target_stress_all/latest

Test location /workspace/coverage/default/40.i2c_target_stress_rd.2529843686
Short name T552
Test name
Test status
Simulation time 6155826924 ps
CPU time 24.8 seconds
Started Aug 12 04:45:37 PM PDT 24
Finished Aug 12 04:46:02 PM PDT 24
Peak memory 237712 kb
Host smart-707bfbea-df9b-4f10-830e-4e61810cf3bf
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=100_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licq
ueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2529843686 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SE
Q=i2c_target_stress_rd_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.i2
c_target_stress_rd.2529843686
Directory /workspace/40.i2c_target_stress_rd/latest

Test location /workspace/coverage/default/40.i2c_target_stress_wr.2257298554
Short name T1097
Test name
Test status
Simulation time 15150086241 ps
CPU time 8.79 seconds
Started Aug 12 04:45:39 PM PDT 24
Finished Aug 12 04:45:47 PM PDT 24
Peak memory 205552 kb
Host smart-0375cece-a9e4-419a-bf95-b06774d3274b
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=600_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licq
ueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2257298554 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SE
Q=i2c_target_stress_wr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.i2
c_target_stress_wr.2257298554
Directory /workspace/40.i2c_target_stress_wr/latest

Test location /workspace/coverage/default/40.i2c_target_stretch.1377262575
Short name T1013
Test name
Test status
Simulation time 3957317195 ps
CPU time 7.42 seconds
Started Aug 12 04:45:38 PM PDT 24
Finished Aug 12 04:45:45 PM PDT 24
Peak memory 293648 kb
Host smart-102a68b1-eb90-40fb-9694-a72ff2a18310
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=400_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licq
ueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1377262575 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SE
Q=i2c_target_stretch_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.i2c_
target_stretch.1377262575
Directory /workspace/40.i2c_target_stretch/latest

Test location /workspace/coverage/default/40.i2c_target_timeout.3285071196
Short name T78
Test name
Test status
Simulation time 6860579275 ps
CPU time 7.31 seconds
Started Aug 12 04:45:40 PM PDT 24
Finished Aug 12 04:45:47 PM PDT 24
Peak memory 213808 kb
Host smart-ca114d51-df81-4c26-8ea9-cc40899c1114
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=50_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3285071196 -assert nopostproc +UVM_TESTNAME=i2c_bas
e_test +UVM_TEST_SEQ=i2c_target_timeout_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/nu
ll -cm_name 40.i2c_target_timeout.3285071196
Directory /workspace/40.i2c_target_timeout/latest

Test location /workspace/coverage/default/40.i2c_target_tx_stretch_ctrl.2875874199
Short name T1093
Test name
Test status
Simulation time 291998828 ps
CPU time 4.81 seconds
Started Aug 12 04:45:50 PM PDT 24
Finished Aug 12 04:45:55 PM PDT 24
Peak memory 205444 kb
Host smart-3d5d3be2-ff73-43d9-85f6-2c7b7eed9022
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2875874199 -assert nopostproc +UVM_TESTNAME=i2c_bas
e_test +UVM_TEST_SEQ=i2c_target_tx_stretch_ctrl_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log
/dev/null -cm_name 40.i2c_target_tx_stretch_ctrl.2875874199
Directory /workspace/40.i2c_target_tx_stretch_ctrl/latest

Test location /workspace/coverage/default/41.i2c_alert_test.1168005148
Short name T339
Test name
Test status
Simulation time 15786011 ps
CPU time 0.63 seconds
Started Aug 12 04:45:51 PM PDT 24
Finished Aug 12 04:45:52 PM PDT 24
Peak memory 204480 kb
Host smart-8414fba7-795d-4369-85b5-0554011288d6
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1168005148 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_common_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.i2c_alert_test.1168005148
Directory /workspace/41.i2c_alert_test/latest

Test location /workspace/coverage/default/41.i2c_host_error_intr.2622252809
Short name T681
Test name
Test status
Simulation time 163175141 ps
CPU time 4.62 seconds
Started Aug 12 04:45:46 PM PDT 24
Finished Aug 12 04:45:51 PM PDT 24
Peak memory 214508 kb
Host smart-f3e84249-f0ac-446e-a0bc-9b14a5a50ce2
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2622252809 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_error_intr_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.i2c_host_error_intr.2622252809
Directory /workspace/41.i2c_host_error_intr/latest

Test location /workspace/coverage/default/41.i2c_host_fifo_fmt_empty.1232010455
Short name T732
Test name
Test status
Simulation time 211735951 ps
CPU time 3.72 seconds
Started Aug 12 04:45:46 PM PDT 24
Finished Aug 12 04:45:50 PM PDT 24
Peak memory 242600 kb
Host smart-dca3e61f-1467-429d-8eeb-095576f27f83
User root
Command /workspace/default/simv +test_timeout_ns=10_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1232010455 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_fifo_fmt_em
pty_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.i2c_host_fifo_fmt_emp
ty.1232010455
Directory /workspace/41.i2c_host_fifo_fmt_empty/latest

Test location /workspace/coverage/default/41.i2c_host_fifo_full.314988576
Short name T1613
Test name
Test status
Simulation time 6212872668 ps
CPU time 107.8 seconds
Started Aug 12 04:45:47 PM PDT 24
Finished Aug 12 04:47:34 PM PDT 24
Peak memory 722772 kb
Host smart-27df8acd-1602-414a-8a6f-0cfa4cfc1b1d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=314988576 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_fifo_full_vseq +en_cov=1 -cm line+cond+f
sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.i2c_host_fifo_full.314988576
Directory /workspace/41.i2c_host_fifo_full/latest

Test location /workspace/coverage/default/41.i2c_host_fifo_overflow.51101799
Short name T1710
Test name
Test status
Simulation time 7111956597 ps
CPU time 61.1 seconds
Started Aug 12 04:45:49 PM PDT 24
Finished Aug 12 04:46:51 PM PDT 24
Peak memory 686700 kb
Host smart-61b2468c-96cf-4df8-98e3-533f74a5413b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=51101799 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_fifo_overflow_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.i2c_host_fifo_overflow.51101799
Directory /workspace/41.i2c_host_fifo_overflow/latest

Test location /workspace/coverage/default/41.i2c_host_fifo_reset_fmt.3848488873
Short name T712
Test name
Test status
Simulation time 98400390 ps
CPU time 1.11 seconds
Started Aug 12 04:45:49 PM PDT 24
Finished Aug 12 04:45:50 PM PDT 24
Peak memory 204932 kb
Host smart-e0756b8b-f4c7-4832-b3ed-86039e7a0b07
User root
Command /workspace/default/simv +test_timeout_ns=10_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3848488873 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_fifo_reset_
fmt_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.i2c_host_fifo_reset_f
mt.3848488873
Directory /workspace/41.i2c_host_fifo_reset_fmt/latest

Test location /workspace/coverage/default/41.i2c_host_fifo_reset_rx.2643710618
Short name T1681
Test name
Test status
Simulation time 237411411 ps
CPU time 5.41 seconds
Started Aug 12 04:45:51 PM PDT 24
Finished Aug 12 04:45:56 PM PDT 24
Peak memory 204532 kb
Host smart-015097a5-9ebc-411e-8fbf-d87b2008d0a0
User root
Command /workspace/default/simv +test_timeout_ns=10_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2643710618 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_fifo_reset_
rx_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.i2c_host_fifo_reset_rx
.2643710618
Directory /workspace/41.i2c_host_fifo_reset_rx/latest

Test location /workspace/coverage/default/41.i2c_host_fifo_watermark.2222214839
Short name T1271
Test name
Test status
Simulation time 4096834009 ps
CPU time 97.97 seconds
Started Aug 12 04:45:54 PM PDT 24
Finished Aug 12 04:47:32 PM PDT 24
Peak memory 1207408 kb
Host smart-c83a623d-b034-4eb8-9792-6d360e03b5f3
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2222214839 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_fifo_watermark_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.i2c_host_fifo_watermark.2222214839
Directory /workspace/41.i2c_host_fifo_watermark/latest

Test location /workspace/coverage/default/41.i2c_host_may_nack.1789429598
Short name T566
Test name
Test status
Simulation time 111882653 ps
CPU time 4.22 seconds
Started Aug 12 04:45:48 PM PDT 24
Finished Aug 12 04:45:52 PM PDT 24
Peak memory 205264 kb
Host smart-77fdd74e-765f-4379-8244-044b5f6034a5
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1789429598 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_may_nack_vseq +en_cov=1 -cm line+cond+f
sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.i2c_host_may_nack.1789429598
Directory /workspace/41.i2c_host_may_nack/latest

Test location /workspace/coverage/default/41.i2c_host_override.2000647254
Short name T1309
Test name
Test status
Simulation time 40462063 ps
CPU time 0.67 seconds
Started Aug 12 04:45:47 PM PDT 24
Finished Aug 12 04:45:48 PM PDT 24
Peak memory 205016 kb
Host smart-4a570e86-edbb-4e16-997d-40b94873bcc0
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2000647254 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_override_vseq +en_cov=1 -cm line+cond+f
sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.i2c_host_override.2000647254
Directory /workspace/41.i2c_host_override/latest

Test location /workspace/coverage/default/41.i2c_host_perf.1071123211
Short name T620
Test name
Test status
Simulation time 6790713855 ps
CPU time 383.15 seconds
Started Aug 12 04:45:47 PM PDT 24
Finished Aug 12 04:52:10 PM PDT 24
Peak memory 777236 kb
Host smart-90fa0828-a69d-4681-a7cb-22ea5dfcd0b3
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1071123211 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_perf_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.i2c_host_perf.1071123211
Directory /workspace/41.i2c_host_perf/latest

Test location /workspace/coverage/default/41.i2c_host_perf_precise.3222588470
Short name T1204
Test name
Test status
Simulation time 2765401817 ps
CPU time 26.03 seconds
Started Aug 12 04:45:47 PM PDT 24
Finished Aug 12 04:46:13 PM PDT 24
Peak memory 222860 kb
Host smart-0039a19f-a9dc-40b7-bcb9-5bfeb0fe7c60
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3222588470 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_perf_precise_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.i2c_host_perf_precise.3222588470
Directory /workspace/41.i2c_host_perf_precise/latest

Test location /workspace/coverage/default/41.i2c_host_smoke.3287416985
Short name T1584
Test name
Test status
Simulation time 3404138220 ps
CPU time 53.32 seconds
Started Aug 12 04:45:50 PM PDT 24
Finished Aug 12 04:46:43 PM PDT 24
Peak memory 314904 kb
Host smart-465ad9e9-647b-442e-aa68-8b0c8f8a3b81
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3287416985 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_smoke_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.i2c_host_smoke.3287416985
Directory /workspace/41.i2c_host_smoke/latest

Test location /workspace/coverage/default/41.i2c_host_stress_all.4186237837
Short name T138
Test name
Test status
Simulation time 33388453769 ps
CPU time 528.68 seconds
Started Aug 12 04:45:49 PM PDT 24
Finished Aug 12 04:54:38 PM PDT 24
Peak memory 989880 kb
Host smart-51a928da-87fa-4d3e-b8e6-53684f40fd7a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4186237837 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_stress_all_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.i2c_host_stress_all.4186237837
Directory /workspace/41.i2c_host_stress_all/latest

Test location /workspace/coverage/default/41.i2c_host_stretch_timeout.3476795134
Short name T1419
Test name
Test status
Simulation time 2478329996 ps
CPU time 10.69 seconds
Started Aug 12 04:45:43 PM PDT 24
Finished Aug 12 04:45:54 PM PDT 24
Peak memory 217800 kb
Host smart-6e6065ad-4329-489e-bc8f-d98005eb23e5
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3476795134 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_stretch_timeout_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.i2c_host_stretch_timeout.3476795134
Directory /workspace/41.i2c_host_stretch_timeout/latest

Test location /workspace/coverage/default/41.i2c_target_bad_addr.888744729
Short name T1657
Test name
Test status
Simulation time 1637732449 ps
CPU time 5.04 seconds
Started Aug 12 04:45:53 PM PDT 24
Finished Aug 12 04:45:58 PM PDT 24
Peak memory 221732 kb
Host smart-492c5a68-520a-48b6-87bd-6c5cbf83ab02
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +i2c_bad_addr_pct=50 +cdc_instrumentation_enabled=1 +UVM_
NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=888744729 -assert nopostproc +
UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_target_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.v
db -cm_log /dev/null -cm_name 41.i2c_target_bad_addr.888744729
Directory /workspace/41.i2c_target_bad_addr/latest

Test location /workspace/coverage/default/41.i2c_target_fifo_reset_acq.1468154994
Short name T1646
Test name
Test status
Simulation time 262147864 ps
CPU time 0.99 seconds
Started Aug 12 04:45:48 PM PDT 24
Finished Aug 12 04:45:49 PM PDT 24
Peak memory 205012 kb
Host smart-517debd2-1fef-4b37-8e43-7f7c239b8de4
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1468154994 -assert nopostproc +UVM_TESTNAME=i2c_bas
e_test +UVM_TEST_SEQ=i2c_target_fifo_reset_acq_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log
/dev/null -cm_name 41.i2c_target_fifo_reset_acq.1468154994
Directory /workspace/41.i2c_target_fifo_reset_acq/latest

Test location /workspace/coverage/default/41.i2c_target_fifo_reset_tx.412146107
Short name T719
Test name
Test status
Simulation time 771281352 ps
CPU time 1.72 seconds
Started Aug 12 04:45:48 PM PDT 24
Finished Aug 12 04:45:50 PM PDT 24
Peak memory 205476 kb
Host smart-3fdf2fab-e142-4723-861a-87c460b921a2
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=412146107 -assert nopostproc +UVM_TESTNAME=i2c_base
_test +UVM_TEST_SEQ=i2c_target_fifo_reset_tx_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /d
ev/null -cm_name 41.i2c_target_fifo_reset_tx.412146107
Directory /workspace/41.i2c_target_fifo_reset_tx/latest

Test location /workspace/coverage/default/41.i2c_target_fifo_watermarks_acq.3699858612
Short name T778
Test name
Test status
Simulation time 671576931 ps
CPU time 2.4 seconds
Started Aug 12 04:45:49 PM PDT 24
Finished Aug 12 04:45:52 PM PDT 24
Peak memory 205568 kb
Host smart-c362eac9-e5ec-4d69-afd7-8a3973fc3bdb
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3699858612 -assert nopostproc +UVM_TESTNAME=i2c_bas
e_test +UVM_TEST_SEQ=i2c_target_fifo_watermarks_acq_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm
_log /dev/null -cm_name 41.i2c_target_fifo_watermarks_acq.3699858612
Directory /workspace/41.i2c_target_fifo_watermarks_acq/latest

Test location /workspace/coverage/default/41.i2c_target_fifo_watermarks_tx.79868357
Short name T347
Test name
Test status
Simulation time 148405958 ps
CPU time 1.29 seconds
Started Aug 12 04:45:46 PM PDT 24
Finished Aug 12 04:45:48 PM PDT 24
Peak memory 205360 kb
Host smart-ceddffab-3fed-4358-b03e-8c7403266eaf
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=79868357 -assert nopostproc +UVM_TESTNAME=i2c_base_
test +UVM_TEST_SEQ=i2c_target_fifo_watermarks_tx_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_lo
g /dev/null -cm_name 41.i2c_target_fifo_watermarks_tx.79868357
Directory /workspace/41.i2c_target_fifo_watermarks_tx/latest

Test location /workspace/coverage/default/41.i2c_target_hrst.740027607
Short name T1423
Test name
Test status
Simulation time 2098100111 ps
CPU time 1.72 seconds
Started Aug 12 04:45:48 PM PDT 24
Finished Aug 12 04:45:50 PM PDT 24
Peak memory 213384 kb
Host smart-4f6bdc03-dd3f-48b4-82f5-6b665afc0222
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=740027607 -assert nopostproc +UVM_TESTNAME=i2c_base
_test +UVM_TEST_SEQ=i2c_target_hrst_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -
cm_name 41.i2c_target_hrst.740027607
Directory /workspace/41.i2c_target_hrst/latest

Test location /workspace/coverage/default/41.i2c_target_intr_smoke.3276873920
Short name T363
Test name
Test status
Simulation time 3669354692 ps
CPU time 5.35 seconds
Started Aug 12 04:45:46 PM PDT 24
Finished Aug 12 04:45:51 PM PDT 24
Peak memory 220372 kb
Host smart-9f3e4466-01d5-4f0f-a276-3f4df4b2c68d
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=200_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VER
BOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3276873920 -assert nopostproc +UVM_TESTNAME=i2c_ba
se_test +UVM_TEST_SEQ=i2c_target_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/nul
l -cm_name 41.i2c_target_intr_smoke.3276873920
Directory /workspace/41.i2c_target_intr_smoke/latest

Test location /workspace/coverage/default/41.i2c_target_intr_stress_wr.3241143043
Short name T326
Test name
Test status
Simulation time 9456257519 ps
CPU time 24.28 seconds
Started Aug 12 04:45:46 PM PDT 24
Finished Aug 12 04:46:10 PM PDT 24
Peak memory 539232 kb
Host smart-66f84e89-48f3-4a22-9370-61fd71ce8eab
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=600_000_000 +use_intr_handler=1 +slow_acq=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNO
TES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3241143043 -assert nopostproc +UVM_TES
TNAME=i2c_base_test +UVM_TEST_SEQ=i2c_target_stress_wr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb
-cm_log /dev/null -cm_name 41.i2c_target_intr_stress_wr.3241143043
Directory /workspace/41.i2c_target_intr_stress_wr/latest

Test location /workspace/coverage/default/41.i2c_target_nack_acqfull.4089514846
Short name T66
Test name
Test status
Simulation time 9367474067 ps
CPU time 2.87 seconds
Started Aug 12 04:45:53 PM PDT 24
Finished Aug 12 04:45:56 PM PDT 24
Peak memory 213700 kb
Host smart-8e6c4a35-4090-4f68-81b6-21c2741fcefe
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4089514846 -assert nopostproc +UVM_TESTNAME=i2c_bas
e_test +UVM_TEST_SEQ=i2c_target_nack_acqfull_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /d
ev/null -cm_name 41.i2c_target_nack_acqfull.4089514846
Directory /workspace/41.i2c_target_nack_acqfull/latest

Test location /workspace/coverage/default/41.i2c_target_nack_acqfull_addr.3099405222
Short name T61
Test name
Test status
Simulation time 2076549787 ps
CPU time 2.68 seconds
Started Aug 12 04:45:57 PM PDT 24
Finished Aug 12 04:46:00 PM PDT 24
Peak memory 205472 kb
Host smart-bd38b0cd-0574-4565-9840-dc54e3de5e82
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3099405222 -assert nopostproc +UVM_TESTNAME=i2c_bas
e_test +UVM_TEST_SEQ=i2c_target_nack_acqfull_addr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_l
og /dev/null -cm_name 41.i2c_target_nack_acqfull_addr.3099405222
Directory /workspace/41.i2c_target_nack_acqfull_addr/latest

Test location /workspace/coverage/default/41.i2c_target_perf.281680957
Short name T405
Test name
Test status
Simulation time 3746864714 ps
CPU time 7.09 seconds
Started Aug 12 04:45:47 PM PDT 24
Finished Aug 12 04:45:54 PM PDT 24
Peak memory 223232 kb
Host smart-b54bd30e-30ee-4e0a-81a7-49592adee422
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=281680957 -assert nopostproc +UVM_TESTNAME=i2c_base
_test +UVM_TEST_SEQ=i2c_target_perf_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -
cm_name 41.i2c_target_perf.281680957
Directory /workspace/41.i2c_target_perf/latest

Test location /workspace/coverage/default/41.i2c_target_smbus_maxlen.1906311512
Short name T748
Test name
Test status
Simulation time 1602442948 ps
CPU time 2.21 seconds
Started Aug 12 04:45:51 PM PDT 24
Finished Aug 12 04:45:53 PM PDT 24
Peak memory 205336 kb
Host smart-2adf3a62-6509-4e38-bc2f-bfb505abd2fa
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1906311512 -assert nopostproc +UVM_TESTNAME=i2c_bas
e_test +UVM_TEST_SEQ=i2c_target_smbus_maxlen_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /d
ev/null -cm_name 41.i2c_target_smbus_maxlen.1906311512
Directory /workspace/41.i2c_target_smbus_maxlen/latest

Test location /workspace/coverage/default/41.i2c_target_smoke.2335288047
Short name T885
Test name
Test status
Simulation time 1292093816 ps
CPU time 18.82 seconds
Started Aug 12 04:45:46 PM PDT 24
Finished Aug 12 04:46:05 PM PDT 24
Peak memory 213804 kb
Host smart-d65324a6-d8a8-4070-8551-581f6e79d3b8
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=100_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licq
ueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2335288047 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SE
Q=i2c_target_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.i2c_ta
rget_smoke.2335288047
Directory /workspace/41.i2c_target_smoke/latest

Test location /workspace/coverage/default/41.i2c_target_stress_all.2544679896
Short name T735
Test name
Test status
Simulation time 26490561285 ps
CPU time 403.35 seconds
Started Aug 12 04:45:45 PM PDT 24
Finished Aug 12 04:52:28 PM PDT 24
Peak memory 3104232 kb
Host smart-9b44cdb7-0302-4749-ae59-c726f0a2ef33
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=300_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VER
BOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2544679896 -assert nopostproc +UVM_TESTNAME=i2c_ba
se_test +UVM_TEST_SEQ=i2c_target_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /de
v/null -cm_name 41.i2c_target_stress_all.2544679896
Directory /workspace/41.i2c_target_stress_all/latest

Test location /workspace/coverage/default/41.i2c_target_stress_rd.2523621619
Short name T1202
Test name
Test status
Simulation time 1345492555 ps
CPU time 13.78 seconds
Started Aug 12 04:45:48 PM PDT 24
Finished Aug 12 04:46:02 PM PDT 24
Peak memory 216016 kb
Host smart-b489ef9b-d545-4cd0-99fc-dbfa7b40ec46
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=100_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licq
ueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2523621619 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SE
Q=i2c_target_stress_rd_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.i2
c_target_stress_rd.2523621619
Directory /workspace/41.i2c_target_stress_rd/latest

Test location /workspace/coverage/default/41.i2c_target_stress_wr.1076371618
Short name T384
Test name
Test status
Simulation time 11563592312 ps
CPU time 21.94 seconds
Started Aug 12 04:45:47 PM PDT 24
Finished Aug 12 04:46:09 PM PDT 24
Peak memory 205608 kb
Host smart-05a8b249-3593-47e4-8de2-7decb3fb9c2f
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=600_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licq
ueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1076371618 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SE
Q=i2c_target_stress_wr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.i2
c_target_stress_wr.1076371618
Directory /workspace/41.i2c_target_stress_wr/latest

Test location /workspace/coverage/default/41.i2c_target_stretch.3486759421
Short name T1206
Test name
Test status
Simulation time 3276819758 ps
CPU time 4.25 seconds
Started Aug 12 04:45:51 PM PDT 24
Finished Aug 12 04:45:55 PM PDT 24
Peak memory 205324 kb
Host smart-b29e298d-86ed-499b-89b7-49c1438c11e6
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=400_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licq
ueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3486759421 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SE
Q=i2c_target_stretch_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.i2c_
target_stretch.3486759421
Directory /workspace/41.i2c_target_stretch/latest

Test location /workspace/coverage/default/41.i2c_target_timeout.1286130044
Short name T1048
Test name
Test status
Simulation time 1129792896 ps
CPU time 6.14 seconds
Started Aug 12 04:45:48 PM PDT 24
Finished Aug 12 04:45:54 PM PDT 24
Peak memory 213708 kb
Host smart-2eaf2ec0-fc5f-4263-ad43-f80fd25539c6
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=50_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1286130044 -assert nopostproc +UVM_TESTNAME=i2c_bas
e_test +UVM_TEST_SEQ=i2c_target_timeout_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/nu
ll -cm_name 41.i2c_target_timeout.1286130044
Directory /workspace/41.i2c_target_timeout/latest

Test location /workspace/coverage/default/41.i2c_target_tx_stretch_ctrl.962767035
Short name T996
Test name
Test status
Simulation time 270208938 ps
CPU time 4.47 seconds
Started Aug 12 04:45:52 PM PDT 24
Finished Aug 12 04:45:56 PM PDT 24
Peak memory 205920 kb
Host smart-989733d2-a6bc-496d-9054-5f2946e6b8fd
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=962767035 -assert nopostproc +UVM_TESTNAME=i2c_base
_test +UVM_TEST_SEQ=i2c_target_tx_stretch_ctrl_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log
/dev/null -cm_name 41.i2c_target_tx_stretch_ctrl.962767035
Directory /workspace/41.i2c_target_tx_stretch_ctrl/latest

Test location /workspace/coverage/default/42.i2c_alert_test.1816068449
Short name T1472
Test name
Test status
Simulation time 28770310 ps
CPU time 0.63 seconds
Started Aug 12 04:46:01 PM PDT 24
Finished Aug 12 04:46:02 PM PDT 24
Peak memory 204412 kb
Host smart-03e5351d-eb63-44bd-9979-af0710c1c62a
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1816068449 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_common_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.i2c_alert_test.1816068449
Directory /workspace/42.i2c_alert_test/latest

Test location /workspace/coverage/default/42.i2c_host_error_intr.3306600762
Short name T1547
Test name
Test status
Simulation time 99197032 ps
CPU time 1.73 seconds
Started Aug 12 04:45:55 PM PDT 24
Finished Aug 12 04:45:57 PM PDT 24
Peak memory 213512 kb
Host smart-175dd019-67ca-4ab0-97ba-84a81f44577c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3306600762 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_error_intr_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.i2c_host_error_intr.3306600762
Directory /workspace/42.i2c_host_error_intr/latest

Test location /workspace/coverage/default/42.i2c_host_fifo_fmt_empty.2941669243
Short name T532
Test name
Test status
Simulation time 289528118 ps
CPU time 6.13 seconds
Started Aug 12 04:45:58 PM PDT 24
Finished Aug 12 04:46:04 PM PDT 24
Peak memory 263592 kb
Host smart-8d355935-7dc2-43e3-9163-f25d48423525
User root
Command /workspace/default/simv +test_timeout_ns=10_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2941669243 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_fifo_fmt_em
pty_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.i2c_host_fifo_fmt_emp
ty.2941669243
Directory /workspace/42.i2c_host_fifo_fmt_empty/latest

Test location /workspace/coverage/default/42.i2c_host_fifo_full.3825724595
Short name T165
Test name
Test status
Simulation time 4239128065 ps
CPU time 50.28 seconds
Started Aug 12 04:45:52 PM PDT 24
Finished Aug 12 04:46:42 PM PDT 24
Peak memory 302372 kb
Host smart-36e7e47f-caa7-4cf1-bd3c-302ec10ae874
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3825724595 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_fifo_full_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.i2c_host_fifo_full.3825724595
Directory /workspace/42.i2c_host_fifo_full/latest

Test location /workspace/coverage/default/42.i2c_host_fifo_overflow.954946889
Short name T1678
Test name
Test status
Simulation time 5772407388 ps
CPU time 45.36 seconds
Started Aug 12 04:45:51 PM PDT 24
Finished Aug 12 04:46:37 PM PDT 24
Peak memory 532760 kb
Host smart-a4d8847d-f3b3-4d31-af8c-b07dc20f53a9
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=954946889 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_fifo_overflow_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.i2c_host_fifo_overflow.954946889
Directory /workspace/42.i2c_host_fifo_overflow/latest

Test location /workspace/coverage/default/42.i2c_host_fifo_reset_fmt.276553744
Short name T378
Test name
Test status
Simulation time 280410691 ps
CPU time 1.07 seconds
Started Aug 12 04:45:53 PM PDT 24
Finished Aug 12 04:45:54 PM PDT 24
Peak memory 204944 kb
Host smart-7686157f-86ef-4815-bf5e-a1c9aca382ff
User root
Command /workspace/default/simv +test_timeout_ns=10_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=276553744 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_fifo_reset_f
mt_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.i2c_host_fifo_reset_fm
t.276553744
Directory /workspace/42.i2c_host_fifo_reset_fmt/latest

Test location /workspace/coverage/default/42.i2c_host_fifo_reset_rx.1128803497
Short name T1336
Test name
Test status
Simulation time 191216892 ps
CPU time 4.75 seconds
Started Aug 12 04:45:50 PM PDT 24
Finished Aug 12 04:45:55 PM PDT 24
Peak memory 237748 kb
Host smart-750d9b4e-144e-4af6-a592-91c912786cb9
User root
Command /workspace/default/simv +test_timeout_ns=10_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1128803497 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_fifo_reset_
rx_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.i2c_host_fifo_reset_rx
.1128803497
Directory /workspace/42.i2c_host_fifo_reset_rx/latest

Test location /workspace/coverage/default/42.i2c_host_fifo_watermark.1475996795
Short name T120
Test name
Test status
Simulation time 31892316978 ps
CPU time 92.54 seconds
Started Aug 12 04:45:50 PM PDT 24
Finished Aug 12 04:47:23 PM PDT 24
Peak memory 1159316 kb
Host smart-52170be5-6258-4d0b-b9e5-15ebc312a69f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1475996795 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_fifo_watermark_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.i2c_host_fifo_watermark.1475996795
Directory /workspace/42.i2c_host_fifo_watermark/latest

Test location /workspace/coverage/default/42.i2c_host_may_nack.3785139593
Short name T1357
Test name
Test status
Simulation time 1943730843 ps
CPU time 20.23 seconds
Started Aug 12 04:46:00 PM PDT 24
Finished Aug 12 04:46:21 PM PDT 24
Peak memory 205188 kb
Host smart-0e24b439-3d2e-4f92-90d1-23b598062c53
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3785139593 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_may_nack_vseq +en_cov=1 -cm line+cond+f
sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.i2c_host_may_nack.3785139593
Directory /workspace/42.i2c_host_may_nack/latest

Test location /workspace/coverage/default/42.i2c_host_override.1474572897
Short name T478
Test name
Test status
Simulation time 44916500 ps
CPU time 0.67 seconds
Started Aug 12 04:45:58 PM PDT 24
Finished Aug 12 04:45:58 PM PDT 24
Peak memory 204908 kb
Host smart-ea4daa6a-67d3-466c-ac71-f063b06b87b8
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1474572897 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_override_vseq +en_cov=1 -cm line+cond+f
sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.i2c_host_override.1474572897
Directory /workspace/42.i2c_host_override/latest

Test location /workspace/coverage/default/42.i2c_host_perf.3599530714
Short name T17
Test name
Test status
Simulation time 6353272351 ps
CPU time 48.44 seconds
Started Aug 12 04:45:52 PM PDT 24
Finished Aug 12 04:46:41 PM PDT 24
Peak memory 213488 kb
Host smart-edf41b94-b97c-44cd-8cb7-12dadd2023a2
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3599530714 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_perf_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.i2c_host_perf.3599530714
Directory /workspace/42.i2c_host_perf/latest

Test location /workspace/coverage/default/42.i2c_host_perf_precise.2703909735
Short name T175
Test name
Test status
Simulation time 198982005 ps
CPU time 2.78 seconds
Started Aug 12 04:45:51 PM PDT 24
Finished Aug 12 04:45:54 PM PDT 24
Peak memory 226008 kb
Host smart-e1e3b3cc-1c84-448e-961b-9c6c93101177
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2703909735 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_perf_precise_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.i2c_host_perf_precise.2703909735
Directory /workspace/42.i2c_host_perf_precise/latest

Test location /workspace/coverage/default/42.i2c_host_smoke.3689530533
Short name T1600
Test name
Test status
Simulation time 3576877044 ps
CPU time 26.66 seconds
Started Aug 12 04:45:57 PM PDT 24
Finished Aug 12 04:46:24 PM PDT 24
Peak memory 319224 kb
Host smart-f0a65c10-7e06-47ea-8517-64ba37552dae
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3689530533 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_smoke_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.i2c_host_smoke.3689530533
Directory /workspace/42.i2c_host_smoke/latest

Test location /workspace/coverage/default/42.i2c_host_stretch_timeout.2153264721
Short name T820
Test name
Test status
Simulation time 742292824 ps
CPU time 14.64 seconds
Started Aug 12 04:45:55 PM PDT 24
Finished Aug 12 04:46:09 PM PDT 24
Peak memory 220992 kb
Host smart-e8e00372-6b1b-4f86-ba61-784791e002b3
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2153264721 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_stretch_timeout_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.i2c_host_stretch_timeout.2153264721
Directory /workspace/42.i2c_host_stretch_timeout/latest

Test location /workspace/coverage/default/42.i2c_target_bad_addr.3848530912
Short name T880
Test name
Test status
Simulation time 1421763679 ps
CPU time 7.24 seconds
Started Aug 12 04:46:01 PM PDT 24
Finished Aug 12 04:46:09 PM PDT 24
Peak memory 221836 kb
Host smart-2fc7398a-18dc-41be-a585-6e4661317aab
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +i2c_bad_addr_pct=50 +cdc_instrumentation_enabled=1 +UVM_
NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3848530912 -assert nopostproc
+UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_target_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.
vdb -cm_log /dev/null -cm_name 42.i2c_target_bad_addr.3848530912
Directory /workspace/42.i2c_target_bad_addr/latest

Test location /workspace/coverage/default/42.i2c_target_fifo_reset_acq.734916781
Short name T249
Test name
Test status
Simulation time 152183746 ps
CPU time 1.04 seconds
Started Aug 12 04:46:00 PM PDT 24
Finished Aug 12 04:46:01 PM PDT 24
Peak memory 205272 kb
Host smart-5e012f19-ef64-4bbc-b6bc-e5e68dd93a31
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=734916781 -assert nopostproc +UVM_TESTNAME=i2c_base
_test +UVM_TEST_SEQ=i2c_target_fifo_reset_acq_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /
dev/null -cm_name 42.i2c_target_fifo_reset_acq.734916781
Directory /workspace/42.i2c_target_fifo_reset_acq/latest

Test location /workspace/coverage/default/42.i2c_target_fifo_reset_tx.1814489417
Short name T1620
Test name
Test status
Simulation time 390448474 ps
CPU time 1.08 seconds
Started Aug 12 04:46:02 PM PDT 24
Finished Aug 12 04:46:03 PM PDT 24
Peak memory 213404 kb
Host smart-7cdf7ce0-0502-4217-873a-a584d387c2f9
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1814489417 -assert nopostproc +UVM_TESTNAME=i2c_bas
e_test +UVM_TEST_SEQ=i2c_target_fifo_reset_tx_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /
dev/null -cm_name 42.i2c_target_fifo_reset_tx.1814489417
Directory /workspace/42.i2c_target_fifo_reset_tx/latest

Test location /workspace/coverage/default/42.i2c_target_fifo_watermarks_acq.1220600811
Short name T1356
Test name
Test status
Simulation time 282784648 ps
CPU time 2.1 seconds
Started Aug 12 04:46:03 PM PDT 24
Finished Aug 12 04:46:05 PM PDT 24
Peak memory 205352 kb
Host smart-53c81e5a-8d71-4937-ab65-f23d5e5308f5
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1220600811 -assert nopostproc +UVM_TESTNAME=i2c_bas
e_test +UVM_TEST_SEQ=i2c_target_fifo_watermarks_acq_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm
_log /dev/null -cm_name 42.i2c_target_fifo_watermarks_acq.1220600811
Directory /workspace/42.i2c_target_fifo_watermarks_acq/latest

Test location /workspace/coverage/default/42.i2c_target_fifo_watermarks_tx.4011339601
Short name T510
Test name
Test status
Simulation time 267945483 ps
CPU time 0.93 seconds
Started Aug 12 04:46:00 PM PDT 24
Finished Aug 12 04:46:01 PM PDT 24
Peak memory 205260 kb
Host smart-e84527d6-e19c-4832-953d-1410a74c1b32
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4011339601 -assert nopostproc +UVM_TESTNAME=i2c_bas
e_test +UVM_TEST_SEQ=i2c_target_fifo_watermarks_tx_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_
log /dev/null -cm_name 42.i2c_target_fifo_watermarks_tx.4011339601
Directory /workspace/42.i2c_target_fifo_watermarks_tx/latest

Test location /workspace/coverage/default/42.i2c_target_intr_smoke.40911376
Short name T369
Test name
Test status
Simulation time 1491749189 ps
CPU time 8.24 seconds
Started Aug 12 04:45:58 PM PDT 24
Finished Aug 12 04:46:06 PM PDT 24
Peak memory 221812 kb
Host smart-513e6e7b-ce5c-46a5-9247-e2c662184018
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=200_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VER
BOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=40911376 -assert nopostproc +UVM_TESTNAME=i2c_base
_test +UVM_TEST_SEQ=i2c_target_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null
-cm_name 42.i2c_target_intr_smoke.40911376
Directory /workspace/42.i2c_target_intr_smoke/latest

Test location /workspace/coverage/default/42.i2c_target_intr_stress_wr.1855642848
Short name T1254
Test name
Test status
Simulation time 10925055456 ps
CPU time 59.03 seconds
Started Aug 12 04:46:00 PM PDT 24
Finished Aug 12 04:46:59 PM PDT 24
Peak memory 1069956 kb
Host smart-3906a106-0d11-4537-822b-d1e9a61b8e95
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=600_000_000 +use_intr_handler=1 +slow_acq=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNO
TES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1855642848 -assert nopostproc +UVM_TES
TNAME=i2c_base_test +UVM_TEST_SEQ=i2c_target_stress_wr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb
-cm_log /dev/null -cm_name 42.i2c_target_intr_stress_wr.1855642848
Directory /workspace/42.i2c_target_intr_stress_wr/latest

Test location /workspace/coverage/default/42.i2c_target_nack_acqfull.3678740848
Short name T171
Test name
Test status
Simulation time 608825227 ps
CPU time 3.31 seconds
Started Aug 12 04:46:00 PM PDT 24
Finished Aug 12 04:46:03 PM PDT 24
Peak memory 213800 kb
Host smart-cd2d1e3a-64fa-4b43-9489-dfc09c09ce05
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3678740848 -assert nopostproc +UVM_TESTNAME=i2c_bas
e_test +UVM_TEST_SEQ=i2c_target_nack_acqfull_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /d
ev/null -cm_name 42.i2c_target_nack_acqfull.3678740848
Directory /workspace/42.i2c_target_nack_acqfull/latest

Test location /workspace/coverage/default/42.i2c_target_nack_acqfull_addr.999801860
Short name T762
Test name
Test status
Simulation time 542956440 ps
CPU time 2.93 seconds
Started Aug 12 04:46:01 PM PDT 24
Finished Aug 12 04:46:04 PM PDT 24
Peak memory 206276 kb
Host smart-fdbe78a7-8c3a-408b-93a7-028e0c3dbde7
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=999801860 -assert nopostproc +UVM_TESTNAME=i2c_base
_test +UVM_TEST_SEQ=i2c_target_nack_acqfull_addr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_lo
g /dev/null -cm_name 42.i2c_target_nack_acqfull_addr.999801860
Directory /workspace/42.i2c_target_nack_acqfull_addr/latest

Test location /workspace/coverage/default/42.i2c_target_perf.521051701
Short name T161
Test name
Test status
Simulation time 939386386 ps
CPU time 7.16 seconds
Started Aug 12 04:46:03 PM PDT 24
Finished Aug 12 04:46:10 PM PDT 24
Peak memory 223188 kb
Host smart-1a0b8f3c-f7b1-4c54-876e-15e6eeca2234
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=521051701 -assert nopostproc +UVM_TESTNAME=i2c_base
_test +UVM_TEST_SEQ=i2c_target_perf_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -
cm_name 42.i2c_target_perf.521051701
Directory /workspace/42.i2c_target_perf/latest

Test location /workspace/coverage/default/42.i2c_target_smbus_maxlen.482356504
Short name T1217
Test name
Test status
Simulation time 1003833866 ps
CPU time 2.31 seconds
Started Aug 12 04:46:01 PM PDT 24
Finished Aug 12 04:46:04 PM PDT 24
Peak memory 205332 kb
Host smart-027e9d22-d9b2-40a8-890a-93a95ab75348
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=482356504 -assert nopostproc +UVM_TESTNAME=i2c_base
_test +UVM_TEST_SEQ=i2c_target_smbus_maxlen_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /de
v/null -cm_name 42.i2c_target_smbus_maxlen.482356504
Directory /workspace/42.i2c_target_smbus_maxlen/latest

Test location /workspace/coverage/default/42.i2c_target_smoke.397954408
Short name T1286
Test name
Test status
Simulation time 556492880 ps
CPU time 7.99 seconds
Started Aug 12 04:45:58 PM PDT 24
Finished Aug 12 04:46:07 PM PDT 24
Peak memory 213712 kb
Host smart-a9ce4f84-429a-4ba8-84b2-db2d42ab1e95
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=100_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licq
ueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=397954408 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ
=i2c_target_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.i2c_tar
get_smoke.397954408
Directory /workspace/42.i2c_target_smoke/latest

Test location /workspace/coverage/default/42.i2c_target_stress_all.1347879123
Short name T807
Test name
Test status
Simulation time 31218516568 ps
CPU time 229.51 seconds
Started Aug 12 04:46:09 PM PDT 24
Finished Aug 12 04:49:58 PM PDT 24
Peak memory 1678164 kb
Host smart-17d360f4-bbfd-4c03-96c7-15cb87aa2c5a
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=300_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VER
BOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1347879123 -assert nopostproc +UVM_TESTNAME=i2c_ba
se_test +UVM_TEST_SEQ=i2c_target_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /de
v/null -cm_name 42.i2c_target_stress_all.1347879123
Directory /workspace/42.i2c_target_stress_all/latest

Test location /workspace/coverage/default/42.i2c_target_stress_rd.2104276964
Short name T1702
Test name
Test status
Simulation time 1348523810 ps
CPU time 21.8 seconds
Started Aug 12 04:45:50 PM PDT 24
Finished Aug 12 04:46:11 PM PDT 24
Peak memory 230900 kb
Host smart-0bb3dba0-199c-421d-a90d-5c03069f33b9
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=100_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licq
ueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2104276964 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SE
Q=i2c_target_stress_rd_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.i2
c_target_stress_rd.2104276964
Directory /workspace/42.i2c_target_stress_rd/latest

Test location /workspace/coverage/default/42.i2c_target_stress_wr.2472904334
Short name T201
Test name
Test status
Simulation time 21556328704 ps
CPU time 11.51 seconds
Started Aug 12 04:45:54 PM PDT 24
Finished Aug 12 04:46:06 PM PDT 24
Peak memory 205532 kb
Host smart-1f312e8b-8982-41d5-8d90-8dd2f5ff6fed
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=600_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licq
ueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2472904334 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SE
Q=i2c_target_stress_wr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.i2
c_target_stress_wr.2472904334
Directory /workspace/42.i2c_target_stress_wr/latest

Test location /workspace/coverage/default/42.i2c_target_stretch.1810715997
Short name T184
Test name
Test status
Simulation time 1474315831 ps
CPU time 5.33 seconds
Started Aug 12 04:45:54 PM PDT 24
Finished Aug 12 04:46:00 PM PDT 24
Peak memory 219772 kb
Host smart-8cf7f3a3-e7bc-4282-917c-69cbc5c583f7
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=400_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licq
ueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1810715997 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SE
Q=i2c_target_stretch_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.i2c_
target_stretch.1810715997
Directory /workspace/42.i2c_target_stretch/latest

Test location /workspace/coverage/default/42.i2c_target_timeout.2230242438
Short name T747
Test name
Test status
Simulation time 1471385409 ps
CPU time 7.43 seconds
Started Aug 12 04:46:03 PM PDT 24
Finished Aug 12 04:46:11 PM PDT 24
Peak memory 221820 kb
Host smart-47b65445-e71c-46f9-9543-9d7134d33e7a
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=50_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2230242438 -assert nopostproc +UVM_TESTNAME=i2c_bas
e_test +UVM_TEST_SEQ=i2c_target_timeout_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/nu
ll -cm_name 42.i2c_target_timeout.2230242438
Directory /workspace/42.i2c_target_timeout/latest

Test location /workspace/coverage/default/42.i2c_target_tx_stretch_ctrl.956612236
Short name T1593
Test name
Test status
Simulation time 146150289 ps
CPU time 3.16 seconds
Started Aug 12 04:46:02 PM PDT 24
Finished Aug 12 04:46:05 PM PDT 24
Peak memory 205600 kb
Host smart-b6cbe2d3-23a6-4900-8c4d-79a68965636a
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=956612236 -assert nopostproc +UVM_TESTNAME=i2c_base
_test +UVM_TEST_SEQ=i2c_target_tx_stretch_ctrl_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log
/dev/null -cm_name 42.i2c_target_tx_stretch_ctrl.956612236
Directory /workspace/42.i2c_target_tx_stretch_ctrl/latest

Test location /workspace/coverage/default/43.i2c_alert_test.1954857234
Short name T550
Test name
Test status
Simulation time 36703938 ps
CPU time 0.63 seconds
Started Aug 12 04:46:08 PM PDT 24
Finished Aug 12 04:46:08 PM PDT 24
Peak memory 204404 kb
Host smart-d5fbff2c-ca06-45e7-8065-ea1e0a9485d9
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1954857234 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_common_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.i2c_alert_test.1954857234
Directory /workspace/43.i2c_alert_test/latest

Test location /workspace/coverage/default/43.i2c_host_error_intr.987584577
Short name T1677
Test name
Test status
Simulation time 583840989 ps
CPU time 2.08 seconds
Started Aug 12 04:46:09 PM PDT 24
Finished Aug 12 04:46:12 PM PDT 24
Peak memory 221600 kb
Host smart-a61f442c-54e2-410c-a25b-66311b89202a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=987584577 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_error_intr_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.i2c_host_error_intr.987584577
Directory /workspace/43.i2c_host_error_intr/latest

Test location /workspace/coverage/default/43.i2c_host_fifo_fmt_empty.2260340469
Short name T504
Test name
Test status
Simulation time 951631272 ps
CPU time 11.12 seconds
Started Aug 12 04:46:03 PM PDT 24
Finished Aug 12 04:46:14 PM PDT 24
Peak memory 243188 kb
Host smart-cb68dd41-b7d3-477f-bb7f-c12125e3a9c1
User root
Command /workspace/default/simv +test_timeout_ns=10_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2260340469 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_fifo_fmt_em
pty_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.i2c_host_fifo_fmt_emp
ty.2260340469
Directory /workspace/43.i2c_host_fifo_fmt_empty/latest

Test location /workspace/coverage/default/43.i2c_host_fifo_full.255329139
Short name T1233
Test name
Test status
Simulation time 5113809629 ps
CPU time 65.73 seconds
Started Aug 12 04:46:00 PM PDT 24
Finished Aug 12 04:47:06 PM PDT 24
Peak memory 486280 kb
Host smart-2e142f5f-b263-43fc-a3df-0631e5e2286a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=255329139 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_fifo_full_vseq +en_cov=1 -cm line+cond+f
sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.i2c_host_fifo_full.255329139
Directory /workspace/43.i2c_host_fifo_full/latest

Test location /workspace/coverage/default/43.i2c_host_fifo_overflow.3716309361
Short name T777
Test name
Test status
Simulation time 2912356508 ps
CPU time 43.28 seconds
Started Aug 12 04:46:00 PM PDT 24
Finished Aug 12 04:46:44 PM PDT 24
Peak memory 518412 kb
Host smart-6f8e7ac3-809c-4582-a8a8-4b3f031ee88f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3716309361 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_fifo_overflow_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.i2c_host_fifo_overflow.3716309361
Directory /workspace/43.i2c_host_fifo_overflow/latest

Test location /workspace/coverage/default/43.i2c_host_fifo_reset_fmt.775248500
Short name T35
Test name
Test status
Simulation time 395846658 ps
CPU time 1.19 seconds
Started Aug 12 04:46:01 PM PDT 24
Finished Aug 12 04:46:02 PM PDT 24
Peak memory 205140 kb
Host smart-9d9501e8-d899-4d06-a661-99c528cffb04
User root
Command /workspace/default/simv +test_timeout_ns=10_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=775248500 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_fifo_reset_f
mt_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.i2c_host_fifo_reset_fm
t.775248500
Directory /workspace/43.i2c_host_fifo_reset_fmt/latest

Test location /workspace/coverage/default/43.i2c_host_fifo_reset_rx.1271019069
Short name T1725
Test name
Test status
Simulation time 149589433 ps
CPU time 4.31 seconds
Started Aug 12 04:46:09 PM PDT 24
Finished Aug 12 04:46:14 PM PDT 24
Peak memory 229720 kb
Host smart-29c41c91-0e0d-4f62-86ac-ed4e4a58dad2
User root
Command /workspace/default/simv +test_timeout_ns=10_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1271019069 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_fifo_reset_
rx_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.i2c_host_fifo_reset_rx
.1271019069
Directory /workspace/43.i2c_host_fifo_reset_rx/latest

Test location /workspace/coverage/default/43.i2c_host_fifo_watermark.2856767938
Short name T1211
Test name
Test status
Simulation time 3200661791 ps
CPU time 191.6 seconds
Started Aug 12 04:46:02 PM PDT 24
Finished Aug 12 04:49:13 PM PDT 24
Peak memory 885340 kb
Host smart-4604e9d7-3c30-47fe-ba14-bf6ff6b1afd9
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2856767938 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_fifo_watermark_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.i2c_host_fifo_watermark.2856767938
Directory /workspace/43.i2c_host_fifo_watermark/latest

Test location /workspace/coverage/default/43.i2c_host_may_nack.2828571785
Short name T926
Test name
Test status
Simulation time 1441184291 ps
CPU time 14.99 seconds
Started Aug 12 04:46:10 PM PDT 24
Finished Aug 12 04:46:25 PM PDT 24
Peak memory 205292 kb
Host smart-3f5fc0b1-ea3f-48f2-9979-f9356d437f03
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2828571785 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_may_nack_vseq +en_cov=1 -cm line+cond+f
sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.i2c_host_may_nack.2828571785
Directory /workspace/43.i2c_host_may_nack/latest

Test location /workspace/coverage/default/43.i2c_host_override.3255444202
Short name T752
Test name
Test status
Simulation time 19744635 ps
CPU time 0.67 seconds
Started Aug 12 04:46:02 PM PDT 24
Finished Aug 12 04:46:03 PM PDT 24
Peak memory 204952 kb
Host smart-670374e8-9ffa-4dd5-b501-d0904cab2c87
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3255444202 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_override_vseq +en_cov=1 -cm line+cond+f
sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.i2c_host_override.3255444202
Directory /workspace/43.i2c_host_override/latest

Test location /workspace/coverage/default/43.i2c_host_perf.1847120522
Short name T38
Test name
Test status
Simulation time 4658543009 ps
CPU time 9.92 seconds
Started Aug 12 04:46:08 PM PDT 24
Finished Aug 12 04:46:19 PM PDT 24
Peak memory 305320 kb
Host smart-57ec757a-4b84-46dd-a034-665a2a8ded48
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1847120522 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_perf_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.i2c_host_perf.1847120522
Directory /workspace/43.i2c_host_perf/latest

Test location /workspace/coverage/default/43.i2c_host_perf_precise.1410336533
Short name T888
Test name
Test status
Simulation time 218236927 ps
CPU time 1.58 seconds
Started Aug 12 04:46:01 PM PDT 24
Finished Aug 12 04:46:03 PM PDT 24
Peak memory 222820 kb
Host smart-6802d12d-5847-40bc-820a-d59703698589
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1410336533 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_perf_precise_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.i2c_host_perf_precise.1410336533
Directory /workspace/43.i2c_host_perf_precise/latest

Test location /workspace/coverage/default/43.i2c_host_smoke.1786887142
Short name T590
Test name
Test status
Simulation time 1850897329 ps
CPU time 29.85 seconds
Started Aug 12 04:46:01 PM PDT 24
Finished Aug 12 04:46:31 PM PDT 24
Peak memory 366896 kb
Host smart-11702d29-8ede-4f51-b11d-f9e95f86a5ce
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1786887142 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_smoke_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.i2c_host_smoke.1786887142
Directory /workspace/43.i2c_host_smoke/latest

Test location /workspace/coverage/default/43.i2c_host_stretch_timeout.2766566308
Short name T1091
Test name
Test status
Simulation time 3531508369 ps
CPU time 41.16 seconds
Started Aug 12 04:46:02 PM PDT 24
Finished Aug 12 04:46:43 PM PDT 24
Peak memory 213500 kb
Host smart-e2f47b1d-81ed-4170-8639-975b4a18837d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2766566308 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_stretch_timeout_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.i2c_host_stretch_timeout.2766566308
Directory /workspace/43.i2c_host_stretch_timeout/latest

Test location /workspace/coverage/default/43.i2c_target_bad_addr.1105543725
Short name T1370
Test name
Test status
Simulation time 3512197033 ps
CPU time 5.11 seconds
Started Aug 12 04:46:08 PM PDT 24
Finished Aug 12 04:46:13 PM PDT 24
Peak memory 221836 kb
Host smart-ebf0d2b0-0b8c-4af2-a851-e377b124bdd3
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +i2c_bad_addr_pct=50 +cdc_instrumentation_enabled=1 +UVM_
NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1105543725 -assert nopostproc
+UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_target_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.
vdb -cm_log /dev/null -cm_name 43.i2c_target_bad_addr.1105543725
Directory /workspace/43.i2c_target_bad_addr/latest

Test location /workspace/coverage/default/43.i2c_target_fifo_reset_acq.2583574447
Short name T1438
Test name
Test status
Simulation time 571184490 ps
CPU time 1.18 seconds
Started Aug 12 04:46:00 PM PDT 24
Finished Aug 12 04:46:01 PM PDT 24
Peak memory 205268 kb
Host smart-a5b02a66-9faa-4f71-969e-d88027d61583
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2583574447 -assert nopostproc +UVM_TESTNAME=i2c_bas
e_test +UVM_TEST_SEQ=i2c_target_fifo_reset_acq_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log
/dev/null -cm_name 43.i2c_target_fifo_reset_acq.2583574447
Directory /workspace/43.i2c_target_fifo_reset_acq/latest

Test location /workspace/coverage/default/43.i2c_target_fifo_reset_tx.3855858488
Short name T534
Test name
Test status
Simulation time 335471746 ps
CPU time 1.23 seconds
Started Aug 12 04:46:07 PM PDT 24
Finished Aug 12 04:46:08 PM PDT 24
Peak memory 205224 kb
Host smart-43f06375-42ee-45ab-843a-d752d1aff09c
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3855858488 -assert nopostproc +UVM_TESTNAME=i2c_bas
e_test +UVM_TEST_SEQ=i2c_target_fifo_reset_tx_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /
dev/null -cm_name 43.i2c_target_fifo_reset_tx.3855858488
Directory /workspace/43.i2c_target_fifo_reset_tx/latest

Test location /workspace/coverage/default/43.i2c_target_fifo_watermarks_acq.169606028
Short name T913
Test name
Test status
Simulation time 136265115 ps
CPU time 1.14 seconds
Started Aug 12 04:46:10 PM PDT 24
Finished Aug 12 04:46:11 PM PDT 24
Peak memory 205232 kb
Host smart-b3f2db47-855b-4de2-96f1-e0f34b3e1bd2
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=169606028 -assert nopostproc +UVM_TESTNAME=i2c_base
_test +UVM_TEST_SEQ=i2c_target_fifo_watermarks_acq_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_
log /dev/null -cm_name 43.i2c_target_fifo_watermarks_acq.169606028
Directory /workspace/43.i2c_target_fifo_watermarks_acq/latest

Test location /workspace/coverage/default/43.i2c_target_fifo_watermarks_tx.379608000
Short name T1570
Test name
Test status
Simulation time 261083567 ps
CPU time 1.42 seconds
Started Aug 12 04:46:06 PM PDT 24
Finished Aug 12 04:46:08 PM PDT 24
Peak memory 205224 kb
Host smart-d16815e3-b23b-4895-ab31-99d02f472154
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=379608000 -assert nopostproc +UVM_TESTNAME=i2c_base
_test +UVM_TEST_SEQ=i2c_target_fifo_watermarks_tx_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_l
og /dev/null -cm_name 43.i2c_target_fifo_watermarks_tx.379608000
Directory /workspace/43.i2c_target_fifo_watermarks_tx/latest

Test location /workspace/coverage/default/43.i2c_target_intr_smoke.4028809870
Short name T306
Test name
Test status
Simulation time 895897914 ps
CPU time 5.55 seconds
Started Aug 12 04:46:00 PM PDT 24
Finished Aug 12 04:46:06 PM PDT 24
Peak memory 221768 kb
Host smart-cafea4ab-190d-4af3-8ee2-632dab91f1c6
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=200_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VER
BOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4028809870 -assert nopostproc +UVM_TESTNAME=i2c_ba
se_test +UVM_TEST_SEQ=i2c_target_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/nul
l -cm_name 43.i2c_target_intr_smoke.4028809870
Directory /workspace/43.i2c_target_intr_smoke/latest

Test location /workspace/coverage/default/43.i2c_target_intr_stress_wr.2845189410
Short name T401
Test name
Test status
Simulation time 12321154435 ps
CPU time 13.37 seconds
Started Aug 12 04:46:09 PM PDT 24
Finished Aug 12 04:46:23 PM PDT 24
Peak memory 356492 kb
Host smart-12116edc-98cc-4a84-ab58-6e8a9e5c4e1b
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=600_000_000 +use_intr_handler=1 +slow_acq=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNO
TES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2845189410 -assert nopostproc +UVM_TES
TNAME=i2c_base_test +UVM_TEST_SEQ=i2c_target_stress_wr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb
-cm_log /dev/null -cm_name 43.i2c_target_intr_stress_wr.2845189410
Directory /workspace/43.i2c_target_intr_stress_wr/latest

Test location /workspace/coverage/default/43.i2c_target_nack_acqfull.2989469775
Short name T1447
Test name
Test status
Simulation time 652824930 ps
CPU time 3.17 seconds
Started Aug 12 04:46:09 PM PDT 24
Finished Aug 12 04:46:13 PM PDT 24
Peak memory 213672 kb
Host smart-27f760a0-1733-4974-93b9-18a4b21c6c47
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2989469775 -assert nopostproc +UVM_TESTNAME=i2c_bas
e_test +UVM_TEST_SEQ=i2c_target_nack_acqfull_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /d
ev/null -cm_name 43.i2c_target_nack_acqfull.2989469775
Directory /workspace/43.i2c_target_nack_acqfull/latest

Test location /workspace/coverage/default/43.i2c_target_nack_acqfull_addr.3576067983
Short name T729
Test name
Test status
Simulation time 3467898813 ps
CPU time 2.52 seconds
Started Aug 12 04:46:10 PM PDT 24
Finished Aug 12 04:46:13 PM PDT 24
Peak memory 205628 kb
Host smart-2e3c0774-0a55-4f51-a0a5-d00ba0450c45
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3576067983 -assert nopostproc +UVM_TESTNAME=i2c_bas
e_test +UVM_TEST_SEQ=i2c_target_nack_acqfull_addr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_l
og /dev/null -cm_name 43.i2c_target_nack_acqfull_addr.3576067983
Directory /workspace/43.i2c_target_nack_acqfull_addr/latest

Test location /workspace/coverage/default/43.i2c_target_nack_txstretch.2429852274
Short name T180
Test name
Test status
Simulation time 158058074 ps
CPU time 1.59 seconds
Started Aug 12 04:46:08 PM PDT 24
Finished Aug 12 04:46:10 PM PDT 24
Peak memory 222368 kb
Host smart-95f7a41f-ad24-432a-91fc-eb748992d153
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2429852274 -assert nopostproc +UVM_TESTNAME=i2c_bas
e_test +UVM_TEST_SEQ=i2c_target_nack_txstretch_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log
/dev/null -cm_name 43.i2c_target_nack_txstretch.2429852274
Directory /workspace/43.i2c_target_nack_txstretch/latest

Test location /workspace/coverage/default/43.i2c_target_perf.3222667898
Short name T500
Test name
Test status
Simulation time 3598368953 ps
CPU time 8 seconds
Started Aug 12 04:46:08 PM PDT 24
Finished Aug 12 04:46:16 PM PDT 24
Peak memory 230088 kb
Host smart-2bb8a307-a352-4604-8dbd-25fd85939c3e
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3222667898 -assert nopostproc +UVM_TESTNAME=i2c_bas
e_test +UVM_TEST_SEQ=i2c_target_perf_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null
-cm_name 43.i2c_target_perf.3222667898
Directory /workspace/43.i2c_target_perf/latest

Test location /workspace/coverage/default/43.i2c_target_smbus_maxlen.2290262486
Short name T476
Test name
Test status
Simulation time 1915663310 ps
CPU time 2.44 seconds
Started Aug 12 04:46:08 PM PDT 24
Finished Aug 12 04:46:11 PM PDT 24
Peak memory 205364 kb
Host smart-cb7804af-18ca-4113-a63c-4562a01b5614
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2290262486 -assert nopostproc +UVM_TESTNAME=i2c_bas
e_test +UVM_TEST_SEQ=i2c_target_smbus_maxlen_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /d
ev/null -cm_name 43.i2c_target_smbus_maxlen.2290262486
Directory /workspace/43.i2c_target_smbus_maxlen/latest

Test location /workspace/coverage/default/43.i2c_target_smoke.2596885227
Short name T671
Test name
Test status
Simulation time 696294609 ps
CPU time 11.03 seconds
Started Aug 12 04:46:01 PM PDT 24
Finished Aug 12 04:46:12 PM PDT 24
Peak memory 213780 kb
Host smart-661b948f-8e80-4578-a386-940f2c9f329a
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=100_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licq
ueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2596885227 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SE
Q=i2c_target_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.i2c_ta
rget_smoke.2596885227
Directory /workspace/43.i2c_target_smoke/latest

Test location /workspace/coverage/default/43.i2c_target_stress_all.760931216
Short name T147
Test name
Test status
Simulation time 17959128260 ps
CPU time 492.18 seconds
Started Aug 12 04:46:07 PM PDT 24
Finished Aug 12 04:54:20 PM PDT 24
Peak memory 2933192 kb
Host smart-450803e0-ddf8-48c2-99b0-86b7879c370b
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=300_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VER
BOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=760931216 -assert nopostproc +UVM_TESTNAME=i2c_bas
e_test +UVM_TEST_SEQ=i2c_target_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev
/null -cm_name 43.i2c_target_stress_all.760931216
Directory /workspace/43.i2c_target_stress_all/latest

Test location /workspace/coverage/default/43.i2c_target_stress_rd.116374692
Short name T995
Test name
Test status
Simulation time 1161245910 ps
CPU time 20.14 seconds
Started Aug 12 04:45:58 PM PDT 24
Finished Aug 12 04:46:18 PM PDT 24
Peak memory 221728 kb
Host smart-796ca7c3-b38a-4fce-b4e8-b2287f46bf6a
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=100_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licq
ueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=116374692 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ
=i2c_target_stress_rd_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.i2c
_target_stress_rd.116374692
Directory /workspace/43.i2c_target_stress_rd/latest

Test location /workspace/coverage/default/43.i2c_target_stress_wr.3088447684
Short name T978
Test name
Test status
Simulation time 64556490476 ps
CPU time 318.35 seconds
Started Aug 12 04:46:00 PM PDT 24
Finished Aug 12 04:51:18 PM PDT 24
Peak memory 2982772 kb
Host smart-d79ba586-df3b-45a5-b2f3-d6dac64aa98e
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=600_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licq
ueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3088447684 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SE
Q=i2c_target_stress_wr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.i2
c_target_stress_wr.3088447684
Directory /workspace/43.i2c_target_stress_wr/latest

Test location /workspace/coverage/default/43.i2c_target_stretch.2947731414
Short name T482
Test name
Test status
Simulation time 3437842628 ps
CPU time 12.77 seconds
Started Aug 12 04:46:01 PM PDT 24
Finished Aug 12 04:46:13 PM PDT 24
Peak memory 381300 kb
Host smart-edaafdca-1b6a-4061-975f-52696bd532ce
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=400_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licq
ueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2947731414 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SE
Q=i2c_target_stretch_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.i2c_
target_stretch.2947731414
Directory /workspace/43.i2c_target_stretch/latest

Test location /workspace/coverage/default/43.i2c_target_timeout.302711091
Short name T850
Test name
Test status
Simulation time 2834012859 ps
CPU time 6.19 seconds
Started Aug 12 04:45:59 PM PDT 24
Finished Aug 12 04:46:06 PM PDT 24
Peak memory 213756 kb
Host smart-d1d3622c-3ea0-4fd6-8fb7-32d849c733b8
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=50_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=302711091 -assert nopostproc +UVM_TESTNAME=i2c_base
_test +UVM_TEST_SEQ=i2c_target_timeout_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/nul
l -cm_name 43.i2c_target_timeout.302711091
Directory /workspace/43.i2c_target_timeout/latest

Test location /workspace/coverage/default/43.i2c_target_tx_stretch_ctrl.1422637351
Short name T1359
Test name
Test status
Simulation time 359028197 ps
CPU time 4.94 seconds
Started Aug 12 04:46:13 PM PDT 24
Finished Aug 12 04:46:18 PM PDT 24
Peak memory 221096 kb
Host smart-bfc6d68a-50cc-4f94-a6ae-5f5c6694d58d
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1422637351 -assert nopostproc +UVM_TESTNAME=i2c_bas
e_test +UVM_TEST_SEQ=i2c_target_tx_stretch_ctrl_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log
/dev/null -cm_name 43.i2c_target_tx_stretch_ctrl.1422637351
Directory /workspace/43.i2c_target_tx_stretch_ctrl/latest

Test location /workspace/coverage/default/44.i2c_alert_test.4018153461
Short name T371
Test name
Test status
Simulation time 14913683 ps
CPU time 0.65 seconds
Started Aug 12 04:46:17 PM PDT 24
Finished Aug 12 04:46:18 PM PDT 24
Peak memory 204408 kb
Host smart-c92dc35f-68c0-48d6-9e85-d9578c5c367a
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4018153461 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_common_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.i2c_alert_test.4018153461
Directory /workspace/44.i2c_alert_test/latest

Test location /workspace/coverage/default/44.i2c_host_error_intr.3670646678
Short name T541
Test name
Test status
Simulation time 100292404 ps
CPU time 1.68 seconds
Started Aug 12 04:46:05 PM PDT 24
Finished Aug 12 04:46:07 PM PDT 24
Peak memory 213560 kb
Host smart-5a01a6bf-1ab3-4a58-851a-9980add97077
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3670646678 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_error_intr_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.i2c_host_error_intr.3670646678
Directory /workspace/44.i2c_host_error_intr/latest

Test location /workspace/coverage/default/44.i2c_host_fifo_fmt_empty.2606573273
Short name T593
Test name
Test status
Simulation time 1092932559 ps
CPU time 5.19 seconds
Started Aug 12 04:46:09 PM PDT 24
Finished Aug 12 04:46:15 PM PDT 24
Peak memory 252152 kb
Host smart-7b7dda6f-c512-4c67-a53e-5869352d49da
User root
Command /workspace/default/simv +test_timeout_ns=10_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2606573273 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_fifo_fmt_em
pty_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.i2c_host_fifo_fmt_emp
ty.2606573273
Directory /workspace/44.i2c_host_fifo_fmt_empty/latest

Test location /workspace/coverage/default/44.i2c_host_fifo_full.1336553366
Short name T1549
Test name
Test status
Simulation time 12422856190 ps
CPU time 177.67 seconds
Started Aug 12 04:46:09 PM PDT 24
Finished Aug 12 04:49:07 PM PDT 24
Peak memory 424264 kb
Host smart-d3406a51-cf9c-43a9-9832-ea8be99e4d99
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1336553366 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_fifo_full_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.i2c_host_fifo_full.1336553366
Directory /workspace/44.i2c_host_fifo_full/latest

Test location /workspace/coverage/default/44.i2c_host_fifo_overflow.2474283117
Short name T1094
Test name
Test status
Simulation time 1553935273 ps
CPU time 41.65 seconds
Started Aug 12 04:46:07 PM PDT 24
Finished Aug 12 04:46:49 PM PDT 24
Peak memory 550136 kb
Host smart-905d47e5-4084-4192-80f5-7617e0eba5f1
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2474283117 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_fifo_overflow_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.i2c_host_fifo_overflow.2474283117
Directory /workspace/44.i2c_host_fifo_overflow/latest

Test location /workspace/coverage/default/44.i2c_host_fifo_reset_fmt.1773556350
Short name T799
Test name
Test status
Simulation time 205085115 ps
CPU time 1.09 seconds
Started Aug 12 04:46:13 PM PDT 24
Finished Aug 12 04:46:14 PM PDT 24
Peak memory 204820 kb
Host smart-406c50a8-2754-4b30-b1b7-87ac7978a282
User root
Command /workspace/default/simv +test_timeout_ns=10_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1773556350 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_fifo_reset_
fmt_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.i2c_host_fifo_reset_f
mt.1773556350
Directory /workspace/44.i2c_host_fifo_reset_fmt/latest

Test location /workspace/coverage/default/44.i2c_host_fifo_reset_rx.3524653244
Short name T879
Test name
Test status
Simulation time 888812223 ps
CPU time 3.53 seconds
Started Aug 12 04:46:14 PM PDT 24
Finished Aug 12 04:46:17 PM PDT 24
Peak memory 205224 kb
Host smart-9dfaa27a-5cf3-43e3-a48c-2bbf394d0696
User root
Command /workspace/default/simv +test_timeout_ns=10_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3524653244 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_fifo_reset_
rx_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.i2c_host_fifo_reset_rx
.3524653244
Directory /workspace/44.i2c_host_fifo_reset_rx/latest

Test location /workspace/coverage/default/44.i2c_host_fifo_watermark.4104964700
Short name T439
Test name
Test status
Simulation time 11493219686 ps
CPU time 266.6 seconds
Started Aug 12 04:46:06 PM PDT 24
Finished Aug 12 04:50:33 PM PDT 24
Peak memory 1115100 kb
Host smart-e410b969-d045-4c98-ada7-4df57395d4c3
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4104964700 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_fifo_watermark_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.i2c_host_fifo_watermark.4104964700
Directory /workspace/44.i2c_host_fifo_watermark/latest

Test location /workspace/coverage/default/44.i2c_host_may_nack.1097988975
Short name T939
Test name
Test status
Simulation time 250496932 ps
CPU time 9.62 seconds
Started Aug 12 04:46:14 PM PDT 24
Finished Aug 12 04:46:24 PM PDT 24
Peak memory 205224 kb
Host smart-efada3d1-c65b-473a-90fb-407fed94997f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1097988975 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_may_nack_vseq +en_cov=1 -cm line+cond+f
sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.i2c_host_may_nack.1097988975
Directory /workspace/44.i2c_host_may_nack/latest

Test location /workspace/coverage/default/44.i2c_host_mode_toggle.3444950339
Short name T1138
Test name
Test status
Simulation time 223731122 ps
CPU time 1.72 seconds
Started Aug 12 04:46:15 PM PDT 24
Finished Aug 12 04:46:17 PM PDT 24
Peak memory 213560 kb
Host smart-15b3c45d-2929-43fc-bffa-3c24c7308821
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3444950339 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_mode_toggle_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.i2c_host_mode_toggle.3444950339
Directory /workspace/44.i2c_host_mode_toggle/latest

Test location /workspace/coverage/default/44.i2c_host_override.1626195289
Short name T1651
Test name
Test status
Simulation time 20321889 ps
CPU time 0.65 seconds
Started Aug 12 04:46:12 PM PDT 24
Finished Aug 12 04:46:13 PM PDT 24
Peak memory 204928 kb
Host smart-8a8620cb-9b83-4114-8118-559c50710e53
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1626195289 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_override_vseq +en_cov=1 -cm line+cond+f
sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.i2c_host_override.1626195289
Directory /workspace/44.i2c_host_override/latest

Test location /workspace/coverage/default/44.i2c_host_perf.3243704192
Short name T702
Test name
Test status
Simulation time 2623952647 ps
CPU time 17.39 seconds
Started Aug 12 04:46:11 PM PDT 24
Finished Aug 12 04:46:28 PM PDT 24
Peak memory 221484 kb
Host smart-ab1dfa64-0c04-42d1-a81b-d8aa810bdc7f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3243704192 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_perf_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.i2c_host_perf.3243704192
Directory /workspace/44.i2c_host_perf/latest

Test location /workspace/coverage/default/44.i2c_host_perf_precise.3723414857
Short name T539
Test name
Test status
Simulation time 199629413 ps
CPU time 2.43 seconds
Started Aug 12 04:46:15 PM PDT 24
Finished Aug 12 04:46:18 PM PDT 24
Peak memory 205108 kb
Host smart-ef2e44b0-b47c-4d90-8236-712141b1ab12
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3723414857 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_perf_precise_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.i2c_host_perf_precise.3723414857
Directory /workspace/44.i2c_host_perf_precise/latest

Test location /workspace/coverage/default/44.i2c_host_smoke.343356389
Short name T1341
Test name
Test status
Simulation time 1013868060 ps
CPU time 15.21 seconds
Started Aug 12 04:46:12 PM PDT 24
Finished Aug 12 04:46:27 PM PDT 24
Peak memory 297596 kb
Host smart-fb8ddfb1-50db-430f-83c6-e039611e3d5f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=343356389 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_smoke_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.i2c_host_smoke.343356389
Directory /workspace/44.i2c_host_smoke/latest

Test location /workspace/coverage/default/44.i2c_host_stretch_timeout.1184472913
Short name T424
Test name
Test status
Simulation time 841305997 ps
CPU time 17.74 seconds
Started Aug 12 04:46:09 PM PDT 24
Finished Aug 12 04:46:26 PM PDT 24
Peak memory 213568 kb
Host smart-ac417b4b-7026-4bce-8374-76ab6a266bf2
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1184472913 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_stretch_timeout_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.i2c_host_stretch_timeout.1184472913
Directory /workspace/44.i2c_host_stretch_timeout/latest

Test location /workspace/coverage/default/44.i2c_target_bad_addr.373721169
Short name T1300
Test name
Test status
Simulation time 780202906 ps
CPU time 4.87 seconds
Started Aug 12 04:46:15 PM PDT 24
Finished Aug 12 04:46:20 PM PDT 24
Peak memory 219288 kb
Host smart-2182bc3f-c8c9-4786-ace4-e4717a786d5a
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +i2c_bad_addr_pct=50 +cdc_instrumentation_enabled=1 +UVM_
NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=373721169 -assert nopostproc +
UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_target_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.v
db -cm_log /dev/null -cm_name 44.i2c_target_bad_addr.373721169
Directory /workspace/44.i2c_target_bad_addr/latest

Test location /workspace/coverage/default/44.i2c_target_fifo_reset_acq.1833993753
Short name T921
Test name
Test status
Simulation time 625173173 ps
CPU time 1.38 seconds
Started Aug 12 04:46:14 PM PDT 24
Finished Aug 12 04:46:15 PM PDT 24
Peak memory 205480 kb
Host smart-60234a14-4fd0-444a-94ce-8b53105d3108
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1833993753 -assert nopostproc +UVM_TESTNAME=i2c_bas
e_test +UVM_TEST_SEQ=i2c_target_fifo_reset_acq_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log
/dev/null -cm_name 44.i2c_target_fifo_reset_acq.1833993753
Directory /workspace/44.i2c_target_fifo_reset_acq/latest

Test location /workspace/coverage/default/44.i2c_target_fifo_reset_tx.2634912284
Short name T1007
Test name
Test status
Simulation time 206932111 ps
CPU time 1.41 seconds
Started Aug 12 04:46:09 PM PDT 24
Finished Aug 12 04:46:11 PM PDT 24
Peak memory 205232 kb
Host smart-e2e34180-3b74-4880-804e-83860c22004d
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2634912284 -assert nopostproc +UVM_TESTNAME=i2c_bas
e_test +UVM_TEST_SEQ=i2c_target_fifo_reset_tx_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /
dev/null -cm_name 44.i2c_target_fifo_reset_tx.2634912284
Directory /workspace/44.i2c_target_fifo_reset_tx/latest

Test location /workspace/coverage/default/44.i2c_target_fifo_watermarks_acq.815618006
Short name T1369
Test name
Test status
Simulation time 1233976473 ps
CPU time 2.24 seconds
Started Aug 12 04:46:14 PM PDT 24
Finished Aug 12 04:46:16 PM PDT 24
Peak memory 205244 kb
Host smart-8c23af7a-14ab-49e8-b39f-e2686bdc0ad8
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=815618006 -assert nopostproc +UVM_TESTNAME=i2c_base
_test +UVM_TEST_SEQ=i2c_target_fifo_watermarks_acq_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_
log /dev/null -cm_name 44.i2c_target_fifo_watermarks_acq.815618006
Directory /workspace/44.i2c_target_fifo_watermarks_acq/latest

Test location /workspace/coverage/default/44.i2c_target_fifo_watermarks_tx.537561915
Short name T1462
Test name
Test status
Simulation time 168442882 ps
CPU time 1.57 seconds
Started Aug 12 04:46:14 PM PDT 24
Finished Aug 12 04:46:16 PM PDT 24
Peak memory 205264 kb
Host smart-76b3e0ab-90c8-498d-9d9c-a55a157400c0
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=537561915 -assert nopostproc +UVM_TESTNAME=i2c_base
_test +UVM_TEST_SEQ=i2c_target_fifo_watermarks_tx_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_l
og /dev/null -cm_name 44.i2c_target_fifo_watermarks_tx.537561915
Directory /workspace/44.i2c_target_fifo_watermarks_tx/latest

Test location /workspace/coverage/default/44.i2c_target_hrst.4185347739
Short name T1135
Test name
Test status
Simulation time 398571163 ps
CPU time 1.72 seconds
Started Aug 12 04:46:14 PM PDT 24
Finished Aug 12 04:46:16 PM PDT 24
Peak memory 213636 kb
Host smart-3a00be58-c952-4e4d-8835-8c01d5807ce9
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4185347739 -assert nopostproc +UVM_TESTNAME=i2c_bas
e_test +UVM_TEST_SEQ=i2c_target_hrst_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null
-cm_name 44.i2c_target_hrst.4185347739
Directory /workspace/44.i2c_target_hrst/latest

Test location /workspace/coverage/default/44.i2c_target_intr_smoke.207051891
Short name T646
Test name
Test status
Simulation time 4856788350 ps
CPU time 6.69 seconds
Started Aug 12 04:46:14 PM PDT 24
Finished Aug 12 04:46:21 PM PDT 24
Peak memory 221900 kb
Host smart-f88efdf5-15de-4b99-92f3-e24284c54384
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=200_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VER
BOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=207051891 -assert nopostproc +UVM_TESTNAME=i2c_bas
e_test +UVM_TEST_SEQ=i2c_target_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null
-cm_name 44.i2c_target_intr_smoke.207051891
Directory /workspace/44.i2c_target_intr_smoke/latest

Test location /workspace/coverage/default/44.i2c_target_intr_stress_wr.3020476717
Short name T492
Test name
Test status
Simulation time 8170972911 ps
CPU time 41.43 seconds
Started Aug 12 04:46:11 PM PDT 24
Finished Aug 12 04:46:52 PM PDT 24
Peak memory 1061940 kb
Host smart-3f8ee219-c1d7-4b49-aedb-dec71fd2f90a
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=600_000_000 +use_intr_handler=1 +slow_acq=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNO
TES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3020476717 -assert nopostproc +UVM_TES
TNAME=i2c_base_test +UVM_TEST_SEQ=i2c_target_stress_wr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb
-cm_log /dev/null -cm_name 44.i2c_target_intr_stress_wr.3020476717
Directory /workspace/44.i2c_target_intr_stress_wr/latest

Test location /workspace/coverage/default/44.i2c_target_nack_acqfull.3395235447
Short name T167
Test name
Test status
Simulation time 2121993806 ps
CPU time 2.88 seconds
Started Aug 12 04:46:14 PM PDT 24
Finished Aug 12 04:46:17 PM PDT 24
Peak memory 213656 kb
Host smart-94d7defc-7ab4-4edc-a10e-2adddbd3a74a
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3395235447 -assert nopostproc +UVM_TESTNAME=i2c_bas
e_test +UVM_TEST_SEQ=i2c_target_nack_acqfull_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /d
ev/null -cm_name 44.i2c_target_nack_acqfull.3395235447
Directory /workspace/44.i2c_target_nack_acqfull/latest

Test location /workspace/coverage/default/44.i2c_target_nack_acqfull_addr.1506440449
Short name T1020
Test name
Test status
Simulation time 473734666 ps
CPU time 2.41 seconds
Started Aug 12 04:46:14 PM PDT 24
Finished Aug 12 04:46:17 PM PDT 24
Peak memory 205504 kb
Host smart-6b59506e-305b-4843-b9c0-37dfe70635d8
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1506440449 -assert nopostproc +UVM_TESTNAME=i2c_bas
e_test +UVM_TEST_SEQ=i2c_target_nack_acqfull_addr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_l
og /dev/null -cm_name 44.i2c_target_nack_acqfull_addr.1506440449
Directory /workspace/44.i2c_target_nack_acqfull_addr/latest

Test location /workspace/coverage/default/44.i2c_target_nack_txstretch.2896916233
Short name T1175
Test name
Test status
Simulation time 154044995 ps
CPU time 1.48 seconds
Started Aug 12 04:46:18 PM PDT 24
Finished Aug 12 04:46:19 PM PDT 24
Peak memory 222020 kb
Host smart-8592a59f-cb62-420f-956a-2bea81ce056a
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2896916233 -assert nopostproc +UVM_TESTNAME=i2c_bas
e_test +UVM_TEST_SEQ=i2c_target_nack_txstretch_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log
/dev/null -cm_name 44.i2c_target_nack_txstretch.2896916233
Directory /workspace/44.i2c_target_nack_txstretch/latest

Test location /workspace/coverage/default/44.i2c_target_perf.1671373378
Short name T47
Test name
Test status
Simulation time 2399986355 ps
CPU time 5.13 seconds
Started Aug 12 04:46:11 PM PDT 24
Finished Aug 12 04:46:16 PM PDT 24
Peak memory 221816 kb
Host smart-7b17a890-4351-4e79-8379-0810105d1c7a
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1671373378 -assert nopostproc +UVM_TESTNAME=i2c_bas
e_test +UVM_TEST_SEQ=i2c_target_perf_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null
-cm_name 44.i2c_target_perf.1671373378
Directory /workspace/44.i2c_target_perf/latest

Test location /workspace/coverage/default/44.i2c_target_smbus_maxlen.3457715426
Short name T763
Test name
Test status
Simulation time 503505383 ps
CPU time 2.51 seconds
Started Aug 12 04:46:15 PM PDT 24
Finished Aug 12 04:46:17 PM PDT 24
Peak memory 205248 kb
Host smart-adb01fb2-b03f-4dcb-981a-56b9942695d6
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3457715426 -assert nopostproc +UVM_TESTNAME=i2c_bas
e_test +UVM_TEST_SEQ=i2c_target_smbus_maxlen_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /d
ev/null -cm_name 44.i2c_target_smbus_maxlen.3457715426
Directory /workspace/44.i2c_target_smbus_maxlen/latest

Test location /workspace/coverage/default/44.i2c_target_smoke.1012013739
Short name T1728
Test name
Test status
Simulation time 742336330 ps
CPU time 8.62 seconds
Started Aug 12 04:46:12 PM PDT 24
Finished Aug 12 04:46:21 PM PDT 24
Peak memory 221828 kb
Host smart-683818a9-1e61-4209-ba43-d384bf1db08d
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=100_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licq
ueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1012013739 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SE
Q=i2c_target_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.i2c_ta
rget_smoke.1012013739
Directory /workspace/44.i2c_target_smoke/latest

Test location /workspace/coverage/default/44.i2c_target_stress_all.3772338047
Short name T1049
Test name
Test status
Simulation time 85481790862 ps
CPU time 246.6 seconds
Started Aug 12 04:46:14 PM PDT 24
Finished Aug 12 04:50:21 PM PDT 24
Peak memory 1259060 kb
Host smart-89ae4187-7909-47bc-8d6e-69a9f17ae259
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=300_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VER
BOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3772338047 -assert nopostproc +UVM_TESTNAME=i2c_ba
se_test +UVM_TEST_SEQ=i2c_target_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /de
v/null -cm_name 44.i2c_target_stress_all.3772338047
Directory /workspace/44.i2c_target_stress_all/latest

Test location /workspace/coverage/default/44.i2c_target_stress_rd.3082543135
Short name T1529
Test name
Test status
Simulation time 5926366162 ps
CPU time 69.75 seconds
Started Aug 12 04:46:09 PM PDT 24
Finished Aug 12 04:47:19 PM PDT 24
Peak memory 217296 kb
Host smart-6b0e57ea-0163-4cff-9b1a-3a3d1e62ab8a
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=100_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licq
ueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3082543135 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SE
Q=i2c_target_stress_rd_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.i2
c_target_stress_rd.3082543135
Directory /workspace/44.i2c_target_stress_rd/latest

Test location /workspace/coverage/default/44.i2c_target_stress_wr.3776130575
Short name T311
Test name
Test status
Simulation time 19354043645 ps
CPU time 10.52 seconds
Started Aug 12 04:46:07 PM PDT 24
Finished Aug 12 04:46:17 PM PDT 24
Peak memory 205576 kb
Host smart-837d8ff4-b9b9-4301-8beb-426907761815
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=600_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licq
ueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3776130575 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SE
Q=i2c_target_stress_wr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.i2
c_target_stress_wr.3776130575
Directory /workspace/44.i2c_target_stress_wr/latest

Test location /workspace/coverage/default/44.i2c_target_stretch.924347329
Short name T1624
Test name
Test status
Simulation time 2482305707 ps
CPU time 52.05 seconds
Started Aug 12 04:46:08 PM PDT 24
Finished Aug 12 04:47:01 PM PDT 24
Peak memory 462824 kb
Host smart-9670139b-a0de-4db4-965a-fceca999ecee
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=400_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licq
ueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=924347329 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ
=i2c_target_stretch_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.i2c_t
arget_stretch.924347329
Directory /workspace/44.i2c_target_stretch/latest

Test location /workspace/coverage/default/44.i2c_target_timeout.2167791814
Short name T521
Test name
Test status
Simulation time 1276989851 ps
CPU time 6.76 seconds
Started Aug 12 04:46:07 PM PDT 24
Finished Aug 12 04:46:14 PM PDT 24
Peak memory 213740 kb
Host smart-480b6509-88a7-4f7c-9862-ef6f682b0428
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=50_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2167791814 -assert nopostproc +UVM_TESTNAME=i2c_bas
e_test +UVM_TEST_SEQ=i2c_target_timeout_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/nu
ll -cm_name 44.i2c_target_timeout.2167791814
Directory /workspace/44.i2c_target_timeout/latest

Test location /workspace/coverage/default/44.i2c_target_tx_stretch_ctrl.3222317353
Short name T848
Test name
Test status
Simulation time 341690171 ps
CPU time 4.51 seconds
Started Aug 12 04:46:14 PM PDT 24
Finished Aug 12 04:46:19 PM PDT 24
Peak memory 205468 kb
Host smart-2f8aa105-9196-4881-8f08-e64eddf903de
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3222317353 -assert nopostproc +UVM_TESTNAME=i2c_bas
e_test +UVM_TEST_SEQ=i2c_target_tx_stretch_ctrl_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log
/dev/null -cm_name 44.i2c_target_tx_stretch_ctrl.3222317353
Directory /workspace/44.i2c_target_tx_stretch_ctrl/latest

Test location /workspace/coverage/default/45.i2c_alert_test.124504129
Short name T1532
Test name
Test status
Simulation time 106143887 ps
CPU time 0.6 seconds
Started Aug 12 04:46:21 PM PDT 24
Finished Aug 12 04:46:22 PM PDT 24
Peak memory 204448 kb
Host smart-f1b464ee-fc1b-4923-918d-80de42d82fef
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=124504129 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_common_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.i2c_alert_test.124504129
Directory /workspace/45.i2c_alert_test/latest

Test location /workspace/coverage/default/45.i2c_host_fifo_fmt_empty.490230918
Short name T1384
Test name
Test status
Simulation time 907005113 ps
CPU time 7.24 seconds
Started Aug 12 04:46:16 PM PDT 24
Finished Aug 12 04:46:23 PM PDT 24
Peak memory 271548 kb
Host smart-31e9eab9-4faa-4573-a82f-f6d1d14e0299
User root
Command /workspace/default/simv +test_timeout_ns=10_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=490230918 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_fifo_fmt_emp
ty_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.i2c_host_fifo_fmt_empt
y.490230918
Directory /workspace/45.i2c_host_fifo_fmt_empty/latest

Test location /workspace/coverage/default/45.i2c_host_fifo_full.1013203017
Short name T1739
Test name
Test status
Simulation time 2321941871 ps
CPU time 116.41 seconds
Started Aug 12 04:46:14 PM PDT 24
Finished Aug 12 04:48:11 PM PDT 24
Peak memory 243980 kb
Host smart-4231560f-ec99-4b45-b703-170173b94050
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1013203017 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_fifo_full_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.i2c_host_fifo_full.1013203017
Directory /workspace/45.i2c_host_fifo_full/latest

Test location /workspace/coverage/default/45.i2c_host_fifo_overflow.2727375040
Short name T585
Test name
Test status
Simulation time 6156249522 ps
CPU time 38.08 seconds
Started Aug 12 04:46:14 PM PDT 24
Finished Aug 12 04:46:53 PM PDT 24
Peak memory 545476 kb
Host smart-9621ac12-cb93-4af9-bd31-a9371cf29551
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2727375040 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_fifo_overflow_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.i2c_host_fifo_overflow.2727375040
Directory /workspace/45.i2c_host_fifo_overflow/latest

Test location /workspace/coverage/default/45.i2c_host_fifo_reset_fmt.1226320303
Short name T1394
Test name
Test status
Simulation time 162048485 ps
CPU time 0.88 seconds
Started Aug 12 04:46:14 PM PDT 24
Finished Aug 12 04:46:16 PM PDT 24
Peak memory 204940 kb
Host smart-8dcf3787-a649-4c94-a479-2fbf87bd31c2
User root
Command /workspace/default/simv +test_timeout_ns=10_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1226320303 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_fifo_reset_
fmt_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.i2c_host_fifo_reset_f
mt.1226320303
Directory /workspace/45.i2c_host_fifo_reset_fmt/latest

Test location /workspace/coverage/default/45.i2c_host_fifo_reset_rx.522748191
Short name T988
Test name
Test status
Simulation time 142431337 ps
CPU time 7.44 seconds
Started Aug 12 04:46:18 PM PDT 24
Finished Aug 12 04:46:25 PM PDT 24
Peak memory 226616 kb
Host smart-6dce14ff-2a89-463c-9652-18c18e39fe96
User root
Command /workspace/default/simv +test_timeout_ns=10_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=522748191 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_fifo_reset_r
x_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.i2c_host_fifo_reset_rx.
522748191
Directory /workspace/45.i2c_host_fifo_reset_rx/latest

Test location /workspace/coverage/default/45.i2c_host_fifo_watermark.955907528
Short name T398
Test name
Test status
Simulation time 13655634439 ps
CPU time 87.78 seconds
Started Aug 12 04:46:16 PM PDT 24
Finished Aug 12 04:47:44 PM PDT 24
Peak memory 962636 kb
Host smart-6498e51e-23a3-4e20-af49-19b0b0346057
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=955907528 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_fifo_watermark_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.i2c_host_fifo_watermark.955907528
Directory /workspace/45.i2c_host_fifo_watermark/latest

Test location /workspace/coverage/default/45.i2c_host_may_nack.2111931613
Short name T706
Test name
Test status
Simulation time 2796928557 ps
CPU time 6.45 seconds
Started Aug 12 04:46:23 PM PDT 24
Finished Aug 12 04:46:30 PM PDT 24
Peak memory 205240 kb
Host smart-11560054-8538-4bca-a0da-5baa7cc45dcb
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2111931613 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_may_nack_vseq +en_cov=1 -cm line+cond+f
sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.i2c_host_may_nack.2111931613
Directory /workspace/45.i2c_host_may_nack/latest

Test location /workspace/coverage/default/45.i2c_host_override.546176765
Short name T708
Test name
Test status
Simulation time 38542881 ps
CPU time 0.64 seconds
Started Aug 12 04:46:15 PM PDT 24
Finished Aug 12 04:46:16 PM PDT 24
Peak memory 204916 kb
Host smart-afc8149a-f2c9-423c-a320-d426000c5255
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=546176765 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_override_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.i2c_host_override.546176765
Directory /workspace/45.i2c_host_override/latest

Test location /workspace/coverage/default/45.i2c_host_perf.4193041715
Short name T1524
Test name
Test status
Simulation time 957336608 ps
CPU time 6.67 seconds
Started Aug 12 04:46:14 PM PDT 24
Finished Aug 12 04:46:21 PM PDT 24
Peak memory 251160 kb
Host smart-4071c30a-63c7-46f1-9664-4e7d15380038
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4193041715 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_perf_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.i2c_host_perf.4193041715
Directory /workspace/45.i2c_host_perf/latest

Test location /workspace/coverage/default/45.i2c_host_perf_precise.514201316
Short name T43
Test name
Test status
Simulation time 63947372 ps
CPU time 1.66 seconds
Started Aug 12 04:46:17 PM PDT 24
Finished Aug 12 04:46:19 PM PDT 24
Peak memory 214240 kb
Host smart-b2f4c2ec-af78-46b5-8a1f-cae1fa44475d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=514201316 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_perf_precise_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.i2c_host_perf_precise.514201316
Directory /workspace/45.i2c_host_perf_precise/latest

Test location /workspace/coverage/default/45.i2c_host_smoke.2039645929
Short name T460
Test name
Test status
Simulation time 1708296225 ps
CPU time 38.29 seconds
Started Aug 12 04:46:15 PM PDT 24
Finished Aug 12 04:46:54 PM PDT 24
Peak memory 310932 kb
Host smart-b81ed5f9-148b-4d51-b688-cf71a9858222
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2039645929 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_smoke_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.i2c_host_smoke.2039645929
Directory /workspace/45.i2c_host_smoke/latest

Test location /workspace/coverage/default/45.i2c_host_stretch_timeout.3513882745
Short name T341
Test name
Test status
Simulation time 1423880436 ps
CPU time 11.43 seconds
Started Aug 12 04:46:12 PM PDT 24
Finished Aug 12 04:46:24 PM PDT 24
Peak memory 213540 kb
Host smart-266f5c2a-97a6-42ec-b657-110b1cc98716
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3513882745 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_stretch_timeout_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.i2c_host_stretch_timeout.3513882745
Directory /workspace/45.i2c_host_stretch_timeout/latest

Test location /workspace/coverage/default/45.i2c_target_bad_addr.1047045429
Short name T1177
Test name
Test status
Simulation time 1089611364 ps
CPU time 6.03 seconds
Started Aug 12 04:46:22 PM PDT 24
Finished Aug 12 04:46:29 PM PDT 24
Peak memory 214156 kb
Host smart-16393b28-9d43-46d8-9f85-823020a173b5
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +i2c_bad_addr_pct=50 +cdc_instrumentation_enabled=1 +UVM_
NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1047045429 -assert nopostproc
+UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_target_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.
vdb -cm_log /dev/null -cm_name 45.i2c_target_bad_addr.1047045429
Directory /workspace/45.i2c_target_bad_addr/latest

Test location /workspace/coverage/default/45.i2c_target_fifo_reset_tx.2916179277
Short name T1671
Test name
Test status
Simulation time 934078501 ps
CPU time 1.39 seconds
Started Aug 12 04:46:17 PM PDT 24
Finished Aug 12 04:46:19 PM PDT 24
Peak memory 205524 kb
Host smart-3c811259-7de3-4c4d-82bf-1c05f0a87b6d
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2916179277 -assert nopostproc +UVM_TESTNAME=i2c_bas
e_test +UVM_TEST_SEQ=i2c_target_fifo_reset_tx_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /
dev/null -cm_name 45.i2c_target_fifo_reset_tx.2916179277
Directory /workspace/45.i2c_target_fifo_reset_tx/latest

Test location /workspace/coverage/default/45.i2c_target_fifo_watermarks_acq.3204118640
Short name T543
Test name
Test status
Simulation time 1834591891 ps
CPU time 2.78 seconds
Started Aug 12 04:46:22 PM PDT 24
Finished Aug 12 04:46:25 PM PDT 24
Peak memory 205348 kb
Host smart-ab916aa8-2db8-4127-8430-4221c2ba9e89
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3204118640 -assert nopostproc +UVM_TESTNAME=i2c_bas
e_test +UVM_TEST_SEQ=i2c_target_fifo_watermarks_acq_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm
_log /dev/null -cm_name 45.i2c_target_fifo_watermarks_acq.3204118640
Directory /workspace/45.i2c_target_fifo_watermarks_acq/latest

Test location /workspace/coverage/default/45.i2c_target_fifo_watermarks_tx.1339815287
Short name T754
Test name
Test status
Simulation time 144387328 ps
CPU time 1.46 seconds
Started Aug 12 04:46:23 PM PDT 24
Finished Aug 12 04:46:24 PM PDT 24
Peak memory 205376 kb
Host smart-81aa0abd-c782-4e61-a5d5-2c51fb6901d0
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1339815287 -assert nopostproc +UVM_TESTNAME=i2c_bas
e_test +UVM_TEST_SEQ=i2c_target_fifo_watermarks_tx_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_
log /dev/null -cm_name 45.i2c_target_fifo_watermarks_tx.1339815287
Directory /workspace/45.i2c_target_fifo_watermarks_tx/latest

Test location /workspace/coverage/default/45.i2c_target_intr_smoke.2453805656
Short name T318
Test name
Test status
Simulation time 685678514 ps
CPU time 4.98 seconds
Started Aug 12 04:46:14 PM PDT 24
Finished Aug 12 04:46:19 PM PDT 24
Peak memory 217244 kb
Host smart-1f631a0f-a286-486c-9604-d20bbf44c367
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=200_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VER
BOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2453805656 -assert nopostproc +UVM_TESTNAME=i2c_ba
se_test +UVM_TEST_SEQ=i2c_target_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/nul
l -cm_name 45.i2c_target_intr_smoke.2453805656
Directory /workspace/45.i2c_target_intr_smoke/latest

Test location /workspace/coverage/default/45.i2c_target_intr_stress_wr.907190019
Short name T1614
Test name
Test status
Simulation time 11506937989 ps
CPU time 10.76 seconds
Started Aug 12 04:46:17 PM PDT 24
Finished Aug 12 04:46:28 PM PDT 24
Peak memory 265408 kb
Host smart-36f150b0-f22c-4679-aafe-2b45897ae076
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=600_000_000 +use_intr_handler=1 +slow_acq=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNO
TES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=907190019 -assert nopostproc +UVM_TEST
NAME=i2c_base_test +UVM_TEST_SEQ=i2c_target_stress_wr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -
cm_log /dev/null -cm_name 45.i2c_target_intr_stress_wr.907190019
Directory /workspace/45.i2c_target_intr_stress_wr/latest

Test location /workspace/coverage/default/45.i2c_target_nack_acqfull.428311489
Short name T56
Test name
Test status
Simulation time 551564668 ps
CPU time 3.05 seconds
Started Aug 12 04:46:24 PM PDT 24
Finished Aug 12 04:46:27 PM PDT 24
Peak memory 213636 kb
Host smart-215fb855-fd4e-4b38-8d72-95933d69081c
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=428311489 -assert nopostproc +UVM_TESTNAME=i2c_base
_test +UVM_TEST_SEQ=i2c_target_nack_acqfull_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /de
v/null -cm_name 45.i2c_target_nack_acqfull.428311489
Directory /workspace/45.i2c_target_nack_acqfull/latest

Test location /workspace/coverage/default/45.i2c_target_nack_acqfull_addr.1829916906
Short name T1324
Test name
Test status
Simulation time 1134029853 ps
CPU time 2.87 seconds
Started Aug 12 04:46:24 PM PDT 24
Finished Aug 12 04:46:27 PM PDT 24
Peak memory 205492 kb
Host smart-88192c47-ecc2-413a-b264-937e09dfeac3
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1829916906 -assert nopostproc +UVM_TESTNAME=i2c_bas
e_test +UVM_TEST_SEQ=i2c_target_nack_acqfull_addr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_l
og /dev/null -cm_name 45.i2c_target_nack_acqfull_addr.1829916906
Directory /workspace/45.i2c_target_nack_acqfull_addr/latest

Test location /workspace/coverage/default/45.i2c_target_perf.1035151736
Short name T1242
Test name
Test status
Simulation time 1129318651 ps
CPU time 8.04 seconds
Started Aug 12 04:46:25 PM PDT 24
Finished Aug 12 04:46:33 PM PDT 24
Peak memory 230684 kb
Host smart-b06df47e-b573-4ea5-be01-500d16b7ab12
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1035151736 -assert nopostproc +UVM_TESTNAME=i2c_bas
e_test +UVM_TEST_SEQ=i2c_target_perf_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null
-cm_name 45.i2c_target_perf.1035151736
Directory /workspace/45.i2c_target_perf/latest

Test location /workspace/coverage/default/45.i2c_target_smbus_maxlen.2023420815
Short name T1608
Test name
Test status
Simulation time 1140401618 ps
CPU time 2.3 seconds
Started Aug 12 04:46:26 PM PDT 24
Finished Aug 12 04:46:28 PM PDT 24
Peak memory 205240 kb
Host smart-98b6c4fa-2c35-4c6a-99f6-3645a6cbbc04
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2023420815 -assert nopostproc +UVM_TESTNAME=i2c_bas
e_test +UVM_TEST_SEQ=i2c_target_smbus_maxlen_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /d
ev/null -cm_name 45.i2c_target_smbus_maxlen.2023420815
Directory /workspace/45.i2c_target_smbus_maxlen/latest

Test location /workspace/coverage/default/45.i2c_target_smoke.179964658
Short name T859
Test name
Test status
Simulation time 4270822980 ps
CPU time 12.91 seconds
Started Aug 12 04:46:14 PM PDT 24
Finished Aug 12 04:46:28 PM PDT 24
Peak memory 213728 kb
Host smart-8932c4ff-192a-4be5-824b-2b66dcbe9644
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=100_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licq
ueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=179964658 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ
=i2c_target_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.i2c_tar
get_smoke.179964658
Directory /workspace/45.i2c_target_smoke/latest

Test location /workspace/coverage/default/45.i2c_target_stress_all.55230452
Short name T795
Test name
Test status
Simulation time 61496123847 ps
CPU time 3112.6 seconds
Started Aug 12 04:46:23 PM PDT 24
Finished Aug 12 05:38:16 PM PDT 24
Peak memory 11476648 kb
Host smart-37dc656a-e268-4422-b864-dc4b6c03ad66
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=300_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VER
BOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=55230452 -assert nopostproc +UVM_TESTNAME=i2c_base
_test +UVM_TEST_SEQ=i2c_target_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/
null -cm_name 45.i2c_target_stress_all.55230452
Directory /workspace/45.i2c_target_stress_all/latest

Test location /workspace/coverage/default/45.i2c_target_stress_rd.381977146
Short name T1585
Test name
Test status
Simulation time 2031483358 ps
CPU time 8.25 seconds
Started Aug 12 04:46:18 PM PDT 24
Finished Aug 12 04:46:26 PM PDT 24
Peak memory 213952 kb
Host smart-efb25303-ced5-44af-92ae-573ea8d2ff3b
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=100_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licq
ueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=381977146 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ
=i2c_target_stress_rd_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.i2c
_target_stress_rd.381977146
Directory /workspace/45.i2c_target_stress_rd/latest

Test location /workspace/coverage/default/45.i2c_target_stress_wr.3401047369
Short name T1443
Test name
Test status
Simulation time 26541234712 ps
CPU time 48.5 seconds
Started Aug 12 04:46:17 PM PDT 24
Finished Aug 12 04:47:06 PM PDT 24
Peak memory 844856 kb
Host smart-58bea0db-80df-457c-aff4-fbfd06dcf64c
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=600_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licq
ueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3401047369 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SE
Q=i2c_target_stress_wr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.i2
c_target_stress_wr.3401047369
Directory /workspace/45.i2c_target_stress_wr/latest

Test location /workspace/coverage/default/45.i2c_target_timeout.3885794001
Short name T725
Test name
Test status
Simulation time 2980808149 ps
CPU time 7.23 seconds
Started Aug 12 04:46:17 PM PDT 24
Finished Aug 12 04:46:24 PM PDT 24
Peak memory 219528 kb
Host smart-fcae12ef-48b4-43b5-9fab-8ccf508a747b
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=50_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3885794001 -assert nopostproc +UVM_TESTNAME=i2c_bas
e_test +UVM_TEST_SEQ=i2c_target_timeout_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/nu
ll -cm_name 45.i2c_target_timeout.3885794001
Directory /workspace/45.i2c_target_timeout/latest

Test location /workspace/coverage/default/45.i2c_target_tx_stretch_ctrl.3040441665
Short name T459
Test name
Test status
Simulation time 106669919 ps
CPU time 2.33 seconds
Started Aug 12 04:46:26 PM PDT 24
Finished Aug 12 04:46:28 PM PDT 24
Peak memory 205468 kb
Host smart-9edea807-2c84-4234-9aaf-9011b012d47d
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3040441665 -assert nopostproc +UVM_TESTNAME=i2c_bas
e_test +UVM_TEST_SEQ=i2c_target_tx_stretch_ctrl_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log
/dev/null -cm_name 45.i2c_target_tx_stretch_ctrl.3040441665
Directory /workspace/45.i2c_target_tx_stretch_ctrl/latest

Test location /workspace/coverage/default/46.i2c_alert_test.71188555
Short name T1113
Test name
Test status
Simulation time 43835308 ps
CPU time 0.65 seconds
Started Aug 12 04:46:31 PM PDT 24
Finished Aug 12 04:46:32 PM PDT 24
Peak memory 204452 kb
Host smart-e5531cae-b184-4ed7-bfbf-f0b8c3985bec
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=71188555 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_common_vseq +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.i2c_alert_test.71188555
Directory /workspace/46.i2c_alert_test/latest

Test location /workspace/coverage/default/46.i2c_host_error_intr.3376596810
Short name T1742
Test name
Test status
Simulation time 494407552 ps
CPU time 1.99 seconds
Started Aug 12 04:46:24 PM PDT 24
Finished Aug 12 04:46:26 PM PDT 24
Peak memory 213468 kb
Host smart-3243e2f5-9af8-4d80-a379-01fb3b6326e8
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3376596810 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_error_intr_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.i2c_host_error_intr.3376596810
Directory /workspace/46.i2c_host_error_intr/latest

Test location /workspace/coverage/default/46.i2c_host_fifo_fmt_empty.3271797902
Short name T854
Test name
Test status
Simulation time 166308173 ps
CPU time 8.1 seconds
Started Aug 12 04:46:25 PM PDT 24
Finished Aug 12 04:46:33 PM PDT 24
Peak memory 212596 kb
Host smart-0a40fdad-d4c3-4040-8949-a1d8c1b92704
User root
Command /workspace/default/simv +test_timeout_ns=10_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3271797902 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_fifo_fmt_em
pty_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.i2c_host_fifo_fmt_emp
ty.3271797902
Directory /workspace/46.i2c_host_fifo_fmt_empty/latest

Test location /workspace/coverage/default/46.i2c_host_fifo_full.4018065651
Short name T1381
Test name
Test status
Simulation time 2674503225 ps
CPU time 100.53 seconds
Started Aug 12 04:46:31 PM PDT 24
Finished Aug 12 04:48:12 PM PDT 24
Peak memory 704524 kb
Host smart-45c49f95-4906-4142-b4e6-d0a4f67802f4
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4018065651 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_fifo_full_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.i2c_host_fifo_full.4018065651
Directory /workspace/46.i2c_host_fifo_full/latest

Test location /workspace/coverage/default/46.i2c_host_fifo_overflow.3344237946
Short name T683
Test name
Test status
Simulation time 18397868444 ps
CPU time 75.43 seconds
Started Aug 12 04:46:23 PM PDT 24
Finished Aug 12 04:47:39 PM PDT 24
Peak memory 778844 kb
Host smart-837efde5-7db6-4124-871e-6c91b48cfc5b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3344237946 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_fifo_overflow_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.i2c_host_fifo_overflow.3344237946
Directory /workspace/46.i2c_host_fifo_overflow/latest

Test location /workspace/coverage/default/46.i2c_host_fifo_reset_fmt.3275185911
Short name T1351
Test name
Test status
Simulation time 240826970 ps
CPU time 1.37 seconds
Started Aug 12 04:46:27 PM PDT 24
Finished Aug 12 04:46:28 PM PDT 24
Peak memory 205188 kb
Host smart-53dbe19d-4bb9-4661-b52d-ef162fac1c7e
User root
Command /workspace/default/simv +test_timeout_ns=10_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3275185911 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_fifo_reset_
fmt_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.i2c_host_fifo_reset_f
mt.3275185911
Directory /workspace/46.i2c_host_fifo_reset_fmt/latest

Test location /workspace/coverage/default/46.i2c_host_fifo_reset_rx.571805425
Short name T685
Test name
Test status
Simulation time 1400284473 ps
CPU time 3.55 seconds
Started Aug 12 04:46:25 PM PDT 24
Finished Aug 12 04:46:28 PM PDT 24
Peak memory 205260 kb
Host smart-b9aadbe6-cdb3-4ac6-a3fe-2559eb2d2432
User root
Command /workspace/default/simv +test_timeout_ns=10_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=571805425 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_fifo_reset_r
x_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.i2c_host_fifo_reset_rx.
571805425
Directory /workspace/46.i2c_host_fifo_reset_rx/latest

Test location /workspace/coverage/default/46.i2c_host_fifo_watermark.1064978661
Short name T118
Test name
Test status
Simulation time 22433148458 ps
CPU time 78.3 seconds
Started Aug 12 04:46:31 PM PDT 24
Finished Aug 12 04:47:49 PM PDT 24
Peak memory 1046924 kb
Host smart-75018426-9531-4b62-a854-aa9a3ff12e78
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1064978661 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_fifo_watermark_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.i2c_host_fifo_watermark.1064978661
Directory /workspace/46.i2c_host_fifo_watermark/latest

Test location /workspace/coverage/default/46.i2c_host_may_nack.3300648029
Short name T1388
Test name
Test status
Simulation time 3176308918 ps
CPU time 8.95 seconds
Started Aug 12 04:46:34 PM PDT 24
Finished Aug 12 04:46:43 PM PDT 24
Peak memory 205240 kb
Host smart-2193ad33-2eac-4532-bbae-fecf571eb423
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3300648029 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_may_nack_vseq +en_cov=1 -cm line+cond+f
sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.i2c_host_may_nack.3300648029
Directory /workspace/46.i2c_host_may_nack/latest

Test location /workspace/coverage/default/46.i2c_host_override.373031847
Short name T82
Test name
Test status
Simulation time 22812358 ps
CPU time 0.7 seconds
Started Aug 12 04:46:27 PM PDT 24
Finished Aug 12 04:46:27 PM PDT 24
Peak memory 204908 kb
Host smart-30ce7539-1666-4276-b94a-921d38075ae4
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=373031847 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_override_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.i2c_host_override.373031847
Directory /workspace/46.i2c_host_override/latest

Test location /workspace/coverage/default/46.i2c_host_perf.3242012120
Short name T335
Test name
Test status
Simulation time 6888958553 ps
CPU time 88.35 seconds
Started Aug 12 04:46:23 PM PDT 24
Finished Aug 12 04:47:52 PM PDT 24
Peak memory 205340 kb
Host smart-0dbd96a9-58be-4b3e-8695-e4aae8c4ce88
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3242012120 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_perf_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.i2c_host_perf.3242012120
Directory /workspace/46.i2c_host_perf/latest

Test location /workspace/coverage/default/46.i2c_host_perf_precise.1836786402
Short name T1244
Test name
Test status
Simulation time 898915130 ps
CPU time 2.18 seconds
Started Aug 12 04:46:23 PM PDT 24
Finished Aug 12 04:46:26 PM PDT 24
Peak memory 205140 kb
Host smart-f6638d59-2fb6-49de-a84a-c7e3345e7074
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1836786402 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_perf_precise_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.i2c_host_perf_precise.1836786402
Directory /workspace/46.i2c_host_perf_precise/latest

Test location /workspace/coverage/default/46.i2c_host_smoke.1522522955
Short name T955
Test name
Test status
Simulation time 6702880415 ps
CPU time 27.75 seconds
Started Aug 12 04:46:24 PM PDT 24
Finished Aug 12 04:46:52 PM PDT 24
Peak memory 375000 kb
Host smart-7e349a9b-d6ab-40b5-956e-026806577bf1
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1522522955 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_smoke_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.i2c_host_smoke.1522522955
Directory /workspace/46.i2c_host_smoke/latest

Test location /workspace/coverage/default/46.i2c_host_stretch_timeout.923470351
Short name T661
Test name
Test status
Simulation time 7737994820 ps
CPU time 31.82 seconds
Started Aug 12 04:46:25 PM PDT 24
Finished Aug 12 04:46:58 PM PDT 24
Peak memory 213400 kb
Host smart-fa9899ae-e300-42bb-acc4-20366426ea9f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=923470351 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_stretch_timeout_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.i2c_host_stretch_timeout.923470351
Directory /workspace/46.i2c_host_stretch_timeout/latest

Test location /workspace/coverage/default/46.i2c_target_bad_addr.864784448
Short name T1104
Test name
Test status
Simulation time 2033062424 ps
CPU time 5.93 seconds
Started Aug 12 04:46:31 PM PDT 24
Finished Aug 12 04:46:37 PM PDT 24
Peak memory 221908 kb
Host smart-d944e3c8-13b8-4871-b9e5-f443227eab1a
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +i2c_bad_addr_pct=50 +cdc_instrumentation_enabled=1 +UVM_
NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=864784448 -assert nopostproc +
UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_target_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.v
db -cm_log /dev/null -cm_name 46.i2c_target_bad_addr.864784448
Directory /workspace/46.i2c_target_bad_addr/latest

Test location /workspace/coverage/default/46.i2c_target_fifo_reset_acq.3116703303
Short name T1108
Test name
Test status
Simulation time 212529965 ps
CPU time 1.36 seconds
Started Aug 12 04:46:31 PM PDT 24
Finished Aug 12 04:46:33 PM PDT 24
Peak memory 205520 kb
Host smart-c87c955f-2066-4894-b418-027581ea890c
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3116703303 -assert nopostproc +UVM_TESTNAME=i2c_bas
e_test +UVM_TEST_SEQ=i2c_target_fifo_reset_acq_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log
/dev/null -cm_name 46.i2c_target_fifo_reset_acq.3116703303
Directory /workspace/46.i2c_target_fifo_reset_acq/latest

Test location /workspace/coverage/default/46.i2c_target_fifo_reset_tx.617592610
Short name T1364
Test name
Test status
Simulation time 164452870 ps
CPU time 1.04 seconds
Started Aug 12 04:46:32 PM PDT 24
Finished Aug 12 04:46:33 PM PDT 24
Peak memory 205416 kb
Host smart-a5389bfd-8979-40f6-b503-5c4cd231b606
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=617592610 -assert nopostproc +UVM_TESTNAME=i2c_base
_test +UVM_TEST_SEQ=i2c_target_fifo_reset_tx_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /d
ev/null -cm_name 46.i2c_target_fifo_reset_tx.617592610
Directory /workspace/46.i2c_target_fifo_reset_tx/latest

Test location /workspace/coverage/default/46.i2c_target_fifo_watermarks_acq.4139849847
Short name T1162
Test name
Test status
Simulation time 467954037 ps
CPU time 2.79 seconds
Started Aug 12 04:46:33 PM PDT 24
Finished Aug 12 04:46:37 PM PDT 24
Peak memory 205500 kb
Host smart-dc00dab1-cd38-4645-968a-2396ab008a13
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4139849847 -assert nopostproc +UVM_TESTNAME=i2c_bas
e_test +UVM_TEST_SEQ=i2c_target_fifo_watermarks_acq_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm
_log /dev/null -cm_name 46.i2c_target_fifo_watermarks_acq.4139849847
Directory /workspace/46.i2c_target_fifo_watermarks_acq/latest

Test location /workspace/coverage/default/46.i2c_target_fifo_watermarks_tx.2490232716
Short name T826
Test name
Test status
Simulation time 304075248 ps
CPU time 1.5 seconds
Started Aug 12 04:46:33 PM PDT 24
Finished Aug 12 04:46:35 PM PDT 24
Peak memory 205344 kb
Host smart-63f27519-b1e5-4ca1-b225-3f1a1d91f334
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2490232716 -assert nopostproc +UVM_TESTNAME=i2c_bas
e_test +UVM_TEST_SEQ=i2c_target_fifo_watermarks_tx_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_
log /dev/null -cm_name 46.i2c_target_fifo_watermarks_tx.2490232716
Directory /workspace/46.i2c_target_fifo_watermarks_tx/latest

Test location /workspace/coverage/default/46.i2c_target_intr_smoke.1758232200
Short name T1430
Test name
Test status
Simulation time 658704469 ps
CPU time 4.08 seconds
Started Aug 12 04:46:25 PM PDT 24
Finished Aug 12 04:46:30 PM PDT 24
Peak memory 221876 kb
Host smart-1b1b3f36-6756-4ba9-b304-169c669061a9
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=200_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VER
BOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1758232200 -assert nopostproc +UVM_TESTNAME=i2c_ba
se_test +UVM_TEST_SEQ=i2c_target_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/nul
l -cm_name 46.i2c_target_intr_smoke.1758232200
Directory /workspace/46.i2c_target_intr_smoke/latest

Test location /workspace/coverage/default/46.i2c_target_intr_stress_wr.723920946
Short name T556
Test name
Test status
Simulation time 34761088617 ps
CPU time 32.11 seconds
Started Aug 12 04:46:25 PM PDT 24
Finished Aug 12 04:46:57 PM PDT 24
Peak memory 693092 kb
Host smart-912ef508-1818-426d-88fd-d98df8550a88
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=600_000_000 +use_intr_handler=1 +slow_acq=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNO
TES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=723920946 -assert nopostproc +UVM_TEST
NAME=i2c_base_test +UVM_TEST_SEQ=i2c_target_stress_wr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -
cm_log /dev/null -cm_name 46.i2c_target_intr_stress_wr.723920946
Directory /workspace/46.i2c_target_intr_stress_wr/latest

Test location /workspace/coverage/default/46.i2c_target_nack_acqfull.1239012071
Short name T54
Test name
Test status
Simulation time 501540542 ps
CPU time 2.98 seconds
Started Aug 12 04:46:34 PM PDT 24
Finished Aug 12 04:46:37 PM PDT 24
Peak memory 213640 kb
Host smart-94253f94-f2c9-4323-ae1c-7015389969a1
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1239012071 -assert nopostproc +UVM_TESTNAME=i2c_bas
e_test +UVM_TEST_SEQ=i2c_target_nack_acqfull_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /d
ev/null -cm_name 46.i2c_target_nack_acqfull.1239012071
Directory /workspace/46.i2c_target_nack_acqfull/latest

Test location /workspace/coverage/default/46.i2c_target_nack_acqfull_addr.1086718171
Short name T1199
Test name
Test status
Simulation time 10107412487 ps
CPU time 2.65 seconds
Started Aug 12 04:46:33 PM PDT 24
Finished Aug 12 04:46:36 PM PDT 24
Peak memory 205500 kb
Host smart-bbd2410c-e86f-446b-8885-80b1bc3da58a
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1086718171 -assert nopostproc +UVM_TESTNAME=i2c_bas
e_test +UVM_TEST_SEQ=i2c_target_nack_acqfull_addr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_l
og /dev/null -cm_name 46.i2c_target_nack_acqfull_addr.1086718171
Directory /workspace/46.i2c_target_nack_acqfull_addr/latest

Test location /workspace/coverage/default/46.i2c_target_nack_txstretch.3686741331
Short name T1024
Test name
Test status
Simulation time 521793811 ps
CPU time 1.53 seconds
Started Aug 12 04:46:33 PM PDT 24
Finished Aug 12 04:46:34 PM PDT 24
Peak memory 222288 kb
Host smart-dcd16a78-8cbe-4597-a568-7be4e8e3425a
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3686741331 -assert nopostproc +UVM_TESTNAME=i2c_bas
e_test +UVM_TEST_SEQ=i2c_target_nack_txstretch_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log
/dev/null -cm_name 46.i2c_target_nack_txstretch.3686741331
Directory /workspace/46.i2c_target_nack_txstretch/latest

Test location /workspace/coverage/default/46.i2c_target_perf.46195143
Short name T814
Test name
Test status
Simulation time 1193224603 ps
CPU time 4.57 seconds
Started Aug 12 04:46:31 PM PDT 24
Finished Aug 12 04:46:35 PM PDT 24
Peak memory 213736 kb
Host smart-7a78ea11-cbe6-4bbc-aa17-42fb9f30733a
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=46195143 -assert nopostproc +UVM_TESTNAME=i2c_base_
test +UVM_TEST_SEQ=i2c_target_perf_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -c
m_name 46.i2c_target_perf.46195143
Directory /workspace/46.i2c_target_perf/latest

Test location /workspace/coverage/default/46.i2c_target_smbus_maxlen.3215132269
Short name T1142
Test name
Test status
Simulation time 624890372 ps
CPU time 2.31 seconds
Started Aug 12 04:46:34 PM PDT 24
Finished Aug 12 04:46:37 PM PDT 24
Peak memory 205244 kb
Host smart-875e649a-ad7f-4790-86eb-9e9bf98eddbe
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3215132269 -assert nopostproc +UVM_TESTNAME=i2c_bas
e_test +UVM_TEST_SEQ=i2c_target_smbus_maxlen_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /d
ev/null -cm_name 46.i2c_target_smbus_maxlen.3215132269
Directory /workspace/46.i2c_target_smbus_maxlen/latest

Test location /workspace/coverage/default/46.i2c_target_smoke.4283241677
Short name T410
Test name
Test status
Simulation time 1163553770 ps
CPU time 17.69 seconds
Started Aug 12 04:46:25 PM PDT 24
Finished Aug 12 04:46:43 PM PDT 24
Peak memory 213608 kb
Host smart-a9e54bf8-8112-4f55-9d12-d71c6b3db4b8
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=100_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licq
ueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4283241677 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SE
Q=i2c_target_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.i2c_ta
rget_smoke.4283241677
Directory /workspace/46.i2c_target_smoke/latest

Test location /workspace/coverage/default/46.i2c_target_stress_all.463752753
Short name T1029
Test name
Test status
Simulation time 32511360386 ps
CPU time 234.78 seconds
Started Aug 12 04:46:32 PM PDT 24
Finished Aug 12 04:50:27 PM PDT 24
Peak memory 2326900 kb
Host smart-ff4a815b-9afa-4ea1-a31f-5891b99cd319
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=300_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VER
BOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=463752753 -assert nopostproc +UVM_TESTNAME=i2c_bas
e_test +UVM_TEST_SEQ=i2c_target_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev
/null -cm_name 46.i2c_target_stress_all.463752753
Directory /workspace/46.i2c_target_stress_all/latest

Test location /workspace/coverage/default/46.i2c_target_stress_rd.2484086179
Short name T1136
Test name
Test status
Simulation time 3121031432 ps
CPU time 15.3 seconds
Started Aug 12 04:46:26 PM PDT 24
Finished Aug 12 04:46:41 PM PDT 24
Peak memory 221796 kb
Host smart-632cacdf-a494-4a66-866b-90f61c71b886
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=100_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licq
ueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2484086179 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SE
Q=i2c_target_stress_rd_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.i2
c_target_stress_rd.2484086179
Directory /workspace/46.i2c_target_stress_rd/latest

Test location /workspace/coverage/default/46.i2c_target_stress_wr.3874222507
Short name T857
Test name
Test status
Simulation time 13436566069 ps
CPU time 23.12 seconds
Started Aug 12 04:46:23 PM PDT 24
Finished Aug 12 04:46:46 PM PDT 24
Peak memory 205640 kb
Host smart-bc06ddfb-efaa-47a2-97c3-e6654279e641
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=600_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licq
ueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3874222507 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SE
Q=i2c_target_stress_wr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.i2
c_target_stress_wr.3874222507
Directory /workspace/46.i2c_target_stress_wr/latest

Test location /workspace/coverage/default/46.i2c_target_stretch.3600295526
Short name T517
Test name
Test status
Simulation time 1710935463 ps
CPU time 32.25 seconds
Started Aug 12 04:46:24 PM PDT 24
Finished Aug 12 04:46:56 PM PDT 24
Peak memory 366524 kb
Host smart-af23ad54-d24c-498f-8383-33d1bf7b44cd
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=400_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licq
ueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3600295526 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SE
Q=i2c_target_stretch_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.i2c_
target_stretch.3600295526
Directory /workspace/46.i2c_target_stretch/latest

Test location /workspace/coverage/default/46.i2c_target_timeout.1655708615
Short name T483
Test name
Test status
Simulation time 1310332949 ps
CPU time 7.74 seconds
Started Aug 12 04:46:26 PM PDT 24
Finished Aug 12 04:46:34 PM PDT 24
Peak memory 221944 kb
Host smart-8ce04052-d88b-46a8-a28b-6942a0ba8c87
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=50_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1655708615 -assert nopostproc +UVM_TESTNAME=i2c_bas
e_test +UVM_TEST_SEQ=i2c_target_timeout_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/nu
ll -cm_name 46.i2c_target_timeout.1655708615
Directory /workspace/46.i2c_target_timeout/latest

Test location /workspace/coverage/default/46.i2c_target_tx_stretch_ctrl.247103583
Short name T1395
Test name
Test status
Simulation time 208202987 ps
CPU time 3.14 seconds
Started Aug 12 04:46:33 PM PDT 24
Finished Aug 12 04:46:36 PM PDT 24
Peak memory 214136 kb
Host smart-9d07a775-fbcd-4786-acc4-0f94927d8eae
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=247103583 -assert nopostproc +UVM_TESTNAME=i2c_base
_test +UVM_TEST_SEQ=i2c_target_tx_stretch_ctrl_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log
/dev/null -cm_name 46.i2c_target_tx_stretch_ctrl.247103583
Directory /workspace/46.i2c_target_tx_stretch_ctrl/latest

Test location /workspace/coverage/default/47.i2c_alert_test.75421459
Short name T979
Test name
Test status
Simulation time 97255037 ps
CPU time 0.64 seconds
Started Aug 12 04:46:43 PM PDT 24
Finished Aug 12 04:46:43 PM PDT 24
Peak memory 204448 kb
Host smart-1a5ab40c-6741-4a2d-be5d-c870799cfc36
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=75421459 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_common_vseq +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.i2c_alert_test.75421459
Directory /workspace/47.i2c_alert_test/latest

Test location /workspace/coverage/default/47.i2c_host_error_intr.982456527
Short name T535
Test name
Test status
Simulation time 302990188 ps
CPU time 3.12 seconds
Started Aug 12 04:46:33 PM PDT 24
Finished Aug 12 04:46:36 PM PDT 24
Peak memory 233000 kb
Host smart-26cdb55f-2458-482e-9d30-2f46bd870ca5
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=982456527 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_error_intr_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.i2c_host_error_intr.982456527
Directory /workspace/47.i2c_host_error_intr/latest

Test location /workspace/coverage/default/47.i2c_host_fifo_fmt_empty.4042533598
Short name T619
Test name
Test status
Simulation time 2439181144 ps
CPU time 11.65 seconds
Started Aug 12 04:46:33 PM PDT 24
Finished Aug 12 04:46:45 PM PDT 24
Peak memory 347012 kb
Host smart-ee355b26-08db-4793-9f7f-25cd702e66ae
User root
Command /workspace/default/simv +test_timeout_ns=10_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4042533598 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_fifo_fmt_em
pty_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.i2c_host_fifo_fmt_emp
ty.4042533598
Directory /workspace/47.i2c_host_fifo_fmt_empty/latest

Test location /workspace/coverage/default/47.i2c_host_fifo_full.2726651093
Short name T1333
Test name
Test status
Simulation time 8575058029 ps
CPU time 53.59 seconds
Started Aug 12 04:46:31 PM PDT 24
Finished Aug 12 04:47:25 PM PDT 24
Peak memory 346148 kb
Host smart-9ffd26b3-9a4c-429e-8efe-3fcbb6468fa6
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2726651093 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_fifo_full_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.i2c_host_fifo_full.2726651093
Directory /workspace/47.i2c_host_fifo_full/latest

Test location /workspace/coverage/default/47.i2c_host_fifo_overflow.1411957930
Short name T415
Test name
Test status
Simulation time 23777760304 ps
CPU time 97.23 seconds
Started Aug 12 04:46:34 PM PDT 24
Finished Aug 12 04:48:12 PM PDT 24
Peak memory 562204 kb
Host smart-0ae88f89-ad74-4b19-8105-313e43b8a504
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1411957930 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_fifo_overflow_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.i2c_host_fifo_overflow.1411957930
Directory /workspace/47.i2c_host_fifo_overflow/latest

Test location /workspace/coverage/default/47.i2c_host_fifo_reset_fmt.1995290718
Short name T538
Test name
Test status
Simulation time 119080255 ps
CPU time 1.09 seconds
Started Aug 12 04:46:34 PM PDT 24
Finished Aug 12 04:46:36 PM PDT 24
Peak memory 204940 kb
Host smart-d736cacf-820b-4c68-936a-ad718b687de4
User root
Command /workspace/default/simv +test_timeout_ns=10_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1995290718 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_fifo_reset_
fmt_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.i2c_host_fifo_reset_f
mt.1995290718
Directory /workspace/47.i2c_host_fifo_reset_fmt/latest

Test location /workspace/coverage/default/47.i2c_host_fifo_reset_rx.4156182536
Short name T865
Test name
Test status
Simulation time 200892384 ps
CPU time 5.75 seconds
Started Aug 12 04:46:33 PM PDT 24
Finished Aug 12 04:46:39 PM PDT 24
Peak memory 242328 kb
Host smart-d20b4c7b-94b8-48ca-b2f6-d0ab115dd8ae
User root
Command /workspace/default/simv +test_timeout_ns=10_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4156182536 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_fifo_reset_
rx_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.i2c_host_fifo_reset_rx
.4156182536
Directory /workspace/47.i2c_host_fifo_reset_rx/latest

Test location /workspace/coverage/default/47.i2c_host_fifo_watermark.1214639993
Short name T1414
Test name
Test status
Simulation time 24024091169 ps
CPU time 392.35 seconds
Started Aug 12 04:46:32 PM PDT 24
Finished Aug 12 04:53:04 PM PDT 24
Peak memory 1492596 kb
Host smart-0855529f-ac9d-4a52-9a69-440633a4e561
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1214639993 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_fifo_watermark_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.i2c_host_fifo_watermark.1214639993
Directory /workspace/47.i2c_host_fifo_watermark/latest

Test location /workspace/coverage/default/47.i2c_host_may_nack.31696773
Short name T270
Test name
Test status
Simulation time 412858633 ps
CPU time 6.36 seconds
Started Aug 12 04:46:40 PM PDT 24
Finished Aug 12 04:46:47 PM PDT 24
Peak memory 205168 kb
Host smart-faf6bf75-9b60-4f1e-a656-f49d2cd8e999
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=31696773 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_may_nack_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.i2c_host_may_nack.31696773
Directory /workspace/47.i2c_host_may_nack/latest

Test location /workspace/coverage/default/47.i2c_host_override.502070005
Short name T455
Test name
Test status
Simulation time 99479423 ps
CPU time 0.68 seconds
Started Aug 12 04:46:33 PM PDT 24
Finished Aug 12 04:46:33 PM PDT 24
Peak memory 204852 kb
Host smart-d538df95-522e-43bb-a7e7-6704ec4892e8
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=502070005 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_override_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.i2c_host_override.502070005
Directory /workspace/47.i2c_host_override/latest

Test location /workspace/coverage/default/47.i2c_host_perf.3022039701
Short name T1427
Test name
Test status
Simulation time 30129701167 ps
CPU time 1343.66 seconds
Started Aug 12 04:46:33 PM PDT 24
Finished Aug 12 05:08:57 PM PDT 24
Peak memory 2246376 kb
Host smart-d8176042-997f-42ca-9ae4-a810cc69adb1
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3022039701 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_perf_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.i2c_host_perf.3022039701
Directory /workspace/47.i2c_host_perf/latest

Test location /workspace/coverage/default/47.i2c_host_perf_precise.65946675
Short name T1014
Test name
Test status
Simulation time 156854942 ps
CPU time 1.59 seconds
Started Aug 12 04:46:33 PM PDT 24
Finished Aug 12 04:46:34 PM PDT 24
Peak memory 205184 kb
Host smart-9f3ba25c-ba91-4d0f-a409-3df161cf2d96
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=65946675 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_perf_precise_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.i2c_host_perf_precise.65946675
Directory /workspace/47.i2c_host_perf_precise/latest

Test location /workspace/coverage/default/47.i2c_host_smoke.1840927882
Short name T381
Test name
Test status
Simulation time 8241680701 ps
CPU time 32.77 seconds
Started Aug 12 04:46:33 PM PDT 24
Finished Aug 12 04:47:06 PM PDT 24
Peak memory 374840 kb
Host smart-20e34c6f-a66e-432d-af84-a2ad86cb6a6c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1840927882 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_smoke_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.i2c_host_smoke.1840927882
Directory /workspace/47.i2c_host_smoke/latest

Test location /workspace/coverage/default/47.i2c_host_stretch_timeout.683802348
Short name T273
Test name
Test status
Simulation time 514576598 ps
CPU time 7.42 seconds
Started Aug 12 04:46:31 PM PDT 24
Finished Aug 12 04:46:38 PM PDT 24
Peak memory 213416 kb
Host smart-587cc3fe-ae1b-46a5-9c54-9d7886cf74c5
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=683802348 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_stretch_timeout_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.i2c_host_stretch_timeout.683802348
Directory /workspace/47.i2c_host_stretch_timeout/latest

Test location /workspace/coverage/default/47.i2c_target_bad_addr.2121275861
Short name T1701
Test name
Test status
Simulation time 876600935 ps
CPU time 4.97 seconds
Started Aug 12 04:46:35 PM PDT 24
Finished Aug 12 04:46:40 PM PDT 24
Peak memory 213652 kb
Host smart-62da2736-edbe-4d66-be32-a147db2f953a
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +i2c_bad_addr_pct=50 +cdc_instrumentation_enabled=1 +UVM_
NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2121275861 -assert nopostproc
+UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_target_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.
vdb -cm_log /dev/null -cm_name 47.i2c_target_bad_addr.2121275861
Directory /workspace/47.i2c_target_bad_addr/latest

Test location /workspace/coverage/default/47.i2c_target_fifo_reset_acq.1902305671
Short name T1479
Test name
Test status
Simulation time 140574388 ps
CPU time 0.99 seconds
Started Aug 12 04:46:32 PM PDT 24
Finished Aug 12 04:46:33 PM PDT 24
Peak memory 205252 kb
Host smart-a6d6da25-0c89-4580-8539-957e79eb6fdb
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1902305671 -assert nopostproc +UVM_TESTNAME=i2c_bas
e_test +UVM_TEST_SEQ=i2c_target_fifo_reset_acq_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log
/dev/null -cm_name 47.i2c_target_fifo_reset_acq.1902305671
Directory /workspace/47.i2c_target_fifo_reset_acq/latest

Test location /workspace/coverage/default/47.i2c_target_fifo_reset_tx.2552857760
Short name T1574
Test name
Test status
Simulation time 727873582 ps
CPU time 1.54 seconds
Started Aug 12 04:46:32 PM PDT 24
Finished Aug 12 04:46:34 PM PDT 24
Peak memory 205344 kb
Host smart-08be3be4-6b5a-464a-82bd-70c39173c41b
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2552857760 -assert nopostproc +UVM_TESTNAME=i2c_bas
e_test +UVM_TEST_SEQ=i2c_target_fifo_reset_tx_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /
dev/null -cm_name 47.i2c_target_fifo_reset_tx.2552857760
Directory /workspace/47.i2c_target_fifo_reset_tx/latest

Test location /workspace/coverage/default/47.i2c_target_fifo_watermarks_acq.1543620546
Short name T526
Test name
Test status
Simulation time 972519158 ps
CPU time 2.31 seconds
Started Aug 12 04:46:40 PM PDT 24
Finished Aug 12 04:46:43 PM PDT 24
Peak memory 205416 kb
Host smart-b0ca7e5a-5a73-46a6-b73a-2a7d7ab5c235
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1543620546 -assert nopostproc +UVM_TESTNAME=i2c_bas
e_test +UVM_TEST_SEQ=i2c_target_fifo_watermarks_acq_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm
_log /dev/null -cm_name 47.i2c_target_fifo_watermarks_acq.1543620546
Directory /workspace/47.i2c_target_fifo_watermarks_acq/latest

Test location /workspace/coverage/default/47.i2c_target_fifo_watermarks_tx.2256651393
Short name T1145
Test name
Test status
Simulation time 1285061320 ps
CPU time 1.26 seconds
Started Aug 12 04:46:39 PM PDT 24
Finished Aug 12 04:46:41 PM PDT 24
Peak memory 205236 kb
Host smart-45c64530-9239-4738-9771-9bbff4ce4d1c
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2256651393 -assert nopostproc +UVM_TESTNAME=i2c_bas
e_test +UVM_TEST_SEQ=i2c_target_fifo_watermarks_tx_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_
log /dev/null -cm_name 47.i2c_target_fifo_watermarks_tx.2256651393
Directory /workspace/47.i2c_target_fifo_watermarks_tx/latest

Test location /workspace/coverage/default/47.i2c_target_intr_smoke.3282262169
Short name T127
Test name
Test status
Simulation time 1162015658 ps
CPU time 6.76 seconds
Started Aug 12 04:46:32 PM PDT 24
Finished Aug 12 04:46:39 PM PDT 24
Peak memory 213748 kb
Host smart-07daf9ce-4309-42ba-bca3-9c6c199d03e4
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=200_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VER
BOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3282262169 -assert nopostproc +UVM_TESTNAME=i2c_ba
se_test +UVM_TEST_SEQ=i2c_target_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/nul
l -cm_name 47.i2c_target_intr_smoke.3282262169
Directory /workspace/47.i2c_target_intr_smoke/latest

Test location /workspace/coverage/default/47.i2c_target_intr_stress_wr.2382353294
Short name T941
Test name
Test status
Simulation time 16983620106 ps
CPU time 334.33 seconds
Started Aug 12 04:46:33 PM PDT 24
Finished Aug 12 04:52:08 PM PDT 24
Peak memory 3894692 kb
Host smart-86fb5b15-4f75-441f-a986-843f576255d8
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=600_000_000 +use_intr_handler=1 +slow_acq=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNO
TES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2382353294 -assert nopostproc +UVM_TES
TNAME=i2c_base_test +UVM_TEST_SEQ=i2c_target_stress_wr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb
-cm_log /dev/null -cm_name 47.i2c_target_intr_stress_wr.2382353294
Directory /workspace/47.i2c_target_intr_stress_wr/latest

Test location /workspace/coverage/default/47.i2c_target_nack_acqfull.362870255
Short name T599
Test name
Test status
Simulation time 497804245 ps
CPU time 2.95 seconds
Started Aug 12 04:46:39 PM PDT 24
Finished Aug 12 04:46:42 PM PDT 24
Peak memory 213756 kb
Host smart-db74382e-8dfb-4bc8-a0b8-e119613c5a20
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=362870255 -assert nopostproc +UVM_TESTNAME=i2c_base
_test +UVM_TEST_SEQ=i2c_target_nack_acqfull_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /de
v/null -cm_name 47.i2c_target_nack_acqfull.362870255
Directory /workspace/47.i2c_target_nack_acqfull/latest

Test location /workspace/coverage/default/47.i2c_target_nack_acqfull_addr.1223594553
Short name T1278
Test name
Test status
Simulation time 4383309627 ps
CPU time 2.85 seconds
Started Aug 12 04:46:46 PM PDT 24
Finished Aug 12 04:46:48 PM PDT 24
Peak memory 205504 kb
Host smart-ff06552f-7acd-40a1-9802-6627bd871367
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1223594553 -assert nopostproc +UVM_TESTNAME=i2c_bas
e_test +UVM_TEST_SEQ=i2c_target_nack_acqfull_addr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_l
og /dev/null -cm_name 47.i2c_target_nack_acqfull_addr.1223594553
Directory /workspace/47.i2c_target_nack_acqfull_addr/latest

Test location /workspace/coverage/default/47.i2c_target_nack_txstretch.3811643409
Short name T177
Test name
Test status
Simulation time 541445057 ps
CPU time 1.79 seconds
Started Aug 12 04:46:43 PM PDT 24
Finished Aug 12 04:46:45 PM PDT 24
Peak memory 222264 kb
Host smart-95fa4f11-d758-4531-8867-59b079920e32
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3811643409 -assert nopostproc +UVM_TESTNAME=i2c_bas
e_test +UVM_TEST_SEQ=i2c_target_nack_txstretch_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log
/dev/null -cm_name 47.i2c_target_nack_txstretch.3811643409
Directory /workspace/47.i2c_target_nack_txstretch/latest

Test location /workspace/coverage/default/47.i2c_target_perf.1689338465
Short name T1641
Test name
Test status
Simulation time 670818960 ps
CPU time 5.04 seconds
Started Aug 12 04:46:32 PM PDT 24
Finished Aug 12 04:46:37 PM PDT 24
Peak memory 218580 kb
Host smart-a28afa4c-d530-488c-8e9f-9633f60c04c6
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1689338465 -assert nopostproc +UVM_TESTNAME=i2c_bas
e_test +UVM_TEST_SEQ=i2c_target_perf_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null
-cm_name 47.i2c_target_perf.1689338465
Directory /workspace/47.i2c_target_perf/latest

Test location /workspace/coverage/default/47.i2c_target_smbus_maxlen.4247811335
Short name T569
Test name
Test status
Simulation time 1840267322 ps
CPU time 2.37 seconds
Started Aug 12 04:46:39 PM PDT 24
Finished Aug 12 04:46:42 PM PDT 24
Peak memory 205248 kb
Host smart-a825ae80-5054-4ecc-a360-951b4c8521ad
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4247811335 -assert nopostproc +UVM_TESTNAME=i2c_bas
e_test +UVM_TEST_SEQ=i2c_target_smbus_maxlen_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /d
ev/null -cm_name 47.i2c_target_smbus_maxlen.4247811335
Directory /workspace/47.i2c_target_smbus_maxlen/latest

Test location /workspace/coverage/default/47.i2c_target_smoke.4134807773
Short name T1571
Test name
Test status
Simulation time 724196539 ps
CPU time 12.21 seconds
Started Aug 12 04:46:34 PM PDT 24
Finished Aug 12 04:46:46 PM PDT 24
Peak memory 218544 kb
Host smart-d45ed122-fa72-48cd-8612-ca7610014e65
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=100_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licq
ueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4134807773 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SE
Q=i2c_target_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.i2c_ta
rget_smoke.4134807773
Directory /workspace/47.i2c_target_smoke/latest

Test location /workspace/coverage/default/47.i2c_target_stress_all.2264788015
Short name T611
Test name
Test status
Simulation time 20376116270 ps
CPU time 182.67 seconds
Started Aug 12 04:46:33 PM PDT 24
Finished Aug 12 04:49:36 PM PDT 24
Peak memory 1694200 kb
Host smart-db06edb7-611a-404e-95e7-f47f7eed687c
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=300_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VER
BOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2264788015 -assert nopostproc +UVM_TESTNAME=i2c_ba
se_test +UVM_TEST_SEQ=i2c_target_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /de
v/null -cm_name 47.i2c_target_stress_all.2264788015
Directory /workspace/47.i2c_target_stress_all/latest

Test location /workspace/coverage/default/47.i2c_target_stress_rd.1828259752
Short name T721
Test name
Test status
Simulation time 2095898765 ps
CPU time 24.46 seconds
Started Aug 12 04:46:40 PM PDT 24
Finished Aug 12 04:47:04 PM PDT 24
Peak memory 213684 kb
Host smart-662b7393-a72e-44fe-98fe-06b2dbd9b808
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=100_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licq
ueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1828259752 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SE
Q=i2c_target_stress_rd_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.i2
c_target_stress_rd.1828259752
Directory /workspace/47.i2c_target_stress_rd/latest

Test location /workspace/coverage/default/47.i2c_target_stress_wr.2372189753
Short name T1053
Test name
Test status
Simulation time 15147340103 ps
CPU time 8.26 seconds
Started Aug 12 04:46:32 PM PDT 24
Finished Aug 12 04:46:41 PM PDT 24
Peak memory 205580 kb
Host smart-a74dfc9b-f960-477f-a22a-db50d916d0e2
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=600_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licq
ueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2372189753 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SE
Q=i2c_target_stress_wr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.i2
c_target_stress_wr.2372189753
Directory /workspace/47.i2c_target_stress_wr/latest

Test location /workspace/coverage/default/47.i2c_target_stretch.963411122
Short name T835
Test name
Test status
Simulation time 3592301717 ps
CPU time 10.95 seconds
Started Aug 12 04:46:32 PM PDT 24
Finished Aug 12 04:46:43 PM PDT 24
Peak memory 242696 kb
Host smart-73bcaebe-3448-48e9-81eb-b2e3255f1323
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=400_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licq
ueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=963411122 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ
=i2c_target_stretch_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.i2c_t
arget_stretch.963411122
Directory /workspace/47.i2c_target_stretch/latest

Test location /workspace/coverage/default/47.i2c_target_timeout.3335102559
Short name T1019
Test name
Test status
Simulation time 7795755967 ps
CPU time 8.53 seconds
Started Aug 12 04:46:32 PM PDT 24
Finished Aug 12 04:46:41 PM PDT 24
Peak memory 221976 kb
Host smart-56d123e6-7d68-4524-adbc-29b849a26e97
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=50_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3335102559 -assert nopostproc +UVM_TESTNAME=i2c_bas
e_test +UVM_TEST_SEQ=i2c_target_timeout_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/nu
ll -cm_name 47.i2c_target_timeout.3335102559
Directory /workspace/47.i2c_target_timeout/latest

Test location /workspace/coverage/default/47.i2c_target_tx_stretch_ctrl.3272173862
Short name T949
Test name
Test status
Simulation time 222799572 ps
CPU time 3.92 seconds
Started Aug 12 04:46:40 PM PDT 24
Finished Aug 12 04:46:44 PM PDT 24
Peak memory 205512 kb
Host smart-98be54a1-5550-4a0b-b00e-86e033647e6c
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3272173862 -assert nopostproc +UVM_TESTNAME=i2c_bas
e_test +UVM_TEST_SEQ=i2c_target_tx_stretch_ctrl_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log
/dev/null -cm_name 47.i2c_target_tx_stretch_ctrl.3272173862
Directory /workspace/47.i2c_target_tx_stretch_ctrl/latest

Test location /workspace/coverage/default/48.i2c_alert_test.2504884050
Short name T1639
Test name
Test status
Simulation time 35520539 ps
CPU time 0.66 seconds
Started Aug 12 04:46:48 PM PDT 24
Finished Aug 12 04:46:49 PM PDT 24
Peak memory 204416 kb
Host smart-5cd9aacd-9d85-4dab-a750-cb5429b36c30
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2504884050 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_common_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.i2c_alert_test.2504884050
Directory /workspace/48.i2c_alert_test/latest

Test location /workspace/coverage/default/48.i2c_host_error_intr.2931088825
Short name T1623
Test name
Test status
Simulation time 472841419 ps
CPU time 1.73 seconds
Started Aug 12 04:46:43 PM PDT 24
Finished Aug 12 04:46:45 PM PDT 24
Peak memory 213520 kb
Host smart-62d5e608-5389-430a-8e24-a0581fa45403
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2931088825 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_error_intr_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.i2c_host_error_intr.2931088825
Directory /workspace/48.i2c_host_error_intr/latest

Test location /workspace/coverage/default/48.i2c_host_fifo_fmt_empty.3524343752
Short name T917
Test name
Test status
Simulation time 216807147 ps
CPU time 10.64 seconds
Started Aug 12 04:46:40 PM PDT 24
Finished Aug 12 04:46:51 PM PDT 24
Peak memory 246528 kb
Host smart-9e64ba77-2c08-4a6c-a6ff-29268033ec31
User root
Command /workspace/default/simv +test_timeout_ns=10_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3524343752 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_fifo_fmt_em
pty_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.i2c_host_fifo_fmt_emp
ty.3524343752
Directory /workspace/48.i2c_host_fifo_fmt_empty/latest

Test location /workspace/coverage/default/48.i2c_host_fifo_full.3359357017
Short name T1407
Test name
Test status
Simulation time 2607563396 ps
CPU time 58.06 seconds
Started Aug 12 04:46:40 PM PDT 24
Finished Aug 12 04:47:38 PM PDT 24
Peak memory 332948 kb
Host smart-e390aa6b-6dee-47ef-8b42-2df2abf8b891
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3359357017 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_fifo_full_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.i2c_host_fifo_full.3359357017
Directory /workspace/48.i2c_host_fifo_full/latest

Test location /workspace/coverage/default/48.i2c_host_fifo_overflow.3554784915
Short name T104
Test name
Test status
Simulation time 1308227064 ps
CPU time 86.04 seconds
Started Aug 12 04:46:42 PM PDT 24
Finished Aug 12 04:48:08 PM PDT 24
Peak memory 500396 kb
Host smart-1870688c-a97b-4e81-84a5-13b15fd9a27e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3554784915 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_fifo_overflow_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.i2c_host_fifo_overflow.3554784915
Directory /workspace/48.i2c_host_fifo_overflow/latest

Test location /workspace/coverage/default/48.i2c_host_fifo_reset_fmt.3390753306
Short name T1451
Test name
Test status
Simulation time 285135452 ps
CPU time 1.1 seconds
Started Aug 12 04:46:38 PM PDT 24
Finished Aug 12 04:46:39 PM PDT 24
Peak memory 204956 kb
Host smart-37bcb5d6-b8a9-4afd-832a-0216d9128199
User root
Command /workspace/default/simv +test_timeout_ns=10_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3390753306 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_fifo_reset_
fmt_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.i2c_host_fifo_reset_f
mt.3390753306
Directory /workspace/48.i2c_host_fifo_reset_fmt/latest

Test location /workspace/coverage/default/48.i2c_host_fifo_reset_rx.599534755
Short name T1279
Test name
Test status
Simulation time 772153972 ps
CPU time 10.89 seconds
Started Aug 12 04:46:42 PM PDT 24
Finished Aug 12 04:46:54 PM PDT 24
Peak memory 242428 kb
Host smart-71a283d9-f36c-4b6d-9692-3ce534c5a6be
User root
Command /workspace/default/simv +test_timeout_ns=10_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=599534755 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_fifo_reset_r
x_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.i2c_host_fifo_reset_rx.
599534755
Directory /workspace/48.i2c_host_fifo_reset_rx/latest

Test location /workspace/coverage/default/48.i2c_host_fifo_watermark.677978309
Short name T182
Test name
Test status
Simulation time 18244206416 ps
CPU time 320.17 seconds
Started Aug 12 04:46:39 PM PDT 24
Finished Aug 12 04:51:59 PM PDT 24
Peak memory 1257288 kb
Host smart-68460547-25b9-4854-8cf9-3788db5f33f0
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=677978309 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_fifo_watermark_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.i2c_host_fifo_watermark.677978309
Directory /workspace/48.i2c_host_fifo_watermark/latest

Test location /workspace/coverage/default/48.i2c_host_may_nack.2145006044
Short name T1231
Test name
Test status
Simulation time 279883603 ps
CPU time 12.04 seconds
Started Aug 12 04:46:47 PM PDT 24
Finished Aug 12 04:46:59 PM PDT 24
Peak memory 205260 kb
Host smart-586da0b7-800c-476c-9020-db87de5c22c3
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2145006044 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_may_nack_vseq +en_cov=1 -cm line+cond+f
sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.i2c_host_may_nack.2145006044
Directory /workspace/48.i2c_host_may_nack/latest

Test location /workspace/coverage/default/48.i2c_host_mode_toggle.4289570557
Short name T1245
Test name
Test status
Simulation time 161717918 ps
CPU time 2.22 seconds
Started Aug 12 04:46:48 PM PDT 24
Finished Aug 12 04:46:50 PM PDT 24
Peak memory 213388 kb
Host smart-db056d8c-fe6f-4f33-be6b-7d8d538bb067
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4289570557 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_mode_toggle_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.i2c_host_mode_toggle.4289570557
Directory /workspace/48.i2c_host_mode_toggle/latest

Test location /workspace/coverage/default/48.i2c_host_override.2258171747
Short name T1634
Test name
Test status
Simulation time 81473165 ps
CPU time 0.7 seconds
Started Aug 12 04:46:40 PM PDT 24
Finished Aug 12 04:46:41 PM PDT 24
Peak memory 204948 kb
Host smart-d2d8f4dc-ff44-4db7-bd24-abab15d4b496
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2258171747 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_override_vseq +en_cov=1 -cm line+cond+f
sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.i2c_host_override.2258171747
Directory /workspace/48.i2c_host_override/latest

Test location /workspace/coverage/default/48.i2c_host_perf.2939652543
Short name T244
Test name
Test status
Simulation time 48677986626 ps
CPU time 2344.11 seconds
Started Aug 12 04:46:38 PM PDT 24
Finished Aug 12 05:25:42 PM PDT 24
Peak memory 894896 kb
Host smart-1edff5fd-3bbe-4323-ad45-7b0ad09fdc5e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2939652543 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_perf_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.i2c_host_perf.2939652543
Directory /workspace/48.i2c_host_perf/latest

Test location /workspace/coverage/default/48.i2c_host_perf_precise.1338363199
Short name T245
Test name
Test status
Simulation time 224299455 ps
CPU time 9.2 seconds
Started Aug 12 04:46:40 PM PDT 24
Finished Aug 12 04:46:49 PM PDT 24
Peak memory 205148 kb
Host smart-a20d2c1e-428b-441e-98e5-6e9831e87be0
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1338363199 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_perf_precise_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.i2c_host_perf_precise.1338363199
Directory /workspace/48.i2c_host_perf_precise/latest

Test location /workspace/coverage/default/48.i2c_host_smoke.3215568462
Short name T1415
Test name
Test status
Simulation time 2129731399 ps
CPU time 97.98 seconds
Started Aug 12 04:46:37 PM PDT 24
Finished Aug 12 04:48:15 PM PDT 24
Peak memory 366028 kb
Host smart-7d6756ff-ae96-4d9f-8762-6b605e471f08
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3215568462 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_smoke_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.i2c_host_smoke.3215568462
Directory /workspace/48.i2c_host_smoke/latest

Test location /workspace/coverage/default/48.i2c_host_stress_all.3646332363
Short name T299
Test name
Test status
Simulation time 39592268975 ps
CPU time 135.16 seconds
Started Aug 12 04:46:40 PM PDT 24
Finished Aug 12 04:48:55 PM PDT 24
Peak memory 1224608 kb
Host smart-763ba162-ff15-4173-b348-1f519c30df5c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3646332363 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_stress_all_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.i2c_host_stress_all.3646332363
Directory /workspace/48.i2c_host_stress_all/latest

Test location /workspace/coverage/default/48.i2c_host_stretch_timeout.3146125337
Short name T630
Test name
Test status
Simulation time 615299845 ps
CPU time 29.07 seconds
Started Aug 12 04:46:40 PM PDT 24
Finished Aug 12 04:47:09 PM PDT 24
Peak memory 213480 kb
Host smart-ce797012-4c31-45d3-81d3-88be044b3e0a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3146125337 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_stretch_timeout_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.i2c_host_stretch_timeout.3146125337
Directory /workspace/48.i2c_host_stretch_timeout/latest

Test location /workspace/coverage/default/48.i2c_target_bad_addr.2867439211
Short name T386
Test name
Test status
Simulation time 2550750213 ps
CPU time 3.32 seconds
Started Aug 12 04:46:46 PM PDT 24
Finished Aug 12 04:46:50 PM PDT 24
Peak memory 216864 kb
Host smart-2b086c57-c788-4bec-919d-b23ede464522
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +i2c_bad_addr_pct=50 +cdc_instrumentation_enabled=1 +UVM_
NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2867439211 -assert nopostproc
+UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_target_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.
vdb -cm_log /dev/null -cm_name 48.i2c_target_bad_addr.2867439211
Directory /workspace/48.i2c_target_bad_addr/latest

Test location /workspace/coverage/default/48.i2c_target_fifo_reset_acq.2102891849
Short name T1425
Test name
Test status
Simulation time 445952383 ps
CPU time 1.1 seconds
Started Aug 12 04:46:48 PM PDT 24
Finished Aug 12 04:46:50 PM PDT 24
Peak memory 205340 kb
Host smart-a2f02ef0-8b51-4d18-9102-b4c847a1b03c
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2102891849 -assert nopostproc +UVM_TESTNAME=i2c_bas
e_test +UVM_TEST_SEQ=i2c_target_fifo_reset_acq_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log
/dev/null -cm_name 48.i2c_target_fifo_reset_acq.2102891849
Directory /workspace/48.i2c_target_fifo_reset_acq/latest

Test location /workspace/coverage/default/48.i2c_target_fifo_reset_tx.4271485991
Short name T1237
Test name
Test status
Simulation time 213993126 ps
CPU time 1.34 seconds
Started Aug 12 04:46:46 PM PDT 24
Finished Aug 12 04:46:47 PM PDT 24
Peak memory 213448 kb
Host smart-f4c6c912-9a99-4f08-b320-3e303f8cc212
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4271485991 -assert nopostproc +UVM_TESTNAME=i2c_bas
e_test +UVM_TEST_SEQ=i2c_target_fifo_reset_tx_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /
dev/null -cm_name 48.i2c_target_fifo_reset_tx.4271485991
Directory /workspace/48.i2c_target_fifo_reset_tx/latest

Test location /workspace/coverage/default/48.i2c_target_fifo_watermarks_acq.2406664012
Short name T1057
Test name
Test status
Simulation time 3233289645 ps
CPU time 1.98 seconds
Started Aug 12 04:46:54 PM PDT 24
Finished Aug 12 04:46:56 PM PDT 24
Peak memory 205480 kb
Host smart-1e69bc4c-ba4f-468e-ac1e-2d2ee4954910
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2406664012 -assert nopostproc +UVM_TESTNAME=i2c_bas
e_test +UVM_TEST_SEQ=i2c_target_fifo_watermarks_acq_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm
_log /dev/null -cm_name 48.i2c_target_fifo_watermarks_acq.2406664012
Directory /workspace/48.i2c_target_fifo_watermarks_acq/latest

Test location /workspace/coverage/default/48.i2c_target_fifo_watermarks_tx.1370647207
Short name T815
Test name
Test status
Simulation time 192273775 ps
CPU time 1.34 seconds
Started Aug 12 04:46:46 PM PDT 24
Finished Aug 12 04:46:48 PM PDT 24
Peak memory 205256 kb
Host smart-0fc665a6-7c4f-4978-805b-42b52c256893
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1370647207 -assert nopostproc +UVM_TESTNAME=i2c_bas
e_test +UVM_TEST_SEQ=i2c_target_fifo_watermarks_tx_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_
log /dev/null -cm_name 48.i2c_target_fifo_watermarks_tx.1370647207
Directory /workspace/48.i2c_target_fifo_watermarks_tx/latest

Test location /workspace/coverage/default/48.i2c_target_intr_smoke.1163699058
Short name T633
Test name
Test status
Simulation time 4377429902 ps
CPU time 5.91 seconds
Started Aug 12 04:46:38 PM PDT 24
Finished Aug 12 04:46:44 PM PDT 24
Peak memory 221104 kb
Host smart-533043db-1e91-458e-8bcf-16adcf96e658
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=200_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VER
BOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1163699058 -assert nopostproc +UVM_TESTNAME=i2c_ba
se_test +UVM_TEST_SEQ=i2c_target_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/nul
l -cm_name 48.i2c_target_intr_smoke.1163699058
Directory /workspace/48.i2c_target_intr_smoke/latest

Test location /workspace/coverage/default/48.i2c_target_intr_stress_wr.752371695
Short name T69
Test name
Test status
Simulation time 18803879369 ps
CPU time 43.94 seconds
Started Aug 12 04:46:39 PM PDT 24
Finished Aug 12 04:47:23 PM PDT 24
Peak memory 780116 kb
Host smart-1733d969-361b-40f2-9fb1-fd997be8d45f
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=600_000_000 +use_intr_handler=1 +slow_acq=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNO
TES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=752371695 -assert nopostproc +UVM_TEST
NAME=i2c_base_test +UVM_TEST_SEQ=i2c_target_stress_wr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -
cm_log /dev/null -cm_name 48.i2c_target_intr_stress_wr.752371695
Directory /workspace/48.i2c_target_intr_stress_wr/latest

Test location /workspace/coverage/default/48.i2c_target_nack_acqfull.3092267250
Short name T972
Test name
Test status
Simulation time 2229774158 ps
CPU time 2.67 seconds
Started Aug 12 04:46:48 PM PDT 24
Finished Aug 12 04:46:51 PM PDT 24
Peak memory 213864 kb
Host smart-b3e88389-3a6e-42eb-8cec-7ffbeb755b79
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3092267250 -assert nopostproc +UVM_TESTNAME=i2c_bas
e_test +UVM_TEST_SEQ=i2c_target_nack_acqfull_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /d
ev/null -cm_name 48.i2c_target_nack_acqfull.3092267250
Directory /workspace/48.i2c_target_nack_acqfull/latest

Test location /workspace/coverage/default/48.i2c_target_nack_acqfull_addr.690543711
Short name T1382
Test name
Test status
Simulation time 2061355380 ps
CPU time 2.71 seconds
Started Aug 12 04:46:47 PM PDT 24
Finished Aug 12 04:46:50 PM PDT 24
Peak memory 205444 kb
Host smart-0604b53a-7640-4c94-84d5-da8361e9dca8
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=690543711 -assert nopostproc +UVM_TESTNAME=i2c_base
_test +UVM_TEST_SEQ=i2c_target_nack_acqfull_addr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_lo
g /dev/null -cm_name 48.i2c_target_nack_acqfull_addr.690543711
Directory /workspace/48.i2c_target_nack_acqfull_addr/latest

Test location /workspace/coverage/default/48.i2c_target_perf.470829866
Short name T1695
Test name
Test status
Simulation time 657977658 ps
CPU time 4.27 seconds
Started Aug 12 04:46:52 PM PDT 24
Finished Aug 12 04:46:56 PM PDT 24
Peak memory 218116 kb
Host smart-eee76021-38a9-4d5c-968f-a85cd2ef484a
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=470829866 -assert nopostproc +UVM_TESTNAME=i2c_base
_test +UVM_TEST_SEQ=i2c_target_perf_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -
cm_name 48.i2c_target_perf.470829866
Directory /workspace/48.i2c_target_perf/latest

Test location /workspace/coverage/default/48.i2c_target_smbus_maxlen.1653531254
Short name T274
Test name
Test status
Simulation time 1054937618 ps
CPU time 2.44 seconds
Started Aug 12 04:46:46 PM PDT 24
Finished Aug 12 04:46:49 PM PDT 24
Peak memory 205200 kb
Host smart-e04208f3-504f-4aae-b0f5-1511c7be8340
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1653531254 -assert nopostproc +UVM_TESTNAME=i2c_bas
e_test +UVM_TEST_SEQ=i2c_target_smbus_maxlen_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /d
ev/null -cm_name 48.i2c_target_smbus_maxlen.1653531254
Directory /workspace/48.i2c_target_smbus_maxlen/latest

Test location /workspace/coverage/default/48.i2c_target_smoke.4254056742
Short name T368
Test name
Test status
Simulation time 855117245 ps
CPU time 12.87 seconds
Started Aug 12 04:46:39 PM PDT 24
Finished Aug 12 04:46:52 PM PDT 24
Peak memory 213720 kb
Host smart-d2404fc5-e207-424c-812c-1f719c69d083
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=100_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licq
ueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4254056742 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SE
Q=i2c_target_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.i2c_ta
rget_smoke.4254056742
Directory /workspace/48.i2c_target_smoke/latest

Test location /workspace/coverage/default/48.i2c_target_stress_all.2121921720
Short name T1080
Test name
Test status
Simulation time 91268124295 ps
CPU time 182.18 seconds
Started Aug 12 04:46:47 PM PDT 24
Finished Aug 12 04:49:49 PM PDT 24
Peak memory 1262792 kb
Host smart-66edb58b-f451-40ed-b5e4-0a57eb3aa0da
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=300_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VER
BOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2121921720 -assert nopostproc +UVM_TESTNAME=i2c_ba
se_test +UVM_TEST_SEQ=i2c_target_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /de
v/null -cm_name 48.i2c_target_stress_all.2121921720
Directory /workspace/48.i2c_target_stress_all/latest

Test location /workspace/coverage/default/48.i2c_target_stress_rd.1109442578
Short name T1315
Test name
Test status
Simulation time 2156863451 ps
CPU time 20.01 seconds
Started Aug 12 04:46:39 PM PDT 24
Finished Aug 12 04:46:59 PM PDT 24
Peak memory 221848 kb
Host smart-017b4b16-c8e4-486c-82b7-e421f02a4db0
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=100_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licq
ueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1109442578 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SE
Q=i2c_target_stress_rd_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.i2
c_target_stress_rd.1109442578
Directory /workspace/48.i2c_target_stress_rd/latest

Test location /workspace/coverage/default/48.i2c_target_stress_wr.3358759858
Short name T790
Test name
Test status
Simulation time 63367289774 ps
CPU time 658.65 seconds
Started Aug 12 04:46:38 PM PDT 24
Finished Aug 12 04:57:37 PM PDT 24
Peak memory 5073288 kb
Host smart-abdf9664-e053-4f08-8590-f338c0ef2207
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=600_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licq
ueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3358759858 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SE
Q=i2c_target_stress_wr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.i2
c_target_stress_wr.3358759858
Directory /workspace/48.i2c_target_stress_wr/latest

Test location /workspace/coverage/default/48.i2c_target_stretch.2457960719
Short name T728
Test name
Test status
Simulation time 3019728944 ps
CPU time 10.14 seconds
Started Aug 12 04:46:40 PM PDT 24
Finished Aug 12 04:46:51 PM PDT 24
Peak memory 232652 kb
Host smart-b4182606-dbb0-4818-b2bc-c12be3bd8492
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=400_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licq
ueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2457960719 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SE
Q=i2c_target_stretch_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.i2c_
target_stretch.2457960719
Directory /workspace/48.i2c_target_stretch/latest

Test location /workspace/coverage/default/48.i2c_target_timeout.2059902600
Short name T1287
Test name
Test status
Simulation time 1405981274 ps
CPU time 7.29 seconds
Started Aug 12 04:46:40 PM PDT 24
Finished Aug 12 04:46:48 PM PDT 24
Peak memory 221876 kb
Host smart-389a2844-1b4b-4cd7-86b4-69eeaaa5f3bb
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=50_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2059902600 -assert nopostproc +UVM_TESTNAME=i2c_bas
e_test +UVM_TEST_SEQ=i2c_target_timeout_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/nu
ll -cm_name 48.i2c_target_timeout.2059902600
Directory /workspace/48.i2c_target_timeout/latest

Test location /workspace/coverage/default/48.i2c_target_tx_stretch_ctrl.370115416
Short name T1599
Test name
Test status
Simulation time 143290240 ps
CPU time 3.22 seconds
Started Aug 12 04:46:47 PM PDT 24
Finished Aug 12 04:46:50 PM PDT 24
Peak memory 206144 kb
Host smart-c796df64-f576-4729-aeff-60076e6a2555
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=370115416 -assert nopostproc +UVM_TESTNAME=i2c_base
_test +UVM_TEST_SEQ=i2c_target_tx_stretch_ctrl_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log
/dev/null -cm_name 48.i2c_target_tx_stretch_ctrl.370115416
Directory /workspace/48.i2c_target_tx_stretch_ctrl/latest

Test location /workspace/coverage/default/49.i2c_alert_test.449604471
Short name T896
Test name
Test status
Simulation time 47560005 ps
CPU time 0.64 seconds
Started Aug 12 04:46:54 PM PDT 24
Finished Aug 12 04:46:54 PM PDT 24
Peak memory 204936 kb
Host smart-2191c019-a86e-481e-83d7-2eaf707d00bf
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=449604471 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_common_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.i2c_alert_test.449604471
Directory /workspace/49.i2c_alert_test/latest

Test location /workspace/coverage/default/49.i2c_host_error_intr.2796806274
Short name T756
Test name
Test status
Simulation time 117927024 ps
CPU time 3.8 seconds
Started Aug 12 04:46:54 PM PDT 24
Finished Aug 12 04:46:58 PM PDT 24
Peak memory 213528 kb
Host smart-ebab2c38-0541-45b1-8f40-69ea7fc1abe4
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2796806274 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_error_intr_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.i2c_host_error_intr.2796806274
Directory /workspace/49.i2c_host_error_intr/latest

Test location /workspace/coverage/default/49.i2c_host_fifo_fmt_empty.2563114188
Short name T346
Test name
Test status
Simulation time 3709403432 ps
CPU time 7.5 seconds
Started Aug 12 04:46:46 PM PDT 24
Finished Aug 12 04:46:53 PM PDT 24
Peak memory 278196 kb
Host smart-b929f4d2-e87d-42d2-8e56-ace08f24d148
User root
Command /workspace/default/simv +test_timeout_ns=10_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2563114188 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_fifo_fmt_em
pty_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.i2c_host_fifo_fmt_emp
ty.2563114188
Directory /workspace/49.i2c_host_fifo_fmt_empty/latest

Test location /workspace/coverage/default/49.i2c_host_fifo_full.1124573950
Short name T1552
Test name
Test status
Simulation time 5961162235 ps
CPU time 159.05 seconds
Started Aug 12 04:46:47 PM PDT 24
Finished Aug 12 04:49:26 PM PDT 24
Peak memory 365156 kb
Host smart-eb41fffc-dfd7-4d1b-b26c-177d04fa8430
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1124573950 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_fifo_full_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.i2c_host_fifo_full.1124573950
Directory /workspace/49.i2c_host_fifo_full/latest

Test location /workspace/coverage/default/49.i2c_host_fifo_overflow.1989987530
Short name T964
Test name
Test status
Simulation time 2681724676 ps
CPU time 91.96 seconds
Started Aug 12 04:46:45 PM PDT 24
Finished Aug 12 04:48:17 PM PDT 24
Peak memory 820256 kb
Host smart-0d81c485-55d0-422e-a7c5-371c886cab3d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1989987530 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_fifo_overflow_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.i2c_host_fifo_overflow.1989987530
Directory /workspace/49.i2c_host_fifo_overflow/latest

Test location /workspace/coverage/default/49.i2c_host_fifo_reset_fmt.631636564
Short name T577
Test name
Test status
Simulation time 140629458 ps
CPU time 1.18 seconds
Started Aug 12 04:46:45 PM PDT 24
Finished Aug 12 04:46:46 PM PDT 24
Peak memory 204928 kb
Host smart-9b019078-7bd3-4c27-b3cb-364e781e0b88
User root
Command /workspace/default/simv +test_timeout_ns=10_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=631636564 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_fifo_reset_f
mt_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.i2c_host_fifo_reset_fm
t.631636564
Directory /workspace/49.i2c_host_fifo_reset_fmt/latest

Test location /workspace/coverage/default/49.i2c_host_fifo_reset_rx.2385905998
Short name T594
Test name
Test status
Simulation time 152592715 ps
CPU time 7.57 seconds
Started Aug 12 04:46:47 PM PDT 24
Finished Aug 12 04:46:54 PM PDT 24
Peak memory 205288 kb
Host smart-502604ae-bab6-463f-8c6a-47f12d3ed3e2
User root
Command /workspace/default/simv +test_timeout_ns=10_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2385905998 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_fifo_reset_
rx_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.i2c_host_fifo_reset_rx
.2385905998
Directory /workspace/49.i2c_host_fifo_reset_rx/latest

Test location /workspace/coverage/default/49.i2c_host_fifo_watermark.1986441178
Short name T1736
Test name
Test status
Simulation time 2887496634 ps
CPU time 191.63 seconds
Started Aug 12 04:46:46 PM PDT 24
Finished Aug 12 04:49:58 PM PDT 24
Peak memory 918192 kb
Host smart-20b4dbf9-b278-45f3-93dc-39a3791abf18
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1986441178 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_fifo_watermark_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.i2c_host_fifo_watermark.1986441178
Directory /workspace/49.i2c_host_fifo_watermark/latest

Test location /workspace/coverage/default/49.i2c_host_may_nack.1529023968
Short name T812
Test name
Test status
Simulation time 386411362 ps
CPU time 5.17 seconds
Started Aug 12 04:46:54 PM PDT 24
Finished Aug 12 04:46:59 PM PDT 24
Peak memory 205204 kb
Host smart-a714c9d4-f698-4af5-bd21-f50f4c68d422
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1529023968 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_may_nack_vseq +en_cov=1 -cm line+cond+f
sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.i2c_host_may_nack.1529023968
Directory /workspace/49.i2c_host_may_nack/latest

Test location /workspace/coverage/default/49.i2c_host_override.3332892689
Short name T315
Test name
Test status
Simulation time 46542363 ps
CPU time 0.73 seconds
Started Aug 12 04:46:47 PM PDT 24
Finished Aug 12 04:46:48 PM PDT 24
Peak memory 204872 kb
Host smart-0ab269ac-ab50-4530-83aa-1ffde908cac2
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3332892689 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_override_vseq +en_cov=1 -cm line+cond+f
sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.i2c_host_override.3332892689
Directory /workspace/49.i2c_host_override/latest

Test location /workspace/coverage/default/49.i2c_host_perf.3754678368
Short name T1402
Test name
Test status
Simulation time 6137033165 ps
CPU time 86.84 seconds
Started Aug 12 04:46:51 PM PDT 24
Finished Aug 12 04:48:18 PM PDT 24
Peak memory 553960 kb
Host smart-c5d4bede-d905-4fd4-8410-e4a48bebd93c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3754678368 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_perf_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.i2c_host_perf.3754678368
Directory /workspace/49.i2c_host_perf/latest

Test location /workspace/coverage/default/49.i2c_host_perf_precise.416297141
Short name T1366
Test name
Test status
Simulation time 376783440 ps
CPU time 4.41 seconds
Started Aug 12 04:46:48 PM PDT 24
Finished Aug 12 04:46:52 PM PDT 24
Peak memory 221424 kb
Host smart-f758079a-02f7-4b3b-878f-79d5c8b81f37
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=416297141 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_perf_precise_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.i2c_host_perf_precise.416297141
Directory /workspace/49.i2c_host_perf_precise/latest

Test location /workspace/coverage/default/49.i2c_host_smoke.3243199045
Short name T808
Test name
Test status
Simulation time 1409932423 ps
CPU time 23.38 seconds
Started Aug 12 04:46:48 PM PDT 24
Finished Aug 12 04:47:12 PM PDT 24
Peak memory 334576 kb
Host smart-3d9750c7-ef41-4d67-bb6c-b8dc86dc5872
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3243199045 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_smoke_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.i2c_host_smoke.3243199045
Directory /workspace/49.i2c_host_smoke/latest

Test location /workspace/coverage/default/49.i2c_host_stress_all.434544734
Short name T1582
Test name
Test status
Simulation time 14334702593 ps
CPU time 798.76 seconds
Started Aug 12 04:46:51 PM PDT 24
Finished Aug 12 05:00:10 PM PDT 24
Peak memory 3329664 kb
Host smart-77f3823e-b4e4-4382-a05b-4c91eca3f761
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=434544734 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_stress_all_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.i2c_host_stress_all.434544734
Directory /workspace/49.i2c_host_stress_all/latest

Test location /workspace/coverage/default/49.i2c_host_stretch_timeout.2516647728
Short name T938
Test name
Test status
Simulation time 881877661 ps
CPU time 14.82 seconds
Started Aug 12 04:46:47 PM PDT 24
Finished Aug 12 04:47:02 PM PDT 24
Peak memory 221568 kb
Host smart-f29d5b39-c3f2-47d1-bbea-6864c4a771c3
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2516647728 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_stretch_timeout_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.i2c_host_stretch_timeout.2516647728
Directory /workspace/49.i2c_host_stretch_timeout/latest

Test location /workspace/coverage/default/49.i2c_target_fifo_reset_acq.1936861619
Short name T1661
Test name
Test status
Simulation time 193364770 ps
CPU time 1.15 seconds
Started Aug 12 04:46:51 PM PDT 24
Finished Aug 12 04:46:52 PM PDT 24
Peak memory 205260 kb
Host smart-9c1d8432-0141-4690-af66-65a42d06daae
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1936861619 -assert nopostproc +UVM_TESTNAME=i2c_bas
e_test +UVM_TEST_SEQ=i2c_target_fifo_reset_acq_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log
/dev/null -cm_name 49.i2c_target_fifo_reset_acq.1936861619
Directory /workspace/49.i2c_target_fifo_reset_acq/latest

Test location /workspace/coverage/default/49.i2c_target_fifo_reset_tx.749601410
Short name T991
Test name
Test status
Simulation time 360858856 ps
CPU time 1.27 seconds
Started Aug 12 04:46:48 PM PDT 24
Finished Aug 12 04:46:50 PM PDT 24
Peak memory 205244 kb
Host smart-070661b8-7f23-40ee-bbeb-f77b58271de0
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=749601410 -assert nopostproc +UVM_TESTNAME=i2c_base
_test +UVM_TEST_SEQ=i2c_target_fifo_reset_tx_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /d
ev/null -cm_name 49.i2c_target_fifo_reset_tx.749601410
Directory /workspace/49.i2c_target_fifo_reset_tx/latest

Test location /workspace/coverage/default/49.i2c_target_fifo_watermarks_acq.403040024
Short name T741
Test name
Test status
Simulation time 2536875836 ps
CPU time 3.31 seconds
Started Aug 12 04:46:54 PM PDT 24
Finished Aug 12 04:46:57 PM PDT 24
Peak memory 205496 kb
Host smart-9c4d4bd6-ebac-4f60-90ff-3870cafe1304
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=403040024 -assert nopostproc +UVM_TESTNAME=i2c_base
_test +UVM_TEST_SEQ=i2c_target_fifo_watermarks_acq_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_
log /dev/null -cm_name 49.i2c_target_fifo_watermarks_acq.403040024
Directory /workspace/49.i2c_target_fifo_watermarks_acq/latest

Test location /workspace/coverage/default/49.i2c_target_fifo_watermarks_tx.3798593842
Short name T1591
Test name
Test status
Simulation time 186184205 ps
CPU time 1.03 seconds
Started Aug 12 04:46:57 PM PDT 24
Finished Aug 12 04:46:58 PM PDT 24
Peak memory 205272 kb
Host smart-e43ed480-4975-475c-96a0-3f148ed03d9b
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3798593842 -assert nopostproc +UVM_TESTNAME=i2c_bas
e_test +UVM_TEST_SEQ=i2c_target_fifo_watermarks_tx_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_
log /dev/null -cm_name 49.i2c_target_fifo_watermarks_tx.3798593842
Directory /workspace/49.i2c_target_fifo_watermarks_tx/latest

Test location /workspace/coverage/default/49.i2c_target_hrst.3935425182
Short name T187
Test name
Test status
Simulation time 232268242 ps
CPU time 2.17 seconds
Started Aug 12 04:46:52 PM PDT 24
Finished Aug 12 04:46:54 PM PDT 24
Peak memory 221732 kb
Host smart-8025179f-6f7e-478d-9114-e02c3843a1ed
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3935425182 -assert nopostproc +UVM_TESTNAME=i2c_bas
e_test +UVM_TEST_SEQ=i2c_target_hrst_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null
-cm_name 49.i2c_target_hrst.3935425182
Directory /workspace/49.i2c_target_hrst/latest

Test location /workspace/coverage/default/49.i2c_target_intr_smoke.2038563821
Short name T717
Test name
Test status
Simulation time 12111450935 ps
CPU time 5.75 seconds
Started Aug 12 04:46:47 PM PDT 24
Finished Aug 12 04:46:53 PM PDT 24
Peak memory 221732 kb
Host smart-4d01df4b-6175-4e1b-aa27-7872595f5ef4
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=200_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VER
BOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2038563821 -assert nopostproc +UVM_TESTNAME=i2c_ba
se_test +UVM_TEST_SEQ=i2c_target_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/nul
l -cm_name 49.i2c_target_intr_smoke.2038563821
Directory /workspace/49.i2c_target_intr_smoke/latest

Test location /workspace/coverage/default/49.i2c_target_intr_stress_wr.2713942634
Short name T1559
Test name
Test status
Simulation time 3210087995 ps
CPU time 7.39 seconds
Started Aug 12 04:46:47 PM PDT 24
Finished Aug 12 04:46:55 PM PDT 24
Peak memory 205512 kb
Host smart-9a09ab8e-fd26-4f0c-ab60-0b55c2cc9719
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=600_000_000 +use_intr_handler=1 +slow_acq=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNO
TES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2713942634 -assert nopostproc +UVM_TES
TNAME=i2c_base_test +UVM_TEST_SEQ=i2c_target_stress_wr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb
-cm_log /dev/null -cm_name 49.i2c_target_intr_stress_wr.2713942634
Directory /workspace/49.i2c_target_intr_stress_wr/latest

Test location /workspace/coverage/default/49.i2c_target_nack_acqfull.837229768
Short name T551
Test name
Test status
Simulation time 2271520194 ps
CPU time 3.19 seconds
Started Aug 12 04:46:52 PM PDT 24
Finished Aug 12 04:46:55 PM PDT 24
Peak memory 213860 kb
Host smart-bfea7c7f-26eb-48d9-91e8-045ad3f909e7
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=837229768 -assert nopostproc +UVM_TESTNAME=i2c_base
_test +UVM_TEST_SEQ=i2c_target_nack_acqfull_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /de
v/null -cm_name 49.i2c_target_nack_acqfull.837229768
Directory /workspace/49.i2c_target_nack_acqfull/latest

Test location /workspace/coverage/default/49.i2c_target_nack_acqfull_addr.1583093902
Short name T1354
Test name
Test status
Simulation time 534110026 ps
CPU time 2.72 seconds
Started Aug 12 04:46:52 PM PDT 24
Finished Aug 12 04:46:55 PM PDT 24
Peak memory 205564 kb
Host smart-aa18ba91-64c8-44d8-9952-7d2c491c9ee0
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1583093902 -assert nopostproc +UVM_TESTNAME=i2c_bas
e_test +UVM_TEST_SEQ=i2c_target_nack_acqfull_addr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_l
og /dev/null -cm_name 49.i2c_target_nack_acqfull_addr.1583093902
Directory /workspace/49.i2c_target_nack_acqfull_addr/latest

Test location /workspace/coverage/default/49.i2c_target_perf.4218714431
Short name T309
Test name
Test status
Simulation time 1732122511 ps
CPU time 3.5 seconds
Started Aug 12 04:46:58 PM PDT 24
Finished Aug 12 04:47:01 PM PDT 24
Peak memory 213684 kb
Host smart-730cc543-7727-492a-9069-bdd0e579e1fb
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4218714431 -assert nopostproc +UVM_TESTNAME=i2c_bas
e_test +UVM_TEST_SEQ=i2c_target_perf_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null
-cm_name 49.i2c_target_perf.4218714431
Directory /workspace/49.i2c_target_perf/latest

Test location /workspace/coverage/default/49.i2c_target_smbus_maxlen.1019239940
Short name T421
Test name
Test status
Simulation time 480696558 ps
CPU time 2.38 seconds
Started Aug 12 04:46:53 PM PDT 24
Finished Aug 12 04:46:55 PM PDT 24
Peak memory 205296 kb
Host smart-be04070f-4dc9-4a96-9acd-e65d84ed1a3a
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1019239940 -assert nopostproc +UVM_TESTNAME=i2c_bas
e_test +UVM_TEST_SEQ=i2c_target_smbus_maxlen_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /d
ev/null -cm_name 49.i2c_target_smbus_maxlen.1019239940
Directory /workspace/49.i2c_target_smbus_maxlen/latest

Test location /workspace/coverage/default/49.i2c_target_smoke.414663565
Short name T506
Test name
Test status
Simulation time 1848233381 ps
CPU time 6.34 seconds
Started Aug 12 04:46:46 PM PDT 24
Finished Aug 12 04:46:52 PM PDT 24
Peak memory 213700 kb
Host smart-36fd704c-254e-4a8b-bbc0-b5e0bd46301d
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=100_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licq
ueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=414663565 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ
=i2c_target_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.i2c_tar
get_smoke.414663565
Directory /workspace/49.i2c_target_smoke/latest

Test location /workspace/coverage/default/49.i2c_target_stress_all.318956273
Short name T861
Test name
Test status
Simulation time 38343489037 ps
CPU time 110.05 seconds
Started Aug 12 04:46:55 PM PDT 24
Finished Aug 12 04:48:46 PM PDT 24
Peak memory 890044 kb
Host smart-b9ed77cc-019a-43c2-b763-0f7864698225
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=300_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VER
BOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=318956273 -assert nopostproc +UVM_TESTNAME=i2c_bas
e_test +UVM_TEST_SEQ=i2c_target_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev
/null -cm_name 49.i2c_target_stress_all.318956273
Directory /workspace/49.i2c_target_stress_all/latest

Test location /workspace/coverage/default/49.i2c_target_stress_rd.4006616386
Short name T436
Test name
Test status
Simulation time 2459109118 ps
CPU time 11.61 seconds
Started Aug 12 04:46:48 PM PDT 24
Finished Aug 12 04:47:00 PM PDT 24
Peak memory 214752 kb
Host smart-9ed01b80-ba0a-4c54-8fa5-b4868722f445
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=100_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licq
ueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4006616386 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SE
Q=i2c_target_stress_rd_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.i2
c_target_stress_rd.4006616386
Directory /workspace/49.i2c_target_stress_rd/latest

Test location /workspace/coverage/default/49.i2c_target_stress_wr.3423638046
Short name T1696
Test name
Test status
Simulation time 56951168458 ps
CPU time 2259.39 seconds
Started Aug 12 04:46:52 PM PDT 24
Finished Aug 12 05:24:32 PM PDT 24
Peak memory 9572296 kb
Host smart-3faf2fa0-ff1d-455c-97f4-e1ffea6a3a69
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=600_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licq
ueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3423638046 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SE
Q=i2c_target_stress_wr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.i2
c_target_stress_wr.3423638046
Directory /workspace/49.i2c_target_stress_wr/latest

Test location /workspace/coverage/default/49.i2c_target_stretch.2853663747
Short name T1077
Test name
Test status
Simulation time 1253785026 ps
CPU time 1.59 seconds
Started Aug 12 04:46:54 PM PDT 24
Finished Aug 12 04:46:55 PM PDT 24
Peak memory 213732 kb
Host smart-170a01ab-bce5-47aa-88cc-f82604f9726f
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=400_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licq
ueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2853663747 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SE
Q=i2c_target_stretch_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.i2c_
target_stretch.2853663747
Directory /workspace/49.i2c_target_stretch/latest

Test location /workspace/coverage/default/49.i2c_target_timeout.3914153481
Short name T990
Test name
Test status
Simulation time 1241884487 ps
CPU time 6.87 seconds
Started Aug 12 04:46:49 PM PDT 24
Finished Aug 12 04:46:56 PM PDT 24
Peak memory 221864 kb
Host smart-33b600c0-e1f7-480a-a59f-1e02901b909e
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=50_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3914153481 -assert nopostproc +UVM_TESTNAME=i2c_bas
e_test +UVM_TEST_SEQ=i2c_target_timeout_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/nu
ll -cm_name 49.i2c_target_timeout.3914153481
Directory /workspace/49.i2c_target_timeout/latest

Test location /workspace/coverage/default/5.i2c_alert_test.3054341522
Short name T1263
Test name
Test status
Simulation time 22149699 ps
CPU time 0.67 seconds
Started Aug 12 04:41:19 PM PDT 24
Finished Aug 12 04:41:20 PM PDT 24
Peak memory 204544 kb
Host smart-1d3904dc-ac37-4ff0-b0ea-4e18cf47e5d7
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3054341522 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_common_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.i2c_alert_test.3054341522
Directory /workspace/5.i2c_alert_test/latest

Test location /workspace/coverage/default/5.i2c_host_error_intr.1053676837
Short name T1292
Test name
Test status
Simulation time 464219154 ps
CPU time 4.3 seconds
Started Aug 12 04:41:11 PM PDT 24
Finished Aug 12 04:41:16 PM PDT 24
Peak memory 229708 kb
Host smart-d4639edf-71e6-4daa-b767-e33115d8999b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1053676837 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_error_intr_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.i2c_host_error_intr.1053676837
Directory /workspace/5.i2c_host_error_intr/latest

Test location /workspace/coverage/default/5.i2c_host_fifo_fmt_empty.1937960907
Short name T467
Test name
Test status
Simulation time 1251243416 ps
CPU time 15.04 seconds
Started Aug 12 04:41:18 PM PDT 24
Finished Aug 12 04:41:33 PM PDT 24
Peak memory 240908 kb
Host smart-26006b97-e872-460e-a10d-875328aa9b09
User root
Command /workspace/default/simv +test_timeout_ns=10_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1937960907 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_fifo_fmt_em
pty_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.i2c_host_fifo_fmt_empt
y.1937960907
Directory /workspace/5.i2c_host_fifo_fmt_empty/latest

Test location /workspace/coverage/default/5.i2c_host_fifo_full.422182403
Short name T640
Test name
Test status
Simulation time 14264383945 ps
CPU time 149.41 seconds
Started Aug 12 04:41:09 PM PDT 24
Finished Aug 12 04:43:39 PM PDT 24
Peak memory 232616 kb
Host smart-f85e5e5a-fc74-4326-ada8-8fb12d332854
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=422182403 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_fifo_full_vseq +en_cov=1 -cm line+cond+f
sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.i2c_host_fifo_full.422182403
Directory /workspace/5.i2c_host_fifo_full/latest

Test location /workspace/coverage/default/5.i2c_host_fifo_overflow.1558462990
Short name T1417
Test name
Test status
Simulation time 22377625785 ps
CPU time 83.28 seconds
Started Aug 12 04:41:11 PM PDT 24
Finished Aug 12 04:42:34 PM PDT 24
Peak memory 765644 kb
Host smart-63260fb7-3bf6-49df-bf70-7f23c0243548
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1558462990 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_fifo_overflow_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.i2c_host_fifo_overflow.1558462990
Directory /workspace/5.i2c_host_fifo_overflow/latest

Test location /workspace/coverage/default/5.i2c_host_fifo_reset_fmt.2817504424
Short name T1487
Test name
Test status
Simulation time 96378653 ps
CPU time 1.04 seconds
Started Aug 12 04:41:11 PM PDT 24
Finished Aug 12 04:41:12 PM PDT 24
Peak memory 205048 kb
Host smart-d7d321af-e855-447f-8369-05594dcc1ed9
User root
Command /workspace/default/simv +test_timeout_ns=10_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2817504424 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_fifo_reset_
fmt_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.i2c_host_fifo_reset_fm
t.2817504424
Directory /workspace/5.i2c_host_fifo_reset_fmt/latest

Test location /workspace/coverage/default/5.i2c_host_fifo_reset_rx.1972778051
Short name T1249
Test name
Test status
Simulation time 260195284 ps
CPU time 8.56 seconds
Started Aug 12 04:41:11 PM PDT 24
Finished Aug 12 04:41:19 PM PDT 24
Peak memory 205344 kb
Host smart-28e9681d-d5c7-4901-bc97-9246bebf7f0e
User root
Command /workspace/default/simv +test_timeout_ns=10_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1972778051 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_fifo_reset_
rx_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.i2c_host_fifo_reset_rx.
1972778051
Directory /workspace/5.i2c_host_fifo_reset_rx/latest

Test location /workspace/coverage/default/5.i2c_host_fifo_watermark.2959160207
Short name T1109
Test name
Test status
Simulation time 6665202631 ps
CPU time 71.72 seconds
Started Aug 12 04:41:12 PM PDT 24
Finished Aug 12 04:42:24 PM PDT 24
Peak memory 809968 kb
Host smart-5dda55b6-4bcf-43e5-b515-c21be9367685
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2959160207 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_fifo_watermark_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.i2c_host_fifo_watermark.2959160207
Directory /workspace/5.i2c_host_fifo_watermark/latest

Test location /workspace/coverage/default/5.i2c_host_may_nack.3790312439
Short name T262
Test name
Test status
Simulation time 2527911961 ps
CPU time 9.83 seconds
Started Aug 12 04:41:27 PM PDT 24
Finished Aug 12 04:41:37 PM PDT 24
Peak memory 205224 kb
Host smart-bf6c9954-7a85-4ca0-9e66-b321209e179a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3790312439 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_may_nack_vseq +en_cov=1 -cm line+cond+f
sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.i2c_host_may_nack.3790312439
Directory /workspace/5.i2c_host_may_nack/latest

Test location /workspace/coverage/default/5.i2c_host_override.3478772373
Short name T975
Test name
Test status
Simulation time 29231917 ps
CPU time 0.67 seconds
Started Aug 12 04:41:11 PM PDT 24
Finished Aug 12 04:41:11 PM PDT 24
Peak memory 204876 kb
Host smart-1df32b26-2aa5-4baa-8446-ffec287c5454
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3478772373 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_override_vseq +en_cov=1 -cm line+cond+f
sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.i2c_host_override.3478772373
Directory /workspace/5.i2c_host_override/latest

Test location /workspace/coverage/default/5.i2c_host_perf.3361802493
Short name T992
Test name
Test status
Simulation time 723173811 ps
CPU time 5.21 seconds
Started Aug 12 04:41:15 PM PDT 24
Finished Aug 12 04:41:20 PM PDT 24
Peak memory 229736 kb
Host smart-20df4979-1c70-4b06-b713-3336de0b2f10
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3361802493 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_perf_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.i2c_host_perf.3361802493
Directory /workspace/5.i2c_host_perf/latest

Test location /workspace/coverage/default/5.i2c_host_perf_precise.2695517700
Short name T1194
Test name
Test status
Simulation time 232636225 ps
CPU time 1.62 seconds
Started Aug 12 04:41:18 PM PDT 24
Finished Aug 12 04:41:20 PM PDT 24
Peak memory 218724 kb
Host smart-f7ab5574-e4d1-4f69-8512-8a426c58566b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2695517700 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_perf_precise_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.i2c_host_perf_precise.2695517700
Directory /workspace/5.i2c_host_perf_precise/latest

Test location /workspace/coverage/default/5.i2c_host_smoke.4255690401
Short name T1060
Test name
Test status
Simulation time 14059345540 ps
CPU time 19.41 seconds
Started Aug 12 04:41:13 PM PDT 24
Finished Aug 12 04:41:33 PM PDT 24
Peak memory 312516 kb
Host smart-3d63666a-a333-4754-806c-78aa5876cfa4
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4255690401 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_smoke_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.i2c_host_smoke.4255690401
Directory /workspace/5.i2c_host_smoke/latest

Test location /workspace/coverage/default/5.i2c_host_stretch_timeout.639734817
Short name T971
Test name
Test status
Simulation time 1337449972 ps
CPU time 12.38 seconds
Started Aug 12 04:41:12 PM PDT 24
Finished Aug 12 04:41:24 PM PDT 24
Peak memory 215588 kb
Host smart-30803616-3190-4819-b4af-b55613c0f5e6
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=639734817 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_stretch_timeout_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.i2c_host_stretch_timeout.639734817
Directory /workspace/5.i2c_host_stretch_timeout/latest

Test location /workspace/coverage/default/5.i2c_target_bad_addr.2068694167
Short name T1170
Test name
Test status
Simulation time 853157091 ps
CPU time 4.37 seconds
Started Aug 12 04:41:21 PM PDT 24
Finished Aug 12 04:41:26 PM PDT 24
Peak memory 213676 kb
Host smart-df682629-f69b-47e3-a36d-33e7928e97cf
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +i2c_bad_addr_pct=50 +cdc_instrumentation_enabled=1 +UVM_
NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2068694167 -assert nopostproc
+UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_target_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.
vdb -cm_log /dev/null -cm_name 5.i2c_target_bad_addr.2068694167
Directory /workspace/5.i2c_target_bad_addr/latest

Test location /workspace/coverage/default/5.i2c_target_fifo_reset_acq.745628615
Short name T1008
Test name
Test status
Simulation time 276044972 ps
CPU time 1.2 seconds
Started Aug 12 04:41:20 PM PDT 24
Finished Aug 12 04:41:22 PM PDT 24
Peak memory 213716 kb
Host smart-39010762-ebdd-42d7-8351-7b819d6f9926
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=745628615 -assert nopostproc +UVM_TESTNAME=i2c_base
_test +UVM_TEST_SEQ=i2c_target_fifo_reset_acq_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /
dev/null -cm_name 5.i2c_target_fifo_reset_acq.745628615
Directory /workspace/5.i2c_target_fifo_reset_acq/latest

Test location /workspace/coverage/default/5.i2c_target_fifo_reset_tx.1453040599
Short name T598
Test name
Test status
Simulation time 107904022 ps
CPU time 0.86 seconds
Started Aug 12 04:41:21 PM PDT 24
Finished Aug 12 04:41:22 PM PDT 24
Peak memory 205264 kb
Host smart-ac9052bb-8326-4a3a-bd76-1da8abdfafb1
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1453040599 -assert nopostproc +UVM_TESTNAME=i2c_bas
e_test +UVM_TEST_SEQ=i2c_target_fifo_reset_tx_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /
dev/null -cm_name 5.i2c_target_fifo_reset_tx.1453040599
Directory /workspace/5.i2c_target_fifo_reset_tx/latest

Test location /workspace/coverage/default/5.i2c_target_fifo_watermarks_acq.1850914322
Short name T1540
Test name
Test status
Simulation time 771572291 ps
CPU time 2.3 seconds
Started Aug 12 04:41:18 PM PDT 24
Finished Aug 12 04:41:20 PM PDT 24
Peak memory 205196 kb
Host smart-52882902-fa76-45e7-abc7-6a6a7bee696d
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1850914322 -assert nopostproc +UVM_TESTNAME=i2c_bas
e_test +UVM_TEST_SEQ=i2c_target_fifo_watermarks_acq_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm
_log /dev/null -cm_name 5.i2c_target_fifo_watermarks_acq.1850914322
Directory /workspace/5.i2c_target_fifo_watermarks_acq/latest

Test location /workspace/coverage/default/5.i2c_target_fifo_watermarks_tx.89648277
Short name T1215
Test name
Test status
Simulation time 262495271 ps
CPU time 1.5 seconds
Started Aug 12 04:41:19 PM PDT 24
Finished Aug 12 04:41:20 PM PDT 24
Peak memory 205292 kb
Host smart-e52eb3fd-6b4b-4ab8-8e91-a3cf729f7e57
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=89648277 -assert nopostproc +UVM_TESTNAME=i2c_base_
test +UVM_TEST_SEQ=i2c_target_fifo_watermarks_tx_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_lo
g /dev/null -cm_name 5.i2c_target_fifo_watermarks_tx.89648277
Directory /workspace/5.i2c_target_fifo_watermarks_tx/latest

Test location /workspace/coverage/default/5.i2c_target_hrst.3219770494
Short name T1129
Test name
Test status
Simulation time 1549234500 ps
CPU time 3.01 seconds
Started Aug 12 04:41:25 PM PDT 24
Finished Aug 12 04:41:28 PM PDT 24
Peak memory 213640 kb
Host smart-0c39180f-568f-4ab6-a3e7-0cbf2982f5a8
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3219770494 -assert nopostproc +UVM_TESTNAME=i2c_bas
e_test +UVM_TEST_SEQ=i2c_target_hrst_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null
-cm_name 5.i2c_target_hrst.3219770494
Directory /workspace/5.i2c_target_hrst/latest

Test location /workspace/coverage/default/5.i2c_target_intr_smoke.2346159189
Short name T1299
Test name
Test status
Simulation time 4850546901 ps
CPU time 7.36 seconds
Started Aug 12 04:41:11 PM PDT 24
Finished Aug 12 04:41:18 PM PDT 24
Peak memory 213820 kb
Host smart-0dbc193b-d84f-42be-9290-f0dfeadcfc6e
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=200_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VER
BOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2346159189 -assert nopostproc +UVM_TESTNAME=i2c_ba
se_test +UVM_TEST_SEQ=i2c_target_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/nul
l -cm_name 5.i2c_target_intr_smoke.2346159189
Directory /workspace/5.i2c_target_intr_smoke/latest

Test location /workspace/coverage/default/5.i2c_target_intr_stress_wr.1911377951
Short name T718
Test name
Test status
Simulation time 1883963725 ps
CPU time 6.03 seconds
Started Aug 12 04:41:18 PM PDT 24
Finished Aug 12 04:41:24 PM PDT 24
Peak memory 355748 kb
Host smart-3a020880-5aff-4554-ba99-603125744ba8
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=600_000_000 +use_intr_handler=1 +slow_acq=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNO
TES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1911377951 -assert nopostproc +UVM_TES
TNAME=i2c_base_test +UVM_TEST_SEQ=i2c_target_stress_wr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb
-cm_log /dev/null -cm_name 5.i2c_target_intr_stress_wr.1911377951
Directory /workspace/5.i2c_target_intr_stress_wr/latest

Test location /workspace/coverage/default/5.i2c_target_nack_acqfull.2570554457
Short name T946
Test name
Test status
Simulation time 1128546959 ps
CPU time 2.87 seconds
Started Aug 12 04:41:20 PM PDT 24
Finished Aug 12 04:41:23 PM PDT 24
Peak memory 213656 kb
Host smart-ac8be91c-d7d9-48d8-8bde-d811dda935e3
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2570554457 -assert nopostproc +UVM_TESTNAME=i2c_bas
e_test +UVM_TEST_SEQ=i2c_target_nack_acqfull_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /d
ev/null -cm_name 5.i2c_target_nack_acqfull.2570554457
Directory /workspace/5.i2c_target_nack_acqfull/latest

Test location /workspace/coverage/default/5.i2c_target_nack_acqfull_addr.1174586864
Short name T925
Test name
Test status
Simulation time 975743505 ps
CPU time 2.58 seconds
Started Aug 12 04:41:21 PM PDT 24
Finished Aug 12 04:41:24 PM PDT 24
Peak memory 205480 kb
Host smart-a35e524f-1305-4de2-b558-460afded1212
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1174586864 -assert nopostproc +UVM_TESTNAME=i2c_bas
e_test +UVM_TEST_SEQ=i2c_target_nack_acqfull_addr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_l
og /dev/null -cm_name 5.i2c_target_nack_acqfull_addr.1174586864
Directory /workspace/5.i2c_target_nack_acqfull_addr/latest

Test location /workspace/coverage/default/5.i2c_target_nack_txstretch.922650421
Short name T176
Test name
Test status
Simulation time 492639527 ps
CPU time 1.48 seconds
Started Aug 12 04:41:21 PM PDT 24
Finished Aug 12 04:41:23 PM PDT 24
Peak memory 222092 kb
Host smart-e0e00652-e976-4539-833f-66d1adef9fc9
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=922650421 -assert nopostproc +UVM_TESTNAME=i2c_base
_test +UVM_TEST_SEQ=i2c_target_nack_txstretch_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /
dev/null -cm_name 5.i2c_target_nack_txstretch.922650421
Directory /workspace/5.i2c_target_nack_txstretch/latest

Test location /workspace/coverage/default/5.i2c_target_perf.2515157073
Short name T825
Test name
Test status
Simulation time 1369519871 ps
CPU time 5.14 seconds
Started Aug 12 04:41:19 PM PDT 24
Finished Aug 12 04:41:24 PM PDT 24
Peak memory 221816 kb
Host smart-53744cb5-6070-4aa8-88ba-56f5395a2b81
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2515157073 -assert nopostproc +UVM_TESTNAME=i2c_bas
e_test +UVM_TEST_SEQ=i2c_target_perf_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null
-cm_name 5.i2c_target_perf.2515157073
Directory /workspace/5.i2c_target_perf/latest

Test location /workspace/coverage/default/5.i2c_target_smbus_maxlen.3043657094
Short name T1605
Test name
Test status
Simulation time 594791863 ps
CPU time 2.76 seconds
Started Aug 12 04:41:26 PM PDT 24
Finished Aug 12 04:41:29 PM PDT 24
Peak memory 205380 kb
Host smart-41f0afff-61db-461e-9c0e-60e235be4df8
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3043657094 -assert nopostproc +UVM_TESTNAME=i2c_bas
e_test +UVM_TEST_SEQ=i2c_target_smbus_maxlen_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /d
ev/null -cm_name 5.i2c_target_smbus_maxlen.3043657094
Directory /workspace/5.i2c_target_smbus_maxlen/latest

Test location /workspace/coverage/default/5.i2c_target_smoke.1986804974
Short name T1694
Test name
Test status
Simulation time 1145610689 ps
CPU time 36.8 seconds
Started Aug 12 04:41:11 PM PDT 24
Finished Aug 12 04:41:48 PM PDT 24
Peak memory 218056 kb
Host smart-fe785dee-e6a0-4537-9b13-5491aa0c9196
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=100_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licq
ueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1986804974 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SE
Q=i2c_target_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.i2c_tar
get_smoke.1986804974
Directory /workspace/5.i2c_target_smoke/latest

Test location /workspace/coverage/default/5.i2c_target_stress_all.428168888
Short name T634
Test name
Test status
Simulation time 80109003964 ps
CPU time 283.73 seconds
Started Aug 12 04:41:25 PM PDT 24
Finished Aug 12 04:46:09 PM PDT 24
Peak memory 1888412 kb
Host smart-d8d888d0-8029-4b28-85b8-d48a3083b2b7
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=300_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VER
BOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=428168888 -assert nopostproc +UVM_TESTNAME=i2c_bas
e_test +UVM_TEST_SEQ=i2c_target_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev
/null -cm_name 5.i2c_target_stress_all.428168888
Directory /workspace/5.i2c_target_stress_all/latest

Test location /workspace/coverage/default/5.i2c_target_stress_rd.916740785
Short name T1519
Test name
Test status
Simulation time 2919722035 ps
CPU time 14.11 seconds
Started Aug 12 04:41:12 PM PDT 24
Finished Aug 12 04:41:26 PM PDT 24
Peak memory 221860 kb
Host smart-f87a4e3a-0e1e-4fff-9e15-5da26295706a
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=100_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licq
ueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=916740785 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ
=i2c_target_stress_rd_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.i2c_
target_stress_rd.916740785
Directory /workspace/5.i2c_target_stress_rd/latest

Test location /workspace/coverage/default/5.i2c_target_stress_wr.1819809980
Short name T1474
Test name
Test status
Simulation time 75026757428 ps
CPU time 1725.18 seconds
Started Aug 12 04:41:11 PM PDT 24
Finished Aug 12 05:09:56 PM PDT 24
Peak memory 8657656 kb
Host smart-59452955-25ac-48ff-a71b-35d4830132a4
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=600_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licq
ueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1819809980 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SE
Q=i2c_target_stress_wr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.i2c
_target_stress_wr.1819809980
Directory /workspace/5.i2c_target_stress_wr/latest

Test location /workspace/coverage/default/5.i2c_target_stretch.1542110177
Short name T149
Test name
Test status
Simulation time 4390114820 ps
CPU time 48.34 seconds
Started Aug 12 04:41:11 PM PDT 24
Finished Aug 12 04:42:00 PM PDT 24
Peak memory 434904 kb
Host smart-ac368527-0252-49b1-81f4-da6ed927c9a0
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=400_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licq
ueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1542110177 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SE
Q=i2c_target_stretch_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.i2c_t
arget_stretch.1542110177
Directory /workspace/5.i2c_target_stretch/latest

Test location /workspace/coverage/default/5.i2c_target_timeout.1047680707
Short name T656
Test name
Test status
Simulation time 1330159249 ps
CPU time 7 seconds
Started Aug 12 04:41:20 PM PDT 24
Finished Aug 12 04:41:27 PM PDT 24
Peak memory 213648 kb
Host smart-4d23f081-b76e-4e17-a5ea-d26d00e979b8
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=50_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1047680707 -assert nopostproc +UVM_TESTNAME=i2c_bas
e_test +UVM_TEST_SEQ=i2c_target_timeout_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/nu
ll -cm_name 5.i2c_target_timeout.1047680707
Directory /workspace/5.i2c_target_timeout/latest

Test location /workspace/coverage/default/5.i2c_target_tx_stretch_ctrl.555071537
Short name T1294
Test name
Test status
Simulation time 64056518 ps
CPU time 1.59 seconds
Started Aug 12 04:41:25 PM PDT 24
Finished Aug 12 04:41:27 PM PDT 24
Peak memory 205508 kb
Host smart-823838fe-4f6f-44e7-a19e-fe720e9945ad
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=555071537 -assert nopostproc +UVM_TESTNAME=i2c_base
_test +UVM_TEST_SEQ=i2c_target_tx_stretch_ctrl_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log
/dev/null -cm_name 5.i2c_target_tx_stretch_ctrl.555071537
Directory /workspace/5.i2c_target_tx_stretch_ctrl/latest

Test location /workspace/coverage/default/6.i2c_alert_test.246518911
Short name T362
Test name
Test status
Simulation time 30306240 ps
CPU time 0.66 seconds
Started Aug 12 04:41:29 PM PDT 24
Finished Aug 12 04:41:30 PM PDT 24
Peak memory 204468 kb
Host smart-84dbfa26-70e4-4353-a869-8ad86e26666b
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=246518911 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_common_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.i2c_alert_test.246518911
Directory /workspace/6.i2c_alert_test/latest

Test location /workspace/coverage/default/6.i2c_host_error_intr.407548219
Short name T1319
Test name
Test status
Simulation time 590032628 ps
CPU time 10.56 seconds
Started Aug 12 04:41:19 PM PDT 24
Finished Aug 12 04:41:30 PM PDT 24
Peak memory 232436 kb
Host smart-8a35d355-136a-47c2-b586-c010c7a21ebb
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=407548219 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_error_intr_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.i2c_host_error_intr.407548219
Directory /workspace/6.i2c_host_error_intr/latest

Test location /workspace/coverage/default/6.i2c_host_fifo_fmt_empty.1725901940
Short name T1575
Test name
Test status
Simulation time 1561374928 ps
CPU time 7.88 seconds
Started Aug 12 04:41:24 PM PDT 24
Finished Aug 12 04:41:32 PM PDT 24
Peak memory 277848 kb
Host smart-ee4cfb7a-2fc1-46e1-84fb-2a4c596ec5ab
User root
Command /workspace/default/simv +test_timeout_ns=10_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1725901940 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_fifo_fmt_em
pty_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.i2c_host_fifo_fmt_empt
y.1725901940
Directory /workspace/6.i2c_host_fifo_fmt_empty/latest

Test location /workspace/coverage/default/6.i2c_host_fifo_full.2339794234
Short name T1084
Test name
Test status
Simulation time 2400324803 ps
CPU time 60.72 seconds
Started Aug 12 04:41:19 PM PDT 24
Finished Aug 12 04:42:19 PM PDT 24
Peak memory 346404 kb
Host smart-72972a90-5893-4014-a4e4-81740f40d0d4
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2339794234 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_fifo_full_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.i2c_host_fifo_full.2339794234
Directory /workspace/6.i2c_host_fifo_full/latest

Test location /workspace/coverage/default/6.i2c_host_fifo_overflow.3162437573
Short name T1365
Test name
Test status
Simulation time 5932633924 ps
CPU time 111.12 seconds
Started Aug 12 04:41:18 PM PDT 24
Finished Aug 12 04:43:09 PM PDT 24
Peak memory 576500 kb
Host smart-57d95d95-28ac-46b1-9c21-e23a79f2f12d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3162437573 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_fifo_overflow_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.i2c_host_fifo_overflow.3162437573
Directory /workspace/6.i2c_host_fifo_overflow/latest

Test location /workspace/coverage/default/6.i2c_host_fifo_reset_fmt.3336369969
Short name T202
Test name
Test status
Simulation time 234115848 ps
CPU time 1.03 seconds
Started Aug 12 04:41:21 PM PDT 24
Finished Aug 12 04:41:23 PM PDT 24
Peak memory 204928 kb
Host smart-4a59a693-1940-4c2a-9cc5-24c208d00b97
User root
Command /workspace/default/simv +test_timeout_ns=10_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3336369969 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_fifo_reset_
fmt_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.i2c_host_fifo_reset_fm
t.3336369969
Directory /workspace/6.i2c_host_fifo_reset_fmt/latest

Test location /workspace/coverage/default/6.i2c_host_fifo_watermark.1954041266
Short name T1075
Test name
Test status
Simulation time 21633554275 ps
CPU time 147.55 seconds
Started Aug 12 04:41:19 PM PDT 24
Finished Aug 12 04:43:47 PM PDT 24
Peak memory 1532048 kb
Host smart-059e8f9c-9745-405e-a428-c6eb515996e4
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1954041266 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_fifo_watermark_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.i2c_host_fifo_watermark.1954041266
Directory /workspace/6.i2c_host_fifo_watermark/latest

Test location /workspace/coverage/default/6.i2c_host_may_nack.1922633565
Short name T1348
Test name
Test status
Simulation time 400806667 ps
CPU time 5.13 seconds
Started Aug 12 04:41:25 PM PDT 24
Finished Aug 12 04:41:30 PM PDT 24
Peak memory 205220 kb
Host smart-f1d26113-b0a1-4e3c-8165-66641ae29e1d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1922633565 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_may_nack_vseq +en_cov=1 -cm line+cond+f
sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.i2c_host_may_nack.1922633565
Directory /workspace/6.i2c_host_may_nack/latest

Test location /workspace/coverage/default/6.i2c_host_override.776126076
Short name T1521
Test name
Test status
Simulation time 30394521 ps
CPU time 0.72 seconds
Started Aug 12 04:41:20 PM PDT 24
Finished Aug 12 04:41:21 PM PDT 24
Peak memory 204924 kb
Host smart-80739df5-c77c-4b88-8d8b-d451a1820ec4
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=776126076 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_override_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.i2c_host_override.776126076
Directory /workspace/6.i2c_host_override/latest

Test location /workspace/coverage/default/6.i2c_host_perf.1264139503
Short name T359
Test name
Test status
Simulation time 399760740 ps
CPU time 6.94 seconds
Started Aug 12 04:41:17 PM PDT 24
Finished Aug 12 04:41:24 PM PDT 24
Peak memory 221052 kb
Host smart-26b967e4-b7bf-47f0-b1af-8250957b4952
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1264139503 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_perf_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.i2c_host_perf.1264139503
Directory /workspace/6.i2c_host_perf/latest

Test location /workspace/coverage/default/6.i2c_host_smoke.395619620
Short name T41
Test name
Test status
Simulation time 1572905945 ps
CPU time 28.17 seconds
Started Aug 12 04:41:20 PM PDT 24
Finished Aug 12 04:41:49 PM PDT 24
Peak memory 352588 kb
Host smart-3a7dbc4c-ac4a-4a38-99aa-e63c8021d33f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=395619620 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_smoke_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.i2c_host_smoke.395619620
Directory /workspace/6.i2c_host_smoke/latest

Test location /workspace/coverage/default/6.i2c_host_stretch_timeout.1769256212
Short name T1486
Test name
Test status
Simulation time 1427572737 ps
CPU time 15.13 seconds
Started Aug 12 04:41:18 PM PDT 24
Finished Aug 12 04:41:33 PM PDT 24
Peak memory 213364 kb
Host smart-f19ce2e9-36f1-427b-90f8-3defaef9a490
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1769256212 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_stretch_timeout_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.i2c_host_stretch_timeout.1769256212
Directory /workspace/6.i2c_host_stretch_timeout/latest

Test location /workspace/coverage/default/6.i2c_target_bad_addr.3705738580
Short name T1212
Test name
Test status
Simulation time 3975020226 ps
CPU time 6.76 seconds
Started Aug 12 04:41:21 PM PDT 24
Finished Aug 12 04:41:28 PM PDT 24
Peak memory 214848 kb
Host smart-a0cc97c0-d218-43e2-bee1-0cc27301b897
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +i2c_bad_addr_pct=50 +cdc_instrumentation_enabled=1 +UVM_
NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3705738580 -assert nopostproc
+UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_target_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.
vdb -cm_log /dev/null -cm_name 6.i2c_target_bad_addr.3705738580
Directory /workspace/6.i2c_target_bad_addr/latest

Test location /workspace/coverage/default/6.i2c_target_fifo_reset_acq.822709773
Short name T1469
Test name
Test status
Simulation time 217083764 ps
CPU time 1.02 seconds
Started Aug 12 04:41:24 PM PDT 24
Finished Aug 12 04:41:25 PM PDT 24
Peak memory 205292 kb
Host smart-83b9a7d3-aeb4-4b41-b49f-19372f197afa
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=822709773 -assert nopostproc +UVM_TESTNAME=i2c_base
_test +UVM_TEST_SEQ=i2c_target_fifo_reset_acq_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /
dev/null -cm_name 6.i2c_target_fifo_reset_acq.822709773
Directory /workspace/6.i2c_target_fifo_reset_acq/latest

Test location /workspace/coverage/default/6.i2c_target_fifo_reset_tx.2225123774
Short name T1096
Test name
Test status
Simulation time 150639104 ps
CPU time 0.92 seconds
Started Aug 12 04:41:21 PM PDT 24
Finished Aug 12 04:41:22 PM PDT 24
Peak memory 205296 kb
Host smart-53b9036e-2952-4725-a3eb-c48118f9bb87
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2225123774 -assert nopostproc +UVM_TESTNAME=i2c_bas
e_test +UVM_TEST_SEQ=i2c_target_fifo_reset_tx_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /
dev/null -cm_name 6.i2c_target_fifo_reset_tx.2225123774
Directory /workspace/6.i2c_target_fifo_reset_tx/latest

Test location /workspace/coverage/default/6.i2c_target_fifo_watermarks_acq.1481763673
Short name T821
Test name
Test status
Simulation time 955462025 ps
CPU time 1.68 seconds
Started Aug 12 04:41:26 PM PDT 24
Finished Aug 12 04:41:28 PM PDT 24
Peak memory 205204 kb
Host smart-82d1969d-a4df-47b0-b511-ed084ef62017
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1481763673 -assert nopostproc +UVM_TESTNAME=i2c_bas
e_test +UVM_TEST_SEQ=i2c_target_fifo_watermarks_acq_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm
_log /dev/null -cm_name 6.i2c_target_fifo_watermarks_acq.1481763673
Directory /workspace/6.i2c_target_fifo_watermarks_acq/latest

Test location /workspace/coverage/default/6.i2c_target_fifo_watermarks_tx.739405838
Short name T847
Test name
Test status
Simulation time 158761355 ps
CPU time 1.06 seconds
Started Aug 12 04:41:25 PM PDT 24
Finished Aug 12 04:41:26 PM PDT 24
Peak memory 205252 kb
Host smart-d0b64e43-c211-419d-9369-2aac73adb5d6
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=739405838 -assert nopostproc +UVM_TESTNAME=i2c_base
_test +UVM_TEST_SEQ=i2c_target_fifo_watermarks_tx_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_l
og /dev/null -cm_name 6.i2c_target_fifo_watermarks_tx.739405838
Directory /workspace/6.i2c_target_fifo_watermarks_tx/latest

Test location /workspace/coverage/default/6.i2c_target_intr_smoke.3644932459
Short name T1036
Test name
Test status
Simulation time 9912801702 ps
CPU time 6.22 seconds
Started Aug 12 04:41:17 PM PDT 24
Finished Aug 12 04:41:24 PM PDT 24
Peak memory 216276 kb
Host smart-3e54b907-ae75-403a-9576-d7abb0e1707a
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=200_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VER
BOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3644932459 -assert nopostproc +UVM_TESTNAME=i2c_ba
se_test +UVM_TEST_SEQ=i2c_target_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/nul
l -cm_name 6.i2c_target_intr_smoke.3644932459
Directory /workspace/6.i2c_target_intr_smoke/latest

Test location /workspace/coverage/default/6.i2c_target_intr_stress_wr.3910381539
Short name T1672
Test name
Test status
Simulation time 22928354143 ps
CPU time 51.3 seconds
Started Aug 12 04:41:21 PM PDT 24
Finished Aug 12 04:42:12 PM PDT 24
Peak memory 1384772 kb
Host smart-b3bcb71c-d1ca-4563-8c27-b03c2ab62fef
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=600_000_000 +use_intr_handler=1 +slow_acq=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNO
TES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3910381539 -assert nopostproc +UVM_TES
TNAME=i2c_base_test +UVM_TEST_SEQ=i2c_target_stress_wr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb
-cm_log /dev/null -cm_name 6.i2c_target_intr_stress_wr.3910381539
Directory /workspace/6.i2c_target_intr_stress_wr/latest

Test location /workspace/coverage/default/6.i2c_target_nack_acqfull.116982329
Short name T1546
Test name
Test status
Simulation time 758292291 ps
CPU time 2.9 seconds
Started Aug 12 04:41:28 PM PDT 24
Finished Aug 12 04:41:31 PM PDT 24
Peak memory 213708 kb
Host smart-1acb1df0-b50c-4087-9770-0767a6543ff9
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=116982329 -assert nopostproc +UVM_TESTNAME=i2c_base
_test +UVM_TEST_SEQ=i2c_target_nack_acqfull_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /de
v/null -cm_name 6.i2c_target_nack_acqfull.116982329
Directory /workspace/6.i2c_target_nack_acqfull/latest

Test location /workspace/coverage/default/6.i2c_target_nack_acqfull_addr.1495658678
Short name T1035
Test name
Test status
Simulation time 2057899674 ps
CPU time 2.47 seconds
Started Aug 12 04:41:35 PM PDT 24
Finished Aug 12 04:41:38 PM PDT 24
Peak memory 205476 kb
Host smart-22d459b0-008a-4326-aaed-8e5a19c14355
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1495658678 -assert nopostproc +UVM_TESTNAME=i2c_bas
e_test +UVM_TEST_SEQ=i2c_target_nack_acqfull_addr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_l
og /dev/null -cm_name 6.i2c_target_nack_acqfull_addr.1495658678
Directory /workspace/6.i2c_target_nack_acqfull_addr/latest

Test location /workspace/coverage/default/6.i2c_target_nack_txstretch.3547022792
Short name T131
Test name
Test status
Simulation time 283502337 ps
CPU time 1.59 seconds
Started Aug 12 04:41:29 PM PDT 24
Finished Aug 12 04:41:31 PM PDT 24
Peak memory 222308 kb
Host smart-bfb77d19-f6bd-4e26-8c5c-1c46cdf50e43
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3547022792 -assert nopostproc +UVM_TESTNAME=i2c_bas
e_test +UVM_TEST_SEQ=i2c_target_nack_txstretch_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log
/dev/null -cm_name 6.i2c_target_nack_txstretch.3547022792
Directory /workspace/6.i2c_target_nack_txstretch/latest

Test location /workspace/coverage/default/6.i2c_target_perf.1442569175
Short name T430
Test name
Test status
Simulation time 1173226664 ps
CPU time 4.22 seconds
Started Aug 12 04:41:20 PM PDT 24
Finished Aug 12 04:41:25 PM PDT 24
Peak memory 221804 kb
Host smart-4adabdf1-7766-4f80-91f6-4a080b0c9f9b
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1442569175 -assert nopostproc +UVM_TESTNAME=i2c_bas
e_test +UVM_TEST_SEQ=i2c_target_perf_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null
-cm_name 6.i2c_target_perf.1442569175
Directory /workspace/6.i2c_target_perf/latest

Test location /workspace/coverage/default/6.i2c_target_smbus_maxlen.1185515065
Short name T780
Test name
Test status
Simulation time 394352370 ps
CPU time 2.14 seconds
Started Aug 12 04:41:35 PM PDT 24
Finished Aug 12 04:41:37 PM PDT 24
Peak memory 205228 kb
Host smart-1870fcb8-497a-48ae-9b94-d96447d8c4ab
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1185515065 -assert nopostproc +UVM_TESTNAME=i2c_bas
e_test +UVM_TEST_SEQ=i2c_target_smbus_maxlen_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /d
ev/null -cm_name 6.i2c_target_smbus_maxlen.1185515065
Directory /workspace/6.i2c_target_smbus_maxlen/latest

Test location /workspace/coverage/default/6.i2c_target_smoke.792593888
Short name T1690
Test name
Test status
Simulation time 638405922 ps
CPU time 9.54 seconds
Started Aug 12 04:41:20 PM PDT 24
Finished Aug 12 04:41:30 PM PDT 24
Peak memory 213764 kb
Host smart-df3ae02b-6b25-40b0-ad02-311991fab96f
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=100_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licq
ueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=792593888 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ
=i2c_target_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.i2c_targ
et_smoke.792593888
Directory /workspace/6.i2c_target_smoke/latest

Test location /workspace/coverage/default/6.i2c_target_stress_all.2162877950
Short name T290
Test name
Test status
Simulation time 26497714132 ps
CPU time 41.37 seconds
Started Aug 12 04:41:18 PM PDT 24
Finished Aug 12 04:42:00 PM PDT 24
Peak memory 430900 kb
Host smart-2503081c-f3e1-42fa-8a6b-3401f935358b
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=300_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VER
BOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2162877950 -assert nopostproc +UVM_TESTNAME=i2c_ba
se_test +UVM_TEST_SEQ=i2c_target_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /de
v/null -cm_name 6.i2c_target_stress_all.2162877950
Directory /workspace/6.i2c_target_stress_all/latest

Test location /workspace/coverage/default/6.i2c_target_stress_rd.1573296858
Short name T886
Test name
Test status
Simulation time 3554838853 ps
CPU time 18.28 seconds
Started Aug 12 04:41:26 PM PDT 24
Finished Aug 12 04:41:45 PM PDT 24
Peak memory 222076 kb
Host smart-d529cb73-9c78-45df-8127-0376c6aa841c
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=100_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licq
ueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1573296858 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SE
Q=i2c_target_stress_rd_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.i2c
_target_stress_rd.1573296858
Directory /workspace/6.i2c_target_stress_rd/latest

Test location /workspace/coverage/default/6.i2c_target_stress_wr.3104813151
Short name T1240
Test name
Test status
Simulation time 52801788117 ps
CPU time 1756.54 seconds
Started Aug 12 04:41:21 PM PDT 24
Finished Aug 12 05:10:38 PM PDT 24
Peak memory 8232680 kb
Host smart-ba0c9955-74e2-450b-b22b-dfda456dbdc8
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=600_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licq
ueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3104813151 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SE
Q=i2c_target_stress_wr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.i2c
_target_stress_wr.3104813151
Directory /workspace/6.i2c_target_stress_wr/latest

Test location /workspace/coverage/default/6.i2c_target_timeout.2389318482
Short name T1172
Test name
Test status
Simulation time 1588886795 ps
CPU time 7.23 seconds
Started Aug 12 04:41:22 PM PDT 24
Finished Aug 12 04:41:29 PM PDT 24
Peak memory 213636 kb
Host smart-c6ef31e3-1720-4529-87c9-d067f465a05b
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=50_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2389318482 -assert nopostproc +UVM_TESTNAME=i2c_bas
e_test +UVM_TEST_SEQ=i2c_target_timeout_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/nu
ll -cm_name 6.i2c_target_timeout.2389318482
Directory /workspace/6.i2c_target_timeout/latest

Test location /workspace/coverage/default/6.i2c_target_tx_stretch_ctrl.2057003047
Short name T1252
Test name
Test status
Simulation time 856372683 ps
CPU time 9.86 seconds
Started Aug 12 04:41:24 PM PDT 24
Finished Aug 12 04:41:34 PM PDT 24
Peak memory 214680 kb
Host smart-2897a12a-d6eb-4fdb-91ce-0676a5469e09
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2057003047 -assert nopostproc +UVM_TESTNAME=i2c_bas
e_test +UVM_TEST_SEQ=i2c_target_tx_stretch_ctrl_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log
/dev/null -cm_name 6.i2c_target_tx_stretch_ctrl.2057003047
Directory /workspace/6.i2c_target_tx_stretch_ctrl/latest

Test location /workspace/coverage/default/7.i2c_alert_test.1634445367
Short name T407
Test name
Test status
Simulation time 25472963 ps
CPU time 0.65 seconds
Started Aug 12 04:41:41 PM PDT 24
Finished Aug 12 04:41:42 PM PDT 24
Peak memory 204396 kb
Host smart-0bc6b2e8-cc83-43f5-8560-d6b36e25b7ab
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1634445367 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_common_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.i2c_alert_test.1634445367
Directory /workspace/7.i2c_alert_test/latest

Test location /workspace/coverage/default/7.i2c_host_error_intr.4221586978
Short name T148
Test name
Test status
Simulation time 569728157 ps
CPU time 5.6 seconds
Started Aug 12 04:41:31 PM PDT 24
Finished Aug 12 04:41:37 PM PDT 24
Peak memory 232884 kb
Host smart-a76e689c-f8fc-4562-ab50-15d6313de96b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4221586978 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_error_intr_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.i2c_host_error_intr.4221586978
Directory /workspace/7.i2c_host_error_intr/latest

Test location /workspace/coverage/default/7.i2c_host_fifo_fmt_empty.2248008065
Short name T613
Test name
Test status
Simulation time 512789809 ps
CPU time 10.78 seconds
Started Aug 12 04:41:32 PM PDT 24
Finished Aug 12 04:41:43 PM PDT 24
Peak memory 310344 kb
Host smart-544faea2-cfdc-4a54-8603-a0673ff5b435
User root
Command /workspace/default/simv +test_timeout_ns=10_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2248008065 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_fifo_fmt_em
pty_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.i2c_host_fifo_fmt_empt
y.2248008065
Directory /workspace/7.i2c_host_fifo_fmt_empty/latest

Test location /workspace/coverage/default/7.i2c_host_fifo_full.4102434181
Short name T454
Test name
Test status
Simulation time 8241363240 ps
CPU time 102.79 seconds
Started Aug 12 04:41:28 PM PDT 24
Finished Aug 12 04:43:11 PM PDT 24
Peak memory 213564 kb
Host smart-17ad5bda-f2d4-494e-a2ad-3fe758cb7219
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4102434181 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_fifo_full_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.i2c_host_fifo_full.4102434181
Directory /workspace/7.i2c_host_fifo_full/latest

Test location /workspace/coverage/default/7.i2c_host_fifo_overflow.2964056450
Short name T83
Test name
Test status
Simulation time 2292336592 ps
CPU time 153.75 seconds
Started Aug 12 04:41:30 PM PDT 24
Finished Aug 12 04:44:04 PM PDT 24
Peak memory 684316 kb
Host smart-878b10ab-0e11-400a-9cf1-a56ed0476de3
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2964056450 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_fifo_overflow_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.i2c_host_fifo_overflow.2964056450
Directory /workspace/7.i2c_host_fifo_overflow/latest

Test location /workspace/coverage/default/7.i2c_host_fifo_reset_fmt.4288105287
Short name T1513
Test name
Test status
Simulation time 188752293 ps
CPU time 1.17 seconds
Started Aug 12 04:41:27 PM PDT 24
Finished Aug 12 04:41:29 PM PDT 24
Peak memory 204864 kb
Host smart-7833f50e-d050-475a-9a0a-5b81ae3cef39
User root
Command /workspace/default/simv +test_timeout_ns=10_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4288105287 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_fifo_reset_
fmt_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.i2c_host_fifo_reset_fm
t.4288105287
Directory /workspace/7.i2c_host_fifo_reset_fmt/latest

Test location /workspace/coverage/default/7.i2c_host_fifo_reset_rx.3312158557
Short name T1098
Test name
Test status
Simulation time 149633541 ps
CPU time 8.06 seconds
Started Aug 12 04:41:28 PM PDT 24
Finished Aug 12 04:41:36 PM PDT 24
Peak memory 205296 kb
Host smart-b2c69756-4969-4cb6-bb83-7e9cfba3bbd5
User root
Command /workspace/default/simv +test_timeout_ns=10_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3312158557 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_fifo_reset_
rx_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.i2c_host_fifo_reset_rx.
3312158557
Directory /workspace/7.i2c_host_fifo_reset_rx/latest

Test location /workspace/coverage/default/7.i2c_host_fifo_watermark.4137773754
Short name T755
Test name
Test status
Simulation time 4223340180 ps
CPU time 296.63 seconds
Started Aug 12 04:41:29 PM PDT 24
Finished Aug 12 04:46:26 PM PDT 24
Peak memory 1228340 kb
Host smart-4e71c61f-35b0-4b3e-be63-6bcefde0d052
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4137773754 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_fifo_watermark_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.i2c_host_fifo_watermark.4137773754
Directory /workspace/7.i2c_host_fifo_watermark/latest

Test location /workspace/coverage/default/7.i2c_host_may_nack.3122964449
Short name T856
Test name
Test status
Simulation time 953877240 ps
CPU time 18.8 seconds
Started Aug 12 04:41:28 PM PDT 24
Finished Aug 12 04:41:47 PM PDT 24
Peak memory 205208 kb
Host smart-513e33ae-6c89-4f48-87f3-fc90909cdbc8
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3122964449 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_may_nack_vseq +en_cov=1 -cm line+cond+f
sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.i2c_host_may_nack.3122964449
Directory /workspace/7.i2c_host_may_nack/latest

Test location /workspace/coverage/default/7.i2c_host_mode_toggle.2694072002
Short name T883
Test name
Test status
Simulation time 147390514 ps
CPU time 3.81 seconds
Started Aug 12 04:41:31 PM PDT 24
Finished Aug 12 04:41:35 PM PDT 24
Peak memory 213452 kb
Host smart-1d98d9e0-9525-4ccf-8c5c-94cb23fbdc1b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2694072002 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_mode_toggle_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.i2c_host_mode_toggle.2694072002
Directory /workspace/7.i2c_host_mode_toggle/latest

Test location /workspace/coverage/default/7.i2c_host_perf.1222933102
Short name T1132
Test name
Test status
Simulation time 25855818328 ps
CPU time 234.18 seconds
Started Aug 12 04:41:28 PM PDT 24
Finished Aug 12 04:45:22 PM PDT 24
Peak memory 205260 kb
Host smart-54c5ce0c-9fd2-4173-a3c8-674feab845a9
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1222933102 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_perf_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.i2c_host_perf.1222933102
Directory /workspace/7.i2c_host_perf/latest

Test location /workspace/coverage/default/7.i2c_host_perf_precise.3235012451
Short name T1494
Test name
Test status
Simulation time 6301992502 ps
CPU time 56.29 seconds
Started Aug 12 04:41:26 PM PDT 24
Finished Aug 12 04:42:23 PM PDT 24
Peak memory 205340 kb
Host smart-58cabad2-6f0b-47fa-8359-db946955558e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3235012451 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_perf_precise_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.i2c_host_perf_precise.3235012451
Directory /workspace/7.i2c_host_perf_precise/latest

Test location /workspace/coverage/default/7.i2c_host_smoke.2706044961
Short name T1729
Test name
Test status
Simulation time 2178091185 ps
CPU time 99.03 seconds
Started Aug 12 04:41:30 PM PDT 24
Finished Aug 12 04:43:09 PM PDT 24
Peak memory 377716 kb
Host smart-2693e5b3-d0c6-4d21-a477-9d7217100791
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2706044961 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_smoke_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.i2c_host_smoke.2706044961
Directory /workspace/7.i2c_host_smoke/latest

Test location /workspace/coverage/default/7.i2c_host_stretch_timeout.490680515
Short name T1196
Test name
Test status
Simulation time 654230605 ps
CPU time 10.26 seconds
Started Aug 12 04:41:27 PM PDT 24
Finished Aug 12 04:41:38 PM PDT 24
Peak memory 221252 kb
Host smart-fe4cb14f-9964-4697-a81e-32948f262e3d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=490680515 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_stretch_timeout_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.i2c_host_stretch_timeout.490680515
Directory /workspace/7.i2c_host_stretch_timeout/latest

Test location /workspace/coverage/default/7.i2c_target_bad_addr.3853278291
Short name T1482
Test name
Test status
Simulation time 597052397 ps
CPU time 3.45 seconds
Started Aug 12 04:41:30 PM PDT 24
Finished Aug 12 04:41:33 PM PDT 24
Peak memory 217696 kb
Host smart-309aba4d-44eb-4fc1-8e81-71c0825a82d6
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +i2c_bad_addr_pct=50 +cdc_instrumentation_enabled=1 +UVM_
NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3853278291 -assert nopostproc
+UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_target_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.
vdb -cm_log /dev/null -cm_name 7.i2c_target_bad_addr.3853278291
Directory /workspace/7.i2c_target_bad_addr/latest

Test location /workspace/coverage/default/7.i2c_target_fifo_reset_acq.998057067
Short name T588
Test name
Test status
Simulation time 489950991 ps
CPU time 1.18 seconds
Started Aug 12 04:41:29 PM PDT 24
Finished Aug 12 04:41:30 PM PDT 24
Peak memory 205528 kb
Host smart-63806002-b9f1-440c-b525-9a0e9626edf2
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=998057067 -assert nopostproc +UVM_TESTNAME=i2c_base
_test +UVM_TEST_SEQ=i2c_target_fifo_reset_acq_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /
dev/null -cm_name 7.i2c_target_fifo_reset_acq.998057067
Directory /workspace/7.i2c_target_fifo_reset_acq/latest

Test location /workspace/coverage/default/7.i2c_target_fifo_reset_tx.1658384585
Short name T579
Test name
Test status
Simulation time 202181469 ps
CPU time 1.38 seconds
Started Aug 12 04:41:28 PM PDT 24
Finished Aug 12 04:41:30 PM PDT 24
Peak memory 205568 kb
Host smart-3fbeee78-9e3f-45df-b085-3400b8a90006
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1658384585 -assert nopostproc +UVM_TESTNAME=i2c_bas
e_test +UVM_TEST_SEQ=i2c_target_fifo_reset_tx_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /
dev/null -cm_name 7.i2c_target_fifo_reset_tx.1658384585
Directory /workspace/7.i2c_target_fifo_reset_tx/latest

Test location /workspace/coverage/default/7.i2c_target_fifo_watermarks_acq.3358074190
Short name T558
Test name
Test status
Simulation time 1127166546 ps
CPU time 3.34 seconds
Started Aug 12 04:41:35 PM PDT 24
Finished Aug 12 04:41:39 PM PDT 24
Peak memory 205436 kb
Host smart-897258ca-6593-416d-824c-eab5d58eada9
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3358074190 -assert nopostproc +UVM_TESTNAME=i2c_bas
e_test +UVM_TEST_SEQ=i2c_target_fifo_watermarks_acq_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm
_log /dev/null -cm_name 7.i2c_target_fifo_watermarks_acq.3358074190
Directory /workspace/7.i2c_target_fifo_watermarks_acq/latest

Test location /workspace/coverage/default/7.i2c_target_fifo_watermarks_tx.73184265
Short name T659
Test name
Test status
Simulation time 53268282 ps
CPU time 0.92 seconds
Started Aug 12 04:41:28 PM PDT 24
Finished Aug 12 04:41:29 PM PDT 24
Peak memory 205256 kb
Host smart-c0535fd4-4adb-4586-8a4c-7881e56477bc
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=73184265 -assert nopostproc +UVM_TESTNAME=i2c_base_
test +UVM_TEST_SEQ=i2c_target_fifo_watermarks_tx_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_lo
g /dev/null -cm_name 7.i2c_target_fifo_watermarks_tx.73184265
Directory /workspace/7.i2c_target_fifo_watermarks_tx/latest

Test location /workspace/coverage/default/7.i2c_target_intr_smoke.10831346
Short name T1210
Test name
Test status
Simulation time 2466230456 ps
CPU time 7.45 seconds
Started Aug 12 04:41:31 PM PDT 24
Finished Aug 12 04:41:39 PM PDT 24
Peak memory 221920 kb
Host smart-9ac55b13-c550-41d3-9349-11443bf2f265
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=200_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VER
BOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=10831346 -assert nopostproc +UVM_TESTNAME=i2c_base
_test +UVM_TEST_SEQ=i2c_target_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null
-cm_name 7.i2c_target_intr_smoke.10831346
Directory /workspace/7.i2c_target_intr_smoke/latest

Test location /workspace/coverage/default/7.i2c_target_intr_stress_wr.2071655636
Short name T1058
Test name
Test status
Simulation time 2744261006 ps
CPU time 2.54 seconds
Started Aug 12 04:41:29 PM PDT 24
Finished Aug 12 04:41:31 PM PDT 24
Peak memory 228184 kb
Host smart-f6691bb2-e918-4b2e-a5b5-0d23532e4300
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=600_000_000 +use_intr_handler=1 +slow_acq=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNO
TES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2071655636 -assert nopostproc +UVM_TES
TNAME=i2c_base_test +UVM_TEST_SEQ=i2c_target_stress_wr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb
-cm_log /dev/null -cm_name 7.i2c_target_intr_stress_wr.2071655636
Directory /workspace/7.i2c_target_intr_stress_wr/latest

Test location /workspace/coverage/default/7.i2c_target_nack_acqfull.3628883163
Short name T1699
Test name
Test status
Simulation time 535603030 ps
CPU time 2.69 seconds
Started Aug 12 04:41:30 PM PDT 24
Finished Aug 12 04:41:32 PM PDT 24
Peak memory 213608 kb
Host smart-4da3883d-b3bd-4b22-97b1-1cc7a85eef25
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3628883163 -assert nopostproc +UVM_TESTNAME=i2c_bas
e_test +UVM_TEST_SEQ=i2c_target_nack_acqfull_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /d
ev/null -cm_name 7.i2c_target_nack_acqfull.3628883163
Directory /workspace/7.i2c_target_nack_acqfull/latest

Test location /workspace/coverage/default/7.i2c_target_nack_acqfull_addr.556003238
Short name T1153
Test name
Test status
Simulation time 1943744866 ps
CPU time 2.69 seconds
Started Aug 12 04:41:38 PM PDT 24
Finished Aug 12 04:41:41 PM PDT 24
Peak memory 205368 kb
Host smart-c2665a90-3679-4e87-aa87-8f3b9e6e432d
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=556003238 -assert nopostproc +UVM_TESTNAME=i2c_base
_test +UVM_TEST_SEQ=i2c_target_nack_acqfull_addr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_lo
g /dev/null -cm_name 7.i2c_target_nack_acqfull_addr.556003238
Directory /workspace/7.i2c_target_nack_acqfull_addr/latest

Test location /workspace/coverage/default/7.i2c_target_perf.3568424484
Short name T1496
Test name
Test status
Simulation time 2170008094 ps
CPU time 3.88 seconds
Started Aug 12 04:41:30 PM PDT 24
Finished Aug 12 04:41:34 PM PDT 24
Peak memory 214784 kb
Host smart-e99a9f25-2359-4347-99af-4a624a3ad267
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3568424484 -assert nopostproc +UVM_TESTNAME=i2c_bas
e_test +UVM_TEST_SEQ=i2c_target_perf_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null
-cm_name 7.i2c_target_perf.3568424484
Directory /workspace/7.i2c_target_perf/latest

Test location /workspace/coverage/default/7.i2c_target_smbus_maxlen.764985385
Short name T1666
Test name
Test status
Simulation time 450558798 ps
CPU time 2.43 seconds
Started Aug 12 04:41:35 PM PDT 24
Finished Aug 12 04:41:37 PM PDT 24
Peak memory 205076 kb
Host smart-f9d09cbb-7822-44b9-bf29-d14817cd4656
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=764985385 -assert nopostproc +UVM_TESTNAME=i2c_base
_test +UVM_TEST_SEQ=i2c_target_smbus_maxlen_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /de
v/null -cm_name 7.i2c_target_smbus_maxlen.764985385
Directory /workspace/7.i2c_target_smbus_maxlen/latest

Test location /workspace/coverage/default/7.i2c_target_smoke.3789037726
Short name T985
Test name
Test status
Simulation time 3668184307 ps
CPU time 13.39 seconds
Started Aug 12 04:41:29 PM PDT 24
Finished Aug 12 04:41:43 PM PDT 24
Peak memory 213776 kb
Host smart-4e3f9820-0e7a-403d-9143-043781e9774a
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=100_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licq
ueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3789037726 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SE
Q=i2c_target_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.i2c_tar
get_smoke.3789037726
Directory /workspace/7.i2c_target_smoke/latest

Test location /workspace/coverage/default/7.i2c_target_stress_all.3060735238
Short name T851
Test name
Test status
Simulation time 22395735301 ps
CPU time 399.56 seconds
Started Aug 12 04:41:28 PM PDT 24
Finished Aug 12 04:48:07 PM PDT 24
Peak memory 4361536 kb
Host smart-09ba7c5b-95be-41d8-bc99-878557134210
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=300_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VER
BOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3060735238 -assert nopostproc +UVM_TESTNAME=i2c_ba
se_test +UVM_TEST_SEQ=i2c_target_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /de
v/null -cm_name 7.i2c_target_stress_all.3060735238
Directory /workspace/7.i2c_target_stress_all/latest

Test location /workspace/coverage/default/7.i2c_target_stress_rd.3624817161
Short name T823
Test name
Test status
Simulation time 5881763359 ps
CPU time 28.33 seconds
Started Aug 12 04:41:35 PM PDT 24
Finished Aug 12 04:42:04 PM PDT 24
Peak memory 230000 kb
Host smart-4a3a2534-1bef-4e03-a75e-659643fb17bc
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=100_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licq
ueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3624817161 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SE
Q=i2c_target_stress_rd_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.i2c
_target_stress_rd.3624817161
Directory /workspace/7.i2c_target_stress_rd/latest

Test location /workspace/coverage/default/7.i2c_target_stress_wr.2594400433
Short name T1326
Test name
Test status
Simulation time 15798739495 ps
CPU time 7.89 seconds
Started Aug 12 04:41:28 PM PDT 24
Finished Aug 12 04:41:36 PM PDT 24
Peak memory 205564 kb
Host smart-bd20a1ca-34ee-46bd-8e20-8db2362bf27a
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=600_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licq
ueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2594400433 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SE
Q=i2c_target_stress_wr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.i2c
_target_stress_wr.2594400433
Directory /workspace/7.i2c_target_stress_wr/latest

Test location /workspace/coverage/default/7.i2c_target_stretch.2389708267
Short name T714
Test name
Test status
Simulation time 3595642017 ps
CPU time 25.19 seconds
Started Aug 12 04:41:28 PM PDT 24
Finished Aug 12 04:41:53 PM PDT 24
Peak memory 569692 kb
Host smart-90bdb56d-aeb6-4e54-9cef-9e8219ea6f6d
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=400_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licq
ueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2389708267 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SE
Q=i2c_target_stretch_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.i2c_t
arget_stretch.2389708267
Directory /workspace/7.i2c_target_stretch/latest

Test location /workspace/coverage/default/7.i2c_target_timeout.292428493
Short name T1050
Test name
Test status
Simulation time 6595853900 ps
CPU time 6.94 seconds
Started Aug 12 04:41:30 PM PDT 24
Finished Aug 12 04:41:37 PM PDT 24
Peak memory 230032 kb
Host smart-be893687-ef51-4d09-8990-f20011a495d4
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=50_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=292428493 -assert nopostproc +UVM_TESTNAME=i2c_base
_test +UVM_TEST_SEQ=i2c_target_timeout_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/nul
l -cm_name 7.i2c_target_timeout.292428493
Directory /workspace/7.i2c_target_timeout/latest

Test location /workspace/coverage/default/7.i2c_target_tx_stretch_ctrl.2534325950
Short name T505
Test name
Test status
Simulation time 333111017 ps
CPU time 4.52 seconds
Started Aug 12 04:41:29 PM PDT 24
Finished Aug 12 04:41:34 PM PDT 24
Peak memory 205480 kb
Host smart-3440a374-0bad-497b-9732-6a36c6a675a7
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2534325950 -assert nopostproc +UVM_TESTNAME=i2c_bas
e_test +UVM_TEST_SEQ=i2c_target_tx_stretch_ctrl_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log
/dev/null -cm_name 7.i2c_target_tx_stretch_ctrl.2534325950
Directory /workspace/7.i2c_target_tx_stretch_ctrl/latest

Test location /workspace/coverage/default/8.i2c_alert_test.2657782159
Short name T513
Test name
Test status
Simulation time 25889392 ps
CPU time 0.63 seconds
Started Aug 12 04:41:42 PM PDT 24
Finished Aug 12 04:41:43 PM PDT 24
Peak memory 204512 kb
Host smart-b0ccd2b5-5aa2-405c-836e-8bdb187be9d1
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2657782159 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_common_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.i2c_alert_test.2657782159
Directory /workspace/8.i2c_alert_test/latest

Test location /workspace/coverage/default/8.i2c_host_error_intr.3404834502
Short name T1528
Test name
Test status
Simulation time 825478090 ps
CPU time 1.32 seconds
Started Aug 12 04:41:38 PM PDT 24
Finished Aug 12 04:41:40 PM PDT 24
Peak memory 221624 kb
Host smart-82138d3e-84fa-44b3-8b6e-d2fcb3fa9a83
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3404834502 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_error_intr_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.i2c_host_error_intr.3404834502
Directory /workspace/8.i2c_host_error_intr/latest

Test location /workspace/coverage/default/8.i2c_host_fifo_fmt_empty.755801435
Short name T438
Test name
Test status
Simulation time 847588976 ps
CPU time 9.77 seconds
Started Aug 12 04:41:43 PM PDT 24
Finished Aug 12 04:41:53 PM PDT 24
Peak memory 301952 kb
Host smart-0dc9cf2e-45cf-4bf1-a2d5-0220c22303f5
User root
Command /workspace/default/simv +test_timeout_ns=10_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=755801435 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_fifo_fmt_emp
ty_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.i2c_host_fifo_fmt_empty
.755801435
Directory /workspace/8.i2c_host_fifo_fmt_empty/latest

Test location /workspace/coverage/default/8.i2c_host_fifo_full.920716815
Short name T1023
Test name
Test status
Simulation time 2754426133 ps
CPU time 83.96 seconds
Started Aug 12 04:41:44 PM PDT 24
Finished Aug 12 04:43:08 PM PDT 24
Peak memory 621648 kb
Host smart-c623a488-8102-4d68-8430-e77a143e71bb
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=920716815 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_fifo_full_vseq +en_cov=1 -cm line+cond+f
sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.i2c_host_fifo_full.920716815
Directory /workspace/8.i2c_host_fifo_full/latest

Test location /workspace/coverage/default/8.i2c_host_fifo_overflow.972836908
Short name T806
Test name
Test status
Simulation time 1978443591 ps
CPU time 58.88 seconds
Started Aug 12 04:41:43 PM PDT 24
Finished Aug 12 04:42:43 PM PDT 24
Peak memory 637656 kb
Host smart-3653b349-55d6-44b0-aaf2-bf648a96b327
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=972836908 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_fifo_overflow_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.i2c_host_fifo_overflow.972836908
Directory /workspace/8.i2c_host_fifo_overflow/latest

Test location /workspace/coverage/default/8.i2c_host_fifo_reset_fmt.3733694505
Short name T587
Test name
Test status
Simulation time 610675092 ps
CPU time 1.18 seconds
Started Aug 12 04:41:39 PM PDT 24
Finished Aug 12 04:41:40 PM PDT 24
Peak memory 204924 kb
Host smart-2c11f1c7-6e9c-4b2a-9eaa-43fb07acb4c7
User root
Command /workspace/default/simv +test_timeout_ns=10_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3733694505 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_fifo_reset_
fmt_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.i2c_host_fifo_reset_fm
t.3733694505
Directory /workspace/8.i2c_host_fifo_reset_fmt/latest

Test location /workspace/coverage/default/8.i2c_host_fifo_reset_rx.2156195349
Short name T464
Test name
Test status
Simulation time 159049539 ps
CPU time 4 seconds
Started Aug 12 04:41:39 PM PDT 24
Finished Aug 12 04:41:43 PM PDT 24
Peak memory 205244 kb
Host smart-37cab2cc-d0f8-430c-8912-76263ac7ca04
User root
Command /workspace/default/simv +test_timeout_ns=10_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2156195349 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_fifo_reset_
rx_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.i2c_host_fifo_reset_rx.
2156195349
Directory /workspace/8.i2c_host_fifo_reset_rx/latest

Test location /workspace/coverage/default/8.i2c_host_fifo_watermark.1658370053
Short name T122
Test name
Test status
Simulation time 6376111766 ps
CPU time 70.5 seconds
Started Aug 12 04:41:40 PM PDT 24
Finished Aug 12 04:42:51 PM PDT 24
Peak memory 954128 kb
Host smart-9a20ebf7-6617-431b-bbcc-1930ebd983f5
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1658370053 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_fifo_watermark_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.i2c_host_fifo_watermark.1658370053
Directory /workspace/8.i2c_host_fifo_watermark/latest

Test location /workspace/coverage/default/8.i2c_host_override.3987130697
Short name T156
Test name
Test status
Simulation time 27273211 ps
CPU time 0.68 seconds
Started Aug 12 04:41:37 PM PDT 24
Finished Aug 12 04:41:38 PM PDT 24
Peak memory 204900 kb
Host smart-648f176b-69d5-4ea1-9d22-3a0fd0d6b6f5
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3987130697 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_override_vseq +en_cov=1 -cm line+cond+f
sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.i2c_host_override.3987130697
Directory /workspace/8.i2c_host_override/latest

Test location /workspace/coverage/default/8.i2c_host_perf.1509247273
Short name T1505
Test name
Test status
Simulation time 597487748 ps
CPU time 3.39 seconds
Started Aug 12 04:41:41 PM PDT 24
Finished Aug 12 04:41:45 PM PDT 24
Peak memory 237756 kb
Host smart-79d490a8-7281-4a36-8269-a112aba10672
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1509247273 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_perf_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.i2c_host_perf.1509247273
Directory /workspace/8.i2c_host_perf/latest

Test location /workspace/coverage/default/8.i2c_host_perf_precise.21137824
Short name T1314
Test name
Test status
Simulation time 6337694892 ps
CPU time 59.81 seconds
Started Aug 12 04:41:40 PM PDT 24
Finished Aug 12 04:42:40 PM PDT 24
Peak memory 205184 kb
Host smart-c8e84aa8-86c5-401a-af4d-58a217dad8c0
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=21137824 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_perf_precise_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.i2c_host_perf_precise.21137824
Directory /workspace/8.i2c_host_perf_precise/latest

Test location /workspace/coverage/default/8.i2c_host_smoke.4238469784
Short name T1377
Test name
Test status
Simulation time 2145681942 ps
CPU time 17.69 seconds
Started Aug 12 04:41:40 PM PDT 24
Finished Aug 12 04:41:58 PM PDT 24
Peak memory 271952 kb
Host smart-6b9a4cec-2e2a-46ca-95e2-def43ddd5977
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4238469784 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_smoke_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.i2c_host_smoke.4238469784
Directory /workspace/8.i2c_host_smoke/latest

Test location /workspace/coverage/default/8.i2c_host_stretch_timeout.2729641028
Short name T982
Test name
Test status
Simulation time 3836117280 ps
CPU time 39.05 seconds
Started Aug 12 04:41:43 PM PDT 24
Finished Aug 12 04:42:23 PM PDT 24
Peak memory 213436 kb
Host smart-bd1bad4a-70af-44bc-8d75-624b594a761e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2729641028 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_stretch_timeout_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.i2c_host_stretch_timeout.2729641028
Directory /workspace/8.i2c_host_stretch_timeout/latest

Test location /workspace/coverage/default/8.i2c_target_bad_addr.4058744866
Short name T1219
Test name
Test status
Simulation time 885574724 ps
CPU time 4.5 seconds
Started Aug 12 04:41:43 PM PDT 24
Finished Aug 12 04:41:48 PM PDT 24
Peak memory 208972 kb
Host smart-548ec68b-1fbf-4af3-b2fc-409330046056
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +i2c_bad_addr_pct=50 +cdc_instrumentation_enabled=1 +UVM_
NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4058744866 -assert nopostproc
+UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_target_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.
vdb -cm_log /dev/null -cm_name 8.i2c_target_bad_addr.4058744866
Directory /workspace/8.i2c_target_bad_addr/latest

Test location /workspace/coverage/default/8.i2c_target_fifo_reset_acq.1613686870
Short name T555
Test name
Test status
Simulation time 312371008 ps
CPU time 1.52 seconds
Started Aug 12 04:41:39 PM PDT 24
Finished Aug 12 04:41:40 PM PDT 24
Peak memory 205304 kb
Host smart-c8f402a8-0cab-4b06-a6fb-a9c4d37f3c39
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1613686870 -assert nopostproc +UVM_TESTNAME=i2c_bas
e_test +UVM_TEST_SEQ=i2c_target_fifo_reset_acq_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log
/dev/null -cm_name 8.i2c_target_fifo_reset_acq.1613686870
Directory /workspace/8.i2c_target_fifo_reset_acq/latest

Test location /workspace/coverage/default/8.i2c_target_fifo_reset_tx.2914277556
Short name T841
Test name
Test status
Simulation time 256026206 ps
CPU time 1.71 seconds
Started Aug 12 04:41:39 PM PDT 24
Finished Aug 12 04:41:41 PM PDT 24
Peak memory 206000 kb
Host smart-5674b8a9-0425-4121-a44b-cb36c106e9d0
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2914277556 -assert nopostproc +UVM_TESTNAME=i2c_bas
e_test +UVM_TEST_SEQ=i2c_target_fifo_reset_tx_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /
dev/null -cm_name 8.i2c_target_fifo_reset_tx.2914277556
Directory /workspace/8.i2c_target_fifo_reset_tx/latest

Test location /workspace/coverage/default/8.i2c_target_fifo_watermarks_acq.3153883285
Short name T1065
Test name
Test status
Simulation time 3204588433 ps
CPU time 2.95 seconds
Started Aug 12 04:41:43 PM PDT 24
Finished Aug 12 04:41:47 PM PDT 24
Peak memory 205464 kb
Host smart-b2589315-8f65-4f49-9503-9d90ff81932b
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3153883285 -assert nopostproc +UVM_TESTNAME=i2c_bas
e_test +UVM_TEST_SEQ=i2c_target_fifo_watermarks_acq_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm
_log /dev/null -cm_name 8.i2c_target_fifo_watermarks_acq.3153883285
Directory /workspace/8.i2c_target_fifo_watermarks_acq/latest

Test location /workspace/coverage/default/8.i2c_target_fifo_watermarks_tx.786014181
Short name T1431
Test name
Test status
Simulation time 280254420 ps
CPU time 1.24 seconds
Started Aug 12 04:41:39 PM PDT 24
Finished Aug 12 04:41:40 PM PDT 24
Peak memory 205172 kb
Host smart-07440ab1-678e-4305-86c2-40216a935c57
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=786014181 -assert nopostproc +UVM_TESTNAME=i2c_base
_test +UVM_TEST_SEQ=i2c_target_fifo_watermarks_tx_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_l
og /dev/null -cm_name 8.i2c_target_fifo_watermarks_tx.786014181
Directory /workspace/8.i2c_target_fifo_watermarks_tx/latest

Test location /workspace/coverage/default/8.i2c_target_intr_smoke.3997412779
Short name T1183
Test name
Test status
Simulation time 2092506566 ps
CPU time 6.66 seconds
Started Aug 12 04:41:42 PM PDT 24
Finished Aug 12 04:41:49 PM PDT 24
Peak memory 218748 kb
Host smart-17cd820b-0f58-4342-b9a5-6cd2463e4f20
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=200_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VER
BOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3997412779 -assert nopostproc +UVM_TESTNAME=i2c_ba
se_test +UVM_TEST_SEQ=i2c_target_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/nul
l -cm_name 8.i2c_target_intr_smoke.3997412779
Directory /workspace/8.i2c_target_intr_smoke/latest

Test location /workspace/coverage/default/8.i2c_target_intr_stress_wr.2771861725
Short name T1679
Test name
Test status
Simulation time 15453744827 ps
CPU time 27.61 seconds
Started Aug 12 04:41:43 PM PDT 24
Finished Aug 12 04:42:11 PM PDT 24
Peak memory 617648 kb
Host smart-1292a58a-1d4e-413f-8b71-29d702a58996
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=600_000_000 +use_intr_handler=1 +slow_acq=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNO
TES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2771861725 -assert nopostproc +UVM_TES
TNAME=i2c_base_test +UVM_TEST_SEQ=i2c_target_stress_wr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb
-cm_log /dev/null -cm_name 8.i2c_target_intr_stress_wr.2771861725
Directory /workspace/8.i2c_target_intr_stress_wr/latest

Test location /workspace/coverage/default/8.i2c_target_nack_acqfull.3452639558
Short name T653
Test name
Test status
Simulation time 9220090571 ps
CPU time 3.06 seconds
Started Aug 12 04:41:38 PM PDT 24
Finished Aug 12 04:41:41 PM PDT 24
Peak memory 213672 kb
Host smart-d70c3f14-1e8d-4829-8ad2-36f2ef640ca0
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3452639558 -assert nopostproc +UVM_TESTNAME=i2c_bas
e_test +UVM_TEST_SEQ=i2c_target_nack_acqfull_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /d
ev/null -cm_name 8.i2c_target_nack_acqfull.3452639558
Directory /workspace/8.i2c_target_nack_acqfull/latest

Test location /workspace/coverage/default/8.i2c_target_nack_acqfull_addr.4278373884
Short name T203
Test name
Test status
Simulation time 1823292613 ps
CPU time 2.48 seconds
Started Aug 12 04:41:42 PM PDT 24
Finished Aug 12 04:41:45 PM PDT 24
Peak memory 205488 kb
Host smart-7b4683c5-df5b-4b0b-846f-272b315e1660
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4278373884 -assert nopostproc +UVM_TESTNAME=i2c_bas
e_test +UVM_TEST_SEQ=i2c_target_nack_acqfull_addr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_l
og /dev/null -cm_name 8.i2c_target_nack_acqfull_addr.4278373884
Directory /workspace/8.i2c_target_nack_acqfull_addr/latest

Test location /workspace/coverage/default/8.i2c_target_nack_txstretch.3559924059
Short name T1456
Test name
Test status
Simulation time 566307308 ps
CPU time 1.46 seconds
Started Aug 12 04:41:40 PM PDT 24
Finished Aug 12 04:41:42 PM PDT 24
Peak memory 222008 kb
Host smart-75843e9c-2f5c-4b09-a44e-6fc36237924f
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3559924059 -assert nopostproc +UVM_TESTNAME=i2c_bas
e_test +UVM_TEST_SEQ=i2c_target_nack_txstretch_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log
/dev/null -cm_name 8.i2c_target_nack_txstretch.3559924059
Directory /workspace/8.i2c_target_nack_txstretch/latest

Test location /workspace/coverage/default/8.i2c_target_perf.2007151272
Short name T664
Test name
Test status
Simulation time 1667444646 ps
CPU time 5.84 seconds
Started Aug 12 04:41:42 PM PDT 24
Finished Aug 12 04:41:48 PM PDT 24
Peak memory 220212 kb
Host smart-336772af-7314-4816-b40d-5fe6d78176b2
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2007151272 -assert nopostproc +UVM_TESTNAME=i2c_bas
e_test +UVM_TEST_SEQ=i2c_target_perf_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null
-cm_name 8.i2c_target_perf.2007151272
Directory /workspace/8.i2c_target_perf/latest

Test location /workspace/coverage/default/8.i2c_target_smbus_maxlen.4190909962
Short name T895
Test name
Test status
Simulation time 915053200 ps
CPU time 2.15 seconds
Started Aug 12 04:41:40 PM PDT 24
Finished Aug 12 04:41:42 PM PDT 24
Peak memory 205364 kb
Host smart-e2db6ece-9329-473e-92bf-a7748a9828b7
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4190909962 -assert nopostproc +UVM_TESTNAME=i2c_bas
e_test +UVM_TEST_SEQ=i2c_target_smbus_maxlen_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /d
ev/null -cm_name 8.i2c_target_smbus_maxlen.4190909962
Directory /workspace/8.i2c_target_smbus_maxlen/latest

Test location /workspace/coverage/default/8.i2c_target_smoke.2123223038
Short name T129
Test name
Test status
Simulation time 3159513467 ps
CPU time 27.47 seconds
Started Aug 12 04:41:43 PM PDT 24
Finished Aug 12 04:42:11 PM PDT 24
Peak memory 222012 kb
Host smart-79cd25db-9009-4cf1-87e6-f4db09955890
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=100_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licq
ueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2123223038 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SE
Q=i2c_target_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.i2c_tar
get_smoke.2123223038
Directory /workspace/8.i2c_target_smoke/latest

Test location /workspace/coverage/default/8.i2c_target_stress_all.561595659
Short name T1473
Test name
Test status
Simulation time 36248779691 ps
CPU time 87.44 seconds
Started Aug 12 04:41:41 PM PDT 24
Finished Aug 12 04:43:09 PM PDT 24
Peak memory 1073152 kb
Host smart-07c3826e-8bec-4f58-9a7b-2050a5998cd8
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=300_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VER
BOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=561595659 -assert nopostproc +UVM_TESTNAME=i2c_bas
e_test +UVM_TEST_SEQ=i2c_target_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev
/null -cm_name 8.i2c_target_stress_all.561595659
Directory /workspace/8.i2c_target_stress_all/latest

Test location /workspace/coverage/default/8.i2c_target_stress_wr.3536132812
Short name T974
Test name
Test status
Simulation time 25193025680 ps
CPU time 12.7 seconds
Started Aug 12 04:41:38 PM PDT 24
Finished Aug 12 04:41:51 PM PDT 24
Peak memory 287128 kb
Host smart-f2ae3d5d-d6e9-43bf-9660-e61b148fe97d
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=600_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licq
ueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3536132812 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SE
Q=i2c_target_stress_wr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.i2c
_target_stress_wr.3536132812
Directory /workspace/8.i2c_target_stress_wr/latest

Test location /workspace/coverage/default/8.i2c_target_stretch.2915395609
Short name T367
Test name
Test status
Simulation time 2553314095 ps
CPU time 54.36 seconds
Started Aug 12 04:41:38 PM PDT 24
Finished Aug 12 04:42:33 PM PDT 24
Peak memory 787748 kb
Host smart-ec3060a1-7a67-445f-a77f-5b3f03685779
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=400_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licq
ueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2915395609 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SE
Q=i2c_target_stretch_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.i2c_t
arget_stretch.2915395609
Directory /workspace/8.i2c_target_stretch/latest

Test location /workspace/coverage/default/8.i2c_target_timeout.2120742197
Short name T1159
Test name
Test status
Simulation time 1257555892 ps
CPU time 6.91 seconds
Started Aug 12 04:41:40 PM PDT 24
Finished Aug 12 04:41:47 PM PDT 24
Peak memory 213644 kb
Host smart-ac0b36de-0581-4324-b71f-fe216173be12
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=50_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2120742197 -assert nopostproc +UVM_TESTNAME=i2c_bas
e_test +UVM_TEST_SEQ=i2c_target_timeout_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/nu
ll -cm_name 8.i2c_target_timeout.2120742197
Directory /workspace/8.i2c_target_timeout/latest

Test location /workspace/coverage/default/8.i2c_target_tx_stretch_ctrl.73227731
Short name T1535
Test name
Test status
Simulation time 220129992 ps
CPU time 2.99 seconds
Started Aug 12 04:41:41 PM PDT 24
Finished Aug 12 04:41:44 PM PDT 24
Peak memory 221124 kb
Host smart-2cb19fe3-cb3c-4a2e-811a-6743476db3cd
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=73227731 -assert nopostproc +UVM_TESTNAME=i2c_base_
test +UVM_TEST_SEQ=i2c_target_tx_stretch_ctrl_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /
dev/null -cm_name 8.i2c_target_tx_stretch_ctrl.73227731
Directory /workspace/8.i2c_target_tx_stretch_ctrl/latest

Test location /workspace/coverage/default/9.i2c_alert_test.3156295760
Short name T1429
Test name
Test status
Simulation time 19989190 ps
CPU time 0.64 seconds
Started Aug 12 04:41:48 PM PDT 24
Finished Aug 12 04:41:49 PM PDT 24
Peak memory 204428 kb
Host smart-16ce5c77-9a45-4848-a5c7-668c93610335
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3156295760 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_common_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.i2c_alert_test.3156295760
Directory /workspace/9.i2c_alert_test/latest

Test location /workspace/coverage/default/9.i2c_host_error_intr.821591443
Short name T684
Test name
Test status
Simulation time 430300400 ps
CPU time 1.54 seconds
Started Aug 12 04:41:46 PM PDT 24
Finished Aug 12 04:41:48 PM PDT 24
Peak memory 213496 kb
Host smart-a2bf28af-f86e-416c-abe6-73d9e8a4c74a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=821591443 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_error_intr_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.i2c_host_error_intr.821591443
Directory /workspace/9.i2c_host_error_intr/latest

Test location /workspace/coverage/default/9.i2c_host_fifo_fmt_empty.3939273749
Short name T400
Test name
Test status
Simulation time 2208459900 ps
CPU time 6.54 seconds
Started Aug 12 04:41:46 PM PDT 24
Finished Aug 12 04:41:53 PM PDT 24
Peak memory 266292 kb
Host smart-e4882f8e-57b9-4c76-a6c9-90fcc439aeb9
User root
Command /workspace/default/simv +test_timeout_ns=10_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3939273749 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_fifo_fmt_em
pty_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.i2c_host_fifo_fmt_empt
y.3939273749
Directory /workspace/9.i2c_host_fifo_fmt_empty/latest

Test location /workspace/coverage/default/9.i2c_host_fifo_full.2758372625
Short name T1458
Test name
Test status
Simulation time 6716473401 ps
CPU time 102.23 seconds
Started Aug 12 04:41:50 PM PDT 24
Finished Aug 12 04:43:33 PM PDT 24
Peak memory 663348 kb
Host smart-7f7e576b-015b-4741-bbb4-450afc4b8824
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2758372625 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_fifo_full_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.i2c_host_fifo_full.2758372625
Directory /workspace/9.i2c_host_fifo_full/latest

Test location /workspace/coverage/default/9.i2c_host_fifo_overflow.657684882
Short name T501
Test name
Test status
Simulation time 1402007438 ps
CPU time 88.78 seconds
Started Aug 12 04:41:46 PM PDT 24
Finished Aug 12 04:43:15 PM PDT 24
Peak memory 511636 kb
Host smart-90cf0645-123c-4ebc-ade2-fbb32347c72f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=657684882 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_fifo_overflow_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.i2c_host_fifo_overflow.657684882
Directory /workspace/9.i2c_host_fifo_overflow/latest

Test location /workspace/coverage/default/9.i2c_host_fifo_reset_fmt.2746889668
Short name T554
Test name
Test status
Simulation time 268646983 ps
CPU time 0.89 seconds
Started Aug 12 04:41:49 PM PDT 24
Finished Aug 12 04:41:50 PM PDT 24
Peak memory 204892 kb
Host smart-3e726ea8-b253-4bcb-b79a-926926293dfe
User root
Command /workspace/default/simv +test_timeout_ns=10_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2746889668 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_fifo_reset_
fmt_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.i2c_host_fifo_reset_fm
t.2746889668
Directory /workspace/9.i2c_host_fifo_reset_fmt/latest

Test location /workspace/coverage/default/9.i2c_host_fifo_reset_rx.1054393832
Short name T518
Test name
Test status
Simulation time 224949118 ps
CPU time 5.34 seconds
Started Aug 12 04:41:49 PM PDT 24
Finished Aug 12 04:41:54 PM PDT 24
Peak memory 246040 kb
Host smart-9cb3900d-a7f4-4f57-a2a4-a088939bbf9c
User root
Command /workspace/default/simv +test_timeout_ns=10_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1054393832 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_fifo_reset_
rx_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.i2c_host_fifo_reset_rx.
1054393832
Directory /workspace/9.i2c_host_fifo_reset_rx/latest

Test location /workspace/coverage/default/9.i2c_host_fifo_watermark.445333049
Short name T1441
Test name
Test status
Simulation time 5061114322 ps
CPU time 406.89 seconds
Started Aug 12 04:41:40 PM PDT 24
Finished Aug 12 04:48:27 PM PDT 24
Peak memory 1495292 kb
Host smart-e8935c9d-d1ec-4eca-bbaa-bec3b8be160b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=445333049 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_fifo_watermark_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.i2c_host_fifo_watermark.445333049
Directory /workspace/9.i2c_host_fifo_watermark/latest

Test location /workspace/coverage/default/9.i2c_host_may_nack.2981700863
Short name T753
Test name
Test status
Simulation time 526624735 ps
CPU time 2.68 seconds
Started Aug 12 04:41:47 PM PDT 24
Finished Aug 12 04:41:50 PM PDT 24
Peak memory 205284 kb
Host smart-f51d0ef8-8911-444e-9a17-5cbf98938d07
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2981700863 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_may_nack_vseq +en_cov=1 -cm line+cond+f
sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.i2c_host_may_nack.2981700863
Directory /workspace/9.i2c_host_may_nack/latest

Test location /workspace/coverage/default/9.i2c_host_override.833925652
Short name T154
Test name
Test status
Simulation time 90925501 ps
CPU time 0.69 seconds
Started Aug 12 04:41:37 PM PDT 24
Finished Aug 12 04:41:38 PM PDT 24
Peak memory 204816 kb
Host smart-5c704755-5444-4efa-b297-7c4695b43de0
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=833925652 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_override_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.i2c_host_override.833925652
Directory /workspace/9.i2c_host_override/latest

Test location /workspace/coverage/default/9.i2c_host_perf.489941701
Short name T576
Test name
Test status
Simulation time 366265500 ps
CPU time 5.45 seconds
Started Aug 12 04:41:45 PM PDT 24
Finished Aug 12 04:41:51 PM PDT 24
Peak memory 233900 kb
Host smart-ae8828a4-2c2d-4698-ac46-eb7d3c40c031
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=489941701 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_perf_vseq +en_cov=1 -cm line+cond+fsm+tg
l+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.i2c_host_perf.489941701
Directory /workspace/9.i2c_host_perf/latest

Test location /workspace/coverage/default/9.i2c_host_perf_precise.3142618983
Short name T373
Test name
Test status
Simulation time 92434210 ps
CPU time 2.09 seconds
Started Aug 12 04:41:49 PM PDT 24
Finished Aug 12 04:41:51 PM PDT 24
Peak memory 205136 kb
Host smart-bd20bbb5-dfc4-44fa-9d5b-f15cc36b97c1
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3142618983 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_perf_precise_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.i2c_host_perf_precise.3142618983
Directory /workspace/9.i2c_host_perf_precise/latest

Test location /workspace/coverage/default/9.i2c_host_smoke.584094072
Short name T516
Test name
Test status
Simulation time 5836560558 ps
CPU time 57.28 seconds
Started Aug 12 04:41:44 PM PDT 24
Finished Aug 12 04:42:41 PM PDT 24
Peak memory 278852 kb
Host smart-b2183d89-3f1f-4567-a851-9f2d3b4f5083
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=584094072 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_smoke_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.i2c_host_smoke.584094072
Directory /workspace/9.i2c_host_smoke/latest

Test location /workspace/coverage/default/9.i2c_host_stretch_timeout.795827159
Short name T399
Test name
Test status
Simulation time 1298811352 ps
CPU time 10.81 seconds
Started Aug 12 04:41:46 PM PDT 24
Finished Aug 12 04:41:57 PM PDT 24
Peak memory 221328 kb
Host smart-6766bc49-f278-4f40-b9ce-fc4af2e30d5c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=795827159 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_stretch_timeout_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.i2c_host_stretch_timeout.795827159
Directory /workspace/9.i2c_host_stretch_timeout/latest

Test location /workspace/coverage/default/9.i2c_target_bad_addr.2062320677
Short name T1236
Test name
Test status
Simulation time 4552716671 ps
CPU time 5.49 seconds
Started Aug 12 04:41:48 PM PDT 24
Finished Aug 12 04:41:54 PM PDT 24
Peak memory 213732 kb
Host smart-ad694589-4a1d-4261-8020-865e72a42d80
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +i2c_bad_addr_pct=50 +cdc_instrumentation_enabled=1 +UVM_
NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2062320677 -assert nopostproc
+UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_target_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.
vdb -cm_log /dev/null -cm_name 9.i2c_target_bad_addr.2062320677
Directory /workspace/9.i2c_target_bad_addr/latest

Test location /workspace/coverage/default/9.i2c_target_fifo_reset_acq.2612644265
Short name T935
Test name
Test status
Simulation time 156817046 ps
CPU time 1.21 seconds
Started Aug 12 04:41:45 PM PDT 24
Finished Aug 12 04:41:46 PM PDT 24
Peak memory 205264 kb
Host smart-78a07c2b-28e1-42a5-8a57-2f6244f63a4c
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2612644265 -assert nopostproc +UVM_TESTNAME=i2c_bas
e_test +UVM_TEST_SEQ=i2c_target_fifo_reset_acq_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log
/dev/null -cm_name 9.i2c_target_fifo_reset_acq.2612644265
Directory /workspace/9.i2c_target_fifo_reset_acq/latest

Test location /workspace/coverage/default/9.i2c_target_fifo_reset_tx.185296686
Short name T1368
Test name
Test status
Simulation time 129958650 ps
CPU time 1.01 seconds
Started Aug 12 04:41:48 PM PDT 24
Finished Aug 12 04:41:49 PM PDT 24
Peak memory 205216 kb
Host smart-a3f086cf-11ee-456e-8bf0-1b7bc3618cbb
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=185296686 -assert nopostproc +UVM_TESTNAME=i2c_base
_test +UVM_TEST_SEQ=i2c_target_fifo_reset_tx_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /d
ev/null -cm_name 9.i2c_target_fifo_reset_tx.185296686
Directory /workspace/9.i2c_target_fifo_reset_tx/latest

Test location /workspace/coverage/default/9.i2c_target_fifo_watermarks_acq.773952027
Short name T604
Test name
Test status
Simulation time 1620679229 ps
CPU time 2.49 seconds
Started Aug 12 04:41:48 PM PDT 24
Finished Aug 12 04:41:51 PM PDT 24
Peak memory 205452 kb
Host smart-aaba6011-d74e-4cce-8473-ef0ce9333461
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=773952027 -assert nopostproc +UVM_TESTNAME=i2c_base
_test +UVM_TEST_SEQ=i2c_target_fifo_watermarks_acq_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_
log /dev/null -cm_name 9.i2c_target_fifo_watermarks_acq.773952027
Directory /workspace/9.i2c_target_fifo_watermarks_acq/latest

Test location /workspace/coverage/default/9.i2c_target_fifo_watermarks_tx.47194944
Short name T1018
Test name
Test status
Simulation time 128035749 ps
CPU time 1.5 seconds
Started Aug 12 04:41:45 PM PDT 24
Finished Aug 12 04:41:47 PM PDT 24
Peak memory 205232 kb
Host smart-c3511346-810c-4fdc-b31e-62f730f6ab6e
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=47194944 -assert nopostproc +UVM_TESTNAME=i2c_base_
test +UVM_TEST_SEQ=i2c_target_fifo_watermarks_tx_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_lo
g /dev/null -cm_name 9.i2c_target_fifo_watermarks_tx.47194944
Directory /workspace/9.i2c_target_fifo_watermarks_tx/latest

Test location /workspace/coverage/default/9.i2c_target_hrst.1321049233
Short name T1490
Test name
Test status
Simulation time 599839959 ps
CPU time 2.42 seconds
Started Aug 12 04:41:55 PM PDT 24
Finished Aug 12 04:41:58 PM PDT 24
Peak memory 216528 kb
Host smart-8562448a-66c2-4623-9d2c-52d145a47893
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1321049233 -assert nopostproc +UVM_TESTNAME=i2c_bas
e_test +UVM_TEST_SEQ=i2c_target_hrst_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null
-cm_name 9.i2c_target_hrst.1321049233
Directory /workspace/9.i2c_target_hrst/latest

Test location /workspace/coverage/default/9.i2c_target_intr_smoke.4197634412
Short name T942
Test name
Test status
Simulation time 2155165743 ps
CPU time 5.98 seconds
Started Aug 12 04:41:48 PM PDT 24
Finished Aug 12 04:41:54 PM PDT 24
Peak memory 220292 kb
Host smart-5957a005-085d-4b75-aa5c-c616a0501424
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=200_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VER
BOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4197634412 -assert nopostproc +UVM_TESTNAME=i2c_ba
se_test +UVM_TEST_SEQ=i2c_target_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/nul
l -cm_name 9.i2c_target_intr_smoke.4197634412
Directory /workspace/9.i2c_target_intr_smoke/latest

Test location /workspace/coverage/default/9.i2c_target_intr_stress_wr.580303684
Short name T682
Test name
Test status
Simulation time 10350081474 ps
CPU time 5.68 seconds
Started Aug 12 04:41:50 PM PDT 24
Finished Aug 12 04:41:56 PM PDT 24
Peak memory 205476 kb
Host smart-72b3b6ed-0eee-4210-a1c0-fc1aa741d582
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=600_000_000 +use_intr_handler=1 +slow_acq=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNO
TES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=580303684 -assert nopostproc +UVM_TEST
NAME=i2c_base_test +UVM_TEST_SEQ=i2c_target_stress_wr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -
cm_log /dev/null -cm_name 9.i2c_target_intr_stress_wr.580303684
Directory /workspace/9.i2c_target_intr_stress_wr/latest

Test location /workspace/coverage/default/9.i2c_target_nack_acqfull.4216781214
Short name T1393
Test name
Test status
Simulation time 2208110561 ps
CPU time 2.96 seconds
Started Aug 12 04:41:50 PM PDT 24
Finished Aug 12 04:41:54 PM PDT 24
Peak memory 213704 kb
Host smart-24da651b-7cb3-4664-8af3-e58d0a676a3c
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4216781214 -assert nopostproc +UVM_TESTNAME=i2c_bas
e_test +UVM_TEST_SEQ=i2c_target_nack_acqfull_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /d
ev/null -cm_name 9.i2c_target_nack_acqfull.4216781214
Directory /workspace/9.i2c_target_nack_acqfull/latest

Test location /workspace/coverage/default/9.i2c_target_nack_acqfull_addr.3831824540
Short name T1306
Test name
Test status
Simulation time 527028885 ps
CPU time 2.72 seconds
Started Aug 12 04:41:45 PM PDT 24
Finished Aug 12 04:41:48 PM PDT 24
Peak memory 206132 kb
Host smart-60f19763-1088-4145-96ce-587c416e4cc9
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3831824540 -assert nopostproc +UVM_TESTNAME=i2c_bas
e_test +UVM_TEST_SEQ=i2c_target_nack_acqfull_addr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_l
og /dev/null -cm_name 9.i2c_target_nack_acqfull_addr.3831824540
Directory /workspace/9.i2c_target_nack_acqfull_addr/latest

Test location /workspace/coverage/default/9.i2c_target_perf.2643614678
Short name T1636
Test name
Test status
Simulation time 526343661 ps
CPU time 4.55 seconds
Started Aug 12 04:41:55 PM PDT 24
Finished Aug 12 04:42:00 PM PDT 24
Peak memory 213708 kb
Host smart-1b06a2e6-e425-459b-97fb-5591e3dd59ec
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2643614678 -assert nopostproc +UVM_TESTNAME=i2c_bas
e_test +UVM_TEST_SEQ=i2c_target_perf_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null
-cm_name 9.i2c_target_perf.2643614678
Directory /workspace/9.i2c_target_perf/latest

Test location /workspace/coverage/default/9.i2c_target_smbus_maxlen.21654663
Short name T1147
Test name
Test status
Simulation time 1830114740 ps
CPU time 2.26 seconds
Started Aug 12 04:41:47 PM PDT 24
Finished Aug 12 04:41:50 PM PDT 24
Peak memory 205212 kb
Host smart-0760c84d-519b-4e24-889a-8f909dabdaca
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=21654663 -assert nopostproc +UVM_TESTNAME=i2c_base_
test +UVM_TEST_SEQ=i2c_target_smbus_maxlen_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev
/null -cm_name 9.i2c_target_smbus_maxlen.21654663
Directory /workspace/9.i2c_target_smbus_maxlen/latest

Test location /workspace/coverage/default/9.i2c_target_smoke.2672318136
Short name T1555
Test name
Test status
Simulation time 8928373231 ps
CPU time 43.78 seconds
Started Aug 12 04:41:55 PM PDT 24
Finished Aug 12 04:42:39 PM PDT 24
Peak memory 213788 kb
Host smart-770bcfc2-e001-4423-aa0d-82bc2028707e
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=100_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licq
ueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2672318136 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SE
Q=i2c_target_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.i2c_tar
get_smoke.2672318136
Directory /workspace/9.i2c_target_smoke/latest

Test location /workspace/coverage/default/9.i2c_target_stress_all.1554847652
Short name T924
Test name
Test status
Simulation time 17151596509 ps
CPU time 39.35 seconds
Started Aug 12 04:41:46 PM PDT 24
Finished Aug 12 04:42:26 PM PDT 24
Peak memory 382944 kb
Host smart-a4c17a74-6f5d-4591-8fad-0e50e1f6331c
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=300_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VER
BOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1554847652 -assert nopostproc +UVM_TESTNAME=i2c_ba
se_test +UVM_TEST_SEQ=i2c_target_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /de
v/null -cm_name 9.i2c_target_stress_all.1554847652
Directory /workspace/9.i2c_target_stress_all/latest

Test location /workspace/coverage/default/9.i2c_target_stress_rd.2309018035
Short name T1499
Test name
Test status
Simulation time 4381580498 ps
CPU time 38.6 seconds
Started Aug 12 04:41:48 PM PDT 24
Finished Aug 12 04:42:26 PM PDT 24
Peak memory 213740 kb
Host smart-a3514100-ed8e-4127-ac8e-e5f62fd75dcf
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=100_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licq
ueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2309018035 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SE
Q=i2c_target_stress_rd_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.i2c
_target_stress_rd.2309018035
Directory /workspace/9.i2c_target_stress_rd/latest

Test location /workspace/coverage/default/9.i2c_target_stress_wr.1290834153
Short name T1626
Test name
Test status
Simulation time 35006998495 ps
CPU time 134.45 seconds
Started Aug 12 04:41:45 PM PDT 24
Finished Aug 12 04:44:00 PM PDT 24
Peak memory 1703156 kb
Host smart-07e1f9a5-87a7-4e92-a668-e9d3813264cf
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=600_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licq
ueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1290834153 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SE
Q=i2c_target_stress_wr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.i2c
_target_stress_wr.1290834153
Directory /workspace/9.i2c_target_stress_wr/latest

Test location /workspace/coverage/default/9.i2c_target_stretch.3984070569
Short name T715
Test name
Test status
Simulation time 343671086 ps
CPU time 9.28 seconds
Started Aug 12 04:41:55 PM PDT 24
Finished Aug 12 04:42:05 PM PDT 24
Peak memory 236724 kb
Host smart-24277f5d-70ea-46b5-a5ba-34d315847aa1
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=400_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licq
ueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3984070569 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SE
Q=i2c_target_stretch_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.i2c_t
arget_stretch.3984070569
Directory /workspace/9.i2c_target_stretch/latest

Test location /workspace/coverage/default/9.i2c_target_timeout.599095706
Short name T458
Test name
Test status
Simulation time 1298390872 ps
CPU time 6.88 seconds
Started Aug 12 04:41:55 PM PDT 24
Finished Aug 12 04:42:02 PM PDT 24
Peak memory 213712 kb
Host smart-0d61c4a1-95f7-482b-9fbc-dd6a5b5c1ac1
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=50_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=599095706 -assert nopostproc +UVM_TESTNAME=i2c_base
_test +UVM_TEST_SEQ=i2c_target_timeout_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/nul
l -cm_name 9.i2c_target_timeout.599095706
Directory /workspace/9.i2c_target_timeout/latest

Test location /workspace/coverage/default/9.i2c_target_tx_stretch_ctrl.3951900816
Short name T761
Test name
Test status
Simulation time 186997706 ps
CPU time 3.36 seconds
Started Aug 12 04:41:49 PM PDT 24
Finished Aug 12 04:41:53 PM PDT 24
Peak memory 205464 kb
Host smart-7ffddbb0-c304-4186-9290-e0aa246a9429
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3951900816 -assert nopostproc +UVM_TESTNAME=i2c_bas
e_test +UVM_TEST_SEQ=i2c_target_tx_stretch_ctrl_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log
/dev/null -cm_name 9.i2c_target_tx_stretch_ctrl.3951900816
Directory /workspace/9.i2c_target_tx_stretch_ctrl/latest
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