Unified Coverage Report :: Group :: cip_base_pkg::intr_cg::SHAPE{(num_interrupts - 1)=14}

Group : cip_base_pkg::intr_cg::SHAPE{(num_interrupts - 1)=14}

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
91.14	1	100	1	64	64

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_dv_cip_lib_0/cip_base_env_cov.sv

---

Summary for Group cip_base_pkg::intr_cg::SHAPE{(num_interrupts - 1)=14}

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	19	0	19	100.00
Crosses	60	7	53	88.33

Variables for Group cip_base_pkg::intr_cg::SHAPE{(num_interrupts - 1)=14}

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
cp_intr	15	0	15	100.00	100	1	1	0
cp_intr_en	2	0	2	100.00	100	1	1	2
cp_intr_state	2	0	2	100.00	100	1	1	2

Crosses for Group cip_base_pkg::intr_cg::SHAPE{(num_interrupts - 1)=14}

CROSS	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	PRINT MISSING	COMMENT
intr_cg_cc	60	7	53	88.33	100	1	1	0

Summary for Variable cp_intr

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	15	0	15	100.00

User Defined Bins for cp_intr

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
all_values[0]	793604	1			T1	2		T2	2		T3	4188
all_values[1]	793604	1			T1	2		T2	2		T3	4188
all_values[2]	793604	1			T1	2		T2	2		T3	4188
all_values[3]	793604	1			T1	2		T2	2		T3	4188
all_values[4]	793604	1			T1	2		T2	2		T3	4188
all_values[5]	793604	1			T1	2		T2	2		T3	4188
all_values[6]	793604	1			T1	2		T2	2		T3	4188
all_values[7]	793604	1			T1	2		T2	2		T3	4188
all_values[8]	793604	1			T1	2		T2	2		T3	4188
all_values[9]	793604	1			T1	2		T2	2		T3	4188
all_values[10]	793604	1			T1	2		T2	2		T3	4188
all_values[11]	793604	1			T1	2		T2	2		T3	4188
all_values[12]	793604	1			T1	2		T2	2		T3	4188
all_values[13]	793604	1			T1	2		T2	2		T3	4188
all_values[14]	793604	1			T1	2		T2	2		T3	4188

---

Summary for Variable cp_intr_en

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cp_intr_en

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

9759896

1

T1

26

T2

26

T3

54426

auto[1]

2144164

1

T1

4

T2

4

T3

8394

---

Summary for Variable cp_intr_state

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cp_intr_state

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

11268493

1

T1

30

T2

30

T3

62820

auto[1]

635567

1

T15

122817

T25

69

T26

199

---

Summary for Cross intr_cg_cc

Samples crossed: cp_intr cp_intr_en cp_intr_state

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	60	7	53	88.33	7

Automatically Generated Cross Bins for intr_cg_cc

Uncovered bins

cp_intr	cp_intr_en	cp_intr_state	COUNT	AT LEAST	NUMBER	STATUS
[all_values[3]]	[auto[1]]	[auto[0]]	0	1	1
[all_values[5] , all_values[6]]	[auto[1]]	[auto[0]]	--	--	2
[all_values[8]]	[auto[1]]	[auto[0]]	0	1	1
[all_values[10]]	[auto[1]]	[auto[0]]	0	1	1
[all_values[13] , all_values[14]]	[auto[1]]	[auto[0]]	--	--	2

Covered bins

cp_intr	cp_intr_en	cp_intr_state	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
all_values[0]	auto[0]	auto[0]	106299	1			T3	2		T6	7		T7	1
all_values[0]	auto[0]	auto[1]	4834	1			T15	1060		T25	4		T26	9
all_values[0]	auto[1]	auto[0]	640580	1			T1	2		T2	2		T3	4186
all_values[0]	auto[1]	auto[1]	41891	1			T15	10104		T25	2		T26	4
all_values[1]	auto[0]	auto[0]	746971	1			T1	2		T2	2		T3	4188
all_values[1]	auto[0]	auto[1]	46292	1			T15	11163		T25	3		T26	11
all_values[1]	auto[1]	auto[0]	200	1			T262	9		T263	2		T11	2
all_values[1]	auto[1]	auto[1]	141	1			T15	3		T25	3		T26	3
all_values[2]	auto[0]	auto[0]	746689	1			T1	2		T2	2		T3	4188
all_values[2]	auto[0]	auto[1]	46592	1			T15	11163		T25	5		T26	8
all_values[2]	auto[1]	auto[0]	191	1			T157	2		T52	1		T233	2
all_values[2]	auto[1]	auto[1]	132	1			T15	1		T25	1		T26	4
all_values[3]	auto[0]	auto[0]	764657	1			T1	2		T2	2		T3	4188
all_values[3]	auto[0]	auto[1]	28801	1			T25	4		T26	10		T36	369
all_values[3]	auto[1]	auto[1]	146	1			T25	2		T26	3		T36	1
all_values[4]	auto[0]	auto[0]	746870	1			T1	2		T2	2		T3	4188
all_values[4]	auto[0]	auto[1]	46586	1			T15	11163		T25	3		T26	7
all_values[4]	auto[1]	auto[0]	15	1			T22	2		T255	1		T264	1
all_values[4]	auto[1]	auto[1]	133	1			T15	3		T25	1		T26	6
all_values[5]	auto[0]	auto[0]	747608	1			T1	2		T2	2		T3	4188
all_values[5]	auto[0]	auto[1]	45832	1			T15	11164		T25	2		T26	6
all_values[5]	auto[1]	auto[1]	164	1			T15	1		T25	4		T26	8
all_values[6]	auto[0]	auto[0]	758044	1			T1	2		T2	2		T3	4188
all_values[6]	auto[0]	auto[1]	35392	1			T25	5		T26	6		T36	366
all_values[6]	auto[1]	auto[1]	168	1			T25	1		T26	8		T36	4
all_values[7]	auto[0]	auto[0]	732102	1			T1	2		T2	2		T3	4168
all_values[7]	auto[0]	auto[1]	34152	1			T25	2		T26	8		T36	323
all_values[7]	auto[1]	auto[0]	25935	1			T3	20		T7	1		T9	1013
all_values[7]	auto[1]	auto[1]	1415	1			T25	4		T26	5		T36	45
all_values[8]	auto[0]	auto[0]	747167	1			T1	2		T2	2		T3	4188
all_values[8]	auto[0]	auto[1]	46264	1			T15	11164		T25	2		T26	7
all_values[8]	auto[1]	auto[1]	173	1			T15	1		T25	2		T26	7
all_values[9]	auto[0]	auto[0]	144842	1			T1	2		T2	2		T3	4186
all_values[9]	auto[0]	auto[1]	7609	1			T15	1093		T25	2		T26	7
all_values[9]	auto[1]	auto[0]	602031	1			T3	2		T7	1		T9	1
all_values[9]	auto[1]	auto[1]	39122	1			T15	10072		T25	3		T26	7
all_values[10]	auto[0]	auto[0]	753093	1			T1	2		T2	2		T3	4188
all_values[10]	auto[0]	auto[1]	40366	1			T15	11164		T26	7		T36	366
all_values[10]	auto[1]	auto[1]	145	1			T15	2		T26	6		T36	3
all_values[11]	auto[0]	auto[0]	2261	1			T3	2		T6	7		T7	1
all_values[11]	auto[0]	auto[1]	251	1			T25	3		T26	10		T36	26
all_values[11]	auto[1]	auto[0]	762005	1			T1	2		T2	2		T3	4186
all_values[11]	auto[1]	auto[1]	29087	1			T25	1		T26	3		T36	343
all_values[12]	auto[0]	auto[0]	746831	1			T1	2		T2	2		T3	4188
all_values[12]	auto[0]	auto[1]	46580	1			T15	11164		T26	10		T36	367
all_values[12]	auto[1]	auto[0]	60	1			T52	1		T53	1		T265	1
all_values[12]	auto[1]	auto[1]	133	1			T15	1		T26	4		T36	3
all_values[13]	auto[0]	auto[0]	746864	1			T1	2		T2	2		T3	4188
all_values[13]	auto[0]	auto[1]	46582	1			T15	11164		T25	5		T26	5
all_values[13]	auto[1]	auto[1]	158	1			T15	1		T26	7		T36	7
all_values[14]	auto[0]	auto[0]	747178	1			T1	2		T2	2		T3	4188
all_values[14]	auto[0]	auto[1]	46287	1			T15	11164		T25	5		T26	7
all_values[14]	auto[1]	auto[1]	139	1			T15	2		T26	6		T36	2