Unified Coverage Report :: Group :: cip_base_pkg::intr_pins_cg::SHAPE{(num_interrupts - 1)=14}

Group : cip_base_pkg::intr_pins_cg::SHAPE{(num_interrupts - 1)=14}

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
100.00	1	100	1	64	64

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_dv_cip_lib_0/cip_base_env_cov.sv

---

Summary for Group cip_base_pkg::intr_pins_cg::SHAPE{(num_interrupts - 1)=14}

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	19	0	19	100.00
Crosses	60	0	60	100.00

Variables for Group cip_base_pkg::intr_pins_cg::SHAPE{(num_interrupts - 1)=14}

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
cp_intr_pin	15	0	15	100.00	100	1	1	0
cp_intr_pin_value	4	0	4	100.00	100	1	1	0

Crosses for Group cip_base_pkg::intr_pins_cg::SHAPE{(num_interrupts - 1)=14}

CROSS	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	PRINT MISSING	COMMENT
cp_intr_pins_all_values	60	0	60	100.00	100	1	1	0

Summary for Variable cp_intr_pin

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	15	0	15	100.00

User Defined Bins for cp_intr_pin

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
all_pins[0]	793604	1			T1	2		T2	2		T3	4188
all_pins[1]	793604	1			T1	2		T2	2		T3	4188
all_pins[2]	793604	1			T1	2		T2	2		T3	4188
all_pins[3]	793604	1			T1	2		T2	2		T3	4188
all_pins[4]	793604	1			T1	2		T2	2		T3	4188
all_pins[5]	793604	1			T1	2		T2	2		T3	4188
all_pins[6]	793604	1			T1	2		T2	2		T3	4188
all_pins[7]	793604	1			T1	2		T2	2		T3	4188
all_pins[8]	793604	1			T1	2		T2	2		T3	4188
all_pins[9]	793604	1			T1	2		T2	2		T3	4188
all_pins[10]	793604	1			T1	2		T2	2		T3	4188
all_pins[11]	793604	1			T1	2		T2	2		T3	4188
all_pins[12]	793604	1			T1	2		T2	2		T3	4188
all_pins[13]	793604	1			T1	2		T2	2		T3	4188
all_pins[14]	793604	1			T1	2		T2	2		T3	4188

---

Summary for Variable cp_intr_pin_value

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	4	0	4	100.00

User Defined Bins for cp_intr_pin_value

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
values[0x0]	9766044	1			T1	26		T2	26		T3	54426
values[0x1]	2138016	1			T1	4		T2	4		T3	8394
transitions[0x0=>0x1]	2137464	1			T1	4		T2	4		T3	8394
transitions[0x1=>0x0]	2136152	1			T1	3		T2	3		T3	8393

---

Summary for Cross cp_intr_pins_all_values

Samples crossed: cp_intr_pin cp_intr_pin_value

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	60	0	60	100.00

Automatically Generated Cross Bins for cp_intr_pins_all_values

Bins

cp_intr_pin	cp_intr_pin_value	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
all_pins[0]	values[0x0]	114685	1			T3	2		T6	7		T7	1
all_pins[0]	values[0x1]	678919	1			T1	2		T2	2		T3	4186
all_pins[0]	transitions[0x0=>0x1]	678641	1			T1	2		T2	2		T3	4186
all_pins[0]	transitions[0x1=>0x0]	40	1			T15	2		T26	2		T36	1
all_pins[1]	values[0x0]	793286	1			T1	2		T2	2		T3	4188
all_pins[1]	values[0x1]	318	1			T262	9		T263	2		T15	2
all_pins[1]	transitions[0x0=>0x1]	305	1			T262	9		T263	2		T15	2
all_pins[1]	transitions[0x1=>0x0]	98	1			T265	1		T271	1		T272	1
all_pins[2]	values[0x0]	793493	1			T1	2		T2	2		T3	4188
all_pins[2]	values[0x1]	111	1			T265	1		T271	1		T272	1
all_pins[2]	transitions[0x0=>0x1]	100	1			T265	1		T271	1		T272	1
all_pins[2]	transitions[0x1=>0x0]	66	1			T25	2		T26	3		T37	3
all_pins[3]	values[0x0]	793527	1			T1	2		T2	2		T3	4188
all_pins[3]	values[0x1]	77	1			T25	2		T26	3		T36	1
all_pins[3]	transitions[0x0=>0x1]	63	1			T25	2		T26	2		T37	3
all_pins[3]	transitions[0x1=>0x0]	72	1			T22	2		T15	3		T273	1
all_pins[4]	values[0x0]	793518	1			T1	2		T2	2		T3	4188
all_pins[4]	values[0x1]	86	1			T22	2		T15	3		T273	1
all_pins[4]	transitions[0x0=>0x1]	74	1			T22	2		T15	2		T273	1
all_pins[4]	transitions[0x1=>0x0]	78	1			T26	1		T36	3		T109	1
all_pins[5]	values[0x0]	793514	1			T1	2		T2	2		T3	4188
all_pins[5]	values[0x1]	90	1			T15	1		T26	2		T36	3
all_pins[5]	transitions[0x0=>0x1]	64	1			T15	1		T36	1		T109	1
all_pins[5]	transitions[0x1=>0x0]	60	1			T25	1		T36	1		T37	2
all_pins[6]	values[0x0]	793518	1			T1	2		T2	2		T3	4188
all_pins[6]	values[0x1]	86	1			T25	1		T26	2		T36	3
all_pins[6]	transitions[0x0=>0x1]	62	1			T25	1		T26	2		T36	3
all_pins[6]	transitions[0x1=>0x0]	29610	1			T3	20		T7	1		T9	1026
all_pins[7]	values[0x0]	763970	1			T1	2		T2	2		T3	4168
all_pins[7]	values[0x1]	29634	1			T3	20		T7	1		T9	1026
all_pins[7]	transitions[0x0=>0x1]	29612	1			T3	20		T7	1		T9	1026
all_pins[7]	transitions[0x1=>0x0]	65	1			T15	1		T26	2		T36	2
all_pins[8]	values[0x0]	793517	1			T1	2		T2	2		T3	4188
all_pins[8]	values[0x1]	87	1			T15	1		T25	2		T26	2
all_pins[8]	transitions[0x0=>0x1]	59	1			T26	1		T36	2		T37	6
all_pins[8]	transitions[0x1=>0x0]	641070	1			T3	2		T7	1		T9	1
all_pins[9]	values[0x0]	152506	1			T1	2		T2	2		T3	4186
all_pins[9]	values[0x1]	641098	1			T3	2		T7	1		T9	1
all_pins[9]	transitions[0x0=>0x1]	641082	1			T3	2		T7	1		T9	1
all_pins[9]	transitions[0x1=>0x0]	64	1			T15	1		T26	1		T36	2
all_pins[10]	values[0x0]	793524	1			T1	2		T2	2		T3	4188
all_pins[10]	values[0x1]	80	1			T15	1		T26	1		T36	2
all_pins[10]	transitions[0x0=>0x1]	63	1			T15	1		T26	1		T36	2
all_pins[10]	transitions[0x1=>0x0]	787127	1			T1	2		T2	2		T3	4186
all_pins[11]	values[0x0]	6460	1			T3	2		T6	7		T7	1
all_pins[11]	values[0x1]	787144	1			T1	2		T2	2		T3	4186
all_pins[11]	transitions[0x0=>0x1]	787118	1			T1	2		T2	2		T3	4186
all_pins[11]	transitions[0x1=>0x0]	101	1			T52	1		T53	1		T55	1
all_pins[12]	values[0x0]	793477	1			T1	2		T2	2		T3	4188
all_pins[12]	values[0x1]	127	1			T52	1		T53	1		T265	1
all_pins[12]	transitions[0x0=>0x1]	111	1			T52	1		T53	1		T265	1
all_pins[12]	transitions[0x1=>0x0]	64	1			T26	3		T36	2		T109	3
all_pins[13]	values[0x0]	793524	1			T1	2		T2	2		T3	4188
all_pins[13]	values[0x1]	80	1			T26	4		T36	4		T109	4
all_pins[13]	transitions[0x0=>0x1]	60	1			T36	3		T109	1		T37	4
all_pins[13]	transitions[0x1=>0x0]	59	1			T15	1		T26	1		T109	1
all_pins[14]	values[0x0]	793525	1			T1	2		T2	2		T3	4188
all_pins[14]	values[0x1]	79	1			T15	1		T26	5		T36	1
all_pins[14]	transitions[0x0=>0x1]	50	1			T15	1		T26	5		T36	1
all_pins[14]	transitions[0x1=>0x0]	677578	1			T1	1		T2	1		T3	4185