Unified Coverage Report :: Group :: cip_base_pkg::intr_test_cg::SHAPE{(num_interrupts - 1)=14}

Group : cip_base_pkg::intr_test_cg::SHAPE{(num_interrupts - 1)=14}

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
100.00	1	100	1	64	64

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_dv_cip_lib_0/cip_base_env_cov.sv

---

Summary for Group cip_base_pkg::intr_test_cg::SHAPE{(num_interrupts - 1)=14}

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	21	0	21	100.00
Crosses	90	0	90	100.00

Variables for Group cip_base_pkg::intr_test_cg::SHAPE{(num_interrupts - 1)=14}

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
cp_intr	15	0	15	100.00	100	1	1	0
cp_intr_en	2	0	2	100.00	100	1	1	2
cp_intr_state	2	0	2	100.00	100	1	1	2
cp_intr_test	2	0	2	100.00	100	1	1	2

Crosses for Group cip_base_pkg::intr_test_cg::SHAPE{(num_interrupts - 1)=14}

CROSS	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	PRINT MISSING	COMMENT
intr_test_cg_cc	90	0	90	100.00	100	1	1	0

Summary for Variable cp_intr

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	15	0	15	100.00

User Defined Bins for cp_intr

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
all_values[0]	339	1			T15	4		T25	4		T26	11
all_values[1]	339	1			T15	4		T25	4		T26	11
all_values[2]	339	1			T15	4		T25	4		T26	11
all_values[3]	339	1			T15	4		T25	4		T26	11
all_values[4]	339	1			T15	4		T25	4		T26	11
all_values[5]	339	1			T15	4		T25	4		T26	11
all_values[6]	339	1			T15	4		T25	4		T26	11
all_values[7]	339	1			T15	4		T25	4		T26	11
all_values[8]	339	1			T15	4		T25	4		T26	11
all_values[9]	339	1			T15	4		T25	4		T26	11
all_values[10]	339	1			T15	4		T25	4		T26	11
all_values[11]	339	1			T15	4		T25	4		T26	11
all_values[12]	339	1			T15	4		T25	4		T26	11
all_values[13]	339	1			T15	4		T25	4		T26	11
all_values[14]	339	1			T15	4		T25	4		T26	11

---

Summary for Variable cp_intr_en

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cp_intr_en

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

2750

1

T15

25

T25

18

T26

86

auto[1]

2335

1

T15

35

T25

42

T26

79

---

Summary for Variable cp_intr_state

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cp_intr_state

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

902

1

T15

25

T25

17

T26

11

auto[1]

4183

1

T15

35

T25

43

T26

154

---

Summary for Variable cp_intr_test

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cp_intr_test

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

3007

1

T15

39

T25

40

T26

96

auto[1]

2078

1

T15

21

T25

20

T26

69

---

Summary for Cross intr_test_cg_cc

Samples crossed: cp_intr cp_intr_test cp_intr_en cp_intr_state

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
TOTAL	90	0	90	100.00
Automatically Generated Cross Bins	90	0	90	100.00
User Defined Cross Bins	0	0	0

Automatically Generated Cross Bins for intr_test_cg_cc

Bins

cp_intr	cp_intr_test	cp_intr_en	cp_intr_state	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
all_values[0]	auto[0]	auto[0]	auto[0]	50	1			T15	2		T26	1		T109	1
all_values[0]	auto[0]	auto[0]	auto[1]	64	1			T15	1		T26	1		T36	2
all_values[0]	auto[0]	auto[1]	auto[0]	14	1			T36	1		T109	1		T274	1
all_values[0]	auto[0]	auto[1]	auto[1]	74	1			T25	2		T26	5		T36	3
all_values[0]	auto[1]	auto[0]	auto[1]	79	1			T15	1		T26	4		T36	1
all_values[0]	auto[1]	auto[1]	auto[1]	58	1			T25	2		T36	1		T109	1
all_values[1]	auto[0]	auto[0]	auto[0]	29	1			T36	3		T109	1		T275	2
all_values[1]	auto[0]	auto[0]	auto[1]	80	1			T15	1		T26	5		T109	3
all_values[1]	auto[0]	auto[1]	auto[0]	26	1			T36	2		T109	2		T276	2
all_values[1]	auto[0]	auto[1]	auto[1]	67	1			T25	1		T26	3		T36	2
all_values[1]	auto[1]	auto[0]	auto[1]	86	1			T25	2		T26	1		T109	1
all_values[1]	auto[1]	auto[1]	auto[1]	51	1			T15	3		T25	1		T26	2
all_values[2]	auto[0]	auto[0]	auto[0]	32	1			T26	2		T277	3		T278	1
all_values[2]	auto[0]	auto[0]	auto[1]	79	1			T15	1		T25	1		T26	4
all_values[2]	auto[0]	auto[1]	auto[0]	32	1			T15	2		T276	1		T274	1
all_values[2]	auto[0]	auto[1]	auto[1]	64	1			T25	2		T26	1		T36	1
all_values[2]	auto[1]	auto[0]	auto[1]	82	1			T15	1		T25	1		T26	3
all_values[2]	auto[1]	auto[1]	auto[1]	50	1			T26	1		T36	2		T109	3
all_values[3]	auto[0]	auto[0]	auto[0]	43	1			T15	1		T274	1		T279	2
all_values[3]	auto[0]	auto[0]	auto[1]	67	1			T26	2		T36	3		T109	2
all_values[3]	auto[0]	auto[1]	auto[0]	31	1			T15	3		T26	1		T276	3
all_values[3]	auto[0]	auto[1]	auto[1]	66	1			T25	2		T26	3		T36	3
all_values[3]	auto[1]	auto[0]	auto[1]	66	1			T26	1		T109	2		T37	1
all_values[3]	auto[1]	auto[1]	auto[1]	66	1			T25	2		T26	4		T36	2
all_values[4]	auto[0]	auto[0]	auto[0]	43	1			T37	1		T276	2		T279	3
all_values[4]	auto[0]	auto[0]	auto[1]	58	1			T26	1		T36	1		T109	1
all_values[4]	auto[0]	auto[1]	auto[0]	24	1			T25	2		T26	1		T36	1
all_values[4]	auto[0]	auto[1]	auto[1]	81	1			T15	1		T25	1		T26	3
all_values[4]	auto[1]	auto[0]	auto[1]	67	1			T26	4		T36	2		T37	1
all_values[4]	auto[1]	auto[1]	auto[1]	66	1			T15	3		T25	1		T26	2
all_values[5]	auto[0]	auto[0]	auto[0]	33	1			T15	1		T280	4		T122	2
all_values[5]	auto[0]	auto[0]	auto[1]	68	1			T25	2		T26	3		T36	2
all_values[5]	auto[0]	auto[1]	auto[0]	21	1			T36	1		T121	1		T122	2
all_values[5]	auto[0]	auto[1]	auto[1]	69	1			T15	1		T26	3		T36	1
all_values[5]	auto[1]	auto[0]	auto[1]	84	1			T15	1		T25	2		T26	4
all_values[5]	auto[1]	auto[1]	auto[1]	64	1			T15	1		T26	1		T36	2
all_values[6]	auto[0]	auto[0]	auto[0]	41	1			T15	1		T109	1		T37	2
all_values[6]	auto[0]	auto[0]	auto[1]	57	1			T26	4		T276	1		T274	2
all_values[6]	auto[0]	auto[1]	auto[0]	27	1			T15	3		T109	1		T37	1
all_values[6]	auto[0]	auto[1]	auto[1]	76	1			T25	2		T26	2		T36	4
all_values[6]	auto[1]	auto[0]	auto[1]	75	1			T26	3		T36	2		T109	2
all_values[6]	auto[1]	auto[1]	auto[1]	63	1			T25	2		T26	2		T36	2
all_values[7]	auto[0]	auto[0]	auto[0]	35	1			T15	1		T36	1		T275	1
all_values[7]	auto[0]	auto[0]	auto[1]	63	1			T25	1		T26	1		T36	4
all_values[7]	auto[0]	auto[1]	auto[0]	25	1			T15	3		T26	1		T36	1
all_values[7]	auto[0]	auto[1]	auto[1]	71	1			T25	2		T26	5		T109	2
all_values[7]	auto[1]	auto[0]	auto[1]	81	1			T25	1		T26	2		T36	1
all_values[7]	auto[1]	auto[1]	auto[1]	64	1			T26	2		T36	1		T109	2
all_values[8]	auto[0]	auto[0]	auto[0]	34	1			T15	1		T37	2		T279	1
all_values[8]	auto[0]	auto[0]	auto[1]	80	1			T26	4		T37	2		T280	3
all_values[8]	auto[0]	auto[1]	auto[0]	18	1			T25	2		T36	5		T109	1
all_values[8]	auto[0]	auto[1]	auto[1]	74	1			T15	1		T25	1		T26	1
all_values[8]	auto[1]	auto[0]	auto[1]	62	1			T15	1		T26	3		T36	1
all_values[8]	auto[1]	auto[1]	auto[1]	71	1			T15	1		T25	1		T26	3
all_values[9]	auto[0]	auto[0]	auto[0]	34	1			T25	1		T109	1		T276	2
all_values[9]	auto[0]	auto[0]	auto[1]	68	1			T26	2		T36	1		T109	2
all_values[9]	auto[0]	auto[1]	auto[0]	24	1			T15	1		T109	1		T276	2
all_values[9]	auto[0]	auto[1]	auto[1]	60	1			T15	1		T25	1		T26	3
all_values[9]	auto[1]	auto[0]	auto[1]	79	1			T25	1		T26	4		T36	3
all_values[9]	auto[1]	auto[1]	auto[1]	74	1			T15	2		T25	1		T26	2
all_values[10]	auto[0]	auto[0]	auto[0]	28	1			T26	1		T109	1		T274	3
all_values[10]	auto[0]	auto[0]	auto[1]	73	1			T15	2		T109	1		T280	2
all_values[10]	auto[0]	auto[1]	auto[0]	15	1			T25	4		T36	1		T109	3
all_values[10]	auto[0]	auto[1]	auto[1]	78	1			T26	4		T36	4		T109	1
all_values[10]	auto[1]	auto[0]	auto[1]	68	1			T26	4		T36	1		T109	1
all_values[10]	auto[1]	auto[1]	auto[1]	77	1			T15	2		T26	2		T36	2
all_values[11]	auto[0]	auto[0]	auto[0]	38	1			T15	1		T37	1		T274	4
all_values[11]	auto[0]	auto[0]	auto[1]	73	1			T26	3		T36	4		T109	2
all_values[11]	auto[0]	auto[1]	auto[0]	19	1			T15	3		T25	2		T26	1
all_values[11]	auto[0]	auto[1]	auto[1]	65	1			T25	1		T26	4		T36	1
all_values[11]	auto[1]	auto[0]	auto[1]	86	1			T26	1		T36	2		T109	1
all_values[11]	auto[1]	auto[1]	auto[1]	58	1			T25	1		T26	2		T109	3
all_values[12]	auto[0]	auto[0]	auto[0]	48	1			T15	1		T25	2		T281	2
all_values[12]	auto[0]	auto[0]	auto[1]	73	1			T15	2		T26	4		T36	2
all_values[12]	auto[0]	auto[1]	auto[0]	26	1			T25	2		T280	1		T276	2
all_values[12]	auto[0]	auto[1]	auto[1]	59	1			T26	3		T36	3		T109	2
all_values[12]	auto[1]	auto[0]	auto[1]	75	1			T15	1		T26	2		T109	3
all_values[12]	auto[1]	auto[1]	auto[1]	58	1			T26	2		T36	3		T109	1
all_values[13]	auto[0]	auto[0]	auto[0]	32	1			T25	1		T26	2		T279	1
all_values[13]	auto[0]	auto[0]	auto[1]	70	1			T15	1		T25	2		T26	3
all_values[13]	auto[0]	auto[1]	auto[0]	18	1			T15	1		T109	1		T37	1
all_values[13]	auto[0]	auto[1]	auto[1]	78	1			T26	2		T36	2		T109	2
all_values[13]	auto[1]	auto[0]	auto[1]	86	1			T15	1		T25	1		T26	2
all_values[13]	auto[1]	auto[1]	auto[1]	55	1			T15	1		T26	2		T36	3
all_values[14]	auto[0]	auto[0]	auto[0]	42	1			T26	1		T36	3		T37	1
all_values[14]	auto[0]	auto[0]	auto[1]	69	1			T15	2		T26	3		T36	1
all_values[14]	auto[0]	auto[1]	auto[0]	20	1			T25	1		T36	1		T280	1
all_values[14]	auto[0]	auto[1]	auto[1]	81	1			T25	2		T26	3		T36	1
all_values[14]	auto[1]	auto[0]	auto[1]	70	1			T26	1		T36	2		T37	2
all_values[14]	auto[1]	auto[1]	auto[1]	57	1			T15	2		T25	1		T26	3

User Defined Cross Bins for intr_test_cg_cc

Excluded/Illegal bins

NAME	COUNT	STATUS
test_1_state_0	0	Illegal