Unified Coverage Report :: Group :: cip_base_pkg::intr_cg::SHAPE{(num_interrupts - 1)=14}

Group : cip_base_pkg::intr_cg::SHAPE{(num_interrupts - 1)=14}

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
91.14	1	100	1	64	64

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_dv_cip_lib_0/cip_base_env_cov.sv

---

Summary for Group cip_base_pkg::intr_cg::SHAPE{(num_interrupts - 1)=14}

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	19	0	19	100.00
Crosses	60	7	53	88.33

Variables for Group cip_base_pkg::intr_cg::SHAPE{(num_interrupts - 1)=14}

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
cp_intr	15	0	15	100.00	100	1	1	0
cp_intr_en	2	0	2	100.00	100	1	1	2
cp_intr_state	2	0	2	100.00	100	1	1	2

Crosses for Group cip_base_pkg::intr_cg::SHAPE{(num_interrupts - 1)=14}

CROSS	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	PRINT MISSING	COMMENT
intr_cg_cc	60	7	53	88.33	100	1	1	0

Summary for Variable cp_intr

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	15	0	15	100.00

User Defined Bins for cp_intr

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
all_values[0]	768695	1			T1	2		T2	2		T3	2
all_values[1]	768695	1			T1	2		T2	2		T3	2
all_values[2]	768695	1			T1	2		T2	2		T3	2
all_values[3]	768695	1			T1	2		T2	2		T3	2
all_values[4]	768695	1			T1	2		T2	2		T3	2
all_values[5]	768695	1			T1	2		T2	2		T3	2
all_values[6]	768695	1			T1	2		T2	2		T3	2
all_values[7]	768695	1			T1	2		T2	2		T3	2
all_values[8]	768695	1			T1	2		T2	2		T3	2
all_values[9]	768695	1			T1	2		T2	2		T3	2
all_values[10]	768695	1			T1	2		T2	2		T3	2
all_values[11]	768695	1			T1	2		T2	2		T3	2
all_values[12]	768695	1			T1	2		T2	2		T3	2
all_values[13]	768695	1			T1	2		T2	2		T3	2
all_values[14]	768695	1			T1	2		T2	2		T3	2

---

Summary for Variable cp_intr_en

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cp_intr_en

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

9465718

1

T1

26

T2

26

T3

26

auto[1]

2064707

1

T1

4

T2

4

T3

4

---

Summary for Variable cp_intr_state

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cp_intr_state

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

10796158

1

T1

30

T2

30

T3

30

auto[1]

734267

1

T15

116

T19

271

T154

328146

---

Summary for Cross intr_cg_cc

Samples crossed: cp_intr cp_intr_en cp_intr_state

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	60	7	53	88.33	7

Automatically Generated Cross Bins for intr_cg_cc

Uncovered bins

cp_intr	cp_intr_en	cp_intr_state	COUNT	AT LEAST	NUMBER	STATUS
[all_values[3]]	[auto[1]]	[auto[0]]	0	1	1
[all_values[5] , all_values[6]]	[auto[1]]	[auto[0]]	--	--	2
[all_values[8]]	[auto[1]]	[auto[0]]	0	1	1
[all_values[10]]	[auto[1]]	[auto[0]]	0	1	1
[all_values[13] , all_values[14]]	[auto[1]]	[auto[0]]	--	--	2

Covered bins

cp_intr	cp_intr_en	cp_intr_state	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
all_values[0]	auto[0]	auto[0]	92349	1			T5	8		T8	2		T10	5
all_values[0]	auto[0]	auto[1]	3378	1			T19	12		T154	2413		T155	25
all_values[0]	auto[1]	auto[0]	618959	1			T1	2		T2	2		T3	2
all_values[0]	auto[1]	auto[1]	54009	1			T15	9		T19	7		T154	27418
all_values[1]	auto[0]	auto[0]	741268	1			T1	2		T2	2		T3	2
all_values[1]	auto[0]	auto[1]	27011	1			T15	5		T19	15		T155	14306
all_values[1]	auto[1]	auto[0]	260	1			T44	7		T154	1		T280	4
all_values[1]	auto[1]	auto[1]	156	1			T15	3		T19	2		T155	8
all_values[2]	auto[0]	auto[0]	740941	1			T1	2		T2	2		T3	2
all_values[2]	auto[0]	auto[1]	27416	1			T15	6		T19	15		T155	14308
all_values[2]	auto[1]	auto[0]	188	1			T45	1		T166	1		T281	1
all_values[2]	auto[1]	auto[1]	150	1			T15	3		T19	4		T155	10
all_values[3]	auto[0]	auto[0]	741149	1			T1	2		T2	2		T3	2
all_values[3]	auto[0]	auto[1]	27378	1			T15	4		T19	13		T155	14309
all_values[3]	auto[1]	auto[1]	168	1			T15	5		T19	5		T155	8
all_values[4]	auto[0]	auto[0]	711281	1			T1	2		T2	2		T3	2
all_values[4]	auto[0]	auto[1]	57252	1			T15	5		T19	14		T154	29830
all_values[4]	auto[1]	auto[0]	19	1			T24	1		T27	1		T276	1
all_values[4]	auto[1]	auto[1]	143	1			T15	3		T19	3		T154	2
all_values[5]	auto[0]	auto[0]	711315	1			T1	2		T2	2		T3	2
all_values[5]	auto[0]	auto[1]	57217	1			T19	15		T154	29830		T155	14302
all_values[5]	auto[1]	auto[1]	163	1			T19	3		T154	2		T155	16
all_values[6]	auto[0]	auto[0]	716237	1			T1	2		T2	2		T3	2
all_values[6]	auto[0]	auto[1]	52295	1			T15	6		T19	15		T154	29830
all_values[6]	auto[1]	auto[1]	163	1			T15	3		T19	4		T154	1
all_values[7]	auto[0]	auto[0]	686817	1			T1	2		T2	2		T3	2
all_values[7]	auto[0]	auto[1]	55265	1			T15	2		T19	13		T154	29349
all_values[7]	auto[1]	auto[0]	24866	1			T10	4		T14	1		T15	226
all_values[7]	auto[1]	auto[1]	1747	1			T15	7		T19	5		T154	483
all_values[8]	auto[0]	auto[0]	711283	1			T1	2		T2	2		T3	2
all_values[8]	auto[0]	auto[1]	57226	1			T15	6		T19	15		T154	29830
all_values[8]	auto[1]	auto[1]	186	1			T15	1		T19	3		T154	1
all_values[9]	auto[0]	auto[0]	163326	1			T1	2		T2	2		T3	2
all_values[9]	auto[0]	auto[1]	8574	1			T15	6		T19	12		T155	464
all_values[9]	auto[1]	auto[0]	578186	1			T14	1		T15	6279		T29	1
all_values[9]	auto[1]	auto[1]	18609	1			T15	1		T19	7		T155	13853
all_values[10]	auto[0]	auto[0]	711291	1			T1	2		T2	2		T3	2
all_values[10]	auto[0]	auto[1]	57268	1			T15	5		T19	17		T154	29830
all_values[10]	auto[1]	auto[1]	136	1			T15	3		T19	2		T154	2
all_values[11]	auto[0]	auto[0]	2329	1			T5	8		T8	2		T10	5
all_values[11]	auto[0]	auto[1]	279	1			T19	11		T154	20		T155	29
all_values[11]	auto[1]	auto[0]	709364	1			T1	2		T2	2		T3	2
all_values[11]	auto[1]	auto[1]	56723	1			T15	9		T19	7		T154	29812
all_values[12]	auto[0]	auto[0]	711640	1			T1	2		T2	2		T3	2
all_values[12]	auto[0]	auto[1]	56857	1			T15	6		T19	16		T154	29829
all_values[12]	auto[1]	auto[0]	61	1			T281	1		T55	1		T57	1
all_values[12]	auto[1]	auto[1]	137	1			T15	3		T19	2		T154	1
all_values[13]	auto[0]	auto[0]	711324	1			T1	2		T2	2		T3	2
all_values[13]	auto[0]	auto[1]	57220	1			T15	4		T19	15		T154	29830
all_values[13]	auto[1]	auto[1]	151	1			T15	4		T19	4		T154	1
all_values[14]	auto[0]	auto[0]	711705	1			T1	2		T2	2		T3	2
all_values[14]	auto[0]	auto[1]	56827	1			T15	2		T19	12		T154	29832
all_values[14]	auto[1]	auto[1]	163	1			T15	5		T19	3		T155	5