ASSERT | PROPERTIES | SEQUENCES | |
Total | 440 | 0 | 10 |
Category 0 | 440 | 0 | 10 |
ASSERT | PROPERTIES | SEQUENCES | |
Total | 440 | 0 | 10 |
Severity 0 | 440 | 0 | 10 |
NUMBER | PERCENT | |
Total Number | 440 | 100.00 |
Uncovered | 7 | 1.59 |
Success | 433 | 98.41 |
Failure | 0 | 0.00 |
Incomplete | 1 | 0.23 |
Without Attempts | 0 | 0.00 |
NUMBER | PERCENT | |
Total Number | 10 | 100.00 |
Uncovered | 0 | 0.00 |
All Matches | 10 | 100.00 |
First Matches | 10 | 100.00 |
ASSERTIONS | CATEGORY | SEVERITY | ATTEMPTS | REAL SUCCESSES | FAILURES | INCOMPLETE | SRC |
tb.dut.i2c_core.u_fifos.AcqWriteStableBeforeHandshake_A | 0 | 0 | 396971971 | 0 | 0 | 0 | |
tb.dut.i2c_core.u_fifos.FmtWriteStableBeforeHandshake_A | 0 | 0 | 399469038 | 0 | 0 | 0 | |
tb.dut.i2c_core.u_fifos.TxWriteStableBeforeHandshake_A | 0 | 0 | 399469038 | 0 | 0 | 0 | |
tb.dut.i2c_core.u_fifos.u_ram_arbiter.LockArbDecision_A | 0 | 0 | 399469038 | 0 | 0 | 0 | |
tb.dut.i2c_core.u_fifos.u_ram_arbiter.NoReadyValidNoGrant_A | 0 | 0 | 399469038 | 0 | 0 | 0 | |
tb.dut.i2c_core.u_fifos.u_ram_arbiter.ReqStaysHighUntilGranted0_M | 0 | 0 | 399469038 | 0 | 0 | 0 | |
tb.dut.i2c_csr_assert.TlulOOBAddrErr_A | 0 | 0 | 400133860 | 0 | 0 | 0 |
ASSERTIONS | CATEGORY | SEVERITY | ATTEMPTS | REAL SUCCESSES | FAILURES | INCOMPLETE | SRC |
tb.dut.i2c_core.u_fifos.u_ram_arbiter.RoundRobin_A | 0 | 0 | 399469038 | 55 | 0 | 1683 |
COVER SEQUENCES | CATEGORY | SEVERITY | ATTEMPTS | ALL MATCHES | FIRST MATCHES | INCOMPLETE | SRC |
tb.dut.tlul_assert_device.gen_device_cov.aValidNotAccepted_C | 0 | 0 | 400135040 | 187077 | 187077 | 0 | |
tb.dut.tlul_assert_device.gen_device_cov.a_addressChangedNotAccepted_C | 0 | 0 | 400135040 | 127 | 127 | 0 | |
tb.dut.tlul_assert_device.gen_device_cov.a_dataChangedNotAccepted_C | 0 | 0 | 400135040 | 137 | 137 | 0 | |
tb.dut.tlul_assert_device.gen_device_cov.a_maskChangedNotAccepted_C | 0 | 0 | 400135040 | 102 | 102 | 0 | |
tb.dut.tlul_assert_device.gen_device_cov.a_opcodeChangedNotAccepted_C | 0 | 0 | 400135040 | 16 | 16 | 0 | |
tb.dut.tlul_assert_device.gen_device_cov.a_sizeChangedNotAccepted_C | 0 | 0 | 400135040 | 71 | 71 | 0 | |
tb.dut.tlul_assert_device.gen_device_cov.a_sourceChangedNotAccepted_C | 0 | 0 | 400135040 | 52 | 52 | 0 | |
tb.dut.tlul_assert_device.gen_device_cov.b2bReqWithSameAddr_C | 0 | 0 | 400135040 | 5248 | 5248 | 0 | |
tb.dut.tlul_assert_device.gen_device_cov.b2bReq_C | 0 | 0 | 400135040 | 2569890 | 2569890 | 0 | |
tb.dut.tlul_assert_device.gen_device_cov.b2bSameSource_C | 0 | 0 | 400135040 | 17472898 | 17472898 | 1827 |
COVER SEQUENCES | CATEGORY | SEVERITY | ATTEMPTS | ALL MATCHES | FIRST MATCHES | INCOMPLETE | SRC |
tb.dut.tlul_assert_device.gen_device_cov.aValidNotAccepted_C | 0 | 0 | 400135040 | 187077 | 187077 | 0 | |
tb.dut.tlul_assert_device.gen_device_cov.a_addressChangedNotAccepted_C | 0 | 0 | 400135040 | 127 | 127 | 0 | |
tb.dut.tlul_assert_device.gen_device_cov.a_dataChangedNotAccepted_C | 0 | 0 | 400135040 | 137 | 137 | 0 | |
tb.dut.tlul_assert_device.gen_device_cov.a_maskChangedNotAccepted_C | 0 | 0 | 400135040 | 102 | 102 | 0 | |
tb.dut.tlul_assert_device.gen_device_cov.a_opcodeChangedNotAccepted_C | 0 | 0 | 400135040 | 16 | 16 | 0 | |
tb.dut.tlul_assert_device.gen_device_cov.a_sizeChangedNotAccepted_C | 0 | 0 | 400135040 | 71 | 71 | 0 | |
tb.dut.tlul_assert_device.gen_device_cov.a_sourceChangedNotAccepted_C | 0 | 0 | 400135040 | 52 | 52 | 0 | |
tb.dut.tlul_assert_device.gen_device_cov.b2bReqWithSameAddr_C | 0 | 0 | 400135040 | 5248 | 5248 | 0 | |
tb.dut.tlul_assert_device.gen_device_cov.b2bReq_C | 0 | 0 | 400135040 | 2569890 | 2569890 | 0 | |
tb.dut.tlul_assert_device.gen_device_cov.b2bSameSource_C | 0 | 0 | 400135040 | 17472898 | 17472898 | 1827 |
0% | 10% | 20% | 30% | 40% | 50% | 60% | 70% | 80% | 90% | 100% |