Unified Coverage Report :: Group :: cip_base_pkg::intr_pins_cg::SHAPE{(num_interrupts - 1)=14}

Group : cip_base_pkg::intr_pins_cg::SHAPE{(num_interrupts - 1)=14}

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
100.00	1	100	1	64	64

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_dv_cip_lib_0/cip_base_env_cov.sv

---

Summary for Group cip_base_pkg::intr_pins_cg::SHAPE{(num_interrupts - 1)=14}

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	19	0	19	100.00
Crosses	60	0	60	100.00

Variables for Group cip_base_pkg::intr_pins_cg::SHAPE{(num_interrupts - 1)=14}

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
cp_intr_pin	15	0	15	100.00	100	1	1	0
cp_intr_pin_value	4	0	4	100.00	100	1	1	0

Crosses for Group cip_base_pkg::intr_pins_cg::SHAPE{(num_interrupts - 1)=14}

CROSS	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	PRINT MISSING	COMMENT
cp_intr_pins_all_values	60	0	60	100.00	100	1	1	0

Summary for Variable cp_intr_pin

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	15	0	15	100.00

User Defined Bins for cp_intr_pin

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
all_pins[0]	768695	1			T1	2		T2	2		T3	2
all_pins[1]	768695	1			T1	2		T2	2		T3	2
all_pins[2]	768695	1			T1	2		T2	2		T3	2
all_pins[3]	768695	1			T1	2		T2	2		T3	2
all_pins[4]	768695	1			T1	2		T2	2		T3	2
all_pins[5]	768695	1			T1	2		T2	2		T3	2
all_pins[6]	768695	1			T1	2		T2	2		T3	2
all_pins[7]	768695	1			T1	2		T2	2		T3	2
all_pins[8]	768695	1			T1	2		T2	2		T3	2
all_pins[9]	768695	1			T1	2		T2	2		T3	2
all_pins[10]	768695	1			T1	2		T2	2		T3	2
all_pins[11]	768695	1			T1	2		T2	2		T3	2
all_pins[12]	768695	1			T1	2		T2	2		T3	2
all_pins[13]	768695	1			T1	2		T2	2		T3	2
all_pins[14]	768695	1			T1	2		T2	2		T3	2

---

Summary for Variable cp_intr_pin_value

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	4	0	4	100.00

User Defined Bins for cp_intr_pin_value

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
values[0x0]	9471675	1			T1	26		T2	26		T3	26
values[0x1]	2058750	1			T1	4		T2	4		T3	4
transitions[0x0=>0x1]	2058152	1			T1	4		T2	4		T3	4
transitions[0x1=>0x0]	2056845	1			T1	3		T2	3		T3	3

---

Summary for Cross cp_intr_pins_all_values

Samples crossed: cp_intr_pin cp_intr_pin_value

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	60	0	60	100.00

Automatically Generated Cross Bins for cp_intr_pins_all_values

Bins

cp_intr_pin	cp_intr_pin_value	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
all_pins[0]	values[0x0]	99080	1			T5	8		T8	2		T10	5
all_pins[0]	values[0x1]	669615	1			T1	2		T2	2		T3	2
all_pins[0]	transitions[0x0=>0x1]	669282	1			T1	2		T2	2		T3	2
all_pins[0]	transitions[0x1=>0x0]	70	1			T19	1		T155	4		T264	1
all_pins[1]	values[0x0]	768292	1			T1	2		T2	2		T3	2
all_pins[1]	values[0x1]	403	1			T15	2		T44	7		T19	1
all_pins[1]	transitions[0x0=>0x1]	390	1			T15	2		T44	7		T19	1
all_pins[1]	transitions[0x1=>0x0]	111	1			T15	2		T281	1		T19	1
all_pins[2]	values[0x0]	768571	1			T1	2		T2	2		T3	2
all_pins[2]	values[0x1]	124	1			T15	2		T281	1		T19	1
all_pins[2]	transitions[0x0=>0x1]	108	1			T15	1		T281	1		T19	1
all_pins[2]	transitions[0x1=>0x0]	61	1			T15	1		T19	1		T155	1
all_pins[3]	values[0x0]	768618	1			T1	2		T2	2		T3	2
all_pins[3]	values[0x1]	77	1			T15	2		T19	1		T155	2
all_pins[3]	transitions[0x0=>0x1]	59	1			T15	1		T19	1		T155	2
all_pins[3]	transitions[0x1=>0x0]	74	1			T15	2		T19	2		T24	1
all_pins[4]	values[0x0]	768603	1			T1	2		T2	2		T3	2
all_pins[4]	values[0x1]	92	1			T15	3		T19	2		T24	1
all_pins[4]	transitions[0x0=>0x1]	77	1			T15	3		T19	2		T24	1
all_pins[4]	transitions[0x1=>0x0]	54	1			T155	2		T247	2		T285	2
all_pins[5]	values[0x0]	768626	1			T1	2		T2	2		T3	2
all_pins[5]	values[0x1]	69	1			T155	3		T247	4		T285	2
all_pins[5]	transitions[0x0=>0x1]	58	1			T155	2		T247	4		T285	2
all_pins[5]	transitions[0x1=>0x0]	59	1			T15	2		T19	2		T155	5
all_pins[6]	values[0x0]	768625	1			T1	2		T2	2		T3	2
all_pins[6]	values[0x1]	70	1			T15	2		T19	2		T155	6
all_pins[6]	transitions[0x0=>0x1]	47	1			T15	1		T19	1		T155	5
all_pins[6]	transitions[0x1=>0x0]	28927	1			T10	4		T14	1		T15	243
all_pins[7]	values[0x0]	739745	1			T1	2		T2	2		T3	2
all_pins[7]	values[0x1]	28950	1			T10	4		T14	1		T15	244
all_pins[7]	transitions[0x0=>0x1]	28925	1			T10	4		T14	1		T15	244
all_pins[7]	transitions[0x1=>0x0]	63	1			T154	1		T155	4		T247	1
all_pins[8]	values[0x0]	768607	1			T1	2		T2	2		T3	2
all_pins[8]	values[0x1]	88	1			T19	1		T154	1		T155	7
all_pins[8]	transitions[0x0=>0x1]	68	1			T154	1		T155	6		T247	3
all_pins[8]	transitions[0x1=>0x0]	596716	1			T14	1		T15	6280		T29	1
all_pins[9]	values[0x0]	171959	1			T1	2		T2	2		T3	2
all_pins[9]	values[0x1]	596736	1			T14	1		T15	6280		T29	1
all_pins[9]	transitions[0x0=>0x1]	596718	1			T14	1		T15	6280		T29	1
all_pins[9]	transitions[0x1=>0x0]	48	1			T19	2		T154	2		T155	1
all_pins[10]	values[0x0]	768629	1			T1	2		T2	2		T3	2
all_pins[10]	values[0x1]	66	1			T19	2		T154	2		T155	3
all_pins[10]	transitions[0x0=>0x1]	54	1			T19	1		T154	1		T155	2
all_pins[10]	transitions[0x1=>0x0]	762172	1			T1	2		T2	2		T3	2
all_pins[11]	values[0x0]	6511	1			T5	8		T8	2		T10	5
all_pins[11]	values[0x1]	762184	1			T1	2		T2	2		T3	2
all_pins[11]	transitions[0x0=>0x1]	762143	1			T1	2		T2	2		T3	2
all_pins[11]	transitions[0x1=>0x0]	100	1			T19	1		T55	1		T57	1
all_pins[12]	values[0x0]	768554	1			T1	2		T2	2		T3	2
all_pins[12]	values[0x1]	141	1			T15	1		T281	1		T19	2
all_pins[12]	transitions[0x0=>0x1]	125	1			T15	1		T281	1		T19	2
all_pins[12]	transitions[0x1=>0x0]	54	1			T15	2		T154	1		T155	1
all_pins[13]	values[0x0]	768625	1			T1	2		T2	2		T3	2
all_pins[13]	values[0x1]	70	1			T15	2		T154	1		T155	1
all_pins[13]	transitions[0x0=>0x1]	60	1			T15	2		T154	1		T247	3
all_pins[13]	transitions[0x1=>0x0]	55	1			T15	1		T155	4		T120	4
all_pins[14]	values[0x0]	768630	1			T1	2		T2	2		T3	2
all_pins[14]	values[0x1]	65	1			T15	1		T155	5		T120	6
all_pins[14]	transitions[0x0=>0x1]	38	1			T155	4		T120	1		T286	2
all_pins[14]	transitions[0x1=>0x0]	668281	1			T1	1		T2	1		T3	1