Unified Coverage Report :: Group :: cip_base_pkg::intr_test_cg::SHAPE{(num_interrupts - 1)=14}

Group : cip_base_pkg::intr_test_cg::SHAPE{(num_interrupts - 1)=14}

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
100.00	1	100	1	64	64

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_dv_cip_lib_0/cip_base_env_cov.sv

---

Summary for Group cip_base_pkg::intr_test_cg::SHAPE{(num_interrupts - 1)=14}

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	21	0	21	100.00
Crosses	90	0	90	100.00

Variables for Group cip_base_pkg::intr_test_cg::SHAPE{(num_interrupts - 1)=14}

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
cp_intr	15	0	15	100.00	100	1	1	0
cp_intr_en	2	0	2	100.00	100	1	1	2
cp_intr_state	2	0	2	100.00	100	1	1	2
cp_intr_test	2	0	2	100.00	100	1	1	2

Crosses for Group cip_base_pkg::intr_test_cg::SHAPE{(num_interrupts - 1)=14}

CROSS	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	PRINT MISSING	COMMENT
intr_test_cg_cc	90	0	90	100.00	100	1	1	0

Summary for Variable cp_intr

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	15	0	15	100.00

User Defined Bins for cp_intr

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
all_values[0]	374	1			T15	7		T19	7		T154	4
all_values[1]	374	1			T15	7		T19	7		T154	4
all_values[2]	374	1			T15	7		T19	7		T154	4
all_values[3]	374	1			T15	7		T19	7		T154	4
all_values[4]	374	1			T15	7		T19	7		T154	4
all_values[5]	374	1			T15	7		T19	7		T154	4
all_values[6]	374	1			T15	7		T19	7		T154	4
all_values[7]	374	1			T15	7		T19	7		T154	4
all_values[8]	374	1			T15	7		T19	7		T154	4
all_values[9]	374	1			T15	7		T19	7		T154	4
all_values[10]	374	1			T15	7		T19	7		T154	4
all_values[11]	374	1			T15	7		T19	7		T154	4
all_values[12]	374	1			T15	7		T19	7		T154	4
all_values[13]	374	1			T15	7		T19	7		T154	4
all_values[14]	374	1			T15	7		T19	7		T154	4

---

Summary for Variable cp_intr_en

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cp_intr_en

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

3036

1

T15

47

T19

62

T154

26

auto[1]

2574

1

T15

58

T19

43

T154

34

---

Summary for Variable cp_intr_state

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cp_intr_state

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

990

1

T15

17

T19

14

T154

22

auto[1]

4620

1

T15

88

T19

91

T154

38

---

Summary for Variable cp_intr_test

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cp_intr_test

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

3405

1

T15

62

T19

60

T154

43

auto[1]

2205

1

T15

43

T19

45

T154

17

---

Summary for Cross intr_test_cg_cc

Samples crossed: cp_intr cp_intr_test cp_intr_en cp_intr_state

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
TOTAL	90	0	90	100.00
Automatically Generated Cross Bins	90	0	90	100.00
User Defined Cross Bins	0	0	0

Automatically Generated Cross Bins for intr_test_cg_cc

Bins

cp_intr	cp_intr_test	cp_intr_en	cp_intr_state	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
all_values[0]	auto[0]	auto[0]	auto[0]	40	1			T154	1		T155	4		T286	1
all_values[0]	auto[0]	auto[0]	auto[1]	80	1			T15	1		T19	2		T154	1
all_values[0]	auto[0]	auto[1]	auto[0]	26	1			T155	3		T247	1		T285	1
all_values[0]	auto[0]	auto[1]	auto[1]	85	1			T15	3		T19	1		T154	1
all_values[0]	auto[1]	auto[0]	auto[1]	69	1			T19	3		T154	1		T155	1
all_values[0]	auto[1]	auto[1]	auto[1]	74	1			T15	3		T19	1		T155	1
all_values[1]	auto[0]	auto[0]	auto[0]	41	1			T19	2		T155	1		T247	3
all_values[1]	auto[0]	auto[0]	auto[1]	68	1			T15	2		T155	10		T120	6
all_values[1]	auto[0]	auto[1]	auto[0]	34	1			T15	1		T154	4		T155	3
all_values[1]	auto[0]	auto[1]	auto[1]	80	1			T15	1		T19	3		T155	2
all_values[1]	auto[1]	auto[0]	auto[1]	73	1			T19	1		T155	4		T247	1
all_values[1]	auto[1]	auto[1]	auto[1]	78	1			T15	3		T19	1		T155	2
all_values[2]	auto[0]	auto[0]	auto[0]	41	1			T154	1		T287	1		T121	1
all_values[2]	auto[0]	auto[0]	auto[1]	86	1			T15	3		T19	2		T155	9
all_values[2]	auto[0]	auto[1]	auto[0]	19	1			T154	3		T247	1		T285	3
all_values[2]	auto[0]	auto[1]	auto[1]	78	1			T15	1		T19	1		T155	3
all_values[2]	auto[1]	auto[0]	auto[1]	79	1			T15	2		T19	4		T155	8
all_values[2]	auto[1]	auto[1]	auto[1]	71	1			T15	1		T155	2		T247	3
all_values[3]	auto[0]	auto[0]	auto[0]	39	1			T19	1		T154	1		T155	1
all_values[3]	auto[0]	auto[0]	auto[1]	65	1			T15	1		T19	2		T155	7
all_values[3]	auto[0]	auto[1]	auto[0]	39	1			T154	3		T285	1		T120	1
all_values[3]	auto[0]	auto[1]	auto[1]	72	1			T15	2		T155	7		T247	1
all_values[3]	auto[1]	auto[0]	auto[1]	90	1			T15	2		T19	3		T155	3
all_values[3]	auto[1]	auto[1]	auto[1]	69	1			T15	2		T19	1		T155	4
all_values[4]	auto[0]	auto[0]	auto[0]	37	1			T15	1		T19	2		T155	1
all_values[4]	auto[0]	auto[0]	auto[1]	92	1			T19	1		T154	1		T155	7
all_values[4]	auto[0]	auto[1]	auto[0]	22	1			T155	2		T247	1		T288	3
all_values[4]	auto[0]	auto[1]	auto[1]	80	1			T15	3		T19	1		T154	1
all_values[4]	auto[1]	auto[0]	auto[1]	86	1			T15	1		T154	1		T155	2
all_values[4]	auto[1]	auto[1]	auto[1]	57	1			T15	2		T19	3		T154	1
all_values[5]	auto[0]	auto[0]	auto[0]	46	1			T15	2		T19	1		T286	1
all_values[5]	auto[0]	auto[0]	auto[1]	78	1			T19	3		T154	1		T155	10
all_values[5]	auto[0]	auto[1]	auto[0]	25	1			T15	5		T289	2		T290	2
all_values[5]	auto[0]	auto[1]	auto[1]	85	1			T19	1		T155	3		T247	4
all_values[5]	auto[1]	auto[0]	auto[1]	94	1			T19	2		T154	3		T155	7
all_values[5]	auto[1]	auto[1]	auto[1]	46	1			T155	2		T247	2		T285	3
all_values[6]	auto[0]	auto[0]	auto[0]	42	1			T154	1		T155	1		T291	2
all_values[6]	auto[0]	auto[0]	auto[1]	76	1			T15	2		T19	2		T154	2
all_values[6]	auto[0]	auto[1]	auto[0]	33	1			T291	4		T292	1		T124	1
all_values[6]	auto[0]	auto[1]	auto[1]	76	1			T15	3		T19	1		T155	2
all_values[6]	auto[1]	auto[0]	auto[1]	78	1			T19	3		T154	1		T155	7
all_values[6]	auto[1]	auto[1]	auto[1]	69	1			T15	2		T19	1		T155	4
all_values[7]	auto[0]	auto[0]	auto[0]	38	1			T19	1		T247	2		T289	2
all_values[7]	auto[0]	auto[0]	auto[1]	75	1			T15	2		T155	6		T247	1
all_values[7]	auto[0]	auto[1]	auto[0]	21	1			T247	2		T293	1		T294	1
all_values[7]	auto[0]	auto[1]	auto[1]	78	1			T19	4		T154	3		T155	3
all_values[7]	auto[1]	auto[0]	auto[1]	81	1			T15	2		T19	1		T154	1
all_values[7]	auto[1]	auto[1]	auto[1]	81	1			T15	3		T19	1		T155	5
all_values[8]	auto[0]	auto[0]	auto[0]	32	1			T15	1		T19	1		T155	2
all_values[8]	auto[0]	auto[0]	auto[1]	91	1			T15	2		T19	1		T154	1
all_values[8]	auto[0]	auto[1]	auto[0]	12	1			T15	1		T154	1		T285	1
all_values[8]	auto[0]	auto[1]	auto[1]	78	1			T15	1		T19	1		T155	9
all_values[8]	auto[1]	auto[0]	auto[1]	90	1			T15	1		T19	3		T155	3
all_values[8]	auto[1]	auto[1]	auto[1]	71	1			T15	1		T19	1		T154	2
all_values[9]	auto[0]	auto[0]	auto[0]	39	1			T15	1		T154	3		T155	1
all_values[9]	auto[0]	auto[0]	auto[1]	80	1			T15	3		T19	3		T155	9
all_values[9]	auto[0]	auto[1]	auto[0]	20	1			T15	1		T154	1		T247	2
all_values[9]	auto[0]	auto[1]	auto[1]	88	1			T19	1		T155	5		T285	2
all_values[9]	auto[1]	auto[0]	auto[1]	84	1			T19	2		T155	3		T247	1
all_values[9]	auto[1]	auto[1]	auto[1]	63	1			T15	2		T19	1		T155	4
all_values[10]	auto[0]	auto[0]	auto[0]	38	1			T15	1		T155	2		T291	1
all_values[10]	auto[0]	auto[0]	auto[1]	104	1			T19	2		T155	2		T247	3
all_values[10]	auto[0]	auto[1]	auto[0]	13	1			T120	1		T295	1		T122	1
all_values[10]	auto[0]	auto[1]	auto[1]	83	1			T15	3		T19	3		T154	2
all_values[10]	auto[1]	auto[0]	auto[1]	81	1			T15	3		T155	3		T247	2
all_values[10]	auto[1]	auto[1]	auto[1]	55	1			T19	2		T154	2		T155	3
all_values[11]	auto[0]	auto[0]	auto[0]	46	1			T19	1		T247	7		T286	1
all_values[11]	auto[0]	auto[0]	auto[1]	76	1			T15	2		T154	1		T155	3
all_values[11]	auto[0]	auto[1]	auto[0]	20	1			T247	2		T120	1		T293	1
all_values[11]	auto[0]	auto[1]	auto[1]	90	1			T15	2		T19	2		T154	1
all_values[11]	auto[1]	auto[0]	auto[1]	76	1			T19	2		T154	1		T155	2
all_values[11]	auto[1]	auto[1]	auto[1]	66	1			T15	3		T19	2		T154	1
all_values[12]	auto[0]	auto[0]	auto[0]	37	1			T154	1		T247	1		T291	1
all_values[12]	auto[0]	auto[0]	auto[1]	76	1			T15	1		T19	1		T155	5
all_values[12]	auto[0]	auto[1]	auto[0]	35	1			T19	1		T154	1		T247	3
all_values[12]	auto[0]	auto[1]	auto[1]	89	1			T15	3		T19	3		T154	1
all_values[12]	auto[1]	auto[0]	auto[1]	75	1			T15	2		T154	1		T155	3
all_values[12]	auto[1]	auto[1]	auto[1]	62	1			T15	1		T19	2		T155	7
all_values[13]	auto[0]	auto[0]	auto[0]	40	1			T15	1		T154	1		T155	1
all_values[13]	auto[0]	auto[0]	auto[1]	77	1			T15	1		T19	3		T155	9
all_values[13]	auto[0]	auto[1]	auto[0]	38	1			T285	2		T120	2		T295	1
all_values[13]	auto[0]	auto[1]	auto[1]	72	1			T15	1		T19	1		T154	2
all_values[13]	auto[1]	auto[0]	auto[1]	82	1			T15	3		T19	3		T155	5
all_values[13]	auto[1]	auto[1]	auto[1]	65	1			T15	1		T154	1		T155	2
all_values[14]	auto[0]	auto[0]	auto[0]	48	1			T15	1		T19	1		T247	4
all_values[14]	auto[0]	auto[0]	auto[1]	85	1			T15	2		T19	1		T155	8
all_values[14]	auto[0]	auto[1]	auto[0]	29	1			T15	1		T19	3		T247	1
all_values[14]	auto[0]	auto[1]	auto[1]	72	1			T154	3		T155	6		T291	1
all_values[14]	auto[1]	auto[0]	auto[1]	85	1			T15	1		T19	2		T154	1
all_values[14]	auto[1]	auto[1]	auto[1]	55	1			T15	2		T155	4		T285	1

User Defined Cross Bins for intr_test_cg_cc

Excluded/Illegal bins

NAME	COUNT	STATUS
test_1_state_0	0	Illegal