Unified Coverage Report :: Group :: tl_agent_pkg::tl_a_chan_cov_cg::SHAPE{(2 << ((valid_source_width - 1) - 1))=128}

Group : tl_agent_pkg::tl_a_chan_cov_cg::SHAPE{(2 << ((valid_source_width - 1) - 1))=128}

SCORE	INSTANCES	WEIGHT	GOAL	AT LEAST	PER INSTANCE	AUTO BIN MAX	PRINT MISSING
100.00	100.00	1	100	1	1	64	64

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_dv_tl_agent_0/tl_agent_cov.sv

1 Instances:

NAME	SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
tl_agent_pkg.uvm_test_top.env.m_tl_agent_i2c_reg_block.cov::m_tl_a_chan_cov_cg	100.00	1	100	1	64	64

---

Group Instance : tl_agent_pkg.uvm_test_top.env.m_tl_agent_i2c_reg_block.cov::m_tl_a_chan_cov_cg

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
100.00	1	100	1	64	64

---

Summary for Group Instance tl_agent_pkg.uvm_test_top.env.m_tl_agent_i2c_reg_block.cov::m_tl_a_chan_cov_cg

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	134	0	134	100.00
Crosses	3	0	3	100.00

Variables for Group Instance tl_agent_pkg.uvm_test_top.env.m_tl_agent_i2c_reg_block.cov::m_tl_a_chan_cov_cg

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
cp_mask	1	0	1	100.00	100	1	1	0
cp_opcode	3	0	3	100.00	100	1	1	0
cp_size	1	0	1	100.00	100	1	1	0
cp_source	129	0	129	100.00	100	1	1	0

Crosses for Group Instance tl_agent_pkg.uvm_test_top.env.m_tl_agent_i2c_reg_block.cov::m_tl_a_chan_cov_cg

CROSS	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	PRINT MISSING	COMMENT
tl_a_chan_cov_cg_cc	3	0	3	100.00	100	1	1	0

Summary for Variable cp_mask

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	1	0	1	100.00

User Defined Bins for cp_mask

Excluded/Illegal bins

NAME	COUNT	STATUS
others	25887797	Excluded

Covered bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

all_enables

6921119

1

T1

462

T2

39

T3

45515

---

Summary for Variable cp_opcode

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	3	0	3	100.00

User Defined Bins for cp_opcode

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
values[0x4]	32014375	1			T1	1185		T2	21		T3	244296
values[0x0]	396517	1			T1	297		T2	38		T3	5043
values[0x1]	398024	1			T1	345		T2	45		T3	4812

---

Summary for Variable cp_size

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	1	0	1	100.00

User Defined Bins for cp_size

Excluded/Illegal bins

NAME	COUNT	STATUS
others	18077635	Excluded

Covered bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

biggest_size

14731281

1

T1

853

T2

58

T3

108629

---

Summary for Variable cp_source

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	129	0	129	100.00

User Defined Bins for cp_source

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
valid_sources[0x00]	143241	1			T1	4		T3	1020		T7	12
valid_sources[0x01]	117354	1			T1	12		T3	824		T7	14
valid_sources[0x02]	113670	1			T1	2		T3	1165		T5	1
valid_sources[0x03]	129305	1			T1	3		T3	913		T7	10
valid_sources[0x04]	126708	1			T1	10		T2	1		T3	825
valid_sources[0x05]	133760	1			T1	11		T3	1144		T5	1
valid_sources[0x06]	121993	1			T1	8		T3	1093		T5	3
valid_sources[0x07]	134917	1			T1	9		T3	986		T5	3
valid_sources[0x08]	131162	1			T1	2		T3	1084		T5	1
valid_sources[0x09]	129760	1			T1	5		T3	824		T6	3
valid_sources[0x0a]	157039	1			T1	10		T2	1		T3	876
valid_sources[0x0b]	131505	1			T1	9		T2	1		T3	831
valid_sources[0x0c]	128242	1			T1	2		T3	919		T7	13
valid_sources[0x0d]	130127	1			T1	6		T3	841		T5	1
valid_sources[0x0e]	152949	1			T1	8		T3	1256		T5	1
valid_sources[0x0f]	115800	1			T1	11		T3	851		T5	1
valid_sources[0x10]	137471	1			T1	7		T2	1		T3	766
valid_sources[0x11]	122515	1			T1	2		T2	1		T3	1189
valid_sources[0x12]	141751	1			T1	8		T3	791		T5	1
valid_sources[0x13]	128246	1			T1	8		T2	1		T3	1109
valid_sources[0x14]	144933	1			T1	11		T3	940		T7	16
valid_sources[0x15]	126948	1			T1	4		T3	974		T5	4
valid_sources[0x16]	141107	1			T1	3		T3	1244		T7	15
valid_sources[0x17]	126079	1			T1	9		T3	1022		T5	1
valid_sources[0x18]	119284	1			T1	10		T2	2		T3	955
valid_sources[0x19]	128914	1			T2	1		T3	1078		T5	1
valid_sources[0x1a]	131325	1			T1	6		T2	1		T3	1351
valid_sources[0x1b]	132953	1			T1	5		T3	1220		T6	40
valid_sources[0x1c]	109213	1			T1	17		T3	852		T5	2
valid_sources[0x1d]	143604	1			T1	10		T2	1		T3	974
valid_sources[0x1e]	140725	1			T1	10		T2	1		T3	1068
valid_sources[0x1f]	129773	1			T1	10		T2	1		T3	1003
valid_sources[0x20]	136978	1			T1	3		T2	1		T3	1114
valid_sources[0x21]	129241	1			T1	14		T3	1117		T5	1
valid_sources[0x22]	127953	1			T1	2		T3	809		T6	7
valid_sources[0x23]	125841	1			T3	741		T5	2		T6	8
valid_sources[0x24]	117292	1			T1	2		T2	1		T3	697
valid_sources[0x25]	124194	1			T1	11		T3	757		T5	4
valid_sources[0x26]	136940	1			T1	3		T3	757		T5	1
valid_sources[0x27]	115206	1			T1	12		T3	1139		T5	1
valid_sources[0x28]	128034	1			T1	1		T3	924		T6	30
valid_sources[0x29]	122621	1			T1	2		T3	1072		T5	1
valid_sources[0x2a]	140055	1			T1	6		T3	1211		T6	12
valid_sources[0x2b]	128311	1			T1	16		T2	2		T3	1025
valid_sources[0x2c]	120114	1			T1	10		T3	962		T7	13
valid_sources[0x2d]	137449	1			T1	1		T3	1021		T5	3
valid_sources[0x2e]	124588	1			T1	9		T2	1		T3	1079
valid_sources[0x2f]	122867	1			T1	5		T3	953		T6	3
valid_sources[0x30]	113311	1			T1	19		T2	2		T3	951
valid_sources[0x31]	118606	1			T1	12		T2	1		T3	1164
valid_sources[0x32]	128462	1			T1	7		T3	1194		T7	15
valid_sources[0x33]	117981	1			T1	9		T2	1		T3	1103
valid_sources[0x34]	129401	1			T1	13		T3	953		T6	6
valid_sources[0x35]	133697	1			T1	3		T2	1		T3	1088
valid_sources[0x36]	123823	1			T1	4		T2	1		T3	973
valid_sources[0x37]	120722	1			T1	3		T3	899		T6	6
valid_sources[0x38]	114101	1			T1	5		T2	1		T3	1146
valid_sources[0x39]	146950	1			T1	17		T3	804		T7	9
valid_sources[0x3a]	114448	1			T1	11		T3	769		T5	1
valid_sources[0x3b]	142995	1			T1	7		T3	952		T5	1
valid_sources[0x3c]	112829	1			T1	3		T2	1		T3	878
valid_sources[0x3d]	133680	1			T1	2		T3	845		T5	1
valid_sources[0x3e]	134855	1			T1	9		T3	748		T6	1
valid_sources[0x3f]	113538	1			T1	10		T2	1		T3	865
valid_sources[0x40]	143521	1			T1	9		T3	811		T5	2
valid_sources[0x41]	127853	1			T1	3		T3	980		T6	33
valid_sources[0x42]	118153	1			T1	3		T2	1		T3	1136
valid_sources[0x43]	129117	1			T1	11		T3	1277		T5	3
valid_sources[0x44]	135251	1			T1	6		T3	1005		T5	1
valid_sources[0x45]	134683	1			T1	5		T3	721		T5	2
valid_sources[0x46]	162744	1			T1	2		T2	1		T3	750
valid_sources[0x47]	128805	1			T1	2		T3	1065		T5	2
valid_sources[0x48]	126957	1			T1	2		T3	1004		T6	17
valid_sources[0x49]	110647	1			T1	4		T3	883		T5	1
valid_sources[0x4a]	130418	1			T1	7		T3	759		T5	1
valid_sources[0x4b]	134386	1			T1	9		T3	739		T5	1
valid_sources[0x4c]	129928	1			T1	14		T3	939		T7	11
valid_sources[0x4d]	125725	1			T1	2		T3	1158		T7	16
valid_sources[0x4e]	131335	1			T1	12		T3	835		T7	13
valid_sources[0x4f]	114343	1			T1	8		T2	2		T3	1093
valid_sources[0x50]	148707	1			T1	2		T3	950		T5	2
valid_sources[0x51]	141038	1			T1	14		T2	1		T3	1199
valid_sources[0x52]	135176	1			T1	4		T2	1		T3	874
valid_sources[0x53]	121045	1			T1	3		T3	865		T5	2
valid_sources[0x54]	114889	1			T1	7		T3	1285		T6	17
valid_sources[0x55]	119694	1			T1	5		T3	737		T6	16
valid_sources[0x56]	107570	1			T1	6		T3	767		T6	3
valid_sources[0x57]	143164	1			T1	10		T2	1		T3	1065
valid_sources[0x58]	140706	1			T1	3		T3	749		T5	3
valid_sources[0x59]	120818	1			T1	8		T3	1131		T5	1
valid_sources[0x5a]	137142	1			T1	1		T2	1		T3	1217
valid_sources[0x5b]	129085	1			T1	4		T3	1062		T5	1
valid_sources[0x5c]	138921	1			T1	19		T2	1		T3	1034
valid_sources[0x5d]	112544	1			T1	13		T3	923		T6	15
valid_sources[0x5e]	140042	1			T1	5		T2	1		T3	983
valid_sources[0x5f]	127257	1			T2	1		T3	1003		T6	16
valid_sources[0x60]	122909	1			T3	1045		T5	1		T7	15
valid_sources[0x61]	180207	1			T1	3		T3	1018		T5	1
valid_sources[0x62]	129570	1			T1	10		T3	1471		T5	1
valid_sources[0x63]	135360	1			T1	9		T3	1243		T5	4
valid_sources[0x64]	125468	1			T1	9		T3	1135		T7	6
valid_sources[0x65]	128573	1			T1	10		T3	1192		T5	3
valid_sources[0x66]	123761	1			T1	4		T3	1036		T7	16
valid_sources[0x67]	131126	1			T1	6		T3	906		T5	2
valid_sources[0x68]	127549	1			T1	14		T3	1040		T5	1
valid_sources[0x69]	122602	1			T1	10		T3	902		T5	1
valid_sources[0x6a]	119817	1			T1	13		T3	1385		T5	1
valid_sources[0x6b]	126367	1			T1	7		T3	1120		T5	1
valid_sources[0x6c]	135467	1			T1	9		T3	810		T5	1
valid_sources[0x6d]	137866	1			T1	12		T3	1050		T6	20
valid_sources[0x6e]	132111	1			T1	11		T2	2		T3	1186
valid_sources[0x6f]	110394	1			T1	6		T3	860		T5	4
valid_sources[0x70]	131256	1			T1	4		T2	1		T3	881
valid_sources[0x71]	145980	1			T1	4		T2	1		T3	910
valid_sources[0x72]	120588	1			T1	10		T2	1		T3	1086
valid_sources[0x73]	118983	1			T1	7		T3	888		T6	9
valid_sources[0x74]	133867	1			T1	6		T3	1238		T5	3
valid_sources[0x75]	140205	1			T1	7		T3	965		T5	4
valid_sources[0x76]	119207	1			T1	7		T2	1		T3	953
valid_sources[0x77]	119708	1			T1	5		T3	1097		T6	15
valid_sources[0x78]	121339	1			T1	9		T2	1		T3	878
valid_sources[0x79]	119879	1			T1	3		T2	1		T3	929
valid_sources[0x7a]	149076	1			T1	10		T3	908		T5	1
valid_sources[0x7b]	126914	1			T1	4		T2	1		T3	1213
valid_sources[0x7c]	125753	1			T1	16		T2	1		T3	1475
valid_sources[0x7d]	123629	1			T1	3		T3	1018		T6	1
valid_sources[0x7e]	125320	1			T1	8		T3	844		T6	15
valid_sources[0x7f]	158504	1			T1	6		T3	964		T6	2
valid_sources[0x80]	111690	1			T1	6		T3	1140		T5	2

---

Summary for Cross tl_a_chan_cov_cg_cc

Samples crossed: cp_opcode cp_mask cp_size

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	3	0	3	100.00

Automatically Generated Cross Bins for tl_a_chan_cov_cg_cc

Bins

cp_opcode

cp_mask

cp_size

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

values[0x4]

all_enables

biggest_size

6563717

1

T1

247

T2

2

T3

41184

values[0x0]

all_enables

biggest_size

211270

1

T1

120

T2

21

T3

2673

values[0x1]

all_enables

biggest_size

146132

1

T1

95

T2

16

T3

1658