Unified Coverage Report :: Module :: i2c_csr_assert_fpv

Module : i2c_csr_assert_fpv

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
93.75						93.75

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_fpv_i2c_csr_assert_0/i2c_csr_assert_fpv.sv

Module self-instances :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
tb.dut.i2c_csr_assert	93.75						93.75

---

Module Instance : tb.dut.i2c_csr_assert

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
93.75						93.75

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
93.75						93.75

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
98.48	100.00	100.00	93.91			100.00	dut

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Since this is the module's only instance, the coverage report is the same as for the module.

Assert Coverage for Module : i2c_csr_assert_fpv

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	16	16	100.00	15	93.75
Cover properties	0	0		0
Cover sequences	0	0		0
Total	16	16	100.00	15	93.75

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
TlulOOBAddrErr_A	376361383	0	0	0
ctrl_rd_A	376361383	2918	0	0
host_fifo_config_rd_A	376361383	3881	0	0
host_nack_handler_timeout_rd_A	376361383	1614	0	0
host_timeout_ctrl_rd_A	376361383	1364	0	0
intr_enable_rd_A	376361383	4886	0	0
ovrd_rd_A	376361383	2143	0	0
target_fifo_config_rd_A	376361383	1777	0	0
target_id_rd_A	376361383	1886	0	0
target_timeout_ctrl_rd_A	376361383	1395	0	0
timeout_ctrl_rd_A	376361383	1703	0	0
timing0_rd_A	376361383	1734	0	0
timing1_rd_A	376361383	1501	0	0
timing2_rd_A	376361383	1721	0	0
timing3_rd_A	376361383	1632	0	0
timing4_rd_A	376361383	1545	0	0

TlulOOBAddrErr_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	376361383	0	0	0

ctrl_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	376361383	2918	0	0
T90	3624	12	0	0
T91	16283	61	0	0
T92	3620	32	0	0
T93	1751	7	0	0
T94	1550	11	0	0
T95	3743	47	0	0
T96	6837	117	0	0
T97	5882	81	0	0
T98	7529	124	0	0
T99	3940	44	0	0

host_fifo_config_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	376361383	3881	0	0
T21	27267	0	0	0
T26	414179	181	0	0
T38	162073	0	0	0
T40	23262	0	0	0
T42	12518	0	0	0
T46	55889	0	0	0
T49	128940	0	0	0
T55	81478	0	0	0
T65	807963	0	0	0
T75	0	154	0	0
T88	6353	0	0	0
T100	0	136	0	0
T101	0	234	0	0
T102	0	84	0	0
T103	0	124	0	0
T104	0	101	0	0
T105	0	221	0	0
T106	0	78	0	0
T107	0	257	0	0

host_nack_handler_timeout_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	376361383	1614	0	0
T90	3624	11	0	0
T91	16283	25	0	0
T92	3620	8	0	0
T93	1751	9	0	0
T94	1550	14	0	0
T95	3743	12	0	0
T96	6837	76	0	0
T97	5882	34	0	0
T98	7529	73	0	0
T99	3940	32	0	0

host_timeout_ctrl_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	376361383	1364	0	0
T90	3624	15	0	0
T91	16283	31	0	0
T92	3620	5	0	0
T94	1550	3	0	0
T95	3743	21	0	0
T96	6837	20	0	0
T97	5882	56	0	0
T98	7529	38	0	0
T99	3940	23	0	0
T108	17040	29	0	0

intr_enable_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	376361383	4886	0	0
T77	83817	0	0	0
T90	0	95	0	0
T91	0	38	0	0
T92	0	25	0	0
T94	0	9	0	0
T109	622054	18	0	0
T110	0	14	0	0
T111	0	7	0	0
T112	0	17	0	0
T113	0	12	0	0
T114	0	3	0	0
T115	55840	0	0	0
T116	477025	0	0	0
T117	122263	0	0	0
T118	1879	0	0	0
T119	39266	0	0	0
T120	7067	0	0	0
T121	180388	0	0	0
T122	39607	0	0	0

ovrd_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	376361383	2143	0	0
T11	15397	0	0	0
T12	10359	0	0	0
T50	735697	0	0	0
T74	0	54	0	0
T87	1213	24	0	0
T123	0	26	0	0
T124	0	45	0	0
T125	0	44	0	0
T126	0	26	0	0
T127	0	36	0	0
T128	0	35	0	0
T129	0	54	0	0
T130	0	48	0	0
T131	55504	0	0	0
T132	63923	0	0	0
T133	19570	0	0	0
T134	32434	0	0	0
T135	76526	0	0	0
T136	104997	0	0	0

target_fifo_config_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	376361383	1777	0	0
T90	3624	20	0	0
T91	16283	44	0	0
T92	3620	20	0	0
T93	1751	3	0	0
T94	1550	13	0	0
T95	3743	22	0	0
T96	6837	58	0	0
T97	5882	59	0	0
T98	7529	78	0	0
T99	3940	55	0	0

target_id_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	376361383	1886	0	0
T90	3624	2	0	0
T91	16283	23	0	0
T92	3620	1	0	0
T93	1751	2	0	0
T94	1550	23	0	0
T95	3743	33	0	0
T96	6837	104	0	0
T97	5882	21	0	0
T98	7529	111	0	0
T99	3940	37	0	0

target_timeout_ctrl_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	376361383	1395	0	0
T90	3624	16	0	0
T91	16283	58	0	0
T92	3620	9	0	0
T93	1751	3	0	0
T94	1550	8	0	0
T95	3743	23	0	0
T96	6837	69	0	0
T97	5882	36	0	0
T98	7529	40	0	0
T99	3940	20	0	0

timeout_ctrl_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	376361383	1703	0	0
T90	3624	9	0	0
T91	16283	31	0	0
T92	3620	1	0	0
T93	1751	5	0	0
T94	1550	15	0	0
T95	3743	25	0	0
T96	6837	45	0	0
T97	5882	29	0	0
T98	7529	104	0	0
T99	3940	33	0	0

timing0_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	376361383	1734	0	0
T90	3624	3	0	0
T91	16283	76	0	0
T92	3620	19	0	0
T93	1751	5	0	0
T94	1550	10	0	0
T95	3743	26	0	0
T96	6837	57	0	0
T97	5882	51	0	0
T98	7529	55	0	0
T99	3940	5	0	0

timing1_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	376361383	1501	0	0
T90	3624	20	0	0
T91	16283	31	0	0
T92	3620	22	0	0
T94	1550	8	0	0
T95	3743	15	0	0
T96	6837	40	0	0
T97	5882	28	0	0
T98	7529	64	0	0
T99	3940	35	0	0
T108	17040	70	0	0

timing2_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	376361383	1721	0	0
T90	3624	7	0	0
T91	16283	41	0	0
T92	3620	22	0	0
T93	1751	6	0	0
T94	1550	1	0	0
T95	3743	27	0	0
T96	6837	35	0	0
T97	5882	39	0	0
T98	7529	76	0	0
T99	3940	25	0	0

timing3_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	376361383	1632	0	0
T90	3624	9	0	0
T91	16283	30	0	0
T92	3620	12	0	0
T94	1550	8	0	0
T95	3743	23	0	0
T96	6837	68	0	0
T97	5882	39	0	0
T98	7529	37	0	0
T99	3940	34	0	0
T108	17040	63	0	0

timing4_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	376361383	1545	0	0
T91	16283	49	0	0
T92	3620	14	0	0
T93	1751	1	0	0
T94	1550	6	0	0
T95	3743	16	0	0
T96	6837	53	0	0
T97	5882	58	0	0
T98	7529	50	0	0
T99	3940	2	0	0
T108	17040	63	0	0