Unified Coverage Report :: Group :: i2c_env_pkg::i2c_interrupts_cg

Group : i2c_env_pkg::i2c_interrupts_cg

SCORE	INSTANCES	WEIGHT	GOAL	AT LEAST	PER INSTANCE	AUTO BIN MAX	PRINT MISSING
100.00	100.00	1	100	1	1	64	64

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_dv_i2c_env_0.1/i2c_env_cov.sv

1 Instances:

NAME	SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
i2c_env_pkg.interrupts_cg	100.00	1	100	1	64	64

---

Group Instance : i2c_env_pkg.interrupts_cg

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
100.00	1	100	1	64	64

---

Summary for Group Instance i2c_env_pkg.interrupts_cg

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	45	0	45	100.00

Variables for Group Instance i2c_env_pkg.interrupts_cg

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
cp_acq_stretch	2	0	2	100.00	100	1	1	2
cp_acq_stretch_test	1	0	1	100.00	100	1	1	2
cp_acq_threshold	2	0	2	100.00	100	1	1	2
cp_acq_threshold_test	1	0	1	100.00	100	1	1	2
cp_cmd_complete	2	0	2	100.00	100	1	1	2
cp_cmd_complete_test	1	0	1	100.00	100	1	1	2
cp_fmt_threshold	2	0	2	100.00	100	1	1	2
cp_fmt_threshold_test	1	0	1	100.00	100	1	1	2
cp_host_timeout	2	0	2	100.00	100	1	1	2
cp_host_timeout_test	1	0	1	100.00	100	1	1	2
cp_nak	2	0	2	100.00	100	1	1	2
cp_nak_test	1	0	1	100.00	100	1	1	2
cp_rx_overflow	2	0	2	100.00	100	1	1	2
cp_rx_overflow_test	1	0	1	100.00	100	1	1	2
cp_rx_threshold	2	0	2	100.00	100	1	1	2
cp_rx_threshold_test	1	0	1	100.00	100	1	1	2
cp_scl_interference	2	0	2	100.00	100	1	1	2
cp_scl_interference_test	1	0	1	100.00	100	1	1	2
cp_sda_interference	2	0	2	100.00	100	1	1	2
cp_sda_interference_test	1	0	1	100.00	100	1	1	2
cp_sda_unstable	2	0	2	100.00	100	1	1	2
cp_sda_unstable_test	1	0	1	100.00	100	1	1	2
cp_stretch_timeout	2	0	2	100.00	100	1	1	2
cp_stretch_timeout_test	1	0	1	100.00	100	1	1	2
cp_tx_stretch	2	0	2	100.00	100	1	1	2
cp_tx_stretch_test	1	0	1	100.00	100	1	1	2
cp_tx_threshold	2	0	2	100.00	100	1	1	2
cp_tx_threshold_test	1	0	1	100.00	100	1	1	2
cp_unexp_stop	2	0	2	100.00	100	1	1	2
cp_unexp_stop_test	1	0	1	100.00	100	1	1	2

Summary for Variable cp_acq_stretch

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cp_acq_stretch

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

727467

1

T1

3

T2

68

T3

3

auto[1]

376

1

T53

1

T55

1

T71

1

---

Summary for Variable cp_acq_stretch_test

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	1	0	1	100.00

Automatically Generated Bins for cp_acq_stretch_test

Excluded/Illegal bins

NAME	COUNT	STATUS
dis	0	Excluded
[auto[0]]	0	Excluded

Covered bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[1]

133

1

T182

3

T180

3

T32

3

---

Summary for Variable cp_acq_threshold

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cp_acq_threshold

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

727179

1

T1

3

T2

68

T3

3

auto[1]

391

1

T162

1

T282

1

T283

1

---

Summary for Variable cp_acq_threshold_test

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	1	0	1	100.00

Automatically Generated Bins for cp_acq_threshold_test

Excluded/Illegal bins

NAME	COUNT	STATUS
dis	0	Excluded
[auto[0]]	0	Excluded

Covered bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[1]

141

1

T182

2

T180

4

T32

2

---

Summary for Variable cp_cmd_complete

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cp_cmd_complete

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

168438

1

T1

3

T2

63

T3

3

auto[1]

559576

1

T2

5

T5

1

T8

1

---

Summary for Variable cp_cmd_complete_test

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	1	0	1	100.00

Automatically Generated Bins for cp_cmd_complete_test

Excluded/Illegal bins

NAME	COUNT	STATUS
dis	0	Excluded
[auto[0]]	0	Excluded

Covered bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[1]

138

1

T182

1

T180

2

T32

3

---

Summary for Variable cp_fmt_threshold

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cp_fmt_threshold

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

90062

1

T1

1

T2

2

T3

1

auto[1]

633774

1

T1

2

T3

2

T4

1

---

Summary for Variable cp_fmt_threshold_test

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	1	0	1	100.00

Automatically Generated Bins for cp_fmt_threshold_test

Excluded/Illegal bins

NAME	COUNT	STATUS
dis	0	Excluded
[auto[0]]	0	Excluded

Covered bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[1]

139

1

T182

2

T180

1

T32

2

---

Summary for Variable cp_host_timeout

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cp_host_timeout

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

727534

1

T1

3

T2

68

T3

3

auto[1]

331

1

T182

5

T180

6

T32

13

---

Summary for Variable cp_host_timeout_test

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	1	0	1	100.00

Automatically Generated Bins for cp_host_timeout_test

Excluded/Illegal bins

NAME	COUNT	STATUS
dis	0	Excluded
[auto[0]]	0	Excluded

Covered bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[1]

141

1

T182

2

T180

1

T32

4

---

Summary for Variable cp_nak

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cp_nak

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

727626

1

T1

3

T2

68

T3

3

auto[1]

333

1

T268

1

T182

4

T180

19

---

Summary for Variable cp_nak_test

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	1	0	1	100.00

Automatically Generated Bins for cp_nak_test

Excluded/Illegal bins

NAME	COUNT	STATUS
dis	0	Excluded
[auto[0]]	0	Excluded

Covered bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[1]

136

1

T182

3

T180

5

T32

2

---

Summary for Variable cp_rx_overflow

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cp_rx_overflow

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

727354

1

T1

3

T2

68

T3

3

auto[1]

284

1

T180

7

T181

1

T116

17

---

Summary for Variable cp_rx_overflow_test

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	1	0	1	100.00

Automatically Generated Bins for cp_rx_overflow_test

Excluded/Illegal bins

NAME	COUNT	STATUS
dis	0	Excluded
[auto[0]]	0	Excluded

Covered bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[1]

128

1

T182

2

T180

2

T32

3

---

Summary for Variable cp_rx_threshold

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cp_rx_threshold

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

727043

1

T1

3

T2

68

T3

3

auto[1]

593

1

T276

1

T277

26

T278

1

---

Summary for Variable cp_rx_threshold_test

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	1	0	1	100.00

Automatically Generated Bins for cp_rx_threshold_test

Excluded/Illegal bins

NAME	COUNT	STATUS
dis	0	Excluded
[auto[0]]	0	Excluded

Covered bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[1]

141

1

T182

1

T180

3

T32

4

---

Summary for Variable cp_scl_interference

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cp_scl_interference

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

723664

1

T1

3

T2

2

T3

3

auto[1]

381

1

T32

11

T181

9

T116

11

---

Summary for Variable cp_scl_interference_test

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	1	0	1	100.00

Automatically Generated Bins for cp_scl_interference_test

Excluded/Illegal bins

NAME	COUNT	STATUS
dis	0	Excluded
[auto[0]]	0	Excluded

Covered bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[1]

142

1

T180

3

T32

5

T181

4

---

Summary for Variable cp_sda_interference

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cp_sda_interference

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

723681

1

T1

3

T2

2

T3

3

auto[1]

310

1

T180

1

T32

14

T181

12

---

Summary for Variable cp_sda_interference_test

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	1	0	1	100.00

Automatically Generated Bins for cp_sda_interference_test

Excluded/Illegal bins

NAME	COUNT	STATUS
dis	0	Excluded
[auto[0]]	0	Excluded

Covered bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[1]

137

1

T182

1

T180

1

T32

3

---

Summary for Variable cp_sda_unstable

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cp_sda_unstable

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

723689

1

T1

3

T2

2

T3

3

auto[1]

346

1

T180

6

T32

7

T181

16

---

Summary for Variable cp_sda_unstable_test

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	1	0	1	100.00

Automatically Generated Bins for cp_sda_unstable_test

Excluded/Illegal bins

NAME	COUNT	STATUS
dis	0	Excluded
[auto[0]]	0	Excluded

Covered bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[1]

141

1

T180

3

T32

3

T181

4

---

Summary for Variable cp_stretch_timeout

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cp_stretch_timeout

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

696691

1

T1

3

T2

2

T3

3

auto[1]

27313

1

T5

1

T8

1

T9

1

---

Summary for Variable cp_stretch_timeout_test

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	1	0	1	100.00

Automatically Generated Bins for cp_stretch_timeout_test

Excluded/Illegal bins

NAME	COUNT	STATUS
dis	0	Excluded
[auto[0]]	0	Excluded

Covered bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[1]

149

1

T182

2

T180

3

T32

4

---

Summary for Variable cp_tx_stretch

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cp_tx_stretch

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

727540

1

T1

3

T2

68

T3

3

auto[1]

340

1

T182

5

T180

18

T32

13

---

Summary for Variable cp_tx_stretch_test

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	1	0	1	100.00

Automatically Generated Bins for cp_tx_stretch_test

Excluded/Illegal bins

NAME	COUNT	STATUS
dis	0	Excluded
[auto[0]]	0	Excluded

Covered bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[1]

134

1

T182

1

T180

4

T32

3

---

Summary for Variable cp_tx_threshold

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cp_tx_threshold

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

4768

1

T1

1

T2

2

T3

1

auto[1]

718906

1

T1

2

T3

2

T4

1

---

Summary for Variable cp_tx_threshold_test

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	1	0	1	100.00

Automatically Generated Bins for cp_tx_threshold_test

Excluded/Illegal bins

NAME	COUNT	STATUS
dis	0	Excluded
[auto[0]]	0	Excluded

Covered bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[1]

139

1

T182

1

T180

2

T32

3

---

Summary for Variable cp_unexp_stop

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cp_unexp_stop

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

727613

1

T1

3

T2

68

T3

3

auto[1]

399

1

T182

4

T180

12

T32

5

---

Summary for Variable cp_unexp_stop_test

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	1	0	1	100.00

Automatically Generated Bins for cp_unexp_stop_test

Excluded/Illegal bins

NAME	COUNT	STATUS
dis	0	Excluded
[auto[0]]	0	Excluded

Covered bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[1]

128

1

T182

2

T180

3

T32

2