Unified Coverage Report :: Group :: tl_agent_pkg::tl_a_chan_cov_cg::SHAPE{(2 << ((valid_source_width - 1) - 1))=128}

Group : tl_agent_pkg::tl_a_chan_cov_cg::SHAPE{(2 << ((valid_source_width - 1) - 1))=128}

SCORE	INSTANCES	WEIGHT	GOAL	AT LEAST	PER INSTANCE	AUTO BIN MAX	PRINT MISSING
100.00	100.00	1	100	1	1	64	64

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_dv_tl_agent_0/tl_agent_cov.sv

1 Instances:

NAME	SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
tl_agent_pkg.uvm_test_top.env.m_tl_agent_i2c_reg_block.cov::m_tl_a_chan_cov_cg	100.00	1	100	1	64	64

---

Group Instance : tl_agent_pkg.uvm_test_top.env.m_tl_agent_i2c_reg_block.cov::m_tl_a_chan_cov_cg

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
100.00	1	100	1	64	64

---

Summary for Group Instance tl_agent_pkg.uvm_test_top.env.m_tl_agent_i2c_reg_block.cov::m_tl_a_chan_cov_cg

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	134	0	134	100.00
Crosses	3	0	3	100.00

Variables for Group Instance tl_agent_pkg.uvm_test_top.env.m_tl_agent_i2c_reg_block.cov::m_tl_a_chan_cov_cg

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
cp_mask	1	0	1	100.00	100	1	1	0
cp_opcode	3	0	3	100.00	100	1	1	0
cp_size	1	0	1	100.00	100	1	1	0
cp_source	129	0	129	100.00	100	1	1	0

Crosses for Group Instance tl_agent_pkg.uvm_test_top.env.m_tl_agent_i2c_reg_block.cov::m_tl_a_chan_cov_cg

CROSS	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	PRINT MISSING	COMMENT
tl_a_chan_cov_cg_cc	3	0	3	100.00	100	1	1	0

Summary for Variable cp_mask

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	1	0	1	100.00

User Defined Bins for cp_mask

Excluded/Illegal bins

NAME	COUNT	STATUS
others	26682889	Excluded

Covered bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

all_enables

7530797

1

T1

439

T2

1480

T3

18

---

Summary for Variable cp_opcode

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	3	0	3	100.00

User Defined Bins for cp_opcode

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
values[0x4]	33435987	1			T1	1612		T2	5366		T3	36
values[0x0]	388511	1			T1	40		T2	135		T3	22
values[0x1]	389188	1			T1	44		T2	122		T3	23

---

Summary for Variable cp_size

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	1	0	1	100.00

User Defined Bins for cp_size

Excluded/Illegal bins

NAME	COUNT	STATUS
others	18680649	Excluded

Covered bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

biggest_size

15533037

1

T1

750

T2

2649

T3

30

---

Summary for Variable cp_source

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	129	0	129	100.00

User Defined Bins for cp_source

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
valid_sources[0x00]	128556	1			T2	24		T5	154		T7	25
valid_sources[0x01]	144223	1			T1	8		T2	16		T5	173
valid_sources[0x02]	114581	1			T1	10		T2	22		T5	145
valid_sources[0x03]	140013	1			T1	9		T2	17		T5	122
valid_sources[0x04]	154224	1			T1	1		T2	22		T4	1
valid_sources[0x05]	128520	1			T1	3		T2	16		T5	123
valid_sources[0x06]	129643	1			T1	5		T2	20		T5	99
valid_sources[0x07]	120789	1			T1	6		T2	25		T5	87
valid_sources[0x08]	139556	1			T1	5		T2	8		T5	152
valid_sources[0x09]	118644	1			T1	5		T2	24		T5	175
valid_sources[0x0a]	132717	1			T1	2		T2	13		T5	139
valid_sources[0x0b]	132205	1			T1	7		T2	16		T5	85
valid_sources[0x0c]	134478	1			T1	6		T2	24		T5	134
valid_sources[0x0d]	135511	1			T1	5		T2	31		T5	85
valid_sources[0x0e]	138169	1			T1	9		T2	23		T5	78
valid_sources[0x0f]	128694	1			T1	5		T2	22		T5	60
valid_sources[0x10]	132752	1			T1	6		T2	23		T5	135
valid_sources[0x11]	129455	1			T1	7		T2	26		T5	121
valid_sources[0x12]	132648	1			T1	6		T2	17		T5	50
valid_sources[0x13]	129860	1			T2	32		T5	101		T7	30
valid_sources[0x14]	124117	1			T1	6		T2	30		T5	123
valid_sources[0x15]	135891	1			T1	4		T2	25		T5	160
valid_sources[0x16]	119862	1			T1	10		T2	35		T5	81
valid_sources[0x17]	127923	1			T1	14		T2	27		T5	131
valid_sources[0x18]	146625	1			T1	2		T2	16		T5	185
valid_sources[0x19]	136597	1			T1	5		T2	17		T5	123
valid_sources[0x1a]	141688	1			T1	4		T2	25		T5	135
valid_sources[0x1b]	130238	1			T1	8		T2	40		T5	92
valid_sources[0x1c]	131213	1			T1	1		T2	23		T5	122
valid_sources[0x1d]	127584	1			T1	14		T2	23		T5	86
valid_sources[0x1e]	127849	1			T1	3		T2	23		T5	105
valid_sources[0x1f]	134018	1			T1	4		T2	26		T5	99
valid_sources[0x20]	133514	1			T1	15		T2	23		T5	130
valid_sources[0x21]	120659	1			T1	12		T2	23		T5	127
valid_sources[0x22]	128437	1			T1	6		T2	18		T5	109
valid_sources[0x23]	132344	1			T1	12		T2	18		T5	122
valid_sources[0x24]	129879	1			T1	8		T2	18		T5	180
valid_sources[0x25]	139332	1			T1	3		T2	20		T5	146
valid_sources[0x26]	126821	1			T1	4		T2	18		T5	162
valid_sources[0x27]	126707	1			T1	7		T2	23		T5	100
valid_sources[0x28]	126371	1			T1	5		T2	33		T5	108
valid_sources[0x29]	134844	1			T1	6		T2	23		T5	97
valid_sources[0x2a]	144225	1			T1	5		T2	30		T5	110
valid_sources[0x2b]	132043	1			T1	3		T2	15		T5	78
valid_sources[0x2c]	143275	1			T1	6		T2	21		T5	129
valid_sources[0x2d]	122807	1			T1	8		T2	22		T5	83
valid_sources[0x2e]	137050	1			T1	18		T2	21		T4	1
valid_sources[0x2f]	121782	1			T1	7		T2	27		T5	132
valid_sources[0x30]	135323	1			T1	2		T2	26		T5	147
valid_sources[0x31]	153066	1			T1	3		T2	31		T5	145
valid_sources[0x32]	148650	1			T2	31		T5	97		T6	1
valid_sources[0x33]	131725	1			T1	2		T2	21		T5	108
valid_sources[0x34]	137461	1			T1	3		T2	27		T5	137
valid_sources[0x35]	122598	1			T1	7		T2	16		T5	147
valid_sources[0x36]	120113	1			T1	8		T2	16		T5	152
valid_sources[0x37]	126438	1			T1	10		T2	17		T5	162
valid_sources[0x38]	137060	1			T1	6		T2	20		T5	115
valid_sources[0x39]	138452	1			T1	6		T2	30		T5	154
valid_sources[0x3a]	134399	1			T1	1		T2	33		T5	100
valid_sources[0x3b]	135683	1			T1	2		T2	22		T5	179
valid_sources[0x3c]	140280	1			T1	5		T2	21		T5	138
valid_sources[0x3d]	127334	1			T1	6		T2	28		T5	110
valid_sources[0x3e]	135237	1			T1	5		T2	25		T5	251
valid_sources[0x3f]	138439	1			T1	4		T2	28		T5	129
valid_sources[0x40]	116351	1			T1	6		T2	29		T5	169
valid_sources[0x41]	138568	1			T1	4		T2	18		T3	81
valid_sources[0x42]	140479	1			T1	7		T2	27		T5	149
valid_sources[0x43]	132170	1			T1	15		T2	21		T5	81
valid_sources[0x44]	135191	1			T1	6		T2	13		T5	135
valid_sources[0x45]	126785	1			T1	5		T2	16		T5	126
valid_sources[0x46]	119770	1			T1	2		T2	24		T5	109
valid_sources[0x47]	126670	1			T1	9		T2	24		T5	125
valid_sources[0x48]	141244	1			T1	2		T2	29		T5	79
valid_sources[0x49]	133703	1			T1	12		T2	25		T5	182
valid_sources[0x4a]	132447	1			T1	1		T2	24		T5	106
valid_sources[0x4b]	139969	1			T1	8		T2	18		T5	133
valid_sources[0x4c]	129284	1			T1	7		T2	17		T5	126
valid_sources[0x4d]	122697	1			T1	7		T2	19		T5	146
valid_sources[0x4e]	125679	1			T1	5		T2	28		T5	112
valid_sources[0x4f]	145478	1			T1	8		T2	12		T5	105
valid_sources[0x50]	138333	1			T1	10		T2	23		T5	113
valid_sources[0x51]	135119	1			T1	5		T2	22		T5	144
valid_sources[0x52]	139217	1			T1	6		T2	23		T5	172
valid_sources[0x53]	125686	1			T1	10		T2	23		T5	133
valid_sources[0x54]	134165	1			T1	9		T2	21		T5	110
valid_sources[0x55]	135022	1			T1	19		T2	12		T5	101
valid_sources[0x56]	121961	1			T1	14		T2	18		T5	131
valid_sources[0x57]	126974	1			T1	6		T2	17		T5	131
valid_sources[0x58]	133849	1			T1	1		T2	13		T5	183
valid_sources[0x59]	135371	1			T1	14		T2	20		T5	155
valid_sources[0x5a]	144130	1			T1	9		T2	24		T5	168
valid_sources[0x5b]	166818	1			T1	2		T2	36		T5	49
valid_sources[0x5c]	147323	1			T1	1		T2	20		T5	170
valid_sources[0x5d]	155516	1			T1	7		T2	30		T5	157
valid_sources[0x5e]	143418	1			T1	6		T2	19		T5	117
valid_sources[0x5f]	135900	1			T1	2		T2	24		T5	148
valid_sources[0x60]	133791	1			T1	7		T2	19		T5	101
valid_sources[0x61]	134266	1			T1	3		T2	26		T5	125
valid_sources[0x62]	141227	1			T1	11		T2	20		T5	87
valid_sources[0x63]	133103	1			T1	5		T2	33		T5	106
valid_sources[0x64]	136433	1			T1	9		T2	17		T5	112
valid_sources[0x65]	124744	1			T1	7		T2	23		T5	97
valid_sources[0x66]	129684	1			T1	5		T2	25		T5	122
valid_sources[0x67]	132699	1			T1	4		T2	27		T5	92
valid_sources[0x68]	159298	1			T1	4		T2	17		T5	135
valid_sources[0x69]	149674	1			T1	4		T2	26		T5	121
valid_sources[0x6a]	124716	1			T1	7		T2	20		T5	154
valid_sources[0x6b]	160804	1			T1	2		T2	21		T5	160
valid_sources[0x6c]	132386	1			T2	15		T5	160		T7	35
valid_sources[0x6d]	129629	1			T1	9		T2	26		T5	153
valid_sources[0x6e]	119766	1			T1	14		T2	19		T5	180
valid_sources[0x6f]	133299	1			T1	12		T2	13		T5	124
valid_sources[0x70]	143040	1			T1	21		T2	10		T5	137
valid_sources[0x71]	124791	1			T1	6		T2	17		T5	156
valid_sources[0x72]	133786	1			T1	17		T2	23		T5	118
valid_sources[0x73]	128927	1			T1	5		T2	23		T5	154
valid_sources[0x74]	131882	1			T1	5		T2	22		T5	108
valid_sources[0x75]	141012	1			T1	6		T2	20		T5	121
valid_sources[0x76]	143576	1			T1	8		T2	24		T5	122
valid_sources[0x77]	123772	1			T1	4		T2	12		T5	118
valid_sources[0x78]	121383	1			T1	14		T2	23		T4	4
valid_sources[0x79]	130493	1			T1	5		T2	18		T5	103
valid_sources[0x7a]	131053	1			T1	4		T2	23		T5	122
valid_sources[0x7b]	124651	1			T1	2		T2	37		T5	118
valid_sources[0x7c]	131402	1			T1	10		T2	32		T5	148
valid_sources[0x7d]	139475	1			T1	4		T2	24		T5	154
valid_sources[0x7e]	131532	1			T1	15		T2	9		T5	104
valid_sources[0x7f]	125482	1			T1	6		T2	21		T5	95
valid_sources[0x80]	133886	1			T1	21		T2	16		T4	9

---

Summary for Cross tl_a_chan_cov_cg_cc

Samples crossed: cp_opcode cp_mask cp_size

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	3	0	3	100.00

Automatically Generated Cross Bins for tl_a_chan_cov_cg_cc

Bins

cp_opcode

cp_mask

cp_size

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

values[0x4]

all_enables

biggest_size

7187002

1

T1

406

T2

1322

T3

2

values[0x0]

all_enables

biggest_size

204543

1

T1

19

T2

90

T3

7

values[0x1]

all_enables

biggest_size

139252

1

T1

14

T2

68

T3

9