Unified Coverage Report :: Group :: i2c_env_pkg::i2c_b2b_txn_cg

Group : i2c_env_pkg::i2c_b2b_txn_cg

SCORE	INSTANCES	WEIGHT	GOAL	AT LEAST	PER INSTANCE	AUTO BIN MAX	PRINT MISSING
100.00	100.00	1	100	1	1	64	64

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_dv_i2c_env_0.1/i2c_env_cov.sv

2 Instances:

NAME	SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
i2c_env_pkg.b2b_txn_host_cg	100.00	1	100	1	64	64
i2c_env_pkg.b2b_txn_target_cg	100.00	1	100	1	64	64

---

Group Instance : i2c_env_pkg.b2b_txn_host_cg

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
100.00	1	100	1	64	64

---

Summary for Group Instance i2c_env_pkg.b2b_txn_host_cg

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	8	0	8	100.00

Variables for Group Instance i2c_env_pkg.b2b_txn_host_cg

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
B2B_txn_cp	8	0	8	100.00	100	1	1	0

---

Group Instance : i2c_env_pkg.b2b_txn_target_cg

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
100.00	1	100	1	64	64

---

Summary for Group Instance i2c_env_pkg.b2b_txn_target_cg

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	8	0	8	100.00

Variables for Group Instance i2c_env_pkg.b2b_txn_target_cg

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
B2B_txn_cp	8	0	8	100.00	100	1	1	0

Summary for Variable B2B_txn_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	8	0	8	100.00

User Defined Bins for B2B_txn_cp

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
b2b_read_different_addr	1848	1			T2	1		T5	2		T8	2
b2b_read_same_addr	290	1			T22	3		T42	6		T150	1
write_after_read_different_addr	1843	1			T2	3		T5	4		T8	3
write_after_read_same_addr	28	1			T293	1		T294	1		T295	1
read_after_write_different_addr	1849	1			T2	3		T5	5		T8	3
read_after_write_same_addr	30	1			T84	1		T107	1		T182	1
b2b_write_different_addr	1820	1			T2	3		T5	5		T8	4
b2b_write_same_addr	360	1			T2	3		T21	2		T22	2

Summary for Variable B2B_txn_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	8	0	8	100.00

User Defined Bins for B2B_txn_cp

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
b2b_read_different_addr	5211	1			T7	71		T74	26		T53	26
b2b_read_same_addr	12632	1			T3	1		T7	141		T50	1
write_after_read_different_addr	5390	1			T7	50		T45	19		T73	18
write_after_read_same_addr	81	1			T7	7		T296	26		T297	1
read_after_write_different_addr	5393	1			T3	1		T7	51		T50	1
read_after_write_same_addr	76	1			T7	6		T296	25		T298	17
b2b_write_different_addr	5261	1			T1	46		T7	44		T65	35
b2b_write_same_addr	12916	1			T1	56		T7	165		T50	3