Unified Coverage Report :: Module :: i2c_csr_assert_fpv

Module : i2c_csr_assert_fpv

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
93.75						93.75

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_fpv_i2c_csr_assert_0/i2c_csr_assert_fpv.sv

Module self-instances :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
tb.dut.i2c_csr_assert	93.75						93.75

---

Module Instance : tb.dut.i2c_csr_assert

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
93.75						93.75

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
93.75						93.75

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
98.48	100.00	100.00	93.91			100.00	dut

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Since this is the module's only instance, the coverage report is the same as for the module.

Assert Coverage for Module : i2c_csr_assert_fpv

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	16	16	100.00	15	93.75
Cover properties	0	0		0
Cover sequences	0	0		0
Total	16	16	100.00	15	93.75

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
TlulOOBAddrErr_A	401011802	0	0	0
ctrl_rd_A	401011802	2856	0	0
host_fifo_config_rd_A	401011802	3329	0	0
host_nack_handler_timeout_rd_A	401011802	1438	0	0
host_timeout_ctrl_rd_A	401011802	1178	0	0
intr_enable_rd_A	401011802	4996	0	0
ovrd_rd_A	401011802	2454	0	0
target_fifo_config_rd_A	401011802	1401	0	0
target_id_rd_A	401011802	1947	0	0
target_timeout_ctrl_rd_A	401011802	1503	0	0
timeout_ctrl_rd_A	401011802	1515	0	0
timing0_rd_A	401011802	1488	0	0
timing1_rd_A	401011802	1343	0	0
timing2_rd_A	401011802	1560	0	0
timing3_rd_A	401011802	1436	0	0
timing4_rd_A	401011802	1410	0	0

TlulOOBAddrErr_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	401011802	0	0	0

ctrl_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	401011802	2856	0	0
T97	5796	44	0	0
T98	9269	33	0	0
T99	13018	310	0	0
T100	5978	20	0	0
T101	14708	289	0	0
T102	3906	28	0	0
T103	7492	141	0	0
T104	9609	26	0	0
T105	14323	298	0	0
T106	3010	37	0	0

host_fifo_config_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	401011802	3329	0	0
T13	9884	0	0	0
T107	272310	77	0	0
T108	0	139	0	0
T109	0	169	0	0
T110	0	178	0	0
T111	0	190	0	0
T112	0	214	0	0
T113	0	70	0	0
T114	0	106	0	0
T115	0	134	0	0
T116	0	146	0	0
T117	147212	0	0	0
T118	7073	0	0	0
T119	134300	0	0	0
T120	17334	0	0	0
T121	8406	0	0	0
T122	224978	0	0	0
T123	51448	0	0	0
T124	54557	0	0	0

host_nack_handler_timeout_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	401011802	1438	0	0
T97	5796	22	0	0
T98	9269	19	0	0
T99	13018	97	0	0
T100	5978	18	0	0
T101	14708	126	0	0
T102	3906	34	0	0
T103	7492	36	0	0
T104	9609	31	0	0
T105	14323	108	0	0
T106	3010	13	0	0

host_timeout_ctrl_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	401011802	1178	0	0
T97	5796	17	0	0
T98	9269	14	0	0
T99	13018	79	0	0
T100	5978	26	0	0
T101	14708	89	0	0
T102	3906	22	0	0
T103	7492	42	0	0
T104	9609	2	0	0
T105	14323	85	0	0
T106	3010	15	0	0

intr_enable_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	401011802	4996	0	0
T97	0	57	0	0
T98	0	13	0	0
T99	0	439	0	0
T100	0	18	0	0
T101	0	727	0	0
T102	0	31	0	0
T116	172424	9	0	0
T125	0	12	0	0
T126	0	16	0	0
T127	0	21	0	0
T128	7779	0	0	0
T129	455958	0	0	0
T130	415287	0	0	0
T131	14123	0	0	0
T132	70952	0	0	0
T133	52410	0	0	0
T134	284657	0	0	0
T135	8143	0	0	0
T136	109211	0	0	0

ovrd_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	401011802	2454	0	0
T22	28466	0	0	0
T30	137370	0	0	0
T38	14895	0	0	0
T44	11815	0	0	0
T45	103844	0	0	0
T50	31286	0	0	0
T57	26170	0	0	0
T72	3681	0	0	0
T76	1705	62	0	0
T77	2607	0	0	0
T137	0	57	0	0
T138	0	32	0	0
T139	0	42	0	0
T140	0	27	0	0
T141	0	72	0	0
T142	0	56	0	0
T143	0	38	0	0
T144	0	41	0	0
T145	0	26	0	0

target_fifo_config_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	401011802	1401	0	0
T97	5796	20	0	0
T98	9269	23	0	0
T99	13018	128	0	0
T100	5978	14	0	0
T101	14708	117	0	0
T102	3906	37	0	0
T103	7492	33	0	0
T104	9609	12	0	0
T105	14323	91	0	0
T106	3010	24	0	0

target_id_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	401011802	1947	0	0
T97	5796	20	0	0
T98	9269	20	0	0
T99	13018	234	0	0
T100	5978	9	0	0
T101	14708	170	0	0
T102	3906	24	0	0
T103	7492	113	0	0
T104	9609	24	0	0
T105	14323	142	0	0
T106	3010	18	0	0

target_timeout_ctrl_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	401011802	1503	0	0
T97	5796	53	0	0
T98	9269	19	0	0
T99	13018	81	0	0
T100	5978	9	0	0
T101	14708	92	0	0
T102	3906	28	0	0
T103	7492	57	0	0
T104	9609	30	0	0
T105	14323	82	0	0
T106	3010	12	0	0

timeout_ctrl_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	401011802	1515	0	0
T97	5796	57	0	0
T98	9269	8	0	0
T99	13018	135	0	0
T100	5978	21	0	0
T101	14708	126	0	0
T102	3906	19	0	0
T103	7492	50	0	0
T104	9609	33	0	0
T105	14323	132	0	0
T106	3010	29	0	0

timing0_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	401011802	1488	0	0
T97	5796	80	0	0
T98	9269	18	0	0
T99	13018	107	0	0
T100	5978	14	0	0
T101	14708	131	0	0
T102	3906	29	0	0
T103	7492	45	0	0
T104	9609	22	0	0
T105	14323	129	0	0
T106	3010	22	0	0

timing1_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	401011802	1343	0	0
T97	5796	28	0	0
T98	9269	32	0	0
T99	13018	118	0	0
T100	5978	13	0	0
T101	14708	95	0	0
T102	3906	26	0	0
T103	7492	40	0	0
T104	9609	40	0	0
T105	14323	102	0	0
T106	3010	12	0	0

timing2_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	401011802	1560	0	0
T97	5796	4	0	0
T98	9269	25	0	0
T99	13018	136	0	0
T100	5978	13	0	0
T101	14708	129	0	0
T102	3906	28	0	0
T103	7492	58	0	0
T104	9609	41	0	0
T105	14323	151	0	0
T106	3010	29	0	0

timing3_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	401011802	1436	0	0
T97	5796	31	0	0
T98	9269	14	0	0
T99	13018	123	0	0
T100	5978	4	0	0
T101	14708	111	0	0
T102	3906	15	0	0
T103	7492	60	0	0
T104	9609	19	0	0
T105	14323	144	0	0
T106	3010	12	0	0

timing4_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	401011802	1410	0	0
T97	5796	25	0	0
T98	9269	19	0	0
T99	13018	115	0	0
T100	5978	21	0	0
T101	14708	103	0	0
T102	3906	18	0	0
T103	7492	39	0	0
T104	9609	38	0	0
T105	14323	135	0	0
T106	3010	17	0	0