Unified Coverage Report :: Group :: tl_agent_pkg::tl_a_chan_cov_cg::SHAPE{(2 << ((valid_source_width - 1) - 1))=128}

Group : tl_agent_pkg::tl_a_chan_cov_cg::SHAPE{(2 << ((valid_source_width - 1) - 1))=128}

SCORE	INSTANCES	WEIGHT	GOAL	AT LEAST	PER INSTANCE	AUTO BIN MAX	PRINT MISSING
100.00	100.00	1	100	1	1	64	64

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_dv_tl_agent_0/tl_agent_cov.sv

1 Instances:

NAME	SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
tl_agent_pkg.uvm_test_top.env.m_tl_agent_i2c_reg_block.cov::m_tl_a_chan_cov_cg	100.00	1	100	1	64	64

---

Group Instance : tl_agent_pkg.uvm_test_top.env.m_tl_agent_i2c_reg_block.cov::m_tl_a_chan_cov_cg

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
100.00	1	100	1	64	64

---

Summary for Group Instance tl_agent_pkg.uvm_test_top.env.m_tl_agent_i2c_reg_block.cov::m_tl_a_chan_cov_cg

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	134	0	134	100.00
Crosses	3	0	3	100.00

Variables for Group Instance tl_agent_pkg.uvm_test_top.env.m_tl_agent_i2c_reg_block.cov::m_tl_a_chan_cov_cg

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
cp_mask	1	0	1	100.00	100	1	1	0
cp_opcode	3	0	3	100.00	100	1	1	0
cp_size	1	0	1	100.00	100	1	1	0
cp_source	129	0	129	100.00	100	1	1	0

Crosses for Group Instance tl_agent_pkg.uvm_test_top.env.m_tl_agent_i2c_reg_block.cov::m_tl_a_chan_cov_cg

CROSS	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	PRINT MISSING	COMMENT
tl_a_chan_cov_cg_cc	3	0	3	100.00	100	1	1	0

Summary for Variable cp_mask

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	1	0	1	100.00

User Defined Bins for cp_mask

Excluded/Illegal bins

NAME	COUNT	STATUS
others	26655235	Excluded

Covered bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

all_enables

7054674

1

T1

10226

T2

299

T3

361

---

Summary for Variable cp_opcode

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	3	0	3	100.00

User Defined Bins for cp_opcode

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
values[0x4]	32963131	1			T1	21233		T2	1099		T3	37463
values[0x0]	373156	1			T1	81		T2	9		T3	203
values[0x1]	373622	1			T1	74		T2	8		T3	183

---

Summary for Variable cp_size

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	1	0	1	100.00

User Defined Bins for cp_size

Excluded/Illegal bins

NAME	COUNT	STATUS
others	18655895	Excluded

Covered bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

biggest_size

15054014

1

T1

12594

T2

484

T3

18854

---

Summary for Variable cp_source

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	129	0	129	100.00

User Defined Bins for cp_source

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
valid_sources[0x00]	127378	1			T1	69		T2	4		T3	140
valid_sources[0x01]	124470	1			T1	99		T2	1		T3	148
valid_sources[0x02]	135938	1			T1	86		T2	6		T3	140
valid_sources[0x03]	125916	1			T1	79		T2	10		T3	161
valid_sources[0x04]	130976	1			T1	81		T2	8		T3	138
valid_sources[0x05]	127846	1			T1	96		T2	8		T3	145
valid_sources[0x06]	146567	1			T1	83		T3	149		T7	1287
valid_sources[0x07]	147588	1			T1	84		T3	126		T5	1
valid_sources[0x08]	123182	1			T1	91		T3	135		T5	4
valid_sources[0x09]	137520	1			T1	89		T2	8		T3	140
valid_sources[0x0a]	131835	1			T1	92		T2	10		T3	139
valid_sources[0x0b]	129597	1			T1	83		T2	3		T3	154
valid_sources[0x0c]	141786	1			T1	76		T2	3		T3	149
valid_sources[0x0d]	155244	1			T1	88		T2	2		T3	148
valid_sources[0x0e]	145375	1			T1	103		T2	5		T3	149
valid_sources[0x0f]	125765	1			T1	84		T2	2		T3	155
valid_sources[0x10]	128855	1			T1	98		T2	4		T3	151
valid_sources[0x11]	131086	1			T1	105		T3	142		T4	5
valid_sources[0x12]	141350	1			T1	89		T2	2		T3	155
valid_sources[0x13]	142503	1			T1	86		T2	7		T3	149
valid_sources[0x14]	125695	1			T1	91		T2	3		T3	163
valid_sources[0x15]	132176	1			T1	68		T2	8		T3	140
valid_sources[0x16]	130411	1			T1	82		T2	3		T3	162
valid_sources[0x17]	137321	1			T1	85		T2	3		T3	159
valid_sources[0x18]	118466	1			T1	97		T2	1		T3	129
valid_sources[0x19]	126513	1			T1	82		T2	2		T3	161
valid_sources[0x1a]	136474	1			T1	76		T2	11		T3	159
valid_sources[0x1b]	125639	1			T1	77		T2	6		T3	154
valid_sources[0x1c]	122327	1			T1	76		T2	3		T3	133
valid_sources[0x1d]	131918	1			T1	71		T2	4		T3	152
valid_sources[0x1e]	125215	1			T1	91		T3	144		T4	8
valid_sources[0x1f]	138283	1			T1	90		T3	136		T7	1315
valid_sources[0x20]	121180	1			T1	77		T3	140		T7	1379
valid_sources[0x21]	127919	1			T1	87		T2	1		T3	166
valid_sources[0x22]	143142	1			T1	73		T2	3		T3	157
valid_sources[0x23]	126694	1			T1	58		T2	3		T3	156
valid_sources[0x24]	141126	1			T1	86		T2	2		T3	131
valid_sources[0x25]	126121	1			T1	83		T2	6		T3	162
valid_sources[0x26]	140982	1			T1	86		T2	7		T3	126
valid_sources[0x27]	140338	1			T1	92		T2	4		T3	122
valid_sources[0x28]	135771	1			T1	88		T2	6		T3	150
valid_sources[0x29]	132957	1			T1	104		T2	6		T3	148
valid_sources[0x2a]	122053	1			T1	101		T2	1		T3	153
valid_sources[0x2b]	160614	1			T1	92		T2	4		T3	158
valid_sources[0x2c]	139510	1			T1	77		T2	8		T3	169
valid_sources[0x2d]	123550	1			T1	86		T2	3		T3	137
valid_sources[0x2e]	148023	1			T1	82		T2	1		T3	140
valid_sources[0x2f]	125250	1			T1	76		T2	8		T3	123
valid_sources[0x30]	135773	1			T1	91		T2	7		T3	162
valid_sources[0x31]	115529	1			T1	85		T2	2		T3	146
valid_sources[0x32]	138055	1			T1	90		T2	5		T3	152
valid_sources[0x33]	126197	1			T1	86		T2	1		T3	152
valid_sources[0x34]	150076	1			T1	95		T2	9		T3	145
valid_sources[0x35]	122635	1			T1	67		T2	3		T3	178
valid_sources[0x36]	171987	1			T1	86		T2	2		T3	141
valid_sources[0x37]	130231	1			T1	83		T2	1		T3	132
valid_sources[0x38]	126172	1			T1	77		T2	1		T3	141
valid_sources[0x39]	128463	1			T1	86		T2	5		T3	146
valid_sources[0x3a]	123864	1			T1	84		T2	5		T3	150
valid_sources[0x3b]	131563	1			T1	90		T2	1		T3	149
valid_sources[0x3c]	121879	1			T1	95		T3	123		T5	4
valid_sources[0x3d]	131234	1			T1	84		T2	1		T3	150
valid_sources[0x3e]	120605	1			T1	92		T2	7		T3	157
valid_sources[0x3f]	139814	1			T1	93		T2	9		T3	144
valid_sources[0x40]	120489	1			T1	86		T2	6		T3	144
valid_sources[0x41]	136423	1			T1	82		T2	7		T3	151
valid_sources[0x42]	122448	1			T1	93		T2	1		T3	145
valid_sources[0x43]	121142	1			T1	95		T2	8		T3	160
valid_sources[0x44]	124750	1			T1	82		T2	2		T3	153
valid_sources[0x45]	137631	1			T1	78		T2	6		T3	155
valid_sources[0x46]	126487	1			T1	80		T2	8		T3	150
valid_sources[0x47]	129428	1			T1	109		T2	5		T3	142
valid_sources[0x48]	124090	1			T1	93		T2	8		T3	161
valid_sources[0x49]	120237	1			T1	81		T2	4		T3	128
valid_sources[0x4a]	126461	1			T1	81		T2	4		T3	148
valid_sources[0x4b]	120943	1			T1	91		T3	120		T4	3
valid_sources[0x4c]	154662	1			T1	88		T2	3		T3	139
valid_sources[0x4d]	126077	1			T1	94		T2	5		T3	141
valid_sources[0x4e]	122639	1			T1	100		T2	1		T3	149
valid_sources[0x4f]	129583	1			T1	78		T2	3		T3	137
valid_sources[0x50]	164906	1			T1	79		T2	5		T3	157
valid_sources[0x51]	128968	1			T1	66		T2	3		T3	157
valid_sources[0x52]	123592	1			T1	89		T2	3		T3	161
valid_sources[0x53]	140818	1			T1	79		T2	7		T3	149
valid_sources[0x54]	122623	1			T1	74		T2	2		T3	124
valid_sources[0x55]	122350	1			T1	93		T2	6		T3	150
valid_sources[0x56]	127679	1			T1	78		T3	171		T7	1364
valid_sources[0x57]	132204	1			T1	67		T2	3		T3	121
valid_sources[0x58]	137774	1			T1	85		T2	2		T3	151
valid_sources[0x59]	152514	1			T1	83		T2	5		T3	140
valid_sources[0x5a]	132464	1			T1	67		T2	2		T3	172
valid_sources[0x5b]	121420	1			T1	85		T3	134		T7	1265
valid_sources[0x5c]	130672	1			T1	64		T2	8		T3	140
valid_sources[0x5d]	130337	1			T1	83		T2	4		T3	157
valid_sources[0x5e]	128206	1			T1	88		T2	2		T3	133
valid_sources[0x5f]	126755	1			T1	68		T2	2		T3	146
valid_sources[0x60]	129167	1			T1	105		T2	7		T3	174
valid_sources[0x61]	120608	1			T1	91		T2	5		T3	131
valid_sources[0x62]	149601	1			T1	81		T2	6		T3	137
valid_sources[0x63]	131927	1			T1	79		T2	10		T3	137
valid_sources[0x64]	123278	1			T1	70		T2	6		T3	144
valid_sources[0x65]	127447	1			T1	88		T2	7		T3	151
valid_sources[0x66]	126165	1			T1	87		T3	167		T4	1
valid_sources[0x67]	131008	1			T1	83		T2	6		T3	151
valid_sources[0x68]	120967	1			T1	74		T2	5		T3	152
valid_sources[0x69]	126812	1			T1	72		T2	1		T3	122
valid_sources[0x6a]	117240	1			T1	74		T2	4		T3	140
valid_sources[0x6b]	129306	1			T1	105		T2	8		T3	167
valid_sources[0x6c]	133455	1			T1	88		T2	1		T3	156
valid_sources[0x6d]	149070	1			T1	84		T2	2		T3	156
valid_sources[0x6e]	125806	1			T1	81		T2	3		T3	159
valid_sources[0x6f]	130600	1			T1	79		T2	6		T3	148
valid_sources[0x70]	124516	1			T1	94		T2	7		T3	138
valid_sources[0x71]	132724	1			T1	74		T2	4		T3	133
valid_sources[0x72]	139590	1			T1	84		T3	143		T5	7
valid_sources[0x73]	136041	1			T1	75		T2	3		T3	149
valid_sources[0x74]	131401	1			T1	107		T2	6		T3	160
valid_sources[0x75]	126458	1			T1	101		T2	5		T3	156
valid_sources[0x76]	131932	1			T1	82		T2	4		T3	168
valid_sources[0x77]	129888	1			T1	89		T2	4		T3	179
valid_sources[0x78]	127095	1			T1	79		T2	9		T3	161
valid_sources[0x79]	133014	1			T1	72		T2	8		T3	132
valid_sources[0x7a]	125968	1			T1	86		T2	2		T3	149
valid_sources[0x7b]	129812	1			T1	76		T2	3		T3	132
valid_sources[0x7c]	124401	1			T1	83		T2	7		T3	167
valid_sources[0x7d]	132604	1			T1	68		T2	9		T3	146
valid_sources[0x7e]	145505	1			T1	72		T2	5		T3	145
valid_sources[0x7f]	137315	1			T1	86		T3	175		T5	3
valid_sources[0x80]	126311	1			T1	84		T2	4		T3	160

---

Summary for Cross tl_a_chan_cov_cg_cc

Samples crossed: cp_opcode cp_mask cp_size

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	3	0	3	100.00

Automatically Generated Cross Bins for tl_a_chan_cov_cg_cc

Bins

cp_opcode

cp_mask

cp_size

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

values[0x4]

all_enables

biggest_size

6716794

1

T1

10094

T2

288

T3

233

values[0x0]

all_enables

biggest_size

198993

1

T1

74

T2

6

T3

77

values[0x1]

all_enables

biggest_size

138887

1

T1

58

T2

5

T3

51