Unified Coverage Report :: Module :: i2c_csr_assert_fpv

Module : i2c_csr_assert_fpv

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
93.75						93.75

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_fpv_i2c_csr_assert_0/i2c_csr_assert_fpv.sv

Module self-instances :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
tb.dut.i2c_csr_assert	93.75						93.75

---

Module Instance : tb.dut.i2c_csr_assert

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
93.75						93.75

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
93.75						93.75

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
98.48	100.00	100.00	93.91			100.00	dut

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Since this is the module's only instance, the coverage report is the same as for the module.

Assert Coverage for Module : i2c_csr_assert_fpv

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	16	16	100.00	15	93.75
Cover properties	0	0		0
Cover sequences	0	0		0
Total	16	16	100.00	15	93.75

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
TlulOOBAddrErr_A	367857992	0	0	0
ctrl_rd_A	367857992	1644	0	0
host_fifo_config_rd_A	367857992	2905	0	0
host_nack_handler_timeout_rd_A	367857992	1107	0	0
host_timeout_ctrl_rd_A	367857992	1127	0	0
intr_enable_rd_A	367857992	2203	0	0
ovrd_rd_A	367857992	2046	0	0
target_fifo_config_rd_A	367857992	1231	0	0
target_id_rd_A	367857992	1408	0	0
target_timeout_ctrl_rd_A	367857992	1213	0	0
timeout_ctrl_rd_A	367857992	1247	0	0
timing0_rd_A	367857992	1089	0	0
timing1_rd_A	367857992	1136	0	0
timing2_rd_A	367857992	1205	0	0
timing3_rd_A	367857992	1381	0	0
timing4_rd_A	367857992	1139	0	0

TlulOOBAddrErr_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	367857992	0	0	0

ctrl_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	367857992	1644	0	0
T91	2882	14	0	0
T92	1764	9	0	0
T93	1491	10	0	0
T94	3631	34	0	0
T95	1344	14	0	0
T96	2578	19	0	0
T97	1431	3	0	0
T98	2082	12	0	0
T99	10770	46	0	0
T100	2521	21	0	0

host_fifo_config_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	367857992	2905	0	0
T17	130921	63	0	0
T20	189560	0	0	0
T34	7233	0	0	0
T40	613913	0	0	0
T41	297409	0	0	0
T42	10838	0	0	0
T54	51943	0	0	0
T72	104048	0	0	0
T87	1545	0	0	0
T90	10079	0	0	0
T101	0	85	0	0
T102	0	183	0	0
T103	0	108	0	0
T104	0	124	0	0
T105	0	52	0	0
T106	0	87	0	0
T107	0	207	0	0
T108	0	202	0	0
T109	0	89	0	0

host_nack_handler_timeout_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	367857992	1107	0	0
T91	2882	6	0	0
T92	1764	9	0	0
T93	1491	4	0	0
T94	3631	20	0	0
T95	1344	2	0	0
T96	2578	5	0	0
T97	1431	5	0	0
T98	2082	29	0	0
T99	10770	36	0	0
T100	2521	13	0	0

host_timeout_ctrl_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	367857992	1127	0	0
T91	2882	3	0	0
T92	1764	1	0	0
T93	1491	2	0	0
T94	3631	9	0	0
T96	2578	5	0	0
T97	1431	2	0	0
T98	2082	7	0	0
T99	10770	17	0	0
T100	2521	21	0	0
T110	6501	79	0	0

intr_enable_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	367857992	2203	0	0
T17	130921	18	0	0
T20	189560	0	0	0
T34	7233	0	0	0
T40	613913	0	0	0
T41	297409	0	0	0
T42	10838	0	0	0
T54	51943	0	0	0
T72	104048	0	0	0
T87	1545	0	0	0
T90	10079	0	0	0
T91	0	124	0	0
T92	0	2	0	0
T93	0	2	0	0
T94	0	4	0	0
T95	0	37	0	0
T111	0	34	0	0
T112	0	13	0	0
T113	0	31	0	0
T114	0	4	0	0

ovrd_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	367857992	2046	0	0
T21	19049	0	0	0
T34	7233	0	0	0
T41	297409	0	0	0
T42	10838	0	0	0
T44	425147	0	0	0
T46	209666	0	0	0
T50	38447	0	0	0
T87	1545	30	0	0
T88	0	35	0	0
T90	10079	0	0	0
T115	0	58	0	0
T116	0	35	0	0
T117	0	81	0	0
T118	0	31	0	0
T119	0	28	0	0
T120	0	56	0	0
T121	0	41	0	0
T122	0	43	0	0
T123	32490	0	0	0

target_fifo_config_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	367857992	1231	0	0
T91	2882	27	0	0
T92	1764	4	0	0
T93	1491	3	0	0
T94	3631	9	0	0
T95	1344	3	0	0
T97	1431	2	0	0
T98	2082	5	0	0
T99	10770	8	0	0
T100	2521	31	0	0
T110	6501	120	0	0

target_id_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	367857992	1408	0	0
T91	2882	27	0	0
T92	1764	8	0	0
T93	1491	7	0	0
T94	3631	28	0	0
T95	1344	8	0	0
T96	2578	16	0	0
T97	1431	2	0	0
T98	2082	21	0	0
T99	10770	9	0	0
T100	2521	29	0	0

target_timeout_ctrl_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	367857992	1213	0	0
T91	2882	16	0	0
T92	1764	1	0	0
T93	1491	4	0	0
T94	3631	23	0	0
T98	2082	15	0	0
T99	10770	18	0	0
T100	2521	12	0	0
T110	6501	90	0	0
T124	8253	20	0	0
T125	52363	419	0	0

timeout_ctrl_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	367857992	1247	0	0
T91	2882	14	0	0
T92	1764	13	0	0
T94	3631	15	0	0
T96	2578	12	0	0
T98	2082	17	0	0
T99	10770	47	0	0
T100	2521	21	0	0
T110	6501	124	0	0
T124	8253	5	0	0
T125	52363	423	0	0

timing0_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	367857992	1089	0	0
T91	2882	17	0	0
T93	1491	3	0	0
T94	3631	11	0	0
T95	1344	5	0	0
T96	2578	11	0	0
T98	2082	5	0	0
T99	10770	31	0	0
T100	2521	46	0	0
T110	6501	116	0	0
T124	8253	10	0	0

timing1_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	367857992	1136	0	0
T91	2882	18	0	0
T92	1764	7	0	0
T93	1491	5	0	0
T94	3631	14	0	0
T95	1344	3	0	0
T96	2578	3	0	0
T97	1431	1	0	0
T98	2082	9	0	0
T99	10770	28	0	0
T110	6501	108	0	0

timing2_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	367857992	1205	0	0
T91	2882	10	0	0
T92	1764	11	0	0
T93	1491	3	0	0
T94	3631	21	0	0
T96	2578	11	0	0
T98	2082	9	0	0
T99	10770	35	0	0
T100	2521	35	0	0
T110	6501	158	0	0
T124	8253	14	0	0

timing3_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	367857992	1381	0	0
T91	2882	18	0	0
T92	1764	3	0	0
T93	1491	2	0	0
T94	3631	33	0	0
T95	1344	6	0	0
T96	2578	7	0	0
T98	2082	18	0	0
T99	10770	10	0	0
T100	2521	4	0	0
T110	6501	124	0	0

timing4_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	367857992	1139	0	0
T91	2882	5	0	0
T92	1764	10	0	0
T93	1491	1	0	0
T94	3631	5	0	0
T96	2578	15	0	0
T97	1431	1	0	0
T98	2082	17	0	0
T99	10770	36	0	0
T100	2521	20	0	0
T110	6501	107	0	0