Unified Coverage Report :: Group :: tl_agent_pkg::tl_a_chan_cov_cg::SHAPE{(2 << ((valid_source_width - 1) - 1))=128}

Group : tl_agent_pkg::tl_a_chan_cov_cg::SHAPE{(2 << ((valid_source_width - 1) - 1))=128}

SCORE	INSTANCES	WEIGHT	GOAL	AT LEAST	PER INSTANCE	AUTO BIN MAX	PRINT MISSING
100.00	100.00	1	100	1	1	64	64

Source File(s) :
/workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/i2c-sim-vcs/default/sim-vcs/../src/lowrisc_dv_tl_agent_0/tl_agent_cov.sv

1 Instances:

NAME	SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
tl_agent_pkg.uvm_test_top.env.m_tl_agent_i2c_reg_block.cov::m_tl_a_chan_cov_cg	100.00	1	100	1	64	64

---

Group Instance : tl_agent_pkg.uvm_test_top.env.m_tl_agent_i2c_reg_block.cov::m_tl_a_chan_cov_cg

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
100.00	1	100	1	64	64

---

Summary for Group Instance tl_agent_pkg.uvm_test_top.env.m_tl_agent_i2c_reg_block.cov::m_tl_a_chan_cov_cg

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	134	0	134	100.00
Crosses	3	0	3	100.00

Variables for Group Instance tl_agent_pkg.uvm_test_top.env.m_tl_agent_i2c_reg_block.cov::m_tl_a_chan_cov_cg

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
cp_mask	1	0	1	100.00	100	1	1	0
cp_opcode	3	0	3	100.00	100	1	1	0
cp_size	1	0	1	100.00	100	1	1	0
cp_source	129	0	129	100.00	100	1	1	0

Crosses for Group Instance tl_agent_pkg.uvm_test_top.env.m_tl_agent_i2c_reg_block.cov::m_tl_a_chan_cov_cg

CROSS	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	PRINT MISSING	COMMENT
tl_a_chan_cov_cg_cc	3	0	3	100.00	100	1	1	0

Summary for Variable cp_mask

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	1	0	1	100.00

User Defined Bins for cp_mask

Excluded/Illegal bins

NAME	COUNT	STATUS
others	29563217	Excluded

Covered bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

all_enables

8104402

1

T1

13

T2

45

T3

61

---

Summary for Variable cp_opcode

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	3	0	3	100.00

User Defined Bins for cp_opcode

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
values[0x4]	36839971	1			T1	17		T2	120		T3	201
values[0x0]	412502	1			T1	13		T2	46		T3	10
values[0x1]	415146	1			T1	7		T2	67		T3	9

---

Summary for Variable cp_size

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	1	0	1	100.00

User Defined Bins for cp_size

Excluded/Illegal bins

NAME	COUNT	STATUS
others	20721778	Excluded

Covered bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

biggest_size

16945841

1

T1

16

T2

100

T3

117

---

Summary for Variable cp_source

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	129	0	129	100.00

User Defined Bins for cp_source

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
valid_sources[0x00]	138665	1			T3	1		T4	21		T29	34
valid_sources[0x01]	133702	1			T1	1		T3	1		T4	18
valid_sources[0x02]	135281	1			T3	1		T4	23		T9	6
valid_sources[0x03]	145690	1			T3	1		T4	17		T50	6
valid_sources[0x04]	139856	1			T3	1		T4	17		T8	3277
valid_sources[0x05]	134737	1			T4	25		T29	6		T50	4
valid_sources[0x06]	160940	1			T2	2		T3	2		T4	17
valid_sources[0x07]	143289	1			T4	19		T49	1		T50	1
valid_sources[0x08]	145232	1			T1	1		T4	27		T50	8
valid_sources[0x09]	143430	1			T2	1		T4	21		T29	2
valid_sources[0x0a]	143662	1			T2	1		T4	24		T29	4
valid_sources[0x0b]	140027	1			T1	1		T2	5		T4	14
valid_sources[0x0c]	141818	1			T4	28		T5	1		T9	7
valid_sources[0x0d]	142340	1			T4	16		T29	9		T50	3
valid_sources[0x0e]	163135	1			T1	1		T4	26		T5	1
valid_sources[0x0f]	138269	1			T4	19		T9	30		T29	14
valid_sources[0x10]	153758	1			T4	28		T29	18		T50	2
valid_sources[0x11]	160009	1			T3	1		T4	25		T29	9
valid_sources[0x12]	148778	1			T3	2		T4	16		T29	6
valid_sources[0x13]	140034	1			T4	33		T9	9		T29	2
valid_sources[0x14]	141965	1			T3	1		T4	24		T9	1
valid_sources[0x15]	137982	1			T4	29		T5	1		T29	24
valid_sources[0x16]	143714	1			T3	1		T4	16		T29	19
valid_sources[0x17]	134595	1			T4	13		T5	27		T29	3
valid_sources[0x18]	142555	1			T3	1		T4	16		T29	8
valid_sources[0x19]	154440	1			T4	15		T9	7		T29	9
valid_sources[0x1a]	131834	1			T4	12		T29	3		T50	2
valid_sources[0x1b]	152023	1			T3	4		T4	17		T9	1
valid_sources[0x1c]	144968	1			T3	2		T4	20		T8	1614
valid_sources[0x1d]	148699	1			T2	8		T4	15		T29	2
valid_sources[0x1e]	147006	1			T4	17		T29	22		T50	3
valid_sources[0x1f]	175024	1			T3	1		T4	16		T8	1865
valid_sources[0x20]	153974	1			T3	3		T4	19		T6	3642
valid_sources[0x21]	134700	1			T2	8		T3	2		T4	22
valid_sources[0x22]	143225	1			T3	1		T4	24		T9	6
valid_sources[0x23]	160447	1			T1	1		T3	2		T4	19
valid_sources[0x24]	137227	1			T1	2		T2	1		T3	2
valid_sources[0x25]	149227	1			T1	1		T3	2		T4	20
valid_sources[0x26]	138624	1			T3	1		T4	25		T29	2
valid_sources[0x27]	143646	1			T1	1		T4	33		T29	2
valid_sources[0x28]	151023	1			T4	24		T5	1		T9	10
valid_sources[0x29]	174145	1			T1	1		T2	1		T3	3
valid_sources[0x2a]	151521	1			T1	1		T3	2		T4	23
valid_sources[0x2b]	137220	1			T4	24		T5	1		T29	2
valid_sources[0x2c]	146106	1			T1	1		T4	20		T29	1
valid_sources[0x2d]	148715	1			T2	4		T4	18		T29	11
valid_sources[0x2e]	149192	1			T4	19		T29	13		T78	4
valid_sources[0x2f]	157811	1			T1	1		T3	2		T4	15
valid_sources[0x30]	135672	1			T2	6		T4	25		T9	5
valid_sources[0x31]	151007	1			T4	14		T8	198		T9	2
valid_sources[0x32]	152796	1			T3	1		T4	27		T9	3
valid_sources[0x33]	156896	1			T2	1		T3	1		T4	23
valid_sources[0x34]	147527	1			T3	3		T4	16		T49	2
valid_sources[0x35]	143783	1			T3	1		T4	18		T5	1
valid_sources[0x36]	137408	1			T4	21		T29	13		T50	3
valid_sources[0x37]	155736	1			T4	15		T5	1		T29	26
valid_sources[0x38]	139029	1			T3	3		T4	20		T49	5
valid_sources[0x39]	145444	1			T3	1		T4	11		T8	1082
valid_sources[0x3a]	142952	1			T1	1		T3	1		T4	24
valid_sources[0x3b]	137257	1			T2	5		T4	19		T9	25
valid_sources[0x3c]	149227	1			T2	1		T3	2		T4	21
valid_sources[0x3d]	151254	1			T3	2		T4	11		T9	10
valid_sources[0x3e]	132758	1			T4	12		T29	15		T49	1
valid_sources[0x3f]	145292	1			T4	20		T5	1		T9	2
valid_sources[0x40]	266904	1			T1	1		T3	1		T4	18
valid_sources[0x41]	142166	1			T2	1		T3	1		T4	29
valid_sources[0x42]	139609	1			T2	4		T4	15		T8	1564
valid_sources[0x43]	136934	1			T4	23		T9	6		T50	7
valid_sources[0x44]	160726	1			T3	1		T4	20		T5	46
valid_sources[0x45]	135247	1			T2	1		T4	12		T29	22
valid_sources[0x46]	153790	1			T1	1		T3	1		T4	19
valid_sources[0x47]	145900	1			T2	3		T4	18		T50	3
valid_sources[0x48]	150536	1			T4	18		T8	2484		T9	2
valid_sources[0x49]	159405	1			T3	1		T4	27		T5	48
valid_sources[0x4a]	141162	1			T4	38		T29	12		T50	2
valid_sources[0x4b]	151365	1			T2	2		T4	19		T9	2
valid_sources[0x4c]	146695	1			T4	18		T9	3		T29	16
valid_sources[0x4d]	150962	1			T4	26		T50	2		T66	1
valid_sources[0x4e]	148614	1			T3	1		T4	22		T5	97
valid_sources[0x4f]	128091	1			T3	1		T4	19		T5	1
valid_sources[0x50]	145556	1			T3	1		T4	20		T50	8
valid_sources[0x51]	152165	1			T1	1		T2	1		T3	2
valid_sources[0x52]	133685	1			T3	2		T4	8		T9	16
valid_sources[0x53]	142799	1			T2	2		T3	1		T4	17
valid_sources[0x54]	159318	1			T3	3		T4	13		T8	2584
valid_sources[0x55]	157206	1			T3	1		T4	25		T29	4
valid_sources[0x56]	147951	1			T2	2		T3	1		T4	31
valid_sources[0x57]	156775	1			T1	1		T4	20		T5	1
valid_sources[0x58]	139037	1			T4	18		T9	16		T50	5
valid_sources[0x59]	139533	1			T3	5		T4	15		T5	1
valid_sources[0x5a]	143166	1			T3	1		T4	23		T8	1640
valid_sources[0x5b]	146880	1			T3	1		T4	9		T9	10
valid_sources[0x5c]	154565	1			T4	31		T49	2		T50	11
valid_sources[0x5d]	142275	1			T4	10		T50	2		T69	9
valid_sources[0x5e]	185620	1			T1	1		T3	1		T4	17
valid_sources[0x5f]	164112	1			T2	11		T3	1		T4	29
valid_sources[0x60]	151091	1			T4	9		T9	37		T50	2
valid_sources[0x61]	143458	1			T4	8		T50	3		T77	2
valid_sources[0x62]	130893	1			T3	1		T4	27		T9	3
valid_sources[0x63]	154579	1			T4	19		T10	130		T29	12
valid_sources[0x64]	152202	1			T3	1		T4	11		T5	45
valid_sources[0x65]	146280	1			T4	18		T9	1		T29	3
valid_sources[0x66]	145637	1			T2	1		T4	25		T5	14
valid_sources[0x67]	158625	1			T4	8		T29	7		T50	4
valid_sources[0x68]	161872	1			T4	18		T29	7		T49	1
valid_sources[0x69]	156593	1			T2	1		T3	2		T4	20
valid_sources[0x6a]	163931	1			T3	3		T4	21		T29	6
valid_sources[0x6b]	163488	1			T3	3		T4	17		T8	706
valid_sources[0x6c]	137912	1			T4	15		T7	84		T29	1
valid_sources[0x6d]	161278	1			T4	18		T29	9		T50	3
valid_sources[0x6e]	154952	1			T1	1		T3	2		T4	12
valid_sources[0x6f]	146874	1			T2	2		T3	1		T4	22
valid_sources[0x70]	130723	1			T2	2		T3	2		T4	20
valid_sources[0x71]	149067	1			T2	1		T4	21		T29	3
valid_sources[0x72]	136776	1			T3	1		T4	10		T9	1
valid_sources[0x73]	146332	1			T2	1		T4	26		T8	2160
valid_sources[0x74]	146503	1			T3	2		T4	21		T29	7
valid_sources[0x75]	188314	1			T3	2		T4	14		T50	6
valid_sources[0x76]	170695	1			T3	2		T4	19		T50	2
valid_sources[0x77]	151687	1			T2	1		T3	1		T4	21
valid_sources[0x78]	152275	1			T4	19		T5	45		T9	10
valid_sources[0x79]	127389	1			T3	1		T4	20		T9	7
valid_sources[0x7a]	146351	1			T4	11		T9	4		T29	10
valid_sources[0x7b]	156564	1			T3	1		T4	16		T49	1
valid_sources[0x7c]	148308	1			T2	1		T4	21		T9	5
valid_sources[0x7d]	162802	1			T3	2		T4	24		T29	9
valid_sources[0x7e]	139735	1			T3	1		T4	19		T50	1
valid_sources[0x7f]	157878	1			T2	7		T3	2		T4	22
valid_sources[0x80]	151332	1			T4	25		T29	22		T77	11

---

Summary for Cross tl_a_chan_cov_cg_cc

Samples crossed: cp_opcode cp_mask cp_size

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	3	0	3	100.00

Automatically Generated Cross Bins for tl_a_chan_cov_cg_cc

Bins

cp_opcode

cp_mask

cp_size

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

values[0x4]

all_enables

biggest_size

7738511

1

T1

9

T3

49

T4

1287

values[0x0]

all_enables

biggest_size

216912

1

T1

4

T2

20

T3

7

values[0x1]

all_enables

biggest_size

148979

1

T2

25

T3

5

T4

12