Unified Coverage Report :: Module :: i2c_csr_assert_fpv

Module : i2c_csr_assert_fpv

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
93.75						93.75

Source File(s) :
/workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/i2c-sim-vcs/default/sim-vcs/../src/lowrisc_fpv_i2c_csr_assert_0/i2c_csr_assert_fpv.sv

Module self-instances :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
tb.dut.i2c_csr_assert	93.75						93.75

---

Module Instance : tb.dut.i2c_csr_assert

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
93.75						93.75

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
93.75						93.75

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
98.48	100.00	100.00	93.91			100.00	dut

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Since this is the module's only instance, the coverage report is the same as for the module.

Assert Coverage for Module : i2c_csr_assert_fpv

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	16	16	100.00	15	93.75
Cover properties	0	0		0
Cover sequences	0	0		0
Total	16	16	100.00	15	93.75

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
TlulOOBAddrErr_A	412438602	0	0	0
ctrl_rd_A	412438602	1726	0	0
host_fifo_config_rd_A	412438602	3315	0	0
host_nack_handler_timeout_rd_A	412438602	980	0	0
host_timeout_ctrl_rd_A	412438602	751	0	0
intr_enable_rd_A	412438602	3195	0	0
ovrd_rd_A	412438602	1856	0	0
target_fifo_config_rd_A	412438602	999	0	0
target_id_rd_A	412438602	1374	0	0
target_timeout_ctrl_rd_A	412438602	1025	0	0
timeout_ctrl_rd_A	412438602	1078	0	0
timing0_rd_A	412438602	923	0	0
timing1_rd_A	412438602	908	0	0
timing2_rd_A	412438602	1033	0	0
timing3_rd_A	412438602	888	0	0
timing4_rd_A	412438602	1021	0	0

TlulOOBAddrErr_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	412438602	0	0	0

ctrl_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	412438602	1726	0	0
T110	5553	122	0	0
T111	1944	4	0	0
T112	2779	22	0	0
T113	5679	88	0	0
T114	13817	363	0	0
T115	5465	22	0	0
T116	2775	9	0	0
T117	7144	143	0	0
T118	3209	5	0	0
T119	2629	60	0	0

host_fifo_config_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	412438602	3315	0	0
T37	16863	0	0	0
T90	307518	62	0	0
T120	0	138	0	0
T121	0	277	0	0
T122	0	198	0	0
T123	0	257	0	0
T124	0	327	0	0
T125	0	66	0	0
T126	0	51	0	0
T127	0	125	0	0
T128	0	141	0	0
T129	225588	0	0	0
T130	14021	0	0	0
T131	116588	0	0	0
T132	22197	0	0	0
T133	9122	0	0	0
T134	46998	0	0	0
T135	64997	0	0	0
T136	43788	0	0	0

host_nack_handler_timeout_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	412438602	980	0	0
T110	5553	113	0	0
T112	2779	10	0	0
T113	5679	121	0	0
T114	13817	144	0	0
T115	5465	23	0	0
T116	2775	17	0	0
T117	7144	50	0	0
T118	3209	7	0	0
T119	2629	14	0	0
T137	1435	8	0	0

host_timeout_ctrl_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	412438602	751	0	0
T110	5553	76	0	0
T112	2779	2	0	0
T113	5679	94	0	0
T114	13817	87	0	0
T115	5465	64	0	0
T116	2775	2	0	0
T117	7144	35	0	0
T118	3209	3	0	0
T119	2629	8	0	0
T137	1435	5	0	0

intr_enable_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	412438602	3195	0	0
T110	0	112	0	0
T124	0	10	0	0
T127	0	5	0	0
T138	166124	36	0	0
T139	0	73	0	0
T140	0	11	0	0
T141	0	11	0	0
T142	0	5	0	0
T143	0	6	0	0
T144	0	18	0	0
T145	144041	0	0	0
T146	105422	0	0	0
T147	54874	0	0	0
T148	1707	0	0	0
T149	50541	0	0	0
T150	10278	0	0	0
T151	316256	0	0	0
T152	458798	0	0	0
T153	12642	0	0	0

ovrd_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	412438602	1856	0	0
T73	52715	0	0	0
T154	1685	63	0	0
T155	0	52	0	0
T156	0	59	0	0
T157	0	52	0	0
T158	0	46	0	0
T159	0	43	0	0
T160	0	66	0	0
T161	0	59	0	0
T162	0	35	0	0
T163	0	80	0	0
T164	43740	0	0	0
T165	58654	0	0	0
T166	32688	0	0	0
T167	12059	0	0	0
T168	60522	0	0	0
T169	106793	0	0	0
T170	549200	0	0	0
T171	5423	0	0	0

target_fifo_config_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	412438602	999	0	0
T110	5553	129	0	0
T111	1944	9	0	0
T112	2779	23	0	0
T113	5679	102	0	0
T114	13817	95	0	0
T115	5465	34	0	0
T116	2775	7	0	0
T117	7144	81	0	0
T118	3209	11	0	0
T119	2629	9	0	0

target_id_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	412438602	1374	0	0
T110	5553	136	0	0
T111	1944	8	0	0
T112	2779	27	0	0
T113	5679	100	0	0
T114	13817	218	0	0
T115	5465	47	0	0
T116	2775	5	0	0
T117	7144	75	0	0
T118	3209	13	0	0
T137	1435	14	0	0

target_timeout_ctrl_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	412438602	1025	0	0
T110	5553	126	0	0
T111	1944	3	0	0
T112	2779	16	0	0
T113	5679	92	0	0
T114	13817	110	0	0
T115	5465	31	0	0
T116	2775	7	0	0
T117	7144	57	0	0
T118	3209	8	0	0
T137	1435	7	0	0

timeout_ctrl_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	412438602	1078	0	0
T110	5553	125	0	0
T112	2779	17	0	0
T113	5679	67	0	0
T114	13817	122	0	0
T115	5465	18	0	0
T116	2775	7	0	0
T117	7144	80	0	0
T118	3209	20	0	0
T119	2629	13	0	0
T137	1435	18	0	0

timing0_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	412438602	923	0	0
T110	5553	115	0	0
T111	1944	4	0	0
T112	2779	6	0	0
T113	5679	86	0	0
T114	13817	122	0	0
T115	5465	37	0	0
T116	2775	7	0	0
T117	7144	68	0	0
T118	3209	21	0	0
T119	2629	8	0	0

timing1_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	412438602	908	0	0
T110	5553	121	0	0
T112	2779	11	0	0
T113	5679	131	0	0
T114	13817	125	0	0
T115	5465	19	0	0
T116	2775	13	0	0
T117	7144	61	0	0
T118	3209	2	0	0
T119	2629	16	0	0
T137	1435	8	0	0

timing2_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	412438602	1033	0	0
T110	5553	101	0	0
T112	2779	16	0	0
T113	5679	102	0	0
T114	13817	145	0	0
T115	5465	54	0	0
T116	2775	7	0	0
T117	7144	52	0	0
T118	3209	13	0	0
T119	2629	11	0	0
T137	1435	2	0	0

timing3_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	412438602	888	0	0
T110	5553	113	0	0
T112	2779	5	0	0
T113	5679	103	0	0
T114	13817	121	0	0
T115	5465	64	0	0
T116	2775	11	0	0
T117	7144	48	0	0
T118	3209	6	0	0
T119	2629	14	0	0
T172	6251	13	0	0

timing4_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	412438602	1021	0	0
T110	5553	116	0	0
T112	2779	16	0	0
T113	5679	89	0	0
T114	13817	111	0	0
T115	5465	53	0	0
T116	2775	5	0	0
T117	7144	54	0	0
T118	3209	14	0	0
T119	2629	10	0	0
T137	1435	9	0	0