Unified Coverage Report :: Group :: tb.dut.u_i2c_protocol_cov::i2c_cmd_complete_cg

Group : tb.dut.u_i2c_protocol_cov::i2c_cmd_complete_cg

SCORE	INSTANCES	WEIGHT	GOAL	AT LEAST	PER INSTANCE	AUTO BIN MAX	PRINT MISSING
100.00	100.00	1	100	1	1	64	64

Source File(s) :
/workspaces/repo/scratch/os_regression_2024_08_22/i2c-sim-vcs/default/sim-vcs/../src/lowrisc_dv_i2c_sva_0.1/i2c_protocol_cov.sv

1 Instances:

NAME	SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
i2c_protocol_cov.unnamed$$_0.cmd_complete_cg	100.00	1	100	1	64	64

---

Group Instance : i2c_protocol_cov.unnamed$$_0.cmd_complete_cg

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
100.00	1	100	1	64	64

---

Summary for Group Instance i2c_protocol_cov.unnamed$$_0.cmd_complete_cg

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	3	0	3	100.00
Crosses	4	0	4	100.00

Variables for Group Instance i2c_protocol_cov.unnamed$$_0.cmd_complete_cg

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
cp_cmd_complete	1	0	1	100.00	100	1	1	0
cp_ip_mode	2	0	2	100.00	100	1	1	0

Crosses for Group Instance i2c_protocol_cov.unnamed$$_0.cmd_complete_cg

CROSS	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	PRINT MISSING	COMMENT
cp_read_x_complete	2	0	2	100.00	100	1	1	0
cp_write_x_complete	2	0	2	100.00	100	1	1	0

Summary for Variable cp_cmd_complete

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	1	0	1	100.00

User Defined Bins for cp_cmd_complete

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

complete

1548

1

T4

1

T5

1

T6

1

---

Summary for Variable cp_ip_mode

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	2	0	2	100.00

User Defined Bins for cp_ip_mode

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

device

993

1

T6

1

T8

1

T9

1

host

555

1

T4

1

T5

1

T7

1

---

Summary for Cross cp_read_x_complete

Samples crossed: cp_cmd_complete cp_ip_mode

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	2	0	2	100.00

Automatically Generated Cross Bins for cp_read_x_complete

Bins

cp_cmd_complete

cp_ip_mode

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

complete

device

412

1

T8

1

T75

1

T77

1

complete

host

242

1

T5

1

T27

1

T49

1

---

Summary for Cross cp_write_x_complete

Samples crossed: cp_cmd_complete cp_ip_mode

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	2	0	2	100.00

Automatically Generated Cross Bins for cp_write_x_complete

Bins

cp_cmd_complete

cp_ip_mode

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

complete

device

545

1

T6

1

T9

1

T10

1

complete

host

313

1

T4

1

T7

1

T14

1