Unified Coverage Report :: Group :: tl_agent_pkg::tl_a_chan_cov_cg::SHAPE{(2 << ((valid_source_width - 1) - 1))=128}

Group : tl_agent_pkg::tl_a_chan_cov_cg::SHAPE{(2 << ((valid_source_width - 1) - 1))=128}

SCORE	INSTANCES	WEIGHT	GOAL	AT LEAST	PER INSTANCE	AUTO BIN MAX	PRINT MISSING
100.00	100.00	1	100	1	1	64	64

Source File(s) :
/workspaces/repo/scratch/os_regression_2024_08_22/i2c-sim-vcs/default/sim-vcs/../src/lowrisc_dv_tl_agent_0/tl_agent_cov.sv

1 Instances:

NAME	SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
tl_agent_pkg.uvm_test_top.env.m_tl_agent_i2c_reg_block.cov::m_tl_a_chan_cov_cg	100.00	1	100	1	64	64

---

Group Instance : tl_agent_pkg.uvm_test_top.env.m_tl_agent_i2c_reg_block.cov::m_tl_a_chan_cov_cg

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
100.00	1	100	1	64	64

---

Summary for Group Instance tl_agent_pkg.uvm_test_top.env.m_tl_agent_i2c_reg_block.cov::m_tl_a_chan_cov_cg

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	134	0	134	100.00
Crosses	3	0	3	100.00

Variables for Group Instance tl_agent_pkg.uvm_test_top.env.m_tl_agent_i2c_reg_block.cov::m_tl_a_chan_cov_cg

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
cp_mask	1	0	1	100.00	100	1	1	0
cp_opcode	3	0	3	100.00	100	1	1	0
cp_size	1	0	1	100.00	100	1	1	0
cp_source	129	0	129	100.00	100	1	1	0

Crosses for Group Instance tl_agent_pkg.uvm_test_top.env.m_tl_agent_i2c_reg_block.cov::m_tl_a_chan_cov_cg

CROSS	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	PRINT MISSING	COMMENT
tl_a_chan_cov_cg_cc	3	0	3	100.00	100	1	1	0

Summary for Variable cp_mask

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	1	0	1	100.00

User Defined Bins for cp_mask

Excluded/Illegal bins

NAME	COUNT	STATUS
others	28753563	Excluded

Covered bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

all_enables

8743776

1

T1

14

T2

51

T3

89

---

Summary for Variable cp_opcode

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	3	0	3	100.00

User Defined Bins for cp_opcode

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
values[0x4]	36633556	1			T1	17		T2	123		T3	198
values[0x0]	432276	1			T1	12		T2	52		T3	59
values[0x1]	431507	1			T1	6		T2	63		T3	58

---

Summary for Variable cp_size

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	1	0	1	100.00

User Defined Bins for cp_size

Excluded/Illegal bins

NAME	COUNT	STATUS
others	20188187	Excluded

Covered bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

biggest_size

17309152

1

T1

17

T2

110

T3

160

---

Summary for Variable cp_source

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	129	0	129	100.00

User Defined Bins for cp_source

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
valid_sources[0x00]	140854	1			T4	1		T8	1		T10	2
valid_sources[0x01]	136506	1			T3	7		T4	2		T5	31
valid_sources[0x02]	161049	1			T4	3		T5	13		T10	7
valid_sources[0x03]	157297	1			T4	7		T5	31		T10	11
valid_sources[0x04]	144512	1			T3	3		T4	1		T5	23
valid_sources[0x05]	129059	1			T3	1		T4	2		T5	6
valid_sources[0x06]	138127	1			T4	1		T5	48		T10	10
valid_sources[0x07]	146366	1			T3	1		T4	2		T10	2
valid_sources[0x08]	139651	1			T4	6		T6	3		T10	1
valid_sources[0x09]	158777	1			T4	4		T5	19		T7	10160
valid_sources[0x0a]	142076	1			T3	1		T4	4		T5	16
valid_sources[0x0b]	145172	1			T2	36		T3	2		T4	7
valid_sources[0x0c]	148107	1			T4	1		T5	17		T10	6
valid_sources[0x0d]	146643	1			T4	6		T5	8		T10	2
valid_sources[0x0e]	136610	1			T3	2		T4	1		T5	50
valid_sources[0x0f]	158195	1			T4	4		T5	36		T10	1
valid_sources[0x10]	144583	1			T4	2		T5	22		T8	1
valid_sources[0x11]	155910	1			T4	2		T5	28		T6	1
valid_sources[0x12]	147972	1			T4	3		T5	26		T10	7
valid_sources[0x13]	154524	1			T4	2		T5	2		T10	5
valid_sources[0x14]	153201	1			T4	5		T5	68		T10	9
valid_sources[0x15]	138262	1			T4	4		T5	53		T10	4
valid_sources[0x16]	161101	1			T4	5		T6	2		T10	1
valid_sources[0x17]	133198	1			T4	6		T5	93		T8	1
valid_sources[0x18]	147761	1			T5	3		T8	1		T10	8
valid_sources[0x19]	147784	1			T3	1		T4	1		T5	10
valid_sources[0x1a]	140996	1			T4	7		T5	12		T10	4
valid_sources[0x1b]	154365	1			T3	2		T4	3		T5	19
valid_sources[0x1c]	141877	1			T4	3		T5	11		T6	1
valid_sources[0x1d]	149732	1			T4	2		T5	25		T8	2
valid_sources[0x1e]	141557	1			T5	12		T6	1		T10	3
valid_sources[0x1f]	145693	1			T4	7		T10	5		T50	1
valid_sources[0x20]	142269	1			T3	2		T4	7		T10	1
valid_sources[0x21]	155124	1			T4	7		T5	6		T8	1
valid_sources[0x22]	137043	1			T3	1		T4	4		T5	22
valid_sources[0x23]	179777	1			T4	4		T5	10		T10	7
valid_sources[0x24]	143609	1			T4	9		T5	98		T10	2
valid_sources[0x25]	137614	1			T2	54		T4	3		T5	53
valid_sources[0x26]	139271	1			T3	7		T4	5		T5	38
valid_sources[0x27]	151975	1			T4	1		T6	1		T10	5
valid_sources[0x28]	163865	1			T4	5		T5	6		T10	12
valid_sources[0x29]	131251	1			T4	2		T10	4		T75	9
valid_sources[0x2a]	155722	1			T4	2		T5	10		T10	4
valid_sources[0x2b]	160857	1			T1	11		T5	89		T10	14
valid_sources[0x2c]	147506	1			T4	1		T5	33		T6	2
valid_sources[0x2d]	134937	1			T3	1		T5	39		T75	6
valid_sources[0x2e]	138723	1			T4	10		T5	18		T10	2
valid_sources[0x2f]	153691	1			T4	1		T5	45		T6	1
valid_sources[0x30]	143855	1			T3	2		T4	5		T5	33
valid_sources[0x31]	136377	1			T2	10		T4	4		T5	5
valid_sources[0x32]	151920	1			T4	4		T5	5		T8	1
valid_sources[0x33]	156277	1			T4	1		T5	18		T10	16
valid_sources[0x34]	146859	1			T4	11		T5	10		T10	9
valid_sources[0x35]	140712	1			T4	8		T5	24		T10	1
valid_sources[0x36]	153452	1			T3	9		T4	3		T5	90
valid_sources[0x37]	154529	1			T5	5		T10	7		T75	15
valid_sources[0x38]	132027	1			T4	3		T5	22		T10	6
valid_sources[0x39]	166490	1			T4	1		T5	97		T6	2
valid_sources[0x3a]	138573	1			T4	4		T5	50		T10	13
valid_sources[0x3b]	147560	1			T4	3		T5	44		T75	7
valid_sources[0x3c]	143914	1			T3	10		T4	2		T5	19
valid_sources[0x3d]	148139	1			T10	6		T14	689		T50	1
valid_sources[0x3e]	142412	1			T3	2		T4	3		T10	8
valid_sources[0x3f]	161862	1			T4	5		T5	5		T10	3
valid_sources[0x40]	144168	1			T3	7		T4	4		T5	22
valid_sources[0x41]	145146	1			T4	2		T5	11		T10	4
valid_sources[0x42]	151699	1			T4	2		T5	3		T6	1
valid_sources[0x43]	139051	1			T3	1		T5	2		T6	1
valid_sources[0x44]	147154	1			T4	3		T10	10		T75	3
valid_sources[0x45]	139716	1			T4	3		T5	1		T10	6
valid_sources[0x46]	139533	1			T4	6		T5	46		T6	1
valid_sources[0x47]	147248	1			T4	6		T5	24		T6	1
valid_sources[0x48]	147350	1			T4	2		T5	78		T10	6
valid_sources[0x49]	137331	1			T4	3		T5	66		T10	5
valid_sources[0x4a]	137862	1			T3	25		T4	6		T5	71
valid_sources[0x4b]	145528	1			T3	1		T4	1		T10	4
valid_sources[0x4c]	137458	1			T3	15		T4	3		T5	67
valid_sources[0x4d]	155644	1			T4	1		T5	83		T10	2
valid_sources[0x4e]	156942	1			T3	1		T4	3		T6	1
valid_sources[0x4f]	146297	1			T4	1		T10	9		T75	3
valid_sources[0x50]	128540	1			T4	9		T5	42		T6	2
valid_sources[0x51]	135813	1			T4	8		T5	34		T10	1
valid_sources[0x52]	148396	1			T6	1		T10	9		T75	8
valid_sources[0x53]	155334	1			T3	1		T4	2		T10	5
valid_sources[0x54]	152736	1			T3	1		T4	1		T5	6
valid_sources[0x55]	145012	1			T4	1		T10	2		T75	4
valid_sources[0x56]	155470	1			T3	5		T10	1		T50	1
valid_sources[0x57]	137638	1			T4	4		T5	68		T10	8
valid_sources[0x58]	145230	1			T4	1		T5	32		T10	12
valid_sources[0x59]	155126	1			T3	1		T4	5		T5	15
valid_sources[0x5a]	144889	1			T4	3		T6	1		T10	6
valid_sources[0x5b]	141800	1			T4	9		T5	14		T10	2
valid_sources[0x5c]	136639	1			T4	2		T5	39		T10	9
valid_sources[0x5d]	134019	1			T4	1		T5	30		T10	13
valid_sources[0x5e]	141002	1			T2	34		T10	5		T50	5
valid_sources[0x5f]	142400	1			T4	2		T5	34		T6	1
valid_sources[0x60]	154087	1			T3	3		T4	1		T5	23
valid_sources[0x61]	147184	1			T4	6		T5	25		T8	1
valid_sources[0x62]	145548	1			T4	8		T5	48		T10	4
valid_sources[0x63]	132722	1			T4	6		T5	35		T10	13
valid_sources[0x64]	174468	1			T4	2		T5	10		T8	1
valid_sources[0x65]	171378	1			T1	8		T3	9		T4	6
valid_sources[0x66]	163742	1			T4	3		T14	507		T50	2
valid_sources[0x67]	142661	1			T4	2		T5	74		T10	7
valid_sources[0x68]	135076	1			T4	3		T5	15		T6	1
valid_sources[0x69]	140423	1			T3	6		T4	5		T5	9
valid_sources[0x6a]	142694	1			T4	1		T5	13		T10	5
valid_sources[0x6b]	140153	1			T5	2		T10	11		T75	9
valid_sources[0x6c]	160951	1			T3	8		T4	6		T5	103
valid_sources[0x6d]	155986	1			T4	1		T5	46		T50	2
valid_sources[0x6e]	162006	1			T4	1		T10	4		T50	1
valid_sources[0x6f]	152213	1			T3	1		T4	2		T5	17
valid_sources[0x70]	140797	1			T4	2		T10	10		T50	2
valid_sources[0x71]	152519	1			T4	2		T5	72		T75	1
valid_sources[0x72]	158057	1			T4	1		T10	4		T50	2
valid_sources[0x73]	159913	1			T4	5		T5	3		T10	10
valid_sources[0x74]	144565	1			T4	3		T10	1		T50	2
valid_sources[0x75]	155606	1			T3	2		T4	2		T10	3
valid_sources[0x76]	138972	1			T3	7		T4	1		T5	49
valid_sources[0x77]	149154	1			T4	1		T10	5		T75	4
valid_sources[0x78]	143735	1			T3	3		T4	4		T10	8
valid_sources[0x79]	147180	1			T4	2		T5	27		T10	13
valid_sources[0x7a]	136522	1			T4	3		T5	74		T10	5
valid_sources[0x7b]	145174	1			T3	15		T4	3		T5	45
valid_sources[0x7c]	140530	1			T4	3		T5	148		T6	1
valid_sources[0x7d]	136527	1			T3	1		T10	1		T75	13
valid_sources[0x7e]	148410	1			T5	22		T50	2		T76	81
valid_sources[0x7f]	159103	1			T4	3		T5	21		T10	1
valid_sources[0x80]	144635	1			T4	5		T8	1		T10	1

---

Summary for Cross tl_a_chan_cov_cg_cc

Samples crossed: cp_opcode cp_mask cp_size

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	3	0	3	100.00

Automatically Generated Cross Bins for tl_a_chan_cov_cg_cc

Bins

cp_opcode

cp_mask

cp_size

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

values[0x4]

all_enables

biggest_size

8361574

1

T1

10

T2

1

T3

19

values[0x0]

all_enables

biggest_size

227324

1

T1

4

T2

29

T3

39

values[0x1]

all_enables

biggest_size

154878

1

T2

21

T3

31

T4

6