Unified Coverage Report :: Module :: i2c_csr_assert_fpv

Module : i2c_csr_assert_fpv

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
93.75						93.75

Source File(s) :
/workspaces/repo/scratch/os_regression_2024_08_22/i2c-sim-vcs/default/sim-vcs/../src/lowrisc_fpv_i2c_csr_assert_0/i2c_csr_assert_fpv.sv

Module self-instances :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
tb.dut.i2c_csr_assert	93.75						93.75

---

Module Instance : tb.dut.i2c_csr_assert

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
93.75						93.75

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
93.75						93.75

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
98.48	100.00	100.00	93.91			100.00	dut

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Since this is the module's only instance, the coverage report is the same as for the module.

Assert Coverage for Module : i2c_csr_assert_fpv

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	16	16	100.00	15	93.75
Cover properties	0	0		0
Cover sequences	0	0		0
Total	16	16	100.00	15	93.75

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
TlulOOBAddrErr_A	404239748	0	0	0
ctrl_rd_A	404239748	2607	0	0
host_fifo_config_rd_A	404239748	4835	0	0
host_nack_handler_timeout_rd_A	404239748	1558	0	0
host_timeout_ctrl_rd_A	404239748	1273	0	0
intr_enable_rd_A	404239748	5713	0	0
ovrd_rd_A	404239748	2331	0	0
target_fifo_config_rd_A	404239748	1398	0	0
target_id_rd_A	404239748	1801	0	0
target_timeout_ctrl_rd_A	404239748	1462	0	0
timeout_ctrl_rd_A	404239748	1803	0	0
timing0_rd_A	404239748	1486	0	0
timing1_rd_A	404239748	1480	0	0
timing2_rd_A	404239748	1442	0	0
timing3_rd_A	404239748	1502	0	0
timing4_rd_A	404239748	1571	0	0

TlulOOBAddrErr_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	404239748	0	0	0

ctrl_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	404239748	2607	0	0
T111	2010	5	0	0
T112	3332	2	0	0
T113	3694	47	0	0
T114	1334	2	0	0
T115	14007	267	0	0
T116	5207	18	0	0
T117	1954	1	0	0
T118	9099	12	0	0
T119	14125	297	0	0
T120	2583	9	0	0

host_fifo_config_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	404239748	4835	0	0
T24	0	132	0	0
T59	752425	0	0	0
T70	71703	0	0	0
T88	301121	75	0	0
T90	0	242	0	0
T121	0	84	0	0
T122	0	232	0	0
T123	0	103	0	0
T124	0	225	0	0
T125	0	250	0	0
T126	0	146	0	0
T127	0	212	0	0
T128	22134	0	0	0
T129	21974	0	0	0
T130	128223	0	0	0
T131	64724	0	0	0
T132	21666	0	0	0
T133	174434	0	0	0
T134	27205	0	0	0

host_nack_handler_timeout_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	404239748	1558	0	0
T111	2010	3	0	0
T112	3332	23	0	0
T113	3694	7	0	0
T115	14007	127	0	0
T116	5207	27	0	0
T117	1954	4	0	0
T118	9099	15	0	0
T119	14125	118	0	0
T120	2583	12	0	0
T135	2459	14	0	0

host_timeout_ctrl_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	404239748	1273	0	0
T111	2010	6	0	0
T112	3332	12	0	0
T113	3694	29	0	0
T114	1334	5	0	0
T115	14007	84	0	0
T116	5207	2	0	0
T117	1954	2	0	0
T118	9099	17	0	0
T119	14125	81	0	0
T120	2583	11	0	0

intr_enable_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	404239748	5713	0	0
T111	0	10	0	0
T112	0	16	0	0
T113	0	20	0	0
T114	0	4	0	0
T115	0	816	0	0
T116	0	6	0	0
T125	175993	15	0	0
T136	0	23	0	0
T137	0	21	0	0
T138	0	1	0	0
T139	42808	0	0	0
T140	50201	0	0	0
T141	43519	0	0	0
T142	14690	0	0	0
T143	53143	0	0	0
T144	1547	0	0	0
T145	2371	0	0	0
T146	11568	0	0	0
T147	140361	0	0	0

ovrd_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	404239748	2331	0	0
T1	3084	34	0	0
T2	14410	0	0	0
T3	6058	0	0	0
T4	3381	0	0	0
T5	14722	0	0	0
T6	11092	0	0	0
T7	22174	0	0	0
T8	10362	0	0	0
T9	131062	0	0	0
T10	122148	0	0	0
T148	0	39	0	0
T149	0	43	0	0
T150	0	22	0	0
T151	0	74	0	0
T152	0	20	0	0
T153	0	32	0	0
T154	0	87	0	0
T155	0	24	0	0
T156	0	38	0	0

target_fifo_config_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	404239748	1398	0	0
T111	2010	2	0	0
T112	3332	1	0	0
T114	1334	3	0	0
T115	14007	80	0	0
T116	5207	20	0	0
T117	1954	9	0	0
T118	9099	25	0	0
T119	14125	104	0	0
T135	2459	10	0	0
T157	6156	22	0	0

target_id_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	404239748	1801	0	0
T111	2010	12	0	0
T112	3332	26	0	0
T113	3694	8	0	0
T115	14007	98	0	0
T116	5207	9	0	0
T117	1954	7	0	0
T118	9099	17	0	0
T119	14125	174	0	0
T120	2583	13	0	0
T135	2459	9	0	0

target_timeout_ctrl_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	404239748	1462	0	0
T111	2010	15	0	0
T112	3332	16	0	0
T113	3694	2	0	0
T115	14007	126	0	0
T116	5207	11	0	0
T118	9099	8	0	0
T119	14125	122	0	0
T120	2583	13	0	0
T135	2459	12	0	0
T157	6156	6	0	0

timeout_ctrl_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	404239748	1803	0	0
T111	2010	6	0	0
T112	3332	16	0	0
T113	3694	16	0	0
T114	1334	7	0	0
T115	14007	144	0	0
T116	5207	45	0	0
T117	1954	10	0	0
T118	9099	13	0	0
T119	14125	151	0	0
T120	2583	19	0	0

timing0_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	404239748	1486	0	0
T111	2010	15	0	0
T112	3332	32	0	0
T113	3694	17	0	0
T114	1334	5	0	0
T115	14007	132	0	0
T116	5207	24	0	0
T117	1954	3	0	0
T118	9099	16	0	0
T119	14125	137	0	0
T120	2583	19	0	0

timing1_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	404239748	1480	0	0
T111	2010	4	0	0
T112	3332	25	0	0
T113	3694	1	0	0
T115	14007	108	0	0
T116	5207	15	0	0
T117	1954	5	0	0
T118	9099	10	0	0
T119	14125	152	0	0
T120	2583	11	0	0
T135	2459	7	0	0

timing2_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	404239748	1442	0	0
T111	2010	4	0	0
T112	3332	30	0	0
T113	3694	6	0	0
T115	14007	126	0	0
T116	5207	27	0	0
T117	1954	10	0	0
T119	14125	132	0	0
T120	2583	13	0	0
T135	2459	9	0	0
T157	6156	11	0	0

timing3_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	404239748	1502	0	0
T111	2010	6	0	0
T112	3332	9	0	0
T113	3694	41	0	0
T115	14007	123	0	0
T116	5207	27	0	0
T117	1954	8	0	0
T118	9099	30	0	0
T119	14125	125	0	0
T120	2583	20	0	0
T135	2459	21	0	0

timing4_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	404239748	1571	0	0
T111	2010	2	0	0
T112	3332	17	0	0
T113	3694	7	0	0
T114	1334	8	0	0
T115	14007	133	0	0
T116	5207	26	0	0
T117	1954	5	0	0
T118	9099	13	0	0
T119	14125	91	0	0
T120	2583	26	0	0