Unified Coverage Report :: Group :: tl_agent_pkg::tl_a_chan_cov_cg::SHAPE{(2 << ((valid_source_width - 1) - 1))=128}

Group : tl_agent_pkg::tl_a_chan_cov_cg::SHAPE{(2 << ((valid_source_width - 1) - 1))=128}

SCORE	INSTANCES	WEIGHT	GOAL	AT LEAST	PER INSTANCE	AUTO BIN MAX	PRINT MISSING
100.00	100.00	1	100	1	1	64	64

Source File(s) :
/workspaces/repo/scratch/os_regression_2024_08_24/i2c-sim-vcs/default/sim-vcs/../src/lowrisc_dv_tl_agent_0/tl_agent_cov.sv

1 Instances:

NAME	SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
tl_agent_pkg.uvm_test_top.env.m_tl_agent_i2c_reg_block.cov::m_tl_a_chan_cov_cg	100.00	1	100	1	64	64

---

Group Instance : tl_agent_pkg.uvm_test_top.env.m_tl_agent_i2c_reg_block.cov::m_tl_a_chan_cov_cg

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
100.00	1	100	1	64	64

---

Summary for Group Instance tl_agent_pkg.uvm_test_top.env.m_tl_agent_i2c_reg_block.cov::m_tl_a_chan_cov_cg

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	134	0	134	100.00
Crosses	3	0	3	100.00

Variables for Group Instance tl_agent_pkg.uvm_test_top.env.m_tl_agent_i2c_reg_block.cov::m_tl_a_chan_cov_cg

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
cp_mask	1	0	1	100.00	100	1	1	0
cp_opcode	3	0	3	100.00	100	1	1	0
cp_size	1	0	1	100.00	100	1	1	0
cp_source	129	0	129	100.00	100	1	1	0

Crosses for Group Instance tl_agent_pkg.uvm_test_top.env.m_tl_agent_i2c_reg_block.cov::m_tl_a_chan_cov_cg

CROSS	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	PRINT MISSING	COMMENT
tl_a_chan_cov_cg_cc	3	0	3	100.00	100	1	1	0

Summary for Variable cp_mask

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	1	0	1	100.00

User Defined Bins for cp_mask

Excluded/Illegal bins

NAME	COUNT	STATUS
others	33121726	Excluded

Covered bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

all_enables

8447074

1

T1

9

T2

41

T3

406

---

Summary for Variable cp_opcode

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	3	0	3	100.00

User Defined Bins for cp_opcode

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
values[0x4]	40713449	1			T1	13		T2	106		T3	1242
values[0x0]	426928	1			T1	9		T2	55		T3	92
values[0x1]	428423	1			T1	4		T2	47		T3	85

---

Summary for Variable cp_size

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	1	0	1	100.00

User Defined Bins for cp_size

Excluded/Illegal bins

NAME	COUNT	STATUS
others	23104317	Excluded

Covered bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

biggest_size

18464483

1

T1

11

T2

94

T3

694

---

Summary for Variable cp_source

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	129	0	129	100.00

User Defined Bins for cp_source

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
valid_sources[0x00]	173799	1			T3	4		T5	23		T6	2
valid_sources[0x01]	158766	1			T5	23		T6	3		T19	17
valid_sources[0x02]	163395	1			T3	1		T5	21		T6	3
valid_sources[0x03]	174783	1			T3	7		T5	17		T6	4
valid_sources[0x04]	150144	1			T3	8		T5	23		T6	2
valid_sources[0x05]	163476	1			T3	15		T4	2		T5	22
valid_sources[0x06]	175801	1			T3	1		T5	19		T6	11
valid_sources[0x07]	159433	1			T3	14		T5	19		T6	1
valid_sources[0x08]	160347	1			T3	1		T5	14		T6	12
valid_sources[0x09]	156786	1			T3	4		T5	20		T6	3
valid_sources[0x0a]	155550	1			T3	9		T5	23		T6	8
valid_sources[0x0b]	160961	1			T3	9		T4	1		T5	19
valid_sources[0x0c]	162044	1			T4	2		T5	10		T6	5
valid_sources[0x0d]	148459	1			T1	3		T5	15		T6	7
valid_sources[0x0e]	167603	1			T1	1		T3	8		T5	23
valid_sources[0x0f]	159490	1			T3	6		T5	13		T6	4
valid_sources[0x10]	172410	1			T3	6		T4	1		T5	24
valid_sources[0x11]	156041	1			T3	15		T5	22		T6	2
valid_sources[0x12]	152935	1			T5	20		T6	5		T9	6
valid_sources[0x13]	156932	1			T3	8		T5	24		T6	5
valid_sources[0x14]	168146	1			T3	15		T5	21		T6	1
valid_sources[0x15]	178788	1			T1	2		T5	16		T6	6
valid_sources[0x16]	170535	1			T3	1		T5	16		T6	5
valid_sources[0x17]	158260	1			T3	3		T5	21		T6	3
valid_sources[0x18]	172847	1			T3	1		T4	1		T5	22
valid_sources[0x19]	160067	1			T5	26		T6	2		T19	10
valid_sources[0x1a]	159299	1			T3	5		T5	18		T6	4
valid_sources[0x1b]	165566	1			T5	17		T6	2		T19	6
valid_sources[0x1c]	183580	1			T3	1		T5	28		T6	6
valid_sources[0x1d]	169545	1			T5	15		T6	3		T19	20
valid_sources[0x1e]	154566	1			T3	2		T5	15		T6	6
valid_sources[0x1f]	215763	1			T3	2		T5	27		T6	1
valid_sources[0x20]	173624	1			T3	4		T4	2		T5	21
valid_sources[0x21]	166896	1			T1	3		T3	17		T5	18
valid_sources[0x22]	151471	1			T5	19		T6	9		T9	1
valid_sources[0x23]	171928	1			T3	10		T5	11		T6	2
valid_sources[0x24]	176891	1			T3	12		T5	22		T6	5
valid_sources[0x25]	161198	1			T5	29		T6	12		T45	3
valid_sources[0x26]	185531	1			T3	5		T5	14		T6	12
valid_sources[0x27]	153754	1			T3	6		T5	26		T6	2
valid_sources[0x28]	138489	1			T5	17		T19	27		T25	24
valid_sources[0x29]	167580	1			T3	1		T5	21		T6	17
valid_sources[0x2a]	161974	1			T3	14		T5	14		T6	2
valid_sources[0x2b]	177408	1			T3	8		T5	19		T6	2
valid_sources[0x2c]	162155	1			T1	1		T3	11		T4	3
valid_sources[0x2d]	164935	1			T3	7		T5	28		T6	8
valid_sources[0x2e]	176180	1			T3	8		T4	1		T5	26
valid_sources[0x2f]	148382	1			T3	4		T5	19		T6	1
valid_sources[0x30]	159952	1			T2	17		T3	13		T5	18
valid_sources[0x31]	138850	1			T5	19		T6	10		T45	1
valid_sources[0x32]	172584	1			T3	3		T5	17		T6	2
valid_sources[0x33]	173613	1			T3	4		T5	13		T6	5
valid_sources[0x34]	183127	1			T3	8		T5	20		T6	3
valid_sources[0x35]	152524	1			T5	27		T6	7		T19	25
valid_sources[0x36]	169992	1			T3	1		T5	28		T6	7
valid_sources[0x37]	165525	1			T5	20		T6	2		T9	1
valid_sources[0x38]	170991	1			T3	13		T5	24		T9	1
valid_sources[0x39]	171902	1			T3	4		T5	18		T6	3
valid_sources[0x3a]	167583	1			T3	6		T5	22		T6	7
valid_sources[0x3b]	151164	1			T3	6		T5	20		T6	8
valid_sources[0x3c]	163303	1			T3	8		T5	18		T6	1
valid_sources[0x3d]	143945	1			T5	19		T6	1		T19	9
valid_sources[0x3e]	178804	1			T3	4		T5	22		T6	7
valid_sources[0x3f]	156189	1			T3	4		T5	27		T6	4
valid_sources[0x40]	160506	1			T3	4		T5	19		T6	2
valid_sources[0x41]	166083	1			T3	8		T5	18		T6	12
valid_sources[0x42]	160958	1			T3	3		T5	19		T6	9
valid_sources[0x43]	171593	1			T3	11		T5	20		T6	1
valid_sources[0x44]	167265	1			T1	1		T3	10		T5	25
valid_sources[0x45]	153162	1			T3	6		T4	2		T5	30
valid_sources[0x46]	158032	1			T3	6		T5	17		T6	1
valid_sources[0x47]	163042	1			T3	1		T5	22		T6	5
valid_sources[0x48]	152289	1			T3	6		T5	16		T6	3
valid_sources[0x49]	143831	1			T3	6		T5	12		T6	12
valid_sources[0x4a]	192697	1			T5	28		T6	3		T19	23
valid_sources[0x4b]	163147	1			T3	8		T5	30		T6	12
valid_sources[0x4c]	165264	1			T4	1		T5	26		T6	3
valid_sources[0x4d]	171467	1			T3	5		T5	13		T6	3
valid_sources[0x4e]	162611	1			T3	1		T5	16		T6	2
valid_sources[0x4f]	166442	1			T3	9		T5	19		T6	3
valid_sources[0x50]	168854	1			T3	3		T5	29		T6	6
valid_sources[0x51]	149260	1			T3	14		T5	21		T6	5
valid_sources[0x52]	174784	1			T3	1		T4	1		T5	12
valid_sources[0x53]	152460	1			T5	21		T6	6		T45	3
valid_sources[0x54]	159722	1			T3	5		T4	1		T5	17
valid_sources[0x55]	171613	1			T3	6		T5	9		T6	4
valid_sources[0x56]	188826	1			T5	27		T25	14		T73	4
valid_sources[0x57]	156910	1			T1	1		T3	2		T5	29
valid_sources[0x58]	152712	1			T3	1		T5	12		T6	1
valid_sources[0x59]	158689	1			T4	1		T5	18		T6	1
valid_sources[0x5a]	148131	1			T4	1		T5	11		T6	2
valid_sources[0x5b]	151595	1			T5	30		T6	8		T70	3
valid_sources[0x5c]	157646	1			T3	9		T5	17		T6	4
valid_sources[0x5d]	152285	1			T3	1		T4	1		T5	16
valid_sources[0x5e]	162142	1			T3	5		T5	30		T6	3
valid_sources[0x5f]	154378	1			T3	24		T5	24		T6	5
valid_sources[0x60]	175750	1			T3	7		T4	2		T5	15
valid_sources[0x61]	154211	1			T3	1		T5	19		T6	2
valid_sources[0x62]	153959	1			T3	1		T4	1		T5	28
valid_sources[0x63]	166798	1			T3	7		T5	16		T6	12
valid_sources[0x64]	166717	1			T3	4		T5	23		T6	4
valid_sources[0x65]	160145	1			T1	1		T3	17		T4	2
valid_sources[0x66]	154413	1			T5	15		T6	3		T45	1
valid_sources[0x67]	150941	1			T3	2		T5	19		T6	8
valid_sources[0x68]	155272	1			T5	23		T6	1		T19	15
valid_sources[0x69]	158686	1			T3	10		T5	22		T6	2
valid_sources[0x6a]	143584	1			T3	5		T5	19		T6	8
valid_sources[0x6b]	160079	1			T3	10		T5	19		T6	12
valid_sources[0x6c]	180985	1			T3	16		T5	19		T6	8
valid_sources[0x6d]	165398	1			T3	1		T5	18		T6	5
valid_sources[0x6e]	151173	1			T3	9		T5	22		T6	7
valid_sources[0x6f]	166334	1			T3	13		T5	23		T6	1
valid_sources[0x70]	168175	1			T3	2		T5	13		T6	5
valid_sources[0x71]	173164	1			T3	5		T5	25		T6	5
valid_sources[0x72]	148953	1			T1	1		T3	11		T5	16
valid_sources[0x73]	163347	1			T3	9		T5	26		T6	6
valid_sources[0x74]	148584	1			T3	1		T4	1		T5	22
valid_sources[0x75]	161294	1			T3	6		T5	16		T6	5
valid_sources[0x76]	159143	1			T5	13		T6	3		T19	5
valid_sources[0x77]	153131	1			T3	9		T5	21		T6	6
valid_sources[0x78]	160523	1			T5	14		T6	7		T19	31
valid_sources[0x79]	159921	1			T1	1		T3	4		T5	21
valid_sources[0x7a]	184007	1			T3	5		T4	2		T5	16
valid_sources[0x7b]	152349	1			T3	4		T5	18		T6	7
valid_sources[0x7c]	154002	1			T2	23		T3	16		T5	19
valid_sources[0x7d]	158211	1			T3	3		T5	14		T6	1
valid_sources[0x7e]	153521	1			T2	1		T4	1		T5	21
valid_sources[0x7f]	148937	1			T3	7		T5	24		T6	5
valid_sources[0x80]	182187	1			T3	2		T5	14		T6	7

---

Summary for Cross tl_a_chan_cov_cg_cc

Samples crossed: cp_opcode cp_mask cp_size

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	3	0	3	100.00

Automatically Generated Cross Bins for tl_a_chan_cov_cg_cc

Bins

cp_opcode

cp_mask

cp_size

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

values[0x4]

all_enables

biggest_size

8071218

1

T1

6

T2

1

T3

274

values[0x0]

all_enables

biggest_size

223505

1

T1

2

T2

27

T3

67

values[0x1]

all_enables

biggest_size

152351

1

T1

1

T2

13

T3

65