Unified Coverage Report :: Module :: i2c_csr_assert_fpv

Module : i2c_csr_assert_fpv

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
93.75						93.75

Source File(s) :
/workspaces/repo/scratch/os_regression_2024_08_24/i2c-sim-vcs/default/sim-vcs/../src/lowrisc_fpv_i2c_csr_assert_0/i2c_csr_assert_fpv.sv

Module self-instances :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
tb.dut.i2c_csr_assert	93.75						93.75

---

Module Instance : tb.dut.i2c_csr_assert

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
93.75						93.75

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
93.75						93.75

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
98.48	100.00	100.00	93.91			100.00	dut

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Since this is the module's only instance, the coverage report is the same as for the module.

Assert Coverage for Module : i2c_csr_assert_fpv

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	16	16	100.00	15	93.75
Cover properties	0	0		0
Cover sequences	0	0		0
Total	16	16	100.00	15	93.75

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
TlulOOBAddrErr_A	439783268	0	0	0
ctrl_rd_A	439783268	2539	0	0
host_fifo_config_rd_A	439783268	3827	0	0
host_nack_handler_timeout_rd_A	439783268	1222	0	0
host_timeout_ctrl_rd_A	439783268	1036	0	0
intr_enable_rd_A	439783268	4580	0	0
ovrd_rd_A	439783268	2310	0	0
target_fifo_config_rd_A	439783268	1369	0	0
target_id_rd_A	439783268	1773	0	0
target_timeout_ctrl_rd_A	439783268	1468	0	0
timeout_ctrl_rd_A	439783268	1612	0	0
timing0_rd_A	439783268	1416	0	0
timing1_rd_A	439783268	1379	0	0
timing2_rd_A	439783268	1444	0	0
timing3_rd_A	439783268	1313	0	0
timing4_rd_A	439783268	1427	0	0

TlulOOBAddrErr_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	439783268	0	0	0

ctrl_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	439783268	2539	0	0
T107	11965	39	0	0
T108	13317	327	0	0
T109	9573	9	0	0
T110	2051	7	0	0
T111	10510	264	0	0
T112	8587	8	0	0
T113	5739	98	0	0
T114	16802	334	0	0
T115	2624	1	0	0
T116	2224	27	0	0

host_fifo_config_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	439783268	3827	0	0
T97	516284	209	0	0
T98	5739	0	0	0
T99	261701	0	0	0
T117	0	207	0	0
T118	0	149	0	0
T119	0	114	0	0
T120	0	248	0	0
T121	0	149	0	0
T122	0	117	0	0
T123	0	73	0	0
T124	0	207	0	0
T125	0	112	0	0
T126	15989	0	0	0
T127	56750	0	0	0
T128	92884	0	0	0
T129	87302	0	0	0
T130	34998	0	0	0
T131	42033	0	0	0
T132	256825	0	0	0

host_nack_handler_timeout_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	439783268	1222	0	0
T107	11965	24	0	0
T108	13317	122	0	0
T109	9573	16	0	0
T110	2051	4	0	0
T111	10510	263	0	0
T112	8587	51	0	0
T113	5739	30	0	0
T114	16802	87	0	0
T115	2624	2	0	0
T133	3112	15	0	0

host_timeout_ctrl_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	439783268	1036	0	0
T107	11965	54	0	0
T108	13317	62	0	0
T109	9573	24	0	0
T110	2051	1	0	0
T111	10510	247	0	0
T112	8587	7	0	0
T113	5739	6	0	0
T114	16802	91	0	0
T116	2224	3	0	0
T133	3112	29	0	0

intr_enable_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	439783268	4580	0	0
T107	0	27	0	0
T108	0	503	0	0
T109	0	28	0	0
T110	0	7	0	0
T111	0	239	0	0
T112	0	2	0	0
T113	0	58	0	0
T114	0	606	0	0
T121	0	22	0	0
T134	729696	2	0	0
T135	54383	0	0	0
T136	288631	0	0	0
T137	58469	0	0	0
T138	194479	0	0	0
T139	57777	0	0	0
T140	245307	0	0	0
T141	43582	0	0	0
T142	14064	0	0	0
T143	16945	0	0	0

ovrd_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	439783268	2310	0	0
T35	85540	0	0	0
T41	31519	0	0	0
T144	3077	41	0	0
T145	0	44	0	0
T146	0	58	0	0
T147	0	44	0	0
T148	0	61	0	0
T149	0	19	0	0
T150	0	49	0	0
T151	0	45	0	0
T152	0	61	0	0
T153	0	48	0	0
T154	101296	0	0	0
T155	11808	0	0	0
T156	13540	0	0	0
T157	16721	0	0	0
T158	1013	0	0	0
T159	6133	0	0	0
T160	294389	0	0	0

target_fifo_config_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	439783268	1369	0	0
T107	11965	44	0	0
T108	13317	89	0	0
T109	9573	46	0	0
T111	10510	243	0	0
T112	8587	32	0	0
T113	5739	85	0	0
T114	16802	107	0	0
T115	2624	3	0	0
T116	2224	8	0	0
T133	3112	11	0	0

target_id_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	439783268	1773	0	0
T107	11965	14	0	0
T108	13317	164	0	0
T109	9573	14	0	0
T110	2051	7	0	0
T111	10510	273	0	0
T112	8587	29	0	0
T113	5739	27	0	0
T114	16802	160	0	0
T115	2624	5	0	0
T116	2224	1	0	0

target_timeout_ctrl_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	439783268	1468	0	0
T107	11965	25	0	0
T108	13317	124	0	0
T109	9573	8	0	0
T110	2051	7	0	0
T111	10510	282	0	0
T112	8587	12	0	0
T113	5739	39	0	0
T114	16802	86	0	0
T133	3112	33	0	0
T161	3769	28	0	0

timeout_ctrl_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	439783268	1612	0	0
T107	11965	16	0	0
T108	13317	158	0	0
T109	9573	16	0	0
T111	10510	200	0	0
T112	8587	32	0	0
T113	5739	50	0	0
T114	16802	162	0	0
T133	3112	13	0	0
T161	3769	19	0	0
T162	9363	17	0	0

timing0_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	439783268	1416	0	0
T107	11965	43	0	0
T108	13317	122	0	0
T109	9573	28	0	0
T110	2051	7	0	0
T111	10510	262	0	0
T112	8587	4	0	0
T113	5739	82	0	0
T114	16802	93	0	0
T115	2624	10	0	0
T133	3112	11	0	0

timing1_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	439783268	1379	0	0
T107	11965	50	0	0
T108	13317	113	0	0
T109	9573	45	0	0
T110	2051	6	0	0
T111	10510	262	0	0
T112	8587	16	0	0
T113	5739	35	0	0
T114	16802	93	0	0
T133	3112	24	0	0
T161	3769	18	0	0

timing2_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	439783268	1444	0	0
T107	11965	23	0	0
T108	13317	126	0	0
T109	9573	35	0	0
T110	2051	7	0	0
T111	10510	239	0	0
T112	8587	35	0	0
T113	5739	77	0	0
T114	16802	133	0	0
T115	2624	8	0	0
T116	2224	7	0	0

timing3_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	439783268	1313	0	0
T107	11965	51	0	0
T108	13317	99	0	0
T109	9573	7	0	0
T111	10510	219	0	0
T112	8587	28	0	0
T113	5739	24	0	0
T114	16802	101	0	0
T115	2624	2	0	0
T116	2224	6	0	0
T133	3112	44	0	0

timing4_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	439783268	1427	0	0
T107	11965	7	0	0
T108	13317	118	0	0
T109	9573	13	0	0
T110	2051	2	0	0
T111	10510	278	0	0
T112	8587	51	0	0
T113	5739	41	0	0
T114	16802	93	0	0
T116	2224	1	0	0
T133	3112	24	0	0