Unified Coverage Report :: Group :: tl_agent_pkg::tl_a_chan_cov_cg::SHAPE{(2 << ((valid_source_width - 1) - 1))=128}

Group : tl_agent_pkg::tl_a_chan_cov_cg::SHAPE{(2 << ((valid_source_width - 1) - 1))=128}

SCORE	INSTANCES	WEIGHT	GOAL	AT LEAST	PER INSTANCE	AUTO BIN MAX	PRINT MISSING
100.00	100.00	1	100	1	1	64	64

Source File(s) :
/workspaces/repo/scratch/os_regression_2024_08_26/i2c-sim-vcs/default/sim-vcs/../src/lowrisc_dv_tl_agent_0/tl_agent_cov.sv

1 Instances:

NAME	SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
tl_agent_pkg.uvm_test_top.env.m_tl_agent_i2c_reg_block.cov::m_tl_a_chan_cov_cg	100.00	1	100	1	64	64

---

Group Instance : tl_agent_pkg.uvm_test_top.env.m_tl_agent_i2c_reg_block.cov::m_tl_a_chan_cov_cg

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
100.00	1	100	1	64	64

---

Summary for Group Instance tl_agent_pkg.uvm_test_top.env.m_tl_agent_i2c_reg_block.cov::m_tl_a_chan_cov_cg

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	134	0	134	100.00
Crosses	3	0	3	100.00

Variables for Group Instance tl_agent_pkg.uvm_test_top.env.m_tl_agent_i2c_reg_block.cov::m_tl_a_chan_cov_cg

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
cp_mask	1	0	1	100.00	100	1	1	0
cp_opcode	3	0	3	100.00	100	1	1	0
cp_size	1	0	1	100.00	100	1	1	0
cp_source	129	0	129	100.00	100	1	1	0

Crosses for Group Instance tl_agent_pkg.uvm_test_top.env.m_tl_agent_i2c_reg_block.cov::m_tl_a_chan_cov_cg

CROSS	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	PRINT MISSING	COMMENT
tl_a_chan_cov_cg_cc	3	0	3	100.00	100	1	1	0

Summary for Variable cp_mask

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	1	0	1	100.00

User Defined Bins for cp_mask

Excluded/Illegal bins

NAME	COUNT	STATUS
others	28008038	Excluded

Covered bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

all_enables

8149927

1

T1

79

T2

204

T3

24

---

Summary for Variable cp_opcode

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	3	0	3	100.00

User Defined Bins for cp_opcode

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
values[0x4]	35345803	1			T1	245		T2	648		T3	4932
values[0x0]	405644	1			T1	9		T2	72		T3	19
values[0x1]	406518	1			T1	9		T2	60		T3	16

---

Summary for Variable cp_size

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	1	0	1	100.00

User Defined Bins for cp_size

Excluded/Illegal bins

NAME	COUNT	STATUS
others	19628980	Excluded

Covered bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

biggest_size

16528985

1

T1

132

T2

385

T3

1225

---

Summary for Variable cp_source

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	129	0	129	100.00

User Defined Bins for cp_source

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
valid_sources[0x00]	152468	1			T3	20		T5	41		T8	2
valid_sources[0x01]	143407	1			T1	2		T2	1		T3	25
valid_sources[0x02]	141545	1			T1	1		T2	3		T3	10
valid_sources[0x03]	140586	1			T1	1		T2	2		T3	22
valid_sources[0x04]	144045	1			T2	1		T3	35		T5	21
valid_sources[0x05]	126772	1			T1	2		T2	3		T3	16
valid_sources[0x06]	145253	1			T2	1		T3	14		T5	11
valid_sources[0x07]	148883	1			T2	1		T3	11		T5	34
valid_sources[0x08]	135761	1			T1	2		T2	2		T3	32
valid_sources[0x09]	138412	1			T2	4		T3	17		T5	8
valid_sources[0x0a]	156321	1			T1	2		T2	3		T3	24
valid_sources[0x0b]	156056	1			T1	3		T2	3		T3	25
valid_sources[0x0c]	134922	1			T2	5		T3	9		T4	1
valid_sources[0x0d]	134875	1			T1	2		T2	1		T3	18
valid_sources[0x0e]	158147	1			T2	3		T3	16		T5	20
valid_sources[0x0f]	123836	1			T2	1		T3	18		T5	29
valid_sources[0x10]	134318	1			T2	2		T3	19		T5	7
valid_sources[0x11]	122649	1			T2	3		T3	11		T5	15
valid_sources[0x12]	141059	1			T1	2		T2	3		T3	18
valid_sources[0x13]	137680	1			T2	3		T3	10		T4	1
valid_sources[0x14]	130884	1			T2	2		T3	22		T5	29
valid_sources[0x15]	140416	1			T1	1		T2	2		T3	25
valid_sources[0x16]	143446	1			T1	1		T3	9		T5	56
valid_sources[0x17]	143044	1			T2	3		T3	3		T4	1
valid_sources[0x18]	133072	1			T2	2		T3	12		T5	30
valid_sources[0x19]	163136	1			T1	1		T2	2		T3	6
valid_sources[0x1a]	140361	1			T2	7		T3	17		T5	28
valid_sources[0x1b]	128108	1			T2	2		T3	6		T4	1
valid_sources[0x1c]	187608	1			T1	1		T2	5		T3	22
valid_sources[0x1d]	131677	1			T1	3		T2	5		T3	27
valid_sources[0x1e]	136408	1			T1	1		T2	5		T3	25
valid_sources[0x1f]	144049	1			T1	1		T2	2		T3	11
valid_sources[0x20]	133916	1			T1	1		T2	5		T3	12
valid_sources[0x21]	140579	1			T2	4		T3	22		T5	23
valid_sources[0x22]	138317	1			T2	5		T3	7		T5	15
valid_sources[0x23]	135299	1			T2	2		T3	39		T5	25
valid_sources[0x24]	183295	1			T2	4		T3	12		T5	25
valid_sources[0x25]	155487	1			T2	3		T3	18		T5	4
valid_sources[0x26]	130414	1			T1	6		T2	3		T3	18
valid_sources[0x27]	160070	1			T2	1		T3	5		T5	16
valid_sources[0x28]	145761	1			T2	4		T3	25		T5	28
valid_sources[0x29]	133605	1			T2	6		T3	22		T5	24
valid_sources[0x2a]	133475	1			T2	5		T3	14		T5	17
valid_sources[0x2b]	155435	1			T2	3		T3	16		T4	1
valid_sources[0x2c]	133653	1			T2	3		T3	21		T5	10
valid_sources[0x2d]	122280	1			T2	5		T3	8		T4	1
valid_sources[0x2e]	136686	1			T1	3		T2	2		T3	29
valid_sources[0x2f]	154556	1			T1	2		T2	1		T3	14
valid_sources[0x30]	133810	1			T2	2		T3	21		T4	1
valid_sources[0x31]	126785	1			T2	2		T3	25		T5	26
valid_sources[0x32]	140399	1			T2	2		T3	21		T5	36
valid_sources[0x33]	307050	1			T1	2		T3	8		T4	1
valid_sources[0x34]	128238	1			T2	2		T3	26		T5	38
valid_sources[0x35]	125828	1			T2	1		T3	20		T5	11
valid_sources[0x36]	145904	1			T2	2		T3	13		T4	2
valid_sources[0x37]	140659	1			T1	1		T3	25		T5	4
valid_sources[0x38]	154962	1			T1	3		T2	3		T3	14
valid_sources[0x39]	128108	1			T2	4		T3	29		T5	26
valid_sources[0x3a]	138023	1			T2	4		T3	17		T5	9
valid_sources[0x3b]	141077	1			T2	4		T3	30		T5	20
valid_sources[0x3c]	144037	1			T1	5		T2	2		T3	21
valid_sources[0x3d]	156858	1			T2	3		T3	18		T5	18
valid_sources[0x3e]	153962	1			T2	1		T3	18		T5	24
valid_sources[0x3f]	130309	1			T1	3		T2	2		T3	17
valid_sources[0x40]	146850	1			T1	1		T2	3		T3	20
valid_sources[0x41]	146869	1			T1	1		T2	2		T3	33
valid_sources[0x42]	142728	1			T2	3		T3	22		T5	19
valid_sources[0x43]	185351	1			T2	2		T3	33		T5	25
valid_sources[0x44]	156131	1			T2	2		T3	15		T4	1
valid_sources[0x45]	143842	1			T2	5		T3	34		T4	1
valid_sources[0x46]	140949	1			T2	1		T3	25		T5	28
valid_sources[0x47]	122329	1			T1	8		T2	6		T3	23
valid_sources[0x48]	139175	1			T1	6		T2	1		T3	22
valid_sources[0x49]	136433	1			T2	2		T3	29		T4	1
valid_sources[0x4a]	146841	1			T1	2		T2	7		T3	22
valid_sources[0x4b]	134951	1			T2	5		T3	14		T5	28
valid_sources[0x4c]	121711	1			T1	1		T2	2		T3	15
valid_sources[0x4d]	142541	1			T1	2		T2	4		T3	12
valid_sources[0x4e]	136375	1			T2	3		T3	16		T4	1
valid_sources[0x4f]	167800	1			T1	1		T2	1		T3	17
valid_sources[0x50]	138864	1			T2	7		T3	25		T5	47
valid_sources[0x51]	132747	1			T2	2		T3	18		T5	19
valid_sources[0x52]	137192	1			T2	2		T3	22		T5	23
valid_sources[0x53]	147753	1			T1	3		T3	22		T4	1
valid_sources[0x54]	145457	1			T2	4		T3	16		T5	17
valid_sources[0x55]	137268	1			T2	2		T3	32		T5	14
valid_sources[0x56]	143340	1			T2	3		T3	6		T5	12
valid_sources[0x57]	152461	1			T2	7		T3	27		T5	14
valid_sources[0x58]	143916	1			T2	2		T3	13		T5	17
valid_sources[0x59]	136586	1			T1	6		T2	2		T3	11
valid_sources[0x5a]	128354	1			T2	6		T3	16		T5	49
valid_sources[0x5b]	131815	1			T1	3		T2	1		T3	32
valid_sources[0x5c]	138593	1			T2	3		T3	19		T5	18
valid_sources[0x5d]	136671	1			T1	10		T2	2		T3	17
valid_sources[0x5e]	131892	1			T2	3		T3	23		T5	40
valid_sources[0x5f]	138742	1			T2	2		T3	14		T5	48
valid_sources[0x60]	149610	1			T1	8		T2	5		T3	12
valid_sources[0x61]	139377	1			T2	2		T3	19		T4	1
valid_sources[0x62]	170817	1			T1	3		T2	3		T3	16
valid_sources[0x63]	133723	1			T2	3		T3	17		T5	23
valid_sources[0x64]	147294	1			T1	1		T2	4		T3	11
valid_sources[0x65]	127899	1			T2	2		T3	34		T5	27
valid_sources[0x66]	124885	1			T1	1		T2	4		T3	15
valid_sources[0x67]	132169	1			T2	2		T3	42		T5	20
valid_sources[0x68]	134616	1			T1	3		T2	2		T3	18
valid_sources[0x69]	146394	1			T1	2		T2	4		T3	20
valid_sources[0x6a]	129620	1			T1	1		T2	8		T3	11
valid_sources[0x6b]	147540	1			T1	1		T3	6		T5	10
valid_sources[0x6c]	133530	1			T1	3		T2	1		T3	18
valid_sources[0x6d]	136917	1			T2	4		T3	13		T4	1
valid_sources[0x6e]	153692	1			T2	3		T3	35		T5	15
valid_sources[0x6f]	153453	1			T1	6		T2	4		T3	24
valid_sources[0x70]	132775	1			T2	7		T3	18		T5	9
valid_sources[0x71]	146182	1			T2	4		T3	23		T4	1
valid_sources[0x72]	145480	1			T1	5		T2	1		T3	14
valid_sources[0x73]	139053	1			T2	1		T3	37		T5	10
valid_sources[0x74]	134454	1			T2	5		T3	33		T5	40
valid_sources[0x75]	151688	1			T2	2		T3	17		T4	4
valid_sources[0x76]	141714	1			T1	4		T2	6		T3	28
valid_sources[0x77]	140474	1			T2	1		T3	25		T5	18
valid_sources[0x78]	126241	1			T1	1		T2	1		T3	24
valid_sources[0x79]	129628	1			T3	18		T5	46		T7	8
valid_sources[0x7a]	134458	1			T2	4		T3	10		T4	1
valid_sources[0x7b]	131796	1			T2	6		T3	3		T5	19
valid_sources[0x7c]	152919	1			T2	3		T3	27		T5	23
valid_sources[0x7d]	149776	1			T1	4		T3	23		T5	14
valid_sources[0x7e]	128064	1			T2	5		T3	20		T5	13
valid_sources[0x7f]	154769	1			T1	1		T3	30		T5	58
valid_sources[0x80]	132197	1			T3	21		T5	21		T7	5

---

Summary for Cross tl_a_chan_cov_cg_cc

Samples crossed: cp_opcode cp_mask cp_size

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	3	0	3	100.00

Automatically Generated Cross Bins for tl_a_chan_cov_cg_cc

Bins

cp_opcode

cp_mask

cp_size

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

values[0x4]

all_enables

biggest_size

7786002

1

T1

67

T2

116

T3

5

values[0x0]

all_enables

biggest_size

215472

1

T1

6

T2

54

T3

11

values[0x1]

all_enables

biggest_size

148453

1

T1

6

T2

34

T3

8