Unified Coverage Report :: Module :: i2c_fifos

Module : i2c_fifos

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
80.00	100.00				100.00	40.00

Source File(s) :
/workspaces/repo/scratch/os_regression_2024_08_26/i2c-sim-vcs/default/sim-vcs/../src/lowrisc_ip_i2c_0.1/rtl/i2c_fifos.sv

Module self-instances :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
tb.dut.i2c_core.u_fifos	80.00	100.00				100.00	40.00

---

Module Instance : tb.dut.i2c_core.u_fifos

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
80.00	100.00				100.00	40.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
93.75	99.86	83.33			98.32	93.48

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
92.58	97.74	79.23			93.33	100.00	i2c_core

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
u_acq_fifo_sram_adapter	95.85	100.00	84.91			98.51	100.00
u_fmt_fifo_sram_adapter	95.54	100.00	83.65			98.51	100.00
u_ram_1p	99.02	97.06				100.00	100.00
u_ram_arbiter	90.93	100.00	82.46			100.00	81.25
u_rx_fifo_sram_adapter	94.69	100.00	81.76			97.01	100.00
u_tx_fifo_sram_adapter	95.54	100.00	83.65			98.51	100.00

---

Since this is the module's only instance, the coverage report is the same as for the module.

Line Coverage for Module : i2c_fifos

	Line No.	Total	Covered	Percent
TOTAL		31	31	100.00
CONT_ASSIGN	114	1	1	100.00
CONT_ASSIGN	115	1	1	100.00
CONT_ASSIGN	147	1	1	100.00
CONT_ASSIGN	148	1	1	100.00
CONT_ASSIGN	150	1	1	100.00
CONT_ASSIGN	182	1	1	100.00
CONT_ASSIGN	183	1	1	100.00
CONT_ASSIGN	185	1	1	100.00
CONT_ASSIGN	217	1	1	100.00
CONT_ASSIGN	218	1	1	100.00
CONT_ASSIGN	220	1	1	100.00
CONT_ASSIGN	254	1	1	100.00
CONT_ASSIGN	255	1	1	100.00
CONT_ASSIGN	256	1	1	100.00
CONT_ASSIGN	257	1	1	100.00
CONT_ASSIGN	258	1	1	100.00
CONT_ASSIGN	259	1	1	100.00
CONT_ASSIGN	260	1	1	100.00
CONT_ASSIGN	261	1	1	100.00
CONT_ASSIGN	262	1	1	100.00
CONT_ASSIGN	263	1	1	100.00
CONT_ASSIGN	264	1	1	100.00
CONT_ASSIGN	265	1	1	100.00
ALWAYS	270	3	3	100.00
CONT_ASSIGN	276	1	1	100.00
CONT_ASSIGN	277	1	1	100.00
CONT_ASSIGN	278	1	1	100.00
CONT_ASSIGN	279	1	1	100.00
CONT_ASSIGN	304	1	1	100.00

113                       );
114        1/1            assign fmt_fifo_wdata = fmt_fifo_wdata_i;
           Tests:       T1 T2 T3 
115        1/1            assign fmt_fifo_rdata_o = fmt_fifo_rdata[FMT_FIFO_WIDTH-1:0];
           Tests:       T1 T2 T3 
116                     
117                       // RAM adapter for RX FIFO
118                       logic [RamWidth-1:0] rx_fifo_wdata, rx_fifo_rdata, rx_ram_wdata;
119                       logic rx_ram_req, rx_ram_gnt, rx_ram_write, rx_ram_rvalid;
120                       logic [RamAw-1:0] rx_ram_addr;
121                       i2c_fifo_sync_sram_adapter #(
122                         .Width       (RamWidth),
123                         .Depth       (FifoDepth),
124                         .SramAw      (RamAw),
125                         .SramBaseAddr(RxFifoRamBaseAddr)
126                       ) u_rx_fifo_sram_adapter (
127                         .clk_i,
128                         .rst_ni,
129                         .clr_i        (rx_fifo_clr_i),
130                         .fifo_wvalid_i(rx_fifo_wvalid_i),
131                         .fifo_wready_o(rx_fifo_wready_o),
132                         .fifo_wdata_i (rx_fifo_wdata),
133                         .fifo_rvalid_o(rx_fifo_rvalid_o),
134                         .fifo_rready_i(rx_fifo_rready_i),
135                         .fifo_rdata_o (rx_fifo_rdata),
136                         .fifo_depth_o (rx_fifo_depth_o),
137                         .sram_req_o   (rx_ram_req),
138                         .sram_gnt_i   (rx_ram_gnt),
139                         .sram_write_o (rx_ram_write),
140                         .sram_addr_o  (rx_ram_addr),
141                         .sram_wdata_o (rx_ram_wdata),
142                         .sram_wmask_o (/* unused */),
143                         .sram_rdata_i (ram_rdata),
144                         .sram_rvalid_i(rx_ram_rvalid),
145                         .err_o        (/* unused */)
146                       );
147        1/1            assign rx_fifo_wdata = {{(RamWidth - RX_FIFO_WIDTH){1'b0}}, rx_fifo_wdata_i};
           Tests:       T1 T2 T3 
148        1/1            assign rx_fifo_rdata_o = rx_fifo_rdata[RX_FIFO_WIDTH-1:0];
           Tests:       T1 T2 T3 
149                       logic unused_rx_fifo_rdata;
150        1/1            assign unused_rx_fifo_rdata = ^rx_fifo_rdata[(RamWidth-1):(RX_FIFO_WIDTH-1)];
           Tests:       T1 T2 T3 
151                     
152                       // RAM adapter for TX FIFO
153                       logic [RamWidth-1:0] tx_fifo_wdata, tx_fifo_rdata, tx_ram_wdata;
154                       logic tx_ram_req, tx_ram_gnt, tx_ram_write, tx_ram_rvalid;
155                       logic [RamAw-1:0] tx_ram_addr;
156                       i2c_fifo_sync_sram_adapter #(
157                         .Width       (RamWidth),
158                         .Depth       (FifoDepth),
159                         .SramAw      (RamAw),
160                         .SramBaseAddr(TxFifoRamBaseAddr)
161                       ) u_tx_fifo_sram_adapter (
162                         .clk_i,
163                         .rst_ni,
164                         .clr_i        (tx_fifo_clr_i),
165                         .fifo_wvalid_i(tx_fifo_wvalid_i),
166                         .fifo_wready_o(tx_fifo_wready_o),
167                         .fifo_wdata_i (tx_fifo_wdata),
168                         .fifo_rvalid_o(tx_fifo_rvalid_o),
169                         .fifo_rready_i(tx_fifo_rready_i),
170                         .fifo_rdata_o (tx_fifo_rdata),
171                         .fifo_depth_o (tx_fifo_depth_o),
172                         .sram_req_o   (tx_ram_req),
173                         .sram_gnt_i   (tx_ram_gnt),
174                         .sram_write_o (tx_ram_write),
175                         .sram_addr_o  (tx_ram_addr),
176                         .sram_wdata_o (tx_ram_wdata),
177                         .sram_wmask_o (/* unused */),
178                         .sram_rdata_i (ram_rdata),
179                         .sram_rvalid_i(tx_ram_rvalid),
180                         .err_o        (/* unused */)
181                       );
182        1/1            assign tx_fifo_wdata = {{(RamWidth - TX_FIFO_WIDTH){1'b0}}, tx_fifo_wdata_i};
           Tests:       T1 T2 T3 
183        1/1            assign tx_fifo_rdata_o = tx_fifo_rdata[TX_FIFO_WIDTH-1:0];
           Tests:       T1 T2 T3 
184                       logic unused_tx_fifo_rdata;
185        1/1            assign unused_tx_fifo_rdata = ^tx_fifo_rdata[(RamWidth-1):(TX_FIFO_WIDTH-1)];
           Tests:       T1 T2 T3 
186                     
187                       // RAM adapter for ACQ FIFO
188                       logic [RamWidth-1:0] acq_fifo_wdata, acq_fifo_rdata, acq_ram_wdata;
189                       logic acq_ram_req, acq_ram_gnt, acq_ram_write, acq_ram_rvalid;
190                       logic [RamAw-1:0] acq_ram_addr;
191                       i2c_fifo_sync_sram_adapter #(
192                         .Width       (RamWidth),
193                         .Depth       (AcqFifoDepth),
194                         .SramAw      (RamAw),
195                         .SramBaseAddr(AcqFifoRamBaseAddr)
196                       ) u_acq_fifo_sram_adapter (
197                         .clk_i,
198                         .rst_ni,
199                         .clr_i        (acq_fifo_clr_i),
200                         .fifo_wvalid_i(acq_fifo_wvalid_i),
201                         .fifo_wready_o(acq_fifo_wready_o),
202                         .fifo_wdata_i (acq_fifo_wdata),
203                         .fifo_rvalid_o(acq_fifo_rvalid_o),
204                         .fifo_rready_i(acq_fifo_rready_i),
205                         .fifo_rdata_o (acq_fifo_rdata),
206                         .fifo_depth_o (acq_fifo_depth_o),
207                         .sram_req_o   (acq_ram_req),
208                         .sram_gnt_i   (acq_ram_gnt),
209                         .sram_write_o (acq_ram_write),
210                         .sram_addr_o  (acq_ram_addr),
211                         .sram_wdata_o (acq_ram_wdata),
212                         .sram_wmask_o (/* unused */),
213                         .sram_rdata_i (ram_rdata),
214                         .sram_rvalid_i(acq_ram_rvalid),
215                         .err_o        (/* unused */)
216                       );
217        1/1            assign acq_fifo_wdata = {{(RamWidth - ACQ_FIFO_WIDTH){1'b0}}, acq_fifo_wdata_i};
           Tests:       T1 T2 T3 
218        1/1            assign acq_fifo_rdata_o = acq_fifo_rdata[ACQ_FIFO_WIDTH-1:0];
           Tests:       T1 T2 T3 
219                       logic unused_acq_fifo_rdata;
220        1/1            assign unused_acq_fifo_rdata = ^acq_fifo_rdata[(RamWidth-1):(ACQ_FIFO_WIDTH-1)];
           Tests:       T1 T2 T3 
221                     
222                       // RAM signals
223                       logic                ram_req,
224                                            ram_write,
225                                            ram_rvalid;
226                       logic [RamAw-1:0]    ram_addr;
227                       logic [RamWidth-1:0] ram_wdata;
228                     
229                       // RAM arbiter
230                       localparam int unsigned RamArbN = 4;
231                       localparam int unsigned RamArbIdxW = prim_util_pkg::vbits(RamArbN);
232                       // Data for arbiter consists of write bit, address, and write data
233                       localparam int unsigned RamArbDw = 1 + RamAw + RamWidth;
234                       logic [RamArbN-1:0] ram_arb_req, ram_arb_gnt;
235                       logic [RamArbIdxW-1:0] ram_arb_idx;
236                       logic [RamArbDw-1:0] ram_arb_inp_data[RamArbN];
237                       logic [RamArbDw-1:0] ram_arb_oup_data;
238                       prim_arbiter_tree #(
239                         .N         (RamArbN),
240                         .DW        (RamArbDw),
241                         .EnDataPort(1)
242                       ) u_ram_arbiter (
243                         .clk_i,
244                         .rst_ni,
245                         .req_chk_i(1'b1),
246                         .req_i    (ram_arb_req),
247                         .data_i   (ram_arb_inp_data),
248                         .gnt_o    (ram_arb_gnt),
249                         .idx_o    (ram_arb_idx),
250                         .valid_o  (ram_req),
251                         .data_o   (ram_arb_oup_data),
252                         .ready_i  (1'b1)
253                       );
254        1/1            assign ram_arb_req[0] = fmt_ram_req;
           Tests:       T1 T2 T3 
255        1/1            assign ram_arb_inp_data[0] = {fmt_ram_write, fmt_ram_addr, fmt_ram_wdata};
           Tests:       T1 T2 T3 
256        1/1            assign fmt_ram_gnt = ram_arb_gnt[0];
           Tests:       T1 T2 T3 
257        1/1            assign ram_arb_req[1] = rx_ram_req;
           Tests:       T1 T2 T3 
258        1/1            assign ram_arb_inp_data[1] = {rx_ram_write, rx_ram_addr, rx_ram_wdata};
           Tests:       T1 T2 T3 
259        1/1            assign rx_ram_gnt = ram_arb_gnt[1];
           Tests:       T1 T2 T3 
260        1/1            assign ram_arb_req[2] = tx_ram_req;
           Tests:       T1 T2 T3 
261        1/1            assign ram_arb_inp_data[2] = {tx_ram_write, tx_ram_addr, tx_ram_wdata};
           Tests:       T1 T2 T3 
262        1/1            assign tx_ram_gnt = ram_arb_gnt[2];
           Tests:       T1 T2 T3 
263        1/1            assign ram_arb_req[3] = acq_ram_req;
           Tests:       T1 T2 T3 
264        1/1            assign ram_arb_inp_data[3] = {acq_ram_write, acq_ram_addr, acq_ram_wdata};
           Tests:       T1 T2 T3 
265        1/1            assign acq_ram_gnt = ram_arb_gnt[3];
           Tests:       T1 T2 T3 
266                     
267                       // Demux `ram_rvalid` based on arbiter index one cycle earlier.
268                       logic [RamArbIdxW-1:0] ram_arb_idx_q;
269                       always_ff @(posedge clk_i or negedge rst_ni) begin
270        1/1              if (!rst_ni) begin
           Tests:       T1 T2 T3 
271        1/1                ram_arb_idx_q <= '0;
           Tests:       T1 T2 T3 
272                         end else begin
273        1/1                ram_arb_idx_q <= ram_arb_idx;
           Tests:       T1 T2 T3 
274                         end
275                       end
276        1/1            assign fmt_ram_rvalid = (ram_arb_idx_q == unsigned'(RamArbIdxW'(0))) && ram_rvalid;
           Tests:       T1 T2 T3 
277        1/1            assign rx_ram_rvalid  = (ram_arb_idx_q == unsigned'(RamArbIdxW'(1))) && ram_rvalid;
           Tests:       T1 T2 T3 
278        1/1            assign tx_ram_rvalid  = (ram_arb_idx_q == unsigned'(RamArbIdxW'(2))) && ram_rvalid;
           Tests:       T1 T2 T3 
279        1/1            assign acq_ram_rvalid = (ram_arb_idx_q == unsigned'(RamArbIdxW'(3))) && ram_rvalid;
           Tests:       T1 T2 T3 
280                     
281                       // RAM instance
282                       prim_ram_1p_adv #(
283                         .Depth               (RamDepth),
284                         .Width               (RamWidth),
285                         .DataBitsPerMask     (RamWidth),
286                         .EnableECC           (1'b0),
287                         .EnableParity        (1'b0),
288                         .EnableInputPipeline (1'b0),
289                         .EnableOutputPipeline(1'b0)
290                       ) u_ram_1p (
291                         .clk_i,
292                         .rst_ni,
293                         .req_i   (ram_req),
294                         .write_i (ram_write),
295                         .addr_i  (ram_addr),
296                         .wdata_i (ram_wdata),
297                         .wmask_i ('1),
298                         .rdata_o (ram_rdata),
299                         .rvalid_o(ram_rvalid),
300                         .rerror_o(/* unused */),
301                         .cfg_i   (ram_cfg_i),
302                         .alert_o (/* unused */)
303                       );
304        1/1            assign {ram_write, ram_addr, ram_wdata} = ram_arb_oup_data;
           Tests:       T1 T2 T3 

---

Branch Coverage for Module : i2c_fifos

	Line No.	Total	Covered	Percent
Branches		2	2	100.00
IF	270	2	2	100.00

270            if (!rst_ni) begin
               -1-  
271              ram_arb_idx_q <= '0;
                 ==>
272            end else begin
273              ram_arb_idx_q <= ram_arb_idx;
                 ==>

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T2,T3

---

Assert Coverage for Module : i2c_fifos

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	5	5	100.00	2	40.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	5	5	100.00	2	40.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
AcqWriteStableBeforeHandshake_A	428617037	0	0	0
FmtWriteStableBeforeHandshake_A	431063773	0	0	0
RamDepthSuffices_A	1697	1697	0	0
RamWidthSuffices_A	1697	1697	0	0
TxWriteStableBeforeHandshake_A	431063773	0	0	0

AcqWriteStableBeforeHandshake_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	428617037	0	0	0

FmtWriteStableBeforeHandshake_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	431063773	0	0	0

RamDepthSuffices_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	1697	1697	0	0
T1	1	1	0	0
T2	1	1	0	0
T3	1	1	0	0
T4	1	1	0	0
T5	1	1	0	0
T6	1	1	0	0
T7	1	1	0	0
T8	1	1	0	0
T9	1	1	0	0
T10	1	1	0	0

RamWidthSuffices_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	1697	1697	0	0
T1	1	1	0	0
T2	1	1	0	0
T3	1	1	0	0
T4	1	1	0	0
T5	1	1	0	0
T6	1	1	0	0
T7	1	1	0	0
T8	1	1	0	0
T9	1	1	0	0
T10	1	1	0	0

TxWriteStableBeforeHandshake_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	431063773	0	0	0