Unified Coverage Report :: Module :: i2c_csr_assert_fpv

Module : i2c_csr_assert_fpv

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
93.75						93.75

Source File(s) :
/workspaces/repo/scratch/os_regression_2024_08_26/i2c-sim-vcs/default/sim-vcs/../src/lowrisc_fpv_i2c_csr_assert_0/i2c_csr_assert_fpv.sv

Module self-instances :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
tb.dut.i2c_csr_assert	93.75						93.75

---

Module Instance : tb.dut.i2c_csr_assert

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
93.75						93.75

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
93.75						93.75

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
98.48	100.00	100.00	93.91			100.00	dut

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Since this is the module's only instance, the coverage report is the same as for the module.

Assert Coverage for Module : i2c_csr_assert_fpv

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	16	16	100.00	15	93.75
Cover properties	0	0		0
Cover sequences	0	0		0
Total	16	16	100.00	15	93.75

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
TlulOOBAddrErr_A	431730382	0	0	0
ctrl_rd_A	431730382	2382	0	0
host_fifo_config_rd_A	431730382	4420	0	0
host_nack_handler_timeout_rd_A	431730382	1149	0	0
host_timeout_ctrl_rd_A	431730382	970	0	0
intr_enable_rd_A	431730382	3927	0	0
ovrd_rd_A	431730382	2126	0	0
target_fifo_config_rd_A	431730382	1149	0	0
target_id_rd_A	431730382	1557	0	0
target_timeout_ctrl_rd_A	431730382	1166	0	0
timeout_ctrl_rd_A	431730382	1446	0	0
timing0_rd_A	431730382	1237	0	0
timing1_rd_A	431730382	1101	0	0
timing2_rd_A	431730382	1220	0	0
timing3_rd_A	431730382	1324	0	0
timing4_rd_A	431730382	1335	0	0

TlulOOBAddrErr_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	431730382	0	0	0

ctrl_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	431730382	2382	0	0
T112	5262	22	0	0
T113	5607	87	0	0
T114	2487	9	0	0
T115	7687	141	0	0
T116	3760	4	0	0
T117	11115	263	0	0
T118	13014	84	0	0
T119	11428	31	0	0
T120	2086	3	0	0
T121	3776	40	0	0

host_fifo_config_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	431730382	4420	0	0
T21	0	134	0	0
T88	296534	134	0	0
T89	0	141	0	0
T90	0	221	0	0
T122	0	217	0	0
T123	0	118	0	0
T124	0	122	0	0
T125	0	98	0	0
T126	0	121	0	0
T127	0	72	0	0
T128	51464	0	0	0
T129	52556	0	0	0
T130	1541	0	0	0
T131	13305	0	0	0
T132	2689	0	0	0
T133	34888	0	0	0
T134	49585	0	0	0
T135	50702	0	0	0
T136	91746	0	0	0

host_nack_handler_timeout_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	431730382	1149	0	0
T112	5262	20	0	0
T113	5607	50	0	0
T114	2487	9	0	0
T115	7687	42	0	0
T116	3760	6	0	0
T117	11115	220	0	0
T118	13014	56	0	0
T119	11428	47	0	0
T120	2086	1	0	0
T121	3776	18	0	0

host_timeout_ctrl_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	431730382	970	0	0
T112	5262	2	0	0
T113	5607	27	0	0
T114	2487	9	0	0
T115	7687	18	0	0
T116	3760	44	0	0
T117	11115	234	0	0
T118	13014	43	0	0
T119	11428	39	0	0
T121	3776	22	0	0
T137	13264	17	0	0

intr_enable_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	431730382	3927	0	0
T21	889962	53	0	0
T47	54046	0	0	0
T112	0	24	0	0
T113	0	32	0	0
T114	0	4	0	0
T115	0	333	0	0
T124	0	9	0	0
T138	0	29	0	0
T139	0	14	0	0
T140	0	17	0	0
T141	0	14	0	0
T142	87724	0	0	0
T143	6041	0	0	0
T144	14481	0	0	0
T145	157513	0	0	0
T146	128135	0	0	0
T147	66019	0	0	0
T148	62030	0	0	0
T149	246112	0	0	0

ovrd_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	431730382	2126	0	0
T12	3413	0	0	0
T13	39710	0	0	0
T42	10680	0	0	0
T71	49086	0	0	0
T72	56035	0	0	0
T78	3000	49	0	0
T79	1601	27	0	0
T109	0	57	0	0
T150	0	33	0	0
T151	0	79	0	0
T152	0	55	0	0
T153	0	58	0	0
T154	0	64	0	0
T155	0	48	0	0
T156	0	38	0	0
T157	103252	0	0	0
T158	23298	0	0	0
T159	22550	0	0	0

target_fifo_config_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	431730382	1149	0	0
T112	5262	6	0	0
T113	5607	58	0	0
T114	2487	7	0	0
T115	7687	42	0	0
T116	3760	1	0	0
T117	11115	224	0	0
T118	13014	27	0	0
T119	11428	31	0	0
T120	2086	7	0	0
T121	3776	17	0	0

target_id_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	431730382	1557	0	0
T112	5262	14	0	0
T113	5607	23	0	0
T114	2487	5	0	0
T115	7687	128	0	0
T116	3760	34	0	0
T117	11115	229	0	0
T118	13014	150	0	0
T119	11428	25	0	0
T120	2086	7	0	0
T121	3776	43	0	0

target_timeout_ctrl_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	431730382	1166	0	0
T112	5262	4	0	0
T113	5607	55	0	0
T114	2487	8	0	0
T115	7687	53	0	0
T116	3760	14	0	0
T117	11115	256	0	0
T118	13014	77	0	0
T119	11428	21	0	0
T121	3776	20	0	0
T137	13264	14	0	0

timeout_ctrl_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	431730382	1446	0	0
T112	5262	10	0	0
T113	5607	45	0	0
T114	2487	10	0	0
T115	7687	63	0	0
T116	3760	22	0	0
T117	11115	242	0	0
T118	13014	95	0	0
T119	11428	20	0	0
T120	2086	7	0	0
T121	3776	44	0	0

timing0_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	431730382	1237	0	0
T113	5607	7	0	0
T114	2487	13	0	0
T115	7687	83	0	0
T116	3760	41	0	0
T117	11115	249	0	0
T118	13014	84	0	0
T119	11428	20	0	0
T121	3776	29	0	0
T137	13264	46	0	0
T160	1808	14	0	0

timing1_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	431730382	1101	0	0
T112	5262	16	0	0
T113	5607	12	0	0
T114	2487	12	0	0
T115	7687	42	0	0
T116	3760	28	0	0
T117	11115	211	0	0
T118	13014	69	0	0
T119	11428	11	0	0
T120	2086	8	0	0
T121	3776	25	0	0

timing2_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	431730382	1220	0	0
T112	5262	18	0	0
T113	5607	39	0	0
T114	2487	9	0	0
T115	7687	40	0	0
T116	3760	26	0	0
T117	11115	232	0	0
T118	13014	94	0	0
T119	11428	19	0	0
T120	2086	7	0	0
T121	3776	20	0	0

timing3_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	431730382	1324	0	0
T112	5262	27	0	0
T113	5607	32	0	0
T114	2487	8	0	0
T115	7687	81	0	0
T116	3760	15	0	0
T117	11115	267	0	0
T118	13014	65	0	0
T119	11428	21	0	0
T120	2086	9	0	0
T121	3776	20	0	0

timing4_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	431730382	1335	0	0
T112	5262	16	0	0
T113	5607	49	0	0
T114	2487	9	0	0
T115	7687	63	0	0
T116	3760	21	0	0
T117	11115	261	0	0
T118	13014	53	0	0
T119	11428	29	0	0
T121	3776	24	0	0
T137	13264	12	0	0