Unified Coverage Report :: Group :: tl_agent_pkg::tl_a_chan_cov_cg::SHAPE{(2 << ((valid_source_width - 1) - 1))=128}

Group : tl_agent_pkg::tl_a_chan_cov_cg::SHAPE{(2 << ((valid_source_width - 1) - 1))=128}

SCORE	INSTANCES	WEIGHT	GOAL	AT LEAST	PER INSTANCE	AUTO BIN MAX	PRINT MISSING
100.00	100.00	1	100	1	1	64	64

Source File(s) :
/workspaces/repo/scratch/os_regression_2024_08_28/i2c-sim-vcs/default/sim-vcs/../src/lowrisc_dv_tl_agent_0/tl_agent_cov.sv

1 Instances:

NAME	SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
tl_agent_pkg.uvm_test_top.env.m_tl_agent_i2c_reg_block.cov::m_tl_a_chan_cov_cg	100.00	1	100	1	64	64

---

Group Instance : tl_agent_pkg.uvm_test_top.env.m_tl_agent_i2c_reg_block.cov::m_tl_a_chan_cov_cg

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
100.00	1	100	1	64	64

---

Summary for Group Instance tl_agent_pkg.uvm_test_top.env.m_tl_agent_i2c_reg_block.cov::m_tl_a_chan_cov_cg

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	134	0	134	100.00
Crosses	3	0	3	100.00

Variables for Group Instance tl_agent_pkg.uvm_test_top.env.m_tl_agent_i2c_reg_block.cov::m_tl_a_chan_cov_cg

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
cp_mask	1	0	1	100.00	100	1	1	0
cp_opcode	3	0	3	100.00	100	1	1	0
cp_size	1	0	1	100.00	100	1	1	0
cp_source	129	0	129	100.00	100	1	1	0

Crosses for Group Instance tl_agent_pkg.uvm_test_top.env.m_tl_agent_i2c_reg_block.cov::m_tl_a_chan_cov_cg

CROSS	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	PRINT MISSING	COMMENT
tl_a_chan_cov_cg_cc	3	0	3	100.00	100	1	1	0

Summary for Variable cp_mask

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	1	0	1	100.00

User Defined Bins for cp_mask

Excluded/Illegal bins

NAME	COUNT	STATUS
others	27354777	Excluded

Covered bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

all_enables

7095066

1

T1

11

T2

58

T3

235

---

Summary for Variable cp_opcode

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	3	0	3	100.00

User Defined Bins for cp_opcode

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
values[0x4]	33658217	1			T1	15		T2	157		T3	581
values[0x0]	394710	1			T1	9		T2	71		T3	77
values[0x1]	396916	1			T1	9		T2	82		T3	79

---

Summary for Variable cp_size

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	1	0	1	100.00

User Defined Bins for cp_size

Excluded/Illegal bins

NAME	COUNT	STATUS
others	19077486	Excluded

Covered bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

biggest_size

15372357

1

T1

14

T2

139

T3

373

---

Summary for Variable cp_source

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	129	0	129	100.00

User Defined Bins for cp_source

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
valid_sources[0x00]	133605	1			T2	1		T3	3		T4	23
valid_sources[0x01]	131547	1			T3	1		T4	29		T7	24
valid_sources[0x02]	130521	1			T2	5		T3	4		T4	31
valid_sources[0x03]	134298	1			T3	1		T4	15		T7	13
valid_sources[0x04]	127429	1			T2	8		T3	5		T4	21
valid_sources[0x05]	126160	1			T2	3		T3	4		T4	16
valid_sources[0x06]	133508	1			T2	7		T4	30		T7	5
valid_sources[0x07]	133817	1			T2	1		T3	2		T4	21
valid_sources[0x08]	126332	1			T2	2		T3	3		T4	34
valid_sources[0x09]	132924	1			T3	3		T4	27		T5	1
valid_sources[0x0a]	135532	1			T3	4		T4	31		T5	3
valid_sources[0x0b]	122382	1			T3	3		T4	30		T5	2
valid_sources[0x0c]	139054	1			T2	1		T3	1		T4	23
valid_sources[0x0d]	135323	1			T3	2		T4	27		T7	13
valid_sources[0x0e]	149149	1			T3	3		T4	20		T5	1
valid_sources[0x0f]	124210	1			T3	1		T4	24		T7	21
valid_sources[0x10]	135369	1			T3	2		T4	24		T7	9
valid_sources[0x11]	127137	1			T2	4		T3	3		T4	23
valid_sources[0x12]	132429	1			T2	3		T3	4		T4	15
valid_sources[0x13]	133489	1			T4	17		T5	1		T7	37
valid_sources[0x14]	153735	1			T3	1		T4	25		T5	1
valid_sources[0x15]	153318	1			T2	4		T3	2		T4	25
valid_sources[0x16]	157526	1			T2	2		T4	29		T5	1
valid_sources[0x17]	130641	1			T3	5		T4	20		T7	26
valid_sources[0x18]	131131	1			T3	2		T4	28		T5	1
valid_sources[0x19]	129577	1			T2	2		T3	1		T4	21
valid_sources[0x1a]	140461	1			T3	2		T4	22		T5	1
valid_sources[0x1b]	133815	1			T1	3		T3	1		T4	19
valid_sources[0x1c]	148935	1			T3	3		T4	18		T5	1
valid_sources[0x1d]	138731	1			T2	1		T3	7		T4	30
valid_sources[0x1e]	144664	1			T2	1		T3	2		T4	21
valid_sources[0x1f]	140771	1			T2	2		T4	25		T7	1
valid_sources[0x20]	134189	1			T2	1		T3	5		T4	28
valid_sources[0x21]	119802	1			T2	2		T3	7		T4	28
valid_sources[0x22]	140511	1			T3	2		T4	32		T7	29
valid_sources[0x23]	135835	1			T3	2		T4	23		T7	34
valid_sources[0x24]	124473	1			T2	2		T3	4		T4	19
valid_sources[0x25]	141233	1			T3	1		T4	18		T7	26
valid_sources[0x26]	136992	1			T4	21		T5	1		T7	8
valid_sources[0x27]	127898	1			T2	4		T3	4		T4	21
valid_sources[0x28]	136702	1			T3	3		T4	27		T5	1
valid_sources[0x29]	127120	1			T4	18		T7	27		T10	27
valid_sources[0x2a]	119013	1			T3	6		T4	24		T5	1
valid_sources[0x2b]	142572	1			T3	3		T4	26		T5	1
valid_sources[0x2c]	129012	1			T3	3		T4	30		T5	2
valid_sources[0x2d]	140075	1			T4	19		T7	56		T8	1
valid_sources[0x2e]	130470	1			T2	1		T3	5		T4	34
valid_sources[0x2f]	130438	1			T3	1		T4	25		T5	2
valid_sources[0x30]	124857	1			T3	1		T4	18		T10	36
valid_sources[0x31]	135629	1			T2	1		T3	5		T4	14
valid_sources[0x32]	128135	1			T2	1		T3	1		T4	19
valid_sources[0x33]	137645	1			T3	3		T4	23		T7	10
valid_sources[0x34]	129835	1			T4	20		T7	36		T10	14
valid_sources[0x35]	129401	1			T2	2		T3	4		T4	18
valid_sources[0x36]	140232	1			T3	3		T4	22		T5	1
valid_sources[0x37]	131100	1			T3	1		T4	29		T7	23
valid_sources[0x38]	131659	1			T2	1		T3	11		T4	21
valid_sources[0x39]	134121	1			T3	3		T4	22		T5	1
valid_sources[0x3a]	133761	1			T2	2		T3	4		T4	26
valid_sources[0x3b]	125035	1			T2	4		T3	3		T4	20
valid_sources[0x3c]	141968	1			T3	3		T4	26		T5	1
valid_sources[0x3d]	132437	1			T2	5		T3	9		T4	22
valid_sources[0x3e]	136418	1			T3	2		T4	17		T7	16
valid_sources[0x3f]	134701	1			T2	1		T3	3		T4	31
valid_sources[0x40]	129388	1			T2	1		T3	9		T4	22
valid_sources[0x41]	134441	1			T2	1		T3	3		T4	26
valid_sources[0x42]	121593	1			T2	5		T3	2		T4	40
valid_sources[0x43]	128317	1			T3	2		T4	33		T5	1
valid_sources[0x44]	120294	1			T3	4		T4	26		T7	15
valid_sources[0x45]	126641	1			T3	1		T4	21		T7	16
valid_sources[0x46]	114312	1			T2	1		T3	3		T4	24
valid_sources[0x47]	145476	1			T2	2		T3	2		T4	21
valid_sources[0x48]	134540	1			T3	3		T4	23		T7	36
valid_sources[0x49]	130828	1			T4	19		T7	20		T8	1
valid_sources[0x4a]	147615	1			T3	1		T4	19		T5	1
valid_sources[0x4b]	160239	1			T3	4		T4	21		T7	32
valid_sources[0x4c]	128984	1			T2	7		T3	4		T4	16
valid_sources[0x4d]	120684	1			T3	5		T4	29		T5	3
valid_sources[0x4e]	134330	1			T2	4		T3	3		T4	31
valid_sources[0x4f]	125237	1			T2	4		T3	2		T4	21
valid_sources[0x50]	142727	1			T4	28		T5	1		T7	8
valid_sources[0x51]	119141	1			T2	1		T3	3		T4	18
valid_sources[0x52]	143969	1			T3	3		T4	14		T7	16
valid_sources[0x53]	121004	1			T2	2		T3	7		T4	17
valid_sources[0x54]	127813	1			T3	3		T4	21		T6	2
valid_sources[0x55]	134358	1			T2	2		T3	1		T4	28
valid_sources[0x56]	136890	1			T2	1		T3	1		T4	21
valid_sources[0x57]	145998	1			T2	1		T3	3		T4	21
valid_sources[0x58]	128727	1			T3	3		T4	25		T5	1
valid_sources[0x59]	130938	1			T3	1		T4	24		T7	11
valid_sources[0x5a]	131375	1			T3	4		T4	30		T7	11
valid_sources[0x5b]	121072	1			T3	3		T4	24		T7	30
valid_sources[0x5c]	127308	1			T2	1		T3	1		T4	17
valid_sources[0x5d]	123044	1			T4	25		T7	17		T10	22
valid_sources[0x5e]	136339	1			T3	5		T4	22		T7	12
valid_sources[0x5f]	132495	1			T3	6		T4	25		T7	18
valid_sources[0x60]	129082	1			T2	8		T3	6		T4	27
valid_sources[0x61]	145010	1			T2	2		T3	5		T4	22
valid_sources[0x62]	128197	1			T2	1		T3	5		T4	21
valid_sources[0x63]	138254	1			T3	1		T4	23		T7	33
valid_sources[0x64]	129737	1			T2	2		T4	15		T7	30
valid_sources[0x65]	137006	1			T2	2		T3	2		T4	28
valid_sources[0x66]	206134	1			T3	3		T4	14		T5	1
valid_sources[0x67]	126630	1			T2	1		T3	4		T4	29
valid_sources[0x68]	128407	1			T2	1		T4	16		T7	9
valid_sources[0x69]	129865	1			T2	2		T3	2		T4	18
valid_sources[0x6a]	128348	1			T4	27		T7	13		T9	2
valid_sources[0x6b]	135536	1			T3	7		T4	31		T7	2
valid_sources[0x6c]	135591	1			T3	3		T4	18		T5	1
valid_sources[0x6d]	147717	1			T3	6		T4	34		T7	20
valid_sources[0x6e]	137893	1			T3	5		T4	21		T7	11
valid_sources[0x6f]	138886	1			T3	1		T4	22		T5	1
valid_sources[0x70]	130802	1			T3	1		T4	15		T7	28
valid_sources[0x71]	137820	1			T2	5		T3	8		T4	24
valid_sources[0x72]	131502	1			T3	2		T4	17		T5	1
valid_sources[0x73]	123704	1			T3	2		T4	20		T7	16
valid_sources[0x74]	122508	1			T2	4		T3	1		T4	21
valid_sources[0x75]	138822	1			T3	1		T4	18		T5	1
valid_sources[0x76]	128670	1			T2	2		T3	5		T4	24
valid_sources[0x77]	122767	1			T4	20		T7	33		T10	30
valid_sources[0x78]	137286	1			T3	1		T4	17		T5	1
valid_sources[0x79]	117645	1			T3	2		T4	33		T5	1
valid_sources[0x7a]	154946	1			T2	2		T3	2		T4	39
valid_sources[0x7b]	138380	1			T2	2		T3	2		T4	26
valid_sources[0x7c]	140859	1			T2	1		T3	4		T4	13
valid_sources[0x7d]	148543	1			T2	4		T3	1		T4	18
valid_sources[0x7e]	124869	1			T3	1		T4	17		T7	6
valid_sources[0x7f]	149950	1			T2	2		T4	25		T7	20
valid_sources[0x80]	139750	1			T4	22		T7	3		T8	1

---

Summary for Cross tl_a_chan_cov_cg_cc

Samples crossed: cp_opcode cp_mask cp_size

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	3	0	3	100.00

Automatically Generated Cross Bins for tl_a_chan_cov_cg_cc

Bins

cp_opcode

cp_mask

cp_size

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

values[0x4]

all_enables

biggest_size

6739763

1

T1

6

T2

1

T3

117

values[0x0]

all_enables

biggest_size

210144

1

T1

4

T2

37

T3

63

values[0x1]

all_enables

biggest_size

145159

1

T1

1

T2

20

T3

55