Unified Coverage Report :: Module :: i2c_fifo_sync_sram_adapter

Module : i2c_fifo_sync_sram_adapter

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
95.59	100.00	82.35			100.00	100.00

Source File(s) :
/workspaces/repo/scratch/os_regression_2024_08_28/i2c-sim-vcs/default/sim-vcs/../src/lowrisc_ip_i2c_0.1/rtl/i2c_fifo_sync_sram_adapter.sv

Module self-instances :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
tb.dut.i2c_core.u_fifos.u_fmt_fifo_sram_adapter	93.63	100.00	74.51			100.00	100.00
tb.dut.i2c_core.u_fifos.u_tx_fifo_sram_adapter	93.63	100.00	74.51			100.00	100.00
tb.dut.i2c_core.u_fifos.u_rx_fifo_sram_adapter	94.12	100.00	76.47			100.00	100.00
tb.dut.i2c_core.u_fifos.u_acq_fifo_sram_adapter	95.59	100.00	82.35			100.00	100.00

---

Module Instance : tb.dut.i2c_core.u_fifos.u_fmt_fifo_sram_adapter

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
93.63	100.00	74.51			100.00	100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
95.54	100.00	83.65			98.51	100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
80.00	100.00				100.00	40.00	u_fifos

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
u_inp_buf	94.32	100.00	81.82			95.45	100.00
u_oup_buf	97.16	100.00	88.64			100.00	100.00
u_sram_ptrs	100.00	100.00	100.00			100.00

---

Module Instance : tb.dut.i2c_core.u_fifos.u_tx_fifo_sram_adapter

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
93.63	100.00	74.51			100.00	100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
95.54	100.00	83.65			98.51	100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
80.00	100.00				100.00	40.00	u_fifos

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
u_inp_buf	94.32	100.00	81.82			95.45	100.00
u_oup_buf	97.16	100.00	88.64			100.00	100.00
u_sram_ptrs	100.00	100.00	100.00			100.00

---

Module Instance : tb.dut.i2c_core.u_fifos.u_rx_fifo_sram_adapter

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
94.12	100.00	76.47			100.00	100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
94.69	100.00	81.76			97.01	100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
80.00	100.00				100.00	40.00	u_fifos

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
u_inp_buf	90.91	100.00	72.73			90.91	100.00
u_oup_buf	97.16	100.00	88.64			100.00	100.00
u_sram_ptrs	100.00	100.00	100.00			100.00

---

Module Instance : tb.dut.i2c_core.u_fifos.u_acq_fifo_sram_adapter

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
95.59	100.00	82.35			100.00	100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
96.32	100.00	86.79			98.51	100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
80.00	100.00				100.00	40.00	u_fifos

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
u_inp_buf	94.32	100.00	81.82			95.45	100.00
u_oup_buf	97.73	100.00	90.91			100.00	100.00
u_sram_ptrs	100.00	100.00	100.00			100.00

Line Coverage for Module : i2c_fifo_sync_sram_adapter ( parameter Width=13,Depth=64,SramAw=9,SramBaseAddr,DepthW=7,OupBufDepth=2,InpBufDepthW=2,OupBufDepthW=2,SramPtrW=6,SramDepthW=6,SramAddrLeadingZeros=3 )
Line Coverage for Module self-instances :

SCORE	LINE
93.63	100.00

tb.dut.i2c_core.u_fifos.u_fmt_fifo_sram_adapter

SCORE	LINE
94.12	100.00

tb.dut.i2c_core.u_fifos.u_rx_fifo_sram_adapter

SCORE	LINE
93.63	100.00

tb.dut.i2c_core.u_fifos.u_tx_fifo_sram_adapter

	Line No.	Total	Covered	Percent
TOTAL		44	44	100.00
CONT_ASSIGN	120	1	1	100.00
CONT_ASSIGN	121	1	1	100.00
CONT_ASSIGN	125	1	1	100.00
CONT_ASSIGN	150	1	1	100.00
CONT_ASSIGN	151	1	1	100.00
CONT_ASSIGN	153	1	1	100.00
CONT_ASSIGN	154	1	1	100.00
CONT_ASSIGN	162	1	1	100.00
ALWAYS	164	3	3	100.00
ALWAYS	174	28	28	100.00
CONT_ASSIGN	228	1	1	100.00
CONT_ASSIGN	236	1	1	100.00
CONT_ASSIGN	240	1	1	100.00
CONT_ASSIGN	244	1	1	100.00
CONT_ASSIGN	249	1	1	100.00

119                       );
120        1/1            assign inp_buf_wvalid = fifo_wvalid_i && fifo_wready_o;
           Tests:       T1 T2 T3 
121        1/1            assign oup_buf_almost_full = oup_buf_depth >= OupBufDepthW'(OupBufDepth - 1);
           Tests:       T1 T2 T3 
122                     
123                       // Signal whether we access the SRAM in this cycle
124                       logic sram_access;
125        1/1            assign sram_access = sram_req_o && sram_gnt_i;
           Tests:       T1 T2 T3 
126                     
127                       // SRAM read and write addresses
128                       logic [SramAw-1:0]     sram_wr_addr, sram_rd_addr;
129                       logic [SramPtrW-1:0]   sram_wr_ptr, sram_rd_ptr;
130                       logic [SramDepthW-1:0] sram_depth;
131                       logic                  sram_incr_wr_ptr, sram_incr_rd_ptr;
132                       logic                  sram_full, sram_empty;
133                       logic                  sram_ptrs_err;
134                       prim_fifo_sync_cnt #(
135                         .Depth (SramFifoDepth),
136                         .Secure(1'b0)
137                       ) u_sram_ptrs (
138                         .clk_i,
139                         .rst_ni,
140                         .clr_i,
141                         .incr_wptr_i(sram_incr_wr_ptr),
142                         .incr_rptr_i(sram_incr_rd_ptr),
143                         .wptr_o     (sram_wr_ptr),
144                         .rptr_o     (sram_rd_ptr),
145                         .full_o     (sram_full),
146                         .empty_o    (sram_empty),
147                         .depth_o    (sram_depth),
148                         .err_o      (sram_ptrs_err)
149                       );
150        1/1            assign sram_incr_wr_ptr = sram_access && sram_write_o;
           Tests:       T1 T2 T3 
151        1/1            assign sram_incr_rd_ptr = sram_access && !sram_write_o;
           Tests:       T1 T2 T3 
152                       if (SramAddrLeadingZeros > 0) begin : gen_zero_extend_sram_addrs
153        1/1              assign sram_wr_addr = {{SramAddrLeadingZeros{1'b0}}, sram_wr_ptr} + SramBaseAddr;
           Tests:       T1 T2 T3 
154        1/1              assign sram_rd_addr = {{SramAddrLeadingZeros{1'b0}}, sram_rd_ptr} + SramBaseAddr;
           Tests:       T1 T2 T3 
155                       end else begin : gen_no_zero_extend_sram_addrs
156                         assign sram_wr_addr = sram_wr_ptr + SramBaseAddr;
157                         assign sram_rd_addr = sram_rd_ptr + SramBaseAddr;
158                       end
159                     
160                       // FF to remember whether we read from the SRAM in the previous clock cycle.
161                       logic sram_read_in_prev_cyc_d, sram_read_in_prev_cyc_q;
162        1/1            assign sram_read_in_prev_cyc_d = clr_i ? 1'b0 : sram_incr_rd_ptr;
           Tests:       T1 T2 T3 
163                       always_ff @(posedge clk_i or negedge rst_ni) begin
164        1/1              if (!rst_ni) begin
           Tests:       T1 T2 T3 
165        1/1                sram_read_in_prev_cyc_q <= 1'b0;
           Tests:       T1 T2 T3 
166                         end else begin
167        1/1                sram_read_in_prev_cyc_q <= sram_read_in_prev_cyc_d;
           Tests:       T1 T2 T3 
168                         end
169                       end
170                     
171                       // Control logic for FIFO interface wready, output buffer writes, and SRAM requests
172                       logic state_err;
173                       always_comb begin
174        1/1              inp_buf_rready = 1'b0;
           Tests:       T1 T2 T3 
175        1/1              oup_buf_wvalid = 1'b0;
           Tests:       T1 T2 T3 
176        1/1              oup_buf_wdata = inp_buf_rdata;
           Tests:       T1 T2 T3 
177        1/1              sram_req_o = 1'b0;
           Tests:       T1 T2 T3 
178        1/1              sram_write_o = 1'b0;
           Tests:       T1 T2 T3 
179        1/1              sram_addr_o = sram_wr_addr;
           Tests:       T1 T2 T3 
180        1/1              state_err = 1'b0;
           Tests:       T1 T2 T3 
181                     
182                         // If the SRAM was read in the previous cycle, write the read data to the output buffer.
183        1/1              if (sram_read_in_prev_cyc_q) begin
           Tests:       T1 T2 T3 
184        1/1                oup_buf_wvalid = 1'b1;
           Tests:       T3 T4 T19 
185        1/1                oup_buf_wdata = sram_rdata_i;
           Tests:       T3 T4 T19 
186                           // The output buffer must be ready; otherwise we are in an erroneous state.
187        1/1                state_err = !oup_buf_wready;
           Tests:       T3 T4 T19 
188                         end
                        MISSING_ELSE
189                     
190                         // If the SRAM is not empty, data from the input buffer must flow via the SRAM.
191        1/1              if (!sram_empty) begin
           Tests:       T1 T2 T3 
192                     
193                           // Prioritize refilling of the output buffer: if the output buffer is not being filled to the
194                           // last slot in the current cycle or it is being read in the current cycle, read from the SRAM
195                           // so the output buffer can be written in the next cycle.
196        1/1                if (!((oup_buf_almost_full && oup_buf_wvalid) || oup_buf_full)
           Tests:       T2 T3 T4 
197                               || (fifo_rvalid_o && fifo_rready_i)) begin
198        1/1                  sram_req_o = 1'b1;
           Tests:       T3 T4 T19 
199        1/1                  sram_write_o = 1'b0;
           Tests:       T3 T4 T19 
200        1/1                  sram_addr_o = sram_rd_addr;
           Tests:       T3 T4 T19 
201                     
202                           // If the output buffer is full (and not being read), drain the input buffer into the SRAM.
203                           end else begin
204        1/1                  sram_req_o = !sram_full && inp_buf_rvalid;
           Tests:       T2 T3 T4 
205        1/1                  sram_write_o = 1'b1;
           Tests:       T2 T3 T4 
206        1/1                  sram_addr_o = sram_wr_addr;
           Tests:       T2 T3 T4 
207        1/1                  inp_buf_rready = !sram_full && sram_gnt_i;
           Tests:       T2 T3 T4 
208                           end
209                     
210                         // If the SRAM is empty, data must flow from the input buffer to the output buffer if the output
211                         // buffer is ready and is not receiving data read from the SRAM in the previous cycle
212        1/1              end else if (oup_buf_wready && !sram_read_in_prev_cyc_q) begin
           Tests:       T1 T2 T3 
213        1/1                oup_buf_wvalid = inp_buf_rvalid;
           Tests:       T1 T2 T3 
214        1/1                oup_buf_wdata = inp_buf_rdata;
           Tests:       T1 T2 T3 
215        1/1                inp_buf_rready = oup_buf_wready;
           Tests:       T1 T2 T3 
216                     
217                         // Otherwise the SRAM is empty but the output buffer cannot take the data from the input buffer,
218                         // so drain the input buffer into the SRAM.
219                         end else begin
220        1/1                sram_req_o = !sram_full && inp_buf_rvalid;
           Tests:       T1 T2 T3 
221        1/1                sram_write_o = 1'b1;
           Tests:       T1 T2 T3 
222        1/1                sram_addr_o = sram_wr_addr;
           Tests:       T1 T2 T3 
223        1/1                inp_buf_rready = !sram_full && sram_gnt_i;
           Tests:       T1 T2 T3 
224                         end
225                       end
226                     
227                       // Error output is high if any of the internal errors is high
228        1/1            assign err_o = |{inp_buf_err, oup_buf_err, sram_ptrs_err, state_err};
           Tests:       T1 T2 T3 
229                     
230                       // The SRAM and the output buffer together form the entire architectural capacity of the FIFO.
231                       // Thus, when both are full, the FIFO is no longer ready to receive writes even though the input
232                       // buffer could store one additional entry.  This ensures that in the cycle after an entry has
233                       // been read from the full FIFO, the next entry can be written to the FIFO.
234                       // (It may be possible that all input buffer slots except one can be counted to the architectural
235                       // capacity of the FIFO, but this is a relatively small optimization left for future work.)
236        1/1            assign fifo_wready_o = inp_buf_wready && !(sram_full && oup_buf_full);
           Tests:       T1 T2 T3 
237                     
238                       // The current depth of the FIFO represented by this module is the depth of all buffers plus the
239                       // FIFO in the SRAM plus one if there's an entry in transition between SRAM and output buffer.
240        1/1            assign fifo_depth_o = DepthW'(inp_buf_depth) + DepthW'(sram_depth) + DepthW'(oup_buf_depth) +
           Tests:       T1 T2 T3 
241                                             DepthW'(sram_read_in_prev_cyc_q);
242                     
243                       // SRAM write data always comes from the input buffer.
244        1/1            assign sram_wdata_o = inp_buf_rdata;
           Tests:       T1 T2 T3 
245                       assign sram_wmask_o = '1;
246                     
247                       // `sram_rvalid_i` is only used for assertions.
248                       logic unused_sram_rvalid;
249        1/1            assign unused_sram_rvalid = sram_rvalid_i;
           Tests:       T1 T2 T3 

---

Line Coverage for Module : i2c_fifo_sync_sram_adapter ( parameter Width=13,Depth=268,SramAw=9,SramBaseAddr=192,DepthW=9,OupBufDepth=2,InpBufDepthW=2,OupBufDepthW=2,SramPtrW=9,SramDepthW=9,SramAddrLeadingZeros=0 )
Line Coverage for Module self-instances :

SCORE	LINE
95.59	100.00

tb.dut.i2c_core.u_fifos.u_acq_fifo_sram_adapter

	Line No.	Total	Covered	Percent
TOTAL		44	44	100.00
CONT_ASSIGN	120	1	1	100.00
CONT_ASSIGN	121	1	1	100.00
CONT_ASSIGN	125	1	1	100.00
CONT_ASSIGN	150	1	1	100.00
CONT_ASSIGN	151	1	1	100.00
CONT_ASSIGN	156	1	1	100.00
CONT_ASSIGN	157	1	1	100.00
CONT_ASSIGN	162	1	1	100.00
ALWAYS	164	3	3	100.00
ALWAYS	174	28	28	100.00
CONT_ASSIGN	228	1	1	100.00
CONT_ASSIGN	236	1	1	100.00
CONT_ASSIGN	240	1	1	100.00
CONT_ASSIGN	244	1	1	100.00
CONT_ASSIGN	249	1	1	100.00

119                       );
120        1/1            assign inp_buf_wvalid = fifo_wvalid_i && fifo_wready_o;
           Tests:       T1 T2 T3 
121        1/1            assign oup_buf_almost_full = oup_buf_depth >= OupBufDepthW'(OupBufDepth - 1);
           Tests:       T1 T2 T3 
122                     
123                       // Signal whether we access the SRAM in this cycle
124                       logic sram_access;
125        1/1            assign sram_access = sram_req_o && sram_gnt_i;
           Tests:       T1 T2 T3 
126                     
127                       // SRAM read and write addresses
128                       logic [SramAw-1:0]     sram_wr_addr, sram_rd_addr;
129                       logic [SramPtrW-1:0]   sram_wr_ptr, sram_rd_ptr;
130                       logic [SramDepthW-1:0] sram_depth;
131                       logic                  sram_incr_wr_ptr, sram_incr_rd_ptr;
132                       logic                  sram_full, sram_empty;
133                       logic                  sram_ptrs_err;
134                       prim_fifo_sync_cnt #(
135                         .Depth (SramFifoDepth),
136                         .Secure(1'b0)
137                       ) u_sram_ptrs (
138                         .clk_i,
139                         .rst_ni,
140                         .clr_i,
141                         .incr_wptr_i(sram_incr_wr_ptr),
142                         .incr_rptr_i(sram_incr_rd_ptr),
143                         .wptr_o     (sram_wr_ptr),
144                         .rptr_o     (sram_rd_ptr),
145                         .full_o     (sram_full),
146                         .empty_o    (sram_empty),
147                         .depth_o    (sram_depth),
148                         .err_o      (sram_ptrs_err)
149                       );
150        1/1            assign sram_incr_wr_ptr = sram_access && sram_write_o;
           Tests:       T1 T2 T3 
151        1/1            assign sram_incr_rd_ptr = sram_access && !sram_write_o;
           Tests:       T1 T2 T3 
152                       if (SramAddrLeadingZeros > 0) begin : gen_zero_extend_sram_addrs
153                         assign sram_wr_addr = {{SramAddrLeadingZeros{1'b0}}, sram_wr_ptr} + SramBaseAddr;
154                         assign sram_rd_addr = {{SramAddrLeadingZeros{1'b0}}, sram_rd_ptr} + SramBaseAddr;
155                       end else begin : gen_no_zero_extend_sram_addrs
156        1/1              assign sram_wr_addr = sram_wr_ptr + SramBaseAddr;
           Tests:       T1 T2 T3 
157        1/1              assign sram_rd_addr = sram_rd_ptr + SramBaseAddr;
           Tests:       T1 T2 T3 
158                       end
159                     
160                       // FF to remember whether we read from the SRAM in the previous clock cycle.
161                       logic sram_read_in_prev_cyc_d, sram_read_in_prev_cyc_q;
162        1/1            assign sram_read_in_prev_cyc_d = clr_i ? 1'b0 : sram_incr_rd_ptr;
           Tests:       T1 T2 T3 
163                       always_ff @(posedge clk_i or negedge rst_ni) begin
164        1/1              if (!rst_ni) begin
           Tests:       T1 T2 T3 
165        1/1                sram_read_in_prev_cyc_q <= 1'b0;
           Tests:       T1 T2 T3 
166                         end else begin
167        1/1                sram_read_in_prev_cyc_q <= sram_read_in_prev_cyc_d;
           Tests:       T1 T2 T3 
168                         end
169                       end
170                     
171                       // Control logic for FIFO interface wready, output buffer writes, and SRAM requests
172                       logic state_err;
173                       always_comb begin
174        1/1              inp_buf_rready = 1'b0;
           Tests:       T1 T2 T3 
175        1/1              oup_buf_wvalid = 1'b0;
           Tests:       T1 T2 T3 
176        1/1              oup_buf_wdata = inp_buf_rdata;
           Tests:       T1 T2 T3 
177        1/1              sram_req_o = 1'b0;
           Tests:       T1 T2 T3 
178        1/1              sram_write_o = 1'b0;
           Tests:       T1 T2 T3 
179        1/1              sram_addr_o = sram_wr_addr;
           Tests:       T1 T2 T3 
180        1/1              state_err = 1'b0;
           Tests:       T1 T2 T3 
181                     
182                         // If the SRAM was read in the previous cycle, write the read data to the output buffer.
183        1/1              if (sram_read_in_prev_cyc_q) begin
           Tests:       T1 T2 T3 
184        1/1                oup_buf_wvalid = 1'b1;
           Tests:       T4 T5 T9 
185        1/1                oup_buf_wdata = sram_rdata_i;
           Tests:       T4 T5 T9 
186                           // The output buffer must be ready; otherwise we are in an erroneous state.
187        1/1                state_err = !oup_buf_wready;
           Tests:       T4 T5 T9 
188                         end
                        MISSING_ELSE
189                     
190                         // If the SRAM is not empty, data from the input buffer must flow via the SRAM.
191        1/1              if (!sram_empty) begin
           Tests:       T1 T2 T3 
192                     
193                           // Prioritize refilling of the output buffer: if the output buffer is not being filled to the
194                           // last slot in the current cycle or it is being read in the current cycle, read from the SRAM
195                           // so the output buffer can be written in the next cycle.
196        1/1                if (!((oup_buf_almost_full && oup_buf_wvalid) || oup_buf_full)
           Tests:       T4 T5 T9 
197                               || (fifo_rvalid_o && fifo_rready_i)) begin
198        1/1                  sram_req_o = 1'b1;
           Tests:       T4 T5 T9 
199        1/1                  sram_write_o = 1'b0;
           Tests:       T4 T5 T9 
200        1/1                  sram_addr_o = sram_rd_addr;
           Tests:       T4 T5 T9 
201                     
202                           // If the output buffer is full (and not being read), drain the input buffer into the SRAM.
203                           end else begin
204        1/1                  sram_req_o = !sram_full && inp_buf_rvalid;
           Tests:       T4 T5 T9 
205        1/1                  sram_write_o = 1'b1;
           Tests:       T4 T5 T9 
206        1/1                  sram_addr_o = sram_wr_addr;
           Tests:       T4 T5 T9 
207        1/1                  inp_buf_rready = !sram_full && sram_gnt_i;
           Tests:       T4 T5 T9 
208                           end
209                     
210                         // If the SRAM is empty, data must flow from the input buffer to the output buffer if the output
211                         // buffer is ready and is not receiving data read from the SRAM in the previous cycle
212        1/1              end else if (oup_buf_wready && !sram_read_in_prev_cyc_q) begin
           Tests:       T1 T2 T3 
213        1/1                oup_buf_wvalid = inp_buf_rvalid;
           Tests:       T1 T2 T3 
214        1/1                oup_buf_wdata = inp_buf_rdata;
           Tests:       T1 T2 T3 
215        1/1                inp_buf_rready = oup_buf_wready;
           Tests:       T1 T2 T3 
216                     
217                         // Otherwise the SRAM is empty but the output buffer cannot take the data from the input buffer,
218                         // so drain the input buffer into the SRAM.
219                         end else begin
220        1/1                sram_req_o = !sram_full && inp_buf_rvalid;
           Tests:       T1 T2 T3 
221        1/1                sram_write_o = 1'b1;
           Tests:       T1 T2 T3 
222        1/1                sram_addr_o = sram_wr_addr;
           Tests:       T1 T2 T3 
223        1/1                inp_buf_rready = !sram_full && sram_gnt_i;
           Tests:       T1 T2 T3 
224                         end
225                       end
226                     
227                       // Error output is high if any of the internal errors is high
228        1/1            assign err_o = |{inp_buf_err, oup_buf_err, sram_ptrs_err, state_err};
           Tests:       T1 T2 T3 
229                     
230                       // The SRAM and the output buffer together form the entire architectural capacity of the FIFO.
231                       // Thus, when both are full, the FIFO is no longer ready to receive writes even though the input
232                       // buffer could store one additional entry.  This ensures that in the cycle after an entry has
233                       // been read from the full FIFO, the next entry can be written to the FIFO.
234                       // (It may be possible that all input buffer slots except one can be counted to the architectural
235                       // capacity of the FIFO, but this is a relatively small optimization left for future work.)
236        1/1            assign fifo_wready_o = inp_buf_wready && !(sram_full && oup_buf_full);
           Tests:       T1 T2 T3 
237                     
238                       // The current depth of the FIFO represented by this module is the depth of all buffers plus the
239                       // FIFO in the SRAM plus one if there's an entry in transition between SRAM and output buffer.
240        1/1            assign fifo_depth_o = DepthW'(inp_buf_depth) + DepthW'(sram_depth) + DepthW'(oup_buf_depth) +
           Tests:       T1 T2 T3 
241                                             DepthW'(sram_read_in_prev_cyc_q);
242                     
243                       // SRAM write data always comes from the input buffer.
244        1/1            assign sram_wdata_o = inp_buf_rdata;
           Tests:       T1 T2 T3 
245                       assign sram_wmask_o = '1;
246                     
247                       // `sram_rvalid_i` is only used for assertions.
248                       logic unused_sram_rvalid;
249        1/1            assign unused_sram_rvalid = sram_rvalid_i;
           Tests:       T1 T2 T3 

---

Cond Coverage for Module : i2c_fifo_sync_sram_adapter

	Total	Covered	Percent
Conditions	51	42	82.35
Logical	51	42	82.35
Non-Logical	0	0
Event	0	0

 LINE       120
 EXPRESSION (fifo_wvalid_i && fifo_wready_o)
             ------1------    ------2------

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Covered	T55,T57,T86
1	1	Covered	T2,T3,T4

 LINE       125
 EXPRESSION (sram_req_o && sram_gnt_i)
             -----1----    -----2----

-1-	-2-	Status	Tests
0	1	Not Covered
1	0	Not Covered
1	1	Covered	T2,T3,T4

 LINE       150
 EXPRESSION (sram_access && sram_write_o)
             -----1-----    ------2-----

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Covered	T3,T4,T19
1	1	Covered	T2,T3,T4

 LINE       151
 EXPRESSION (sram_access && ((!sram_write_o)))
             -----1-----    --------2--------

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Covered	T2,T3,T4
1	1	Covered	T3,T4,T19

 LINE       162
 EXPRESSION (clr_i ? 1'b0 : sram_incr_rd_ptr)
             --1--

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T1,T2,T3

 LINE       196
 EXPRESSION (( ! ((oup_buf_almost_full && oup_buf_wvalid) || oup_buf_full) ) || (fifo_rvalid_o && fifo_rready_i))
             -------------------------------1-------------------------------    ----------------2---------------

-1-	-2-	Status	Tests
0	0	Covered	T2,T3,T4
0	1	Covered	T3,T4,T19
1	0	Covered	T55,T89,T160

 LINE       196
 SUB-EXPRESSION ( ! ((oup_buf_almost_full && oup_buf_wvalid) || oup_buf_full) )
                    ----------------------------1----------------------------

-1-	Status	Tests
0	Covered	T55,T89,T160
1	Covered	T2,T3,T4

 LINE       196
 SUB-EXPRESSION ((oup_buf_almost_full && oup_buf_wvalid) || oup_buf_full)
                 -------------------1-------------------    ------2-----

-1-	-2-	Status	Tests
0	0	Covered	T55,T89,T160
0	1	Covered	T2,T3,T4
1	0	Covered	T3,T4,T19

 LINE       196
 SUB-EXPRESSION (oup_buf_almost_full && oup_buf_wvalid)
                 ---------1---------    -------2------

-1-	-2-	Status	Tests
0	1	Not Covered
1	0	Covered	T2,T3,T4
1	1	Covered	T3,T4,T19

 LINE       196
 SUB-EXPRESSION (fifo_rvalid_o && fifo_rready_i)
                 ------1------    ------2------

-1-	-2-	Status	Tests
0	1	Not Covered
1	0	Covered	T2,T3,T4
1	1	Covered	T3,T4,T19

 LINE       204
 EXPRESSION (((!sram_full)) && inp_buf_rvalid)
             -------1------    -------2------

-1-	-2-	Status	Tests
0	1	Not Covered
1	0	Covered	T2,T3,T4
1	1	Covered	T2,T3,T4

 LINE       207
 EXPRESSION (((!sram_full)) && sram_gnt_i)
             -------1------    -----2----

-1-	-2-	Status	Tests
0	1	Not Covered
1	0	Covered	T2,T3,T4
1	1	Covered	T2,T3,T4

 LINE       212
 EXPRESSION (oup_buf_wready && ((!sram_read_in_prev_cyc_q)))
             -------1------    --------------2-------------

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Covered	T3,T4,T19
1	1	Covered	T1,T2,T3

 LINE       220
 EXPRESSION (((!sram_full)) && inp_buf_rvalid)
             -------1------    -------2------

-1-	-2-	Status	Tests
0	1	Not Covered
1	0	Covered	T1,T2,T3
1	1	Covered	T2,T3,T4

 LINE       223
 EXPRESSION (((!sram_full)) && sram_gnt_i)
             -------1------    -----2----

-1-	-2-	Status	Tests
0	1	Not Covered
1	0	Covered	T1,T2,T3
1	1	Covered	T2,T3,T4

 LINE       236
 EXPRESSION (inp_buf_wready && ( ! (sram_full && oup_buf_full) ))
             -------1------    ----------------2----------------

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Covered	T10,T19,T40
1	1	Covered	T1,T2,T3

 LINE       236
 SUB-EXPRESSION ( ! (sram_full && oup_buf_full) )
                    -------------1-------------

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T10,T19,T40

 LINE       236
 SUB-EXPRESSION (sram_full && oup_buf_full)
                 ----1----    ------2-----

-1-	-2-	Status	Tests
0	1	Covered	T2,T3,T4
1	0	Not Covered
1	1	Covered	T10,T19,T40

---

Branch Coverage for Module : i2c_fifo_sync_sram_adapter

	Line No.	Total	Covered	Percent
Branches		10	10	100.00
TERNARY	162	2	2	100.00
IF	164	2	2	100.00
IF	183	2	2	100.00
IF	191	4	4	100.00

162          assign sram_read_in_prev_cyc_d = clr_i ? 1'b0 : sram_incr_rd_ptr;
                                                    -1-  
                                                    ==>  
                                                    ==>  

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T2,T3

164            if (!rst_ni) begin
               -1-  
165              sram_read_in_prev_cyc_q <= 1'b0;
                 ==>
166            end else begin
167              sram_read_in_prev_cyc_q <= sram_read_in_prev_cyc_d;
                 ==>

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T2,T3

183            if (sram_read_in_prev_cyc_q) begin
               -1-  
184              oup_buf_wvalid = 1'b1;
                 ==>
185              oup_buf_wdata = sram_rdata_i;
186              // The output buffer must be ready; otherwise we are in an erroneous state.
187              state_err = !oup_buf_wready;
188            end
               MISSING_ELSE
               ==>

Branches:

-1-	Status	Tests
1	Covered	T3,T4,T19
0	Covered	T1,T2,T3

191            if (!sram_empty) begin
               -1-  
192        
193              // Prioritize refilling of the output buffer: if the output buffer is not being filled to the
194              // last slot in the current cycle or it is being read in the current cycle, read from the SRAM
195              // so the output buffer can be written in the next cycle.
196              if (!((oup_buf_almost_full && oup_buf_wvalid) || oup_buf_full)
                 -2-  
197                  || (fifo_rvalid_o && fifo_rready_i)) begin
198                sram_req_o = 1'b1;
                   ==>
199                sram_write_o = 1'b0;
200                sram_addr_o = sram_rd_addr;
201        
202              // If the output buffer is full (and not being read), drain the input buffer into the SRAM.
203              end else begin
204                sram_req_o = !sram_full && inp_buf_rvalid;
                   ==>
205                sram_write_o = 1'b1;
206                sram_addr_o = sram_wr_addr;
207                inp_buf_rready = !sram_full && sram_gnt_i;
208              end
209        
210            // If the SRAM is empty, data must flow from the input buffer to the output buffer if the output
211            // buffer is ready and is not receiving data read from the SRAM in the previous cycle
212            end else if (oup_buf_wready && !sram_read_in_prev_cyc_q) begin
                        -3-  
213              oup_buf_wvalid = inp_buf_rvalid;
                 ==>
214              oup_buf_wdata = inp_buf_rdata;
215              inp_buf_rready = oup_buf_wready;
216        
217            // Otherwise the SRAM is empty but the output buffer cannot take the data from the input buffer,
218            // so drain the input buffer into the SRAM.
219            end else begin
220              sram_req_o = !sram_full && inp_buf_rvalid;
                 ==>

Branches:

-1-	-2-	-3-	Status	Tests
1	1	-	Covered	T3,T4,T19
1	0	-	Covered	T2,T3,T4
0	-	1	Covered	T1,T2,T3
0	-	0	Covered	T1,T2,T3

---

Assert Coverage for Module : i2c_fifo_sync_sram_adapter

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	7	7	100.00	7	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	7	7	100.00	7	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
MinimalSramAw_A	6700	6700	0	0
MinimalSramFifoDepth_A	6700	6700	0	0
NoErr_A	1635847044	1635151184	0	0
NoSramReadWhenEmpty_A	1635847044	1283848393	0	0
NoSramWriteWhenFull_A	1635847044	26352654	0	0
OupBufWreadyAfterSramRead_A	1635847044	661920	0	0
SramRvalidAfterRead_A	1635847044	661920	0	0

MinimalSramAw_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	6700	6700	0	0
T1	4	4	0	0
T2	4	4	0	0
T3	4	4	0	0
T4	4	4	0	0
T5	4	4	0	0
T6	4	4	0	0
T7	4	4	0	0
T8	4	4	0	0
T9	4	4	0	0
T10	4	4	0	0

MinimalSramFifoDepth_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	6700	6700	0	0
T1	4	4	0	0
T2	4	4	0	0
T3	4	4	0	0
T4	4	4	0	0
T5	4	4	0	0
T6	4	4	0	0
T7	4	4	0	0
T8	4	4	0	0
T9	4	4	0	0
T10	4	4	0	0

NoErr_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	1635847044	1635151184	0	0
T1	7692	7452	0	0
T2	41224	40964	0	0
T3	55604	52712	0	0
T4	1986616	1986264	0	0
T5	84852	84576	0	0
T6	38484	38216	0	0
T7	50288	49976	0	0
T8	29376	28996	0	0
T9	38768	38556	0	0
T10	58820	58476	0	0

NoSramReadWhenEmpty_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	1635847044	1283848393	0	0
T1	7692	7452	0	0
T2	41224	34700	0	0
T3	55604	51931	0	0
T4	1986616	1608816	0	0
T5	84852	74871	0	0
T6	38484	35592	0	0
T7	50288	49976	0	0
T8	29376	23073	0	0
T9	38768	30342	0	0
T10	58820	46394	0	0

NoSramWriteWhenFull_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	1635847044	26352654	0	0
T10	14705	4	0	0
T11	82718	0	0	0
T16	0	49853	0	0
T17	12278	0	0	0
T19	426990	59826	0	0
T27	134215	0	0	0
T28	35167	0	0	0
T30	23456	0	0	0
T35	0	80295	0	0
T47	0	93221	0	0
T49	57668	0	0	0
T50	20238	0	0	0
T51	98672	0	0	0
T55	375410	26	0	0
T57	0	21	0	0
T68	45068	1624	0	0
T69	85700	23	0	0
T70	0	8	0	0
T73	0	1360	0	0
T74	0	1527	0	0
T75	20900	0	0	0
T78	23009	0	0	0
T79	134343	0	0	0
T80	245643	0	0	0
T81	211990	0	0	0
T94	0	4003	0	0
T98	0	36513	0	0
T102	1634	0	0	0
T105	2464	0	0	0
T126	0	6269	0	0
T161	0	5224	0	0
T162	0	6	0	0
T163	0	5	0	0
T164	0	765	0	0
T165	0	3575	0	0
T166	0	95520	0	0
T167	129424	0	0	0

OupBufWreadyAfterSramRead_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	1635847044	661920	0	0
T3	13901	2	0	0
T4	993308	1435	0	0
T5	42426	6	0	0
T6	19242	0	0	0
T7	25144	0	0	0
T8	14688	0	0	0
T9	19384	52	0	0
T10	29410	0	0	0
T11	0	64	0	0
T12	0	143	0	0
T19	0	1130	0	0
T27	0	3	0	0
T28	0	109	0	0
T37	0	1	0	0
T41	0	23	0	0
T48	0	58	0	0
T49	115336	272	0	0
T50	40476	0	0	0
T51	0	130	0	0
T69	0	266	0	0
T71	0	144	0	0
T74	55698	0	0	0
T77	7746	0	0	0
T78	23009	44	0	0
T80	0	29	0	0
T86	170699	744	0	0
T167	0	435	0	0
T168	0	274	0	0
T169	3970	0	0	0
T170	2357	0	0	0
T171	55351	0	0	0
T172	7750	0	0	0
T173	39984	0	0	0
T174	72922	0	0	0
T175	29871	0	0	0

SramRvalidAfterRead_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	1635847044	661920	0	0
T3	13901	2	0	0
T4	993308	1435	0	0
T5	42426	6	0	0
T6	19242	0	0	0
T7	25144	0	0	0
T8	14688	0	0	0
T9	19384	52	0	0
T10	29410	0	0	0
T11	0	64	0	0
T12	0	143	0	0
T19	0	1130	0	0
T27	0	3	0	0
T28	0	109	0	0
T37	0	1	0	0
T41	0	23	0	0
T48	0	58	0	0
T49	115336	272	0	0
T50	40476	0	0	0
T51	0	130	0	0
T69	0	266	0	0
T71	0	144	0	0
T74	55698	0	0	0
T77	7746	0	0	0
T78	23009	44	0	0
T80	0	29	0	0
T86	170699	744	0	0
T167	0	435	0	0
T168	0	274	0	0
T169	3970	0	0	0
T170	2357	0	0	0
T171	55351	0	0	0
T172	7750	0	0	0
T173	39984	0	0	0
T174	72922	0	0	0
T175	29871	0	0	0

Line Coverage for Instance : tb.dut.i2c_core.u_fifos.u_fmt_fifo_sram_adapter

	Line No.	Total	Covered	Percent
TOTAL		44	44	100.00
CONT_ASSIGN	120	1	1	100.00
CONT_ASSIGN	121	1	1	100.00
CONT_ASSIGN	125	1	1	100.00
CONT_ASSIGN	150	1	1	100.00
CONT_ASSIGN	151	1	1	100.00
CONT_ASSIGN	153	1	1	100.00
CONT_ASSIGN	154	1	1	100.00
CONT_ASSIGN	162	1	1	100.00
ALWAYS	164	3	3	100.00
ALWAYS	174	28	28	100.00
CONT_ASSIGN	228	1	1	100.00
CONT_ASSIGN	236	1	1	100.00
CONT_ASSIGN	240	1	1	100.00
CONT_ASSIGN	244	1	1	100.00
CONT_ASSIGN	249	1	1	100.00

119                       );
120        1/1            assign inp_buf_wvalid = fifo_wvalid_i && fifo_wready_o;
           Tests:       T1 T2 T3 
121        1/1            assign oup_buf_almost_full = oup_buf_depth >= OupBufDepthW'(OupBufDepth - 1);
           Tests:       T1 T2 T3 
122                     
123                       // Signal whether we access the SRAM in this cycle
124                       logic sram_access;
125        1/1            assign sram_access = sram_req_o && sram_gnt_i;
           Tests:       T1 T2 T3 
126                     
127                       // SRAM read and write addresses
128                       logic [SramAw-1:0]     sram_wr_addr, sram_rd_addr;
129                       logic [SramPtrW-1:0]   sram_wr_ptr, sram_rd_ptr;
130                       logic [SramDepthW-1:0] sram_depth;
131                       logic                  sram_incr_wr_ptr, sram_incr_rd_ptr;
132                       logic                  sram_full, sram_empty;
133                       logic                  sram_ptrs_err;
134                       prim_fifo_sync_cnt #(
135                         .Depth (SramFifoDepth),
136                         .Secure(1'b0)
137                       ) u_sram_ptrs (
138                         .clk_i,
139                         .rst_ni,
140                         .clr_i,
141                         .incr_wptr_i(sram_incr_wr_ptr),
142                         .incr_rptr_i(sram_incr_rd_ptr),
143                         .wptr_o     (sram_wr_ptr),
144                         .rptr_o     (sram_rd_ptr),
145                         .full_o     (sram_full),
146                         .empty_o    (sram_empty),
147                         .depth_o    (sram_depth),
148                         .err_o      (sram_ptrs_err)
149                       );
150        1/1            assign sram_incr_wr_ptr = sram_access && sram_write_o;
           Tests:       T1 T2 T3 
151        1/1            assign sram_incr_rd_ptr = sram_access && !sram_write_o;
           Tests:       T1 T2 T3 
152                       if (SramAddrLeadingZeros > 0) begin : gen_zero_extend_sram_addrs
153        1/1              assign sram_wr_addr = {{SramAddrLeadingZeros{1'b0}}, sram_wr_ptr} + SramBaseAddr;
           Tests:       T1 T2 T3 
154        1/1              assign sram_rd_addr = {{SramAddrLeadingZeros{1'b0}}, sram_rd_ptr} + SramBaseAddr;
           Tests:       T1 T2 T3 
155                       end else begin : gen_no_zero_extend_sram_addrs
156                         assign sram_wr_addr = sram_wr_ptr + SramBaseAddr;
157                         assign sram_rd_addr = sram_rd_ptr + SramBaseAddr;
158                       end
159                     
160                       // FF to remember whether we read from the SRAM in the previous clock cycle.
161                       logic sram_read_in_prev_cyc_d, sram_read_in_prev_cyc_q;
162        1/1            assign sram_read_in_prev_cyc_d = clr_i ? 1'b0 : sram_incr_rd_ptr;
           Tests:       T1 T2 T3 
163                       always_ff @(posedge clk_i or negedge rst_ni) begin
164        1/1              if (!rst_ni) begin
           Tests:       T1 T2 T3 
165        1/1                sram_read_in_prev_cyc_q <= 1'b0;
           Tests:       T1 T2 T3 
166                         end else begin
167        1/1                sram_read_in_prev_cyc_q <= sram_read_in_prev_cyc_d;
           Tests:       T1 T2 T3 
168                         end
169                       end
170                     
171                       // Control logic for FIFO interface wready, output buffer writes, and SRAM requests
172                       logic state_err;
173                       always_comb begin
174        1/1              inp_buf_rready = 1'b0;
           Tests:       T1 T2 T3 
175        1/1              oup_buf_wvalid = 1'b0;
           Tests:       T1 T2 T3 
176        1/1              oup_buf_wdata = inp_buf_rdata;
           Tests:       T1 T2 T3 
177        1/1              sram_req_o = 1'b0;
           Tests:       T1 T2 T3 
178        1/1              sram_write_o = 1'b0;
           Tests:       T1 T2 T3 
179        1/1              sram_addr_o = sram_wr_addr;
           Tests:       T1 T2 T3 
180        1/1              state_err = 1'b0;
           Tests:       T1 T2 T3 
181                     
182                         // If the SRAM was read in the previous cycle, write the read data to the output buffer.
183        1/1              if (sram_read_in_prev_cyc_q) begin
           Tests:       T1 T2 T3 
184        1/1                oup_buf_wvalid = 1'b1;
           Tests:       T3 T19 T11 
185        1/1                oup_buf_wdata = sram_rdata_i;
           Tests:       T3 T19 T11 
186                           // The output buffer must be ready; otherwise we are in an erroneous state.
187        1/1                state_err = !oup_buf_wready;
           Tests:       T3 T19 T11 
188                         end
                        MISSING_ELSE
189                     
190                         // If the SRAM is not empty, data from the input buffer must flow via the SRAM.
191        1/1              if (!sram_empty) begin
           Tests:       T1 T2 T3 
192                     
193                           // Prioritize refilling of the output buffer: if the output buffer is not being filled to the
194                           // last slot in the current cycle or it is being read in the current cycle, read from the SRAM
195                           // so the output buffer can be written in the next cycle.
196        1/1                if (!((oup_buf_almost_full && oup_buf_wvalid) || oup_buf_full)
           Tests:       T2 T3 T19 
197                               || (fifo_rvalid_o && fifo_rready_i)) begin
198        1/1                  sram_req_o = 1'b1;
           Tests:       T3 T19 T17 
199        1/1                  sram_write_o = 1'b0;
           Tests:       T3 T19 T17 
200        1/1                  sram_addr_o = sram_rd_addr;
           Tests:       T3 T19 T17 
201                     
202                           // If the output buffer is full (and not being read), drain the input buffer into the SRAM.
203                           end else begin
204        1/1                  sram_req_o = !sram_full && inp_buf_rvalid;
           Tests:       T2 T3 T19 
205        1/1                  sram_write_o = 1'b1;
           Tests:       T2 T3 T19 
206        1/1                  sram_addr_o = sram_wr_addr;
           Tests:       T2 T3 T19 
207        1/1                  inp_buf_rready = !sram_full && sram_gnt_i;
           Tests:       T2 T3 T19 
208                           end
209                     
210                         // If the SRAM is empty, data must flow from the input buffer to the output buffer if the output
211                         // buffer is ready and is not receiving data read from the SRAM in the previous cycle
212        1/1              end else if (oup_buf_wready && !sram_read_in_prev_cyc_q) begin
           Tests:       T1 T2 T3 
213        1/1                oup_buf_wvalid = inp_buf_rvalid;
           Tests:       T1 T2 T3 
214        1/1                oup_buf_wdata = inp_buf_rdata;
           Tests:       T1 T2 T3 
215        1/1                inp_buf_rready = oup_buf_wready;
           Tests:       T1 T2 T3 
216                     
217                         // Otherwise the SRAM is empty but the output buffer cannot take the data from the input buffer,
218                         // so drain the input buffer into the SRAM.
219                         end else begin
220        1/1                sram_req_o = !sram_full && inp_buf_rvalid;
           Tests:       T1 T2 T3 
221        1/1                sram_write_o = 1'b1;
           Tests:       T1 T2 T3 
222        1/1                sram_addr_o = sram_wr_addr;
           Tests:       T1 T2 T3 
223        1/1                inp_buf_rready = !sram_full && sram_gnt_i;
           Tests:       T1 T2 T3 
224                         end
225                       end
226                     
227                       // Error output is high if any of the internal errors is high
228        1/1            assign err_o = |{inp_buf_err, oup_buf_err, sram_ptrs_err, state_err};
           Tests:       T1 T2 T3 
229                     
230                       // The SRAM and the output buffer together form the entire architectural capacity of the FIFO.
231                       // Thus, when both are full, the FIFO is no longer ready to receive writes even though the input
232                       // buffer could store one additional entry.  This ensures that in the cycle after an entry has
233                       // been read from the full FIFO, the next entry can be written to the FIFO.
234                       // (It may be possible that all input buffer slots except one can be counted to the architectural
235                       // capacity of the FIFO, but this is a relatively small optimization left for future work.)
236        1/1            assign fifo_wready_o = inp_buf_wready && !(sram_full && oup_buf_full);
           Tests:       T1 T2 T3 
237                     
238                       // The current depth of the FIFO represented by this module is the depth of all buffers plus the
239                       // FIFO in the SRAM plus one if there's an entry in transition between SRAM and output buffer.
240        1/1            assign fifo_depth_o = DepthW'(inp_buf_depth) + DepthW'(sram_depth) + DepthW'(oup_buf_depth) +
           Tests:       T1 T2 T3 
241                                             DepthW'(sram_read_in_prev_cyc_q);
242                     
243                       // SRAM write data always comes from the input buffer.
244        1/1            assign sram_wdata_o = inp_buf_rdata;
           Tests:       T1 T2 T3 
245                       assign sram_wmask_o = '1;
246                     
247                       // `sram_rvalid_i` is only used for assertions.
248                       logic unused_sram_rvalid;
249        1/1            assign unused_sram_rvalid = sram_rvalid_i;
           Tests:       T1 T2 T3 

---

Cond Coverage for Instance : tb.dut.i2c_core.u_fifos.u_fmt_fifo_sram_adapter

	Total	Covered	Percent
Conditions	51	38	74.51
Logical	51	38	74.51
Non-Logical	0	0
Event	0	0

 LINE       120
 EXPRESSION (fifo_wvalid_i && fifo_wready_o)
             ------1------    ------2------

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Not Covered
1	1	Covered	T2,T3,T7

 LINE       125
 EXPRESSION (sram_req_o && sram_gnt_i)
             -----1----    -----2----

-1-	-2-	Status	Tests
0	1	Not Covered
1	0	Not Covered
1	1	Covered	T2,T3,T19

 LINE       150
 EXPRESSION (sram_access && sram_write_o)
             -----1-----    ------2-----

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Covered	T3,T19,T17
1	1	Covered	T2,T3,T19

 LINE       151
 EXPRESSION (sram_access && ((!sram_write_o)))
             -----1-----    --------2--------

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Covered	T2,T3,T19
1	1	Covered	T3,T19,T17

 LINE       162
 EXPRESSION (clr_i ? 1'b0 : sram_incr_rd_ptr)
             --1--

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T1,T2,T3

 LINE       196
 EXPRESSION (( ! ((oup_buf_almost_full && oup_buf_wvalid) || oup_buf_full) ) || (fifo_rvalid_o && fifo_rready_i))
             -------------------------------1-------------------------------    ----------------2---------------

-1-	-2-	Status	Tests
0	0	Covered	T2,T3,T19
0	1	Covered	T3,T19,T17
1	0	Not Covered

 LINE       196
 SUB-EXPRESSION ( ! ((oup_buf_almost_full && oup_buf_wvalid) || oup_buf_full) )
                    ----------------------------1----------------------------

-1-	Status	Tests
0	Not Covered
1	Covered	T2,T3,T19

 LINE       196
 SUB-EXPRESSION ((oup_buf_almost_full && oup_buf_wvalid) || oup_buf_full)
                 -------------------1-------------------    ------2-----

-1-	-2-	Status	Tests
0	0	Not Covered
0	1	Covered	T2,T3,T19
1	0	Covered	T3,T19,T11

 LINE       196
 SUB-EXPRESSION (oup_buf_almost_full && oup_buf_wvalid)
                 ---------1---------    -------2------

-1-	-2-	Status	Tests
0	1	Not Covered
1	0	Covered	T2,T3,T19
1	1	Covered	T3,T19,T11

 LINE       196
 SUB-EXPRESSION (fifo_rvalid_o && fifo_rready_i)
                 ------1------    ------2------

-1-	-2-	Status	Tests
0	1	Not Covered
1	0	Covered	T2,T3,T19
1	1	Covered	T3,T19,T17

 LINE       204
 EXPRESSION (((!sram_full)) && inp_buf_rvalid)
             -------1------    -------2------

-1-	-2-	Status	Tests
0	1	Not Covered
1	0	Covered	T2,T3,T19
1	1	Covered	T2,T3,T19

 LINE       207
 EXPRESSION (((!sram_full)) && sram_gnt_i)
             -------1------    -----2----

-1-	-2-	Status	Tests
0	1	Not Covered
1	0	Covered	T2,T3,T19
1	1	Covered	T2,T3,T19

 LINE       212
 EXPRESSION (oup_buf_wready && ((!sram_read_in_prev_cyc_q)))
             -------1------    --------------2-------------

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Covered	T3,T19,T11
1	1	Covered	T1,T2,T3

 LINE       220
 EXPRESSION (((!sram_full)) && inp_buf_rvalid)
             -------1------    -------2------

-1-	-2-	Status	Tests
0	1	Not Covered
1	0	Covered	T1,T2,T3
1	1	Covered	T2,T3,T19

 LINE       223
 EXPRESSION (((!sram_full)) && sram_gnt_i)
             -------1------    -----2----

-1-	-2-	Status	Tests
0	1	Not Covered
1	0	Covered	T1,T2,T3
1	1	Covered	T2,T3,T19

 LINE       236
 EXPRESSION (inp_buf_wready && ( ! (sram_full && oup_buf_full) ))
             -------1------    ----------------2----------------

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Covered	T19,T161,T94
1	1	Covered	T1,T2,T3

 LINE       236
 SUB-EXPRESSION ( ! (sram_full && oup_buf_full) )
                    -------------1-------------

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T19,T161,T94

 LINE       236
 SUB-EXPRESSION (sram_full && oup_buf_full)
                 ----1----    ------2-----

-1-	-2-	Status	Tests
0	1	Covered	T2,T3,T7
1	0	Not Covered
1	1	Covered	T19,T161,T94

---

Branch Coverage for Instance : tb.dut.i2c_core.u_fifos.u_fmt_fifo_sram_adapter

	Line No.	Total	Covered	Percent
Branches		10	10	100.00
TERNARY	162	2	2	100.00
IF	164	2	2	100.00
IF	183	2	2	100.00
IF	191	4	4	100.00

162          assign sram_read_in_prev_cyc_d = clr_i ? 1'b0 : sram_incr_rd_ptr;
                                                    -1-  
                                                    ==>  
                                                    ==>  

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T2,T3

164            if (!rst_ni) begin
               -1-  
165              sram_read_in_prev_cyc_q <= 1'b0;
                 ==>
166            end else begin
167              sram_read_in_prev_cyc_q <= sram_read_in_prev_cyc_d;
                 ==>

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T2,T3

183            if (sram_read_in_prev_cyc_q) begin
               -1-  
184              oup_buf_wvalid = 1'b1;
                 ==>
185              oup_buf_wdata = sram_rdata_i;
186              // The output buffer must be ready; otherwise we are in an erroneous state.
187              state_err = !oup_buf_wready;
188            end
               MISSING_ELSE
               ==>

Branches:

-1-	Status	Tests
1	Covered	T3,T19,T11
0	Covered	T1,T2,T3

191            if (!sram_empty) begin
               -1-  
192        
193              // Prioritize refilling of the output buffer: if the output buffer is not being filled to the
194              // last slot in the current cycle or it is being read in the current cycle, read from the SRAM
195              // so the output buffer can be written in the next cycle.
196              if (!((oup_buf_almost_full && oup_buf_wvalid) || oup_buf_full)
                 -2-  
197                  || (fifo_rvalid_o && fifo_rready_i)) begin
198                sram_req_o = 1'b1;
                   ==>
199                sram_write_o = 1'b0;
200                sram_addr_o = sram_rd_addr;
201        
202              // If the output buffer is full (and not being read), drain the input buffer into the SRAM.
203              end else begin
204                sram_req_o = !sram_full && inp_buf_rvalid;
                   ==>
205                sram_write_o = 1'b1;
206                sram_addr_o = sram_wr_addr;
207                inp_buf_rready = !sram_full && sram_gnt_i;
208              end
209        
210            // If the SRAM is empty, data must flow from the input buffer to the output buffer if the output
211            // buffer is ready and is not receiving data read from the SRAM in the previous cycle
212            end else if (oup_buf_wready && !sram_read_in_prev_cyc_q) begin
                        -3-  
213              oup_buf_wvalid = inp_buf_rvalid;
                 ==>
214              oup_buf_wdata = inp_buf_rdata;
215              inp_buf_rready = oup_buf_wready;
216        
217            // Otherwise the SRAM is empty but the output buffer cannot take the data from the input buffer,
218            // so drain the input buffer into the SRAM.
219            end else begin
220              sram_req_o = !sram_full && inp_buf_rvalid;
                 ==>

Branches:

-1-	-2-	-3-	Status	Tests
1	1	-	Covered	T3,T19,T17
1	0	-	Covered	T2,T3,T19
0	-	1	Covered	T1,T2,T3
0	-	0	Covered	T1,T2,T3

---

Assert Coverage for Instance : tb.dut.i2c_core.u_fifos.u_fmt_fifo_sram_adapter

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	7	7	100.00	7	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	7	7	100.00	7	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
MinimalSramAw_A	1675	1675	0	0
MinimalSramFifoDepth_A	1675	1675	0	0
NoErr_A	408961761	408787796	0	0
NoSramReadWhenEmpty_A	408961761	345434746	0	0
NoSramWriteWhenFull_A	408961761	25778919	0	0
OupBufWreadyAfterSramRead_A	408961761	182060	0	0
SramRvalidAfterRead_A	408961761	182060	0	0

MinimalSramAw_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	1675	1675	0	0
T1	1	1	0	0
T2	1	1	0	0
T3	1	1	0	0
T4	1	1	0	0
T5	1	1	0	0
T6	1	1	0	0
T7	1	1	0	0
T8	1	1	0	0
T9	1	1	0	0
T10	1	1	0	0

MinimalSramFifoDepth_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	1675	1675	0	0
T1	1	1	0	0
T2	1	1	0	0
T3	1	1	0	0
T4	1	1	0	0
T5	1	1	0	0
T6	1	1	0	0
T7	1	1	0	0
T8	1	1	0	0
T9	1	1	0	0
T10	1	1	0	0

NoErr_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	408961761	408787796	0	0
T1	1923	1863	0	0
T2	10306	10241	0	0
T3	13901	13178	0	0
T4	496654	496566	0	0
T5	21213	21144	0	0
T6	9621	9554	0	0
T7	12572	12494	0	0
T8	7344	7249	0	0
T9	9692	9639	0	0
T10	14705	14619	0	0

NoSramReadWhenEmpty_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	408961761	345434746	0	0
T1	1923	1863	0	0
T2	10306	3977	0	0
T3	13901	12397	0	0
T4	496654	496566	0	0
T5	21213	21144	0	0
T6	9621	9554	0	0
T7	12572	12494	0	0
T8	7344	7249	0	0
T9	9692	9639	0	0
T10	14705	14619	0	0

NoSramWriteWhenFull_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	408961761	25778919	0	0
T11	41359	0	0	0
T16	0	49853	0	0
T17	6139	0	0	0
T19	213495	59826	0	0
T27	134215	0	0	0
T28	35167	0	0	0
T30	11728	0	0	0
T35	0	80295	0	0
T47	0	93221	0	0
T55	187705	0	0	0
T69	42850	0	0	0
T75	10450	0	0	0
T81	105995	0	0	0
T94	0	4003	0	0
T98	0	36513	0	0
T126	0	6269	0	0
T161	0	5224	0	0
T165	0	3575	0	0
T166	0	95520	0	0

OupBufWreadyAfterSramRead_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	408961761	182060	0	0
T3	13901	2	0	0
T4	496654	0	0	0
T5	21213	0	0	0
T6	9621	0	0	0
T7	12572	0	0	0
T8	7344	0	0	0
T9	9692	0	0	0
T10	14705	0	0	0
T11	0	64	0	0
T12	0	143	0	0
T19	0	1130	0	0
T27	0	3	0	0
T28	0	109	0	0
T37	0	1	0	0
T41	0	23	0	0
T48	0	58	0	0
T49	57668	0	0	0
T50	20238	0	0	0
T168	0	274	0	0

SramRvalidAfterRead_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	408961761	182060	0	0
T3	13901	2	0	0
T4	496654	0	0	0
T5	21213	0	0	0
T6	9621	0	0	0
T7	12572	0	0	0
T8	7344	0	0	0
T9	9692	0	0	0
T10	14705	0	0	0
T11	0	64	0	0
T12	0	143	0	0
T19	0	1130	0	0
T27	0	3	0	0
T28	0	109	0	0
T37	0	1	0	0
T41	0	23	0	0
T48	0	58	0	0
T49	57668	0	0	0
T50	20238	0	0	0
T168	0	274	0	0

Line Coverage for Instance : tb.dut.i2c_core.u_fifos.u_tx_fifo_sram_adapter

	Line No.	Total	Covered	Percent
TOTAL		44	44	100.00
CONT_ASSIGN	120	1	1	100.00
CONT_ASSIGN	121	1	1	100.00
CONT_ASSIGN	125	1	1	100.00
CONT_ASSIGN	150	1	1	100.00
CONT_ASSIGN	151	1	1	100.00
CONT_ASSIGN	153	1	1	100.00
CONT_ASSIGN	154	1	1	100.00
CONT_ASSIGN	162	1	1	100.00
ALWAYS	164	3	3	100.00
ALWAYS	174	28	28	100.00
CONT_ASSIGN	228	1	1	100.00
CONT_ASSIGN	236	1	1	100.00
CONT_ASSIGN	240	1	1	100.00
CONT_ASSIGN	244	1	1	100.00
CONT_ASSIGN	249	1	1	100.00

119                       );
120        1/1            assign inp_buf_wvalid = fifo_wvalid_i && fifo_wready_o;
           Tests:       T1 T2 T3 
121        1/1            assign oup_buf_almost_full = oup_buf_depth >= OupBufDepthW'(OupBufDepth - 1);
           Tests:       T1 T2 T3 
122                     
123                       // Signal whether we access the SRAM in this cycle
124                       logic sram_access;
125        1/1            assign sram_access = sram_req_o && sram_gnt_i;
           Tests:       T1 T2 T3 
126                     
127                       // SRAM read and write addresses
128                       logic [SramAw-1:0]     sram_wr_addr, sram_rd_addr;
129                       logic [SramPtrW-1:0]   sram_wr_ptr, sram_rd_ptr;
130                       logic [SramDepthW-1:0] sram_depth;
131                       logic                  sram_incr_wr_ptr, sram_incr_rd_ptr;
132                       logic                  sram_full, sram_empty;
133                       logic                  sram_ptrs_err;
134                       prim_fifo_sync_cnt #(
135                         .Depth (SramFifoDepth),
136                         .Secure(1'b0)
137                       ) u_sram_ptrs (
138                         .clk_i,
139                         .rst_ni,
140                         .clr_i,
141                         .incr_wptr_i(sram_incr_wr_ptr),
142                         .incr_rptr_i(sram_incr_rd_ptr),
143                         .wptr_o     (sram_wr_ptr),
144                         .rptr_o     (sram_rd_ptr),
145                         .full_o     (sram_full),
146                         .empty_o    (sram_empty),
147                         .depth_o    (sram_depth),
148                         .err_o      (sram_ptrs_err)
149                       );
150        1/1            assign sram_incr_wr_ptr = sram_access && sram_write_o;
           Tests:       T1 T2 T3 
151        1/1            assign sram_incr_rd_ptr = sram_access && !sram_write_o;
           Tests:       T1 T2 T3 
152                       if (SramAddrLeadingZeros > 0) begin : gen_zero_extend_sram_addrs
153        1/1              assign sram_wr_addr = {{SramAddrLeadingZeros{1'b0}}, sram_wr_ptr} + SramBaseAddr;
           Tests:       T1 T2 T3 
154        1/1              assign sram_rd_addr = {{SramAddrLeadingZeros{1'b0}}, sram_rd_ptr} + SramBaseAddr;
           Tests:       T1 T2 T3 
155                       end else begin : gen_no_zero_extend_sram_addrs
156                         assign sram_wr_addr = sram_wr_ptr + SramBaseAddr;
157                         assign sram_rd_addr = sram_rd_ptr + SramBaseAddr;
158                       end
159                     
160                       // FF to remember whether we read from the SRAM in the previous clock cycle.
161                       logic sram_read_in_prev_cyc_d, sram_read_in_prev_cyc_q;
162        1/1            assign sram_read_in_prev_cyc_d = clr_i ? 1'b0 : sram_incr_rd_ptr;
           Tests:       T1 T2 T3 
163                       always_ff @(posedge clk_i or negedge rst_ni) begin
164        1/1              if (!rst_ni) begin
           Tests:       T1 T2 T3 
165        1/1                sram_read_in_prev_cyc_q <= 1'b0;
           Tests:       T1 T2 T3 
166                         end else begin
167        1/1                sram_read_in_prev_cyc_q <= sram_read_in_prev_cyc_d;
           Tests:       T1 T2 T3 
168                         end
169                       end
170                     
171                       // Control logic for FIFO interface wready, output buffer writes, and SRAM requests
172                       logic state_err;
173                       always_comb begin
174        1/1              inp_buf_rready = 1'b0;
           Tests:       T1 T2 T3 
175        1/1              oup_buf_wvalid = 1'b0;
           Tests:       T1 T2 T3 
176        1/1              oup_buf_wdata = inp_buf_rdata;
           Tests:       T1 T2 T3 
177        1/1              sram_req_o = 1'b0;
           Tests:       T1 T2 T3 
178        1/1              sram_write_o = 1'b0;
           Tests:       T1 T2 T3 
179        1/1              sram_addr_o = sram_wr_addr;
           Tests:       T1 T2 T3 
180        1/1              state_err = 1'b0;
           Tests:       T1 T2 T3 
181                     
182                         // If the SRAM was read in the previous cycle, write the read data to the output buffer.
183        1/1              if (sram_read_in_prev_cyc_q) begin
           Tests:       T1 T2 T3 
184        1/1                oup_buf_wvalid = 1'b1;
           Tests:       T4 T5 T6 
185        1/1                oup_buf_wdata = sram_rdata_i;
           Tests:       T4 T5 T6 
186                           // The output buffer must be ready; otherwise we are in an erroneous state.
187        1/1                state_err = !oup_buf_wready;
           Tests:       T4 T5 T6 
188                         end
                        MISSING_ELSE
189                     
190                         // If the SRAM is not empty, data from the input buffer must flow via the SRAM.
191        1/1              if (!sram_empty) begin
           Tests:       T1 T2 T3 
192                     
193                           // Prioritize refilling of the output buffer: if the output buffer is not being filled to the
194                           // last slot in the current cycle or it is being read in the current cycle, read from the SRAM
195                           // so the output buffer can be written in the next cycle.
196        1/1                if (!((oup_buf_almost_full && oup_buf_wvalid) || oup_buf_full)
           Tests:       T4 T5 T6 
197                               || (fifo_rvalid_o && fifo_rready_i)) begin
198        1/1                  sram_req_o = 1'b1;
           Tests:       T4 T5 T6 
199        1/1                  sram_write_o = 1'b0;
           Tests:       T4 T5 T6 
200        1/1                  sram_addr_o = sram_rd_addr;
           Tests:       T4 T5 T6 
201                     
202                           // If the output buffer is full (and not being read), drain the input buffer into the SRAM.
203                           end else begin
204        1/1                  sram_req_o = !sram_full && inp_buf_rvalid;
           Tests:       T4 T5 T6 
205        1/1                  sram_write_o = 1'b1;
           Tests:       T4 T5 T6 
206        1/1                  sram_addr_o = sram_wr_addr;
           Tests:       T4 T5 T6 
207        1/1                  inp_buf_rready = !sram_full && sram_gnt_i;
           Tests:       T4 T5 T6 
208                           end
209                     
210                         // If the SRAM is empty, data must flow from the input buffer to the output buffer if the output
211                         // buffer is ready and is not receiving data read from the SRAM in the previous cycle
212        1/1              end else if (oup_buf_wready && !sram_read_in_prev_cyc_q) begin
           Tests:       T1 T2 T3 
213        1/1                oup_buf_wvalid = inp_buf_rvalid;
           Tests:       T1 T2 T3 
214        1/1                oup_buf_wdata = inp_buf_rdata;
           Tests:       T1 T2 T3 
215        1/1                inp_buf_rready = oup_buf_wready;
           Tests:       T1 T2 T3 
216                     
217                         // Otherwise the SRAM is empty but the output buffer cannot take the data from the input buffer,
218                         // so drain the input buffer into the SRAM.
219                         end else begin
220        1/1                sram_req_o = !sram_full && inp_buf_rvalid;
           Tests:       T1 T2 T3 
221        1/1                sram_write_o = 1'b1;
           Tests:       T1 T2 T3 
222        1/1                sram_addr_o = sram_wr_addr;
           Tests:       T1 T2 T3 
223        1/1                inp_buf_rready = !sram_full && sram_gnt_i;
           Tests:       T1 T2 T3 
224                         end
225                       end
226                     
227                       // Error output is high if any of the internal errors is high
228        1/1            assign err_o = |{inp_buf_err, oup_buf_err, sram_ptrs_err, state_err};
           Tests:       T1 T2 T3 
229                     
230                       // The SRAM and the output buffer together form the entire architectural capacity of the FIFO.
231                       // Thus, when both are full, the FIFO is no longer ready to receive writes even though the input
232                       // buffer could store one additional entry.  This ensures that in the cycle after an entry has
233                       // been read from the full FIFO, the next entry can be written to the FIFO.
234                       // (It may be possible that all input buffer slots except one can be counted to the architectural
235                       // capacity of the FIFO, but this is a relatively small optimization left for future work.)
236        1/1            assign fifo_wready_o = inp_buf_wready && !(sram_full && oup_buf_full);
           Tests:       T1 T2 T3 
237                     
238                       // The current depth of the FIFO represented by this module is the depth of all buffers plus the
239                       // FIFO in the SRAM plus one if there's an entry in transition between SRAM and output buffer.
240        1/1            assign fifo_depth_o = DepthW'(inp_buf_depth) + DepthW'(sram_depth) + DepthW'(oup_buf_depth) +
           Tests:       T1 T2 T3 
241                                             DepthW'(sram_read_in_prev_cyc_q);
242                     
243                       // SRAM write data always comes from the input buffer.
244        1/1            assign sram_wdata_o = inp_buf_rdata;
           Tests:       T1 T2 T3 
245                       assign sram_wmask_o = '1;
246                     
247                       // `sram_rvalid_i` is only used for assertions.
248                       logic unused_sram_rvalid;
249        1/1            assign unused_sram_rvalid = sram_rvalid_i;
           Tests:       T1 T2 T3 

---

Cond Coverage for Instance : tb.dut.i2c_core.u_fifos.u_tx_fifo_sram_adapter

	Total	Covered	Percent
Conditions	51	38	74.51
Logical	51	38	74.51
Non-Logical	0	0
Event	0	0

 LINE       120
 EXPRESSION (fifo_wvalid_i && fifo_wready_o)
             ------1------    ------2------

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Not Covered
1	1	Covered	T4,T5,T6

 LINE       125
 EXPRESSION (sram_req_o && sram_gnt_i)
             -----1----    -----2----

-1-	-2-	Status	Tests
0	1	Not Covered
1	0	Not Covered
1	1	Covered	T4,T5,T6

 LINE       150
 EXPRESSION (sram_access && sram_write_o)
             -----1-----    ------2-----

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Covered	T4,T5,T6
1	1	Covered	T4,T5,T6

 LINE       151
 EXPRESSION (sram_access && ((!sram_write_o)))
             -----1-----    --------2--------

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Covered	T4,T5,T6
1	1	Covered	T4,T5,T6

 LINE       162
 EXPRESSION (clr_i ? 1'b0 : sram_incr_rd_ptr)
             --1--

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T1,T2,T3

 LINE       196
 EXPRESSION (( ! ((oup_buf_almost_full && oup_buf_wvalid) || oup_buf_full) ) || (fifo_rvalid_o && fifo_rready_i))
             -------------------------------1-------------------------------    ----------------2---------------

-1-	-2-	Status	Tests
0	0	Covered	T4,T5,T6
0	1	Covered	T4,T5,T6
1	0	Not Covered

 LINE       196
 SUB-EXPRESSION ( ! ((oup_buf_almost_full && oup_buf_wvalid) || oup_buf_full) )
                    ----------------------------1----------------------------

-1-	Status	Tests
0	Not Covered
1	Covered	T4,T5,T6

 LINE       196
 SUB-EXPRESSION ((oup_buf_almost_full && oup_buf_wvalid) || oup_buf_full)
                 -------------------1-------------------    ------2-----

-1-	-2-	Status	Tests
0	0	Not Covered
0	1	Covered	T4,T5,T6
1	0	Covered	T4,T5,T6

 LINE       196
 SUB-EXPRESSION (oup_buf_almost_full && oup_buf_wvalid)
                 ---------1---------    -------2------

-1-	-2-	Status	Tests
0	1	Not Covered
1	0	Covered	T4,T5,T6
1	1	Covered	T4,T5,T6

 LINE       196
 SUB-EXPRESSION (fifo_rvalid_o && fifo_rready_i)
                 ------1------    ------2------

-1-	-2-	Status	Tests
0	1	Not Covered
1	0	Covered	T4,T5,T6
1	1	Covered	T4,T5,T6

 LINE       204
 EXPRESSION (((!sram_full)) && inp_buf_rvalid)
             -------1------    -------2------

-1-	-2-	Status	Tests
0	1	Not Covered
1	0	Covered	T4,T5,T6
1	1	Covered	T4,T5,T6

 LINE       207
 EXPRESSION (((!sram_full)) && sram_gnt_i)
             -------1------    -----2----

-1-	-2-	Status	Tests
0	1	Not Covered
1	0	Covered	T4,T5,T6
1	1	Covered	T4,T5,T6

 LINE       212
 EXPRESSION (oup_buf_wready && ((!sram_read_in_prev_cyc_q)))
             -------1------    --------------2-------------

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Covered	T4,T5,T6
1	1	Covered	T1,T2,T3

 LINE       220
 EXPRESSION (((!sram_full)) && inp_buf_rvalid)
             -------1------    -------2------

-1-	-2-	Status	Tests
0	1	Not Covered
1	0	Covered	T1,T2,T3
1	1	Covered	T4,T5,T6

 LINE       223
 EXPRESSION (((!sram_full)) && sram_gnt_i)
             -------1------    -----2----

-1-	-2-	Status	Tests
0	1	Not Covered
1	0	Covered	T1,T2,T3
1	1	Covered	T4,T5,T6

 LINE       236
 EXPRESSION (inp_buf_wready && ( ! (sram_full && oup_buf_full) ))
             -------1------    ----------------2----------------

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Covered	T65,T66,T176
1	1	Covered	T1,T2,T3

 LINE       236
 SUB-EXPRESSION ( ! (sram_full && oup_buf_full) )
                    -------------1-------------

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T65,T66,T176

 LINE       236
 SUB-EXPRESSION (sram_full && oup_buf_full)
                 ----1----    ------2-----

-1-	-2-	Status	Tests
0	1	Covered	T4,T5,T6
1	0	Not Covered
1	1	Covered	T65,T66,T176

---

Branch Coverage for Instance : tb.dut.i2c_core.u_fifos.u_tx_fifo_sram_adapter

	Line No.	Total	Covered	Percent
Branches		10	10	100.00
TERNARY	162	2	2	100.00
IF	164	2	2	100.00
IF	183	2	2	100.00
IF	191	4	4	100.00

162          assign sram_read_in_prev_cyc_d = clr_i ? 1'b0 : sram_incr_rd_ptr;
                                                    -1-  
                                                    ==>  
                                                    ==>  

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T2,T3

164            if (!rst_ni) begin
               -1-  
165              sram_read_in_prev_cyc_q <= 1'b0;
                 ==>
166            end else begin
167              sram_read_in_prev_cyc_q <= sram_read_in_prev_cyc_d;
                 ==>

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T2,T3

183            if (sram_read_in_prev_cyc_q) begin
               -1-  
184              oup_buf_wvalid = 1'b1;
                 ==>
185              oup_buf_wdata = sram_rdata_i;
186              // The output buffer must be ready; otherwise we are in an erroneous state.
187              state_err = !oup_buf_wready;
188            end
               MISSING_ELSE
               ==>

Branches:

-1-	Status	Tests
1	Covered	T4,T5,T6
0	Covered	T1,T2,T3

191            if (!sram_empty) begin
               -1-  
192        
193              // Prioritize refilling of the output buffer: if the output buffer is not being filled to the
194              // last slot in the current cycle or it is being read in the current cycle, read from the SRAM
195              // so the output buffer can be written in the next cycle.
196              if (!((oup_buf_almost_full && oup_buf_wvalid) || oup_buf_full)
                 -2-  
197                  || (fifo_rvalid_o && fifo_rready_i)) begin
198                sram_req_o = 1'b1;
                   ==>
199                sram_write_o = 1'b0;
200                sram_addr_o = sram_rd_addr;
201        
202              // If the output buffer is full (and not being read), drain the input buffer into the SRAM.
203              end else begin
204                sram_req_o = !sram_full && inp_buf_rvalid;
                   ==>
205                sram_write_o = 1'b1;
206                sram_addr_o = sram_wr_addr;
207                inp_buf_rready = !sram_full && sram_gnt_i;
208              end
209        
210            // If the SRAM is empty, data must flow from the input buffer to the output buffer if the output
211            // buffer is ready and is not receiving data read from the SRAM in the previous cycle
212            end else if (oup_buf_wready && !sram_read_in_prev_cyc_q) begin
                        -3-  
213              oup_buf_wvalid = inp_buf_rvalid;
                 ==>
214              oup_buf_wdata = inp_buf_rdata;
215              inp_buf_rready = oup_buf_wready;
216        
217            // Otherwise the SRAM is empty but the output buffer cannot take the data from the input buffer,
218            // so drain the input buffer into the SRAM.
219            end else begin
220              sram_req_o = !sram_full && inp_buf_rvalid;
                 ==>

Branches:

-1-	-2-	-3-	Status	Tests
1	1	-	Covered	T4,T5,T6
1	0	-	Covered	T4,T5,T6
0	-	1	Covered	T1,T2,T3
0	-	0	Covered	T1,T2,T3

---

Assert Coverage for Instance : tb.dut.i2c_core.u_fifos.u_tx_fifo_sram_adapter

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	7	7	100.00	7	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	7	7	100.00	7	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
MinimalSramAw_A	1675	1675	0	0
MinimalSramFifoDepth_A	1675	1675	0	0
NoErr_A	408961761	408787796	0	0
NoSramReadWhenEmpty_A	408961761	387783051	0	0
NoSramWriteWhenFull_A	408961761	282391	0	0
OupBufWreadyAfterSramRead_A	408961761	114646	0	0
SramRvalidAfterRead_A	408961761	114646	0	0

MinimalSramAw_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	1675	1675	0	0
T1	1	1	0	0
T2	1	1	0	0
T3	1	1	0	0
T4	1	1	0	0
T5	1	1	0	0
T6	1	1	0	0
T7	1	1	0	0
T8	1	1	0	0
T9	1	1	0	0
T10	1	1	0	0

MinimalSramFifoDepth_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	1675	1675	0	0
T1	1	1	0	0
T2	1	1	0	0
T3	1	1	0	0
T4	1	1	0	0
T5	1	1	0	0
T6	1	1	0	0
T7	1	1	0	0
T8	1	1	0	0
T9	1	1	0	0
T10	1	1	0	0

NoErr_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	408961761	408787796	0	0
T1	1923	1863	0	0
T2	10306	10241	0	0
T3	13901	13178	0	0
T4	496654	496566	0	0
T5	21213	21144	0	0
T6	9621	9554	0	0
T7	12572	12494	0	0
T8	7344	7249	0	0
T9	9692	9639	0	0
T10	14705	14619	0	0

NoSramReadWhenEmpty_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	408961761	387783051	0	0
T1	1923	1863	0	0
T2	10306	10241	0	0
T3	13901	13178	0	0
T4	496654	353799	0	0
T5	21213	13194	0	0
T6	9621	6930	0	0
T7	12572	12494	0	0
T8	7344	1326	0	0
T9	9692	9639	0	0
T10	14705	14619	0	0

NoSramWriteWhenFull_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	408961761	282391	0	0
T13	41344	0	0	0
T22	4156	0	0	0
T61	674056	0	0	0
T62	420539	0	0	0
T65	14158	7659	0	0
T66	0	12784	0	0
T67	0	8799	0	0
T163	46316	0	0	0
T164	51677	0	0	0
T176	0	41	0	0
T177	0	2175	0	0
T178	0	8	0	0
T179	0	6147	0	0
T180	0	1398	0	0
T181	0	9398	0	0
T182	0	10753	0	0
T183	123548	0	0	0
T184	12229	0	0	0
T185	89372	0	0	0

OupBufWreadyAfterSramRead_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	408961761	114646	0	0
T4	496654	814	0	0
T5	21213	48	0	0
T6	9621	14	0	0
T7	12572	0	0	0
T8	7344	42	0	0
T9	9692	0	0	0
T10	14705	0	0	0
T49	57668	89	0	0
T50	20238	23	0	0
T51	0	145	0	0
T78	23009	63	0	0
T79	0	282	0	0
T80	0	2	0	0

SramRvalidAfterRead_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	408961761	114646	0	0
T4	496654	814	0	0
T5	21213	48	0	0
T6	9621	14	0	0
T7	12572	0	0	0
T8	7344	42	0	0
T9	9692	0	0	0
T10	14705	0	0	0
T49	57668	89	0	0
T50	20238	23	0	0
T51	0	145	0	0
T78	23009	63	0	0
T79	0	282	0	0
T80	0	2	0	0

Line Coverage for Instance : tb.dut.i2c_core.u_fifos.u_rx_fifo_sram_adapter

	Line No.	Total	Covered	Percent
TOTAL		44	44	100.00
CONT_ASSIGN	120	1	1	100.00
CONT_ASSIGN	121	1	1	100.00
CONT_ASSIGN	125	1	1	100.00
CONT_ASSIGN	150	1	1	100.00
CONT_ASSIGN	151	1	1	100.00
CONT_ASSIGN	153	1	1	100.00
CONT_ASSIGN	154	1	1	100.00
CONT_ASSIGN	162	1	1	100.00
ALWAYS	164	3	3	100.00
ALWAYS	174	28	28	100.00
CONT_ASSIGN	228	1	1	100.00
CONT_ASSIGN	236	1	1	100.00
CONT_ASSIGN	240	1	1	100.00
CONT_ASSIGN	244	1	1	100.00
CONT_ASSIGN	249	1	1	100.00

119                       );
120        1/1            assign inp_buf_wvalid = fifo_wvalid_i && fifo_wready_o;
           Tests:       T1 T2 T3 
121        1/1            assign oup_buf_almost_full = oup_buf_depth >= OupBufDepthW'(OupBufDepth - 1);
           Tests:       T1 T2 T3 
122                     
123                       // Signal whether we access the SRAM in this cycle
124                       logic sram_access;
125        1/1            assign sram_access = sram_req_o && sram_gnt_i;
           Tests:       T1 T2 T3 
126                     
127                       // SRAM read and write addresses
128                       logic [SramAw-1:0]     sram_wr_addr, sram_rd_addr;
129                       logic [SramPtrW-1:0]   sram_wr_ptr, sram_rd_ptr;
130                       logic [SramDepthW-1:0] sram_depth;
131                       logic                  sram_incr_wr_ptr, sram_incr_rd_ptr;
132                       logic                  sram_full, sram_empty;
133                       logic                  sram_ptrs_err;
134                       prim_fifo_sync_cnt #(
135                         .Depth (SramFifoDepth),
136                         .Secure(1'b0)
137                       ) u_sram_ptrs (
138                         .clk_i,
139                         .rst_ni,
140                         .clr_i,
141                         .incr_wptr_i(sram_incr_wr_ptr),
142                         .incr_rptr_i(sram_incr_rd_ptr),
143                         .wptr_o     (sram_wr_ptr),
144                         .rptr_o     (sram_rd_ptr),
145                         .full_o     (sram_full),
146                         .empty_o    (sram_empty),
147                         .depth_o    (sram_depth),
148                         .err_o      (sram_ptrs_err)
149                       );
150        1/1            assign sram_incr_wr_ptr = sram_access && sram_write_o;
           Tests:       T1 T2 T3 
151        1/1            assign sram_incr_rd_ptr = sram_access && !sram_write_o;
           Tests:       T1 T2 T3 
152                       if (SramAddrLeadingZeros > 0) begin : gen_zero_extend_sram_addrs
153        1/1              assign sram_wr_addr = {{SramAddrLeadingZeros{1'b0}}, sram_wr_ptr} + SramBaseAddr;
           Tests:       T1 T2 T3 
154        1/1              assign sram_rd_addr = {{SramAddrLeadingZeros{1'b0}}, sram_rd_ptr} + SramBaseAddr;
           Tests:       T1 T2 T3 
155                       end else begin : gen_no_zero_extend_sram_addrs
156                         assign sram_wr_addr = sram_wr_ptr + SramBaseAddr;
157                         assign sram_rd_addr = sram_rd_ptr + SramBaseAddr;
158                       end
159                     
160                       // FF to remember whether we read from the SRAM in the previous clock cycle.
161                       logic sram_read_in_prev_cyc_d, sram_read_in_prev_cyc_q;
162        1/1            assign sram_read_in_prev_cyc_d = clr_i ? 1'b0 : sram_incr_rd_ptr;
           Tests:       T1 T2 T3 
163                       always_ff @(posedge clk_i or negedge rst_ni) begin
164        1/1              if (!rst_ni) begin
           Tests:       T1 T2 T3 
165        1/1                sram_read_in_prev_cyc_q <= 1'b0;
           Tests:       T1 T2 T3 
166                         end else begin
167        1/1                sram_read_in_prev_cyc_q <= sram_read_in_prev_cyc_d;
           Tests:       T1 T2 T3 
168                         end
169                       end
170                     
171                       // Control logic for FIFO interface wready, output buffer writes, and SRAM requests
172                       logic state_err;
173                       always_comb begin
174        1/1              inp_buf_rready = 1'b0;
           Tests:       T1 T2 T3 
175        1/1              oup_buf_wvalid = 1'b0;
           Tests:       T1 T2 T3 
176        1/1              oup_buf_wdata = inp_buf_rdata;
           Tests:       T1 T2 T3 
177        1/1              sram_req_o = 1'b0;
           Tests:       T1 T2 T3 
178        1/1              sram_write_o = 1'b0;
           Tests:       T1 T2 T3 
179        1/1              sram_addr_o = sram_wr_addr;
           Tests:       T1 T2 T3 
180        1/1              state_err = 1'b0;
           Tests:       T1 T2 T3 
181                     
182                         // If the SRAM was read in the previous cycle, write the read data to the output buffer.
183        1/1              if (sram_read_in_prev_cyc_q) begin
           Tests:       T1 T2 T3 
184        1/1                oup_buf_wvalid = 1'b1;
           Tests:       T86 T42 T87 
185        1/1                oup_buf_wdata = sram_rdata_i;
           Tests:       T86 T42 T87 
186                           // The output buffer must be ready; otherwise we are in an erroneous state.
187        1/1                state_err = !oup_buf_wready;
           Tests:       T86 T42 T87 
188                         end
                        MISSING_ELSE
189                     
190                         // If the SRAM is not empty, data from the input buffer must flow via the SRAM.
191        1/1              if (!sram_empty) begin
           Tests:       T1 T2 T3 
192                     
193                           // Prioritize refilling of the output buffer: if the output buffer is not being filled to the
194                           // last slot in the current cycle or it is being read in the current cycle, read from the SRAM
195                           // so the output buffer can be written in the next cycle.
196        1/1                if (!((oup_buf_almost_full && oup_buf_wvalid) || oup_buf_full)
           Tests:       T10 T40 T86 
197                               || (fifo_rvalid_o && fifo_rready_i)) begin
198        1/1                  sram_req_o = 1'b1;
           Tests:       T86 T42 T87 
199        1/1                  sram_write_o = 1'b0;
           Tests:       T86 T42 T87 
200        1/1                  sram_addr_o = sram_rd_addr;
           Tests:       T86 T42 T87 
201                     
202                           // If the output buffer is full (and not being read), drain the input buffer into the SRAM.
203                           end else begin
204        1/1                  sram_req_o = !sram_full && inp_buf_rvalid;
           Tests:       T10 T40 T86 
205        1/1                  sram_write_o = 1'b1;
           Tests:       T10 T40 T86 
206        1/1                  sram_addr_o = sram_wr_addr;
           Tests:       T10 T40 T86 
207        1/1                  inp_buf_rready = !sram_full && sram_gnt_i;
           Tests:       T10 T40 T86 
208                           end
209                     
210                         // If the SRAM is empty, data must flow from the input buffer to the output buffer if the output
211                         // buffer is ready and is not receiving data read from the SRAM in the previous cycle
212        1/1              end else if (oup_buf_wready && !sram_read_in_prev_cyc_q) begin
           Tests:       T1 T2 T3 
213        1/1                oup_buf_wvalid = inp_buf_rvalid;
           Tests:       T1 T2 T3 
214        1/1                oup_buf_wdata = inp_buf_rdata;
           Tests:       T1 T2 T3 
215        1/1                inp_buf_rready = oup_buf_wready;
           Tests:       T1 T2 T3 
216                     
217                         // Otherwise the SRAM is empty but the output buffer cannot take the data from the input buffer,
218                         // so drain the input buffer into the SRAM.
219                         end else begin
220        1/1                sram_req_o = !sram_full && inp_buf_rvalid;
           Tests:       T1 T2 T3 
221        1/1                sram_write_o = 1'b1;
           Tests:       T1 T2 T3 
222        1/1                sram_addr_o = sram_wr_addr;
           Tests:       T1 T2 T3 
223        1/1                inp_buf_rready = !sram_full && sram_gnt_i;
           Tests:       T1 T2 T3 
224                         end
225                       end
226                     
227                       // Error output is high if any of the internal errors is high
228        1/1            assign err_o = |{inp_buf_err, oup_buf_err, sram_ptrs_err, state_err};
           Tests:       T1 T2 T3 
229                     
230                       // The SRAM and the output buffer together form the entire architectural capacity of the FIFO.
231                       // Thus, when both are full, the FIFO is no longer ready to receive writes even though the input
232                       // buffer could store one additional entry.  This ensures that in the cycle after an entry has
233                       // been read from the full FIFO, the next entry can be written to the FIFO.
234                       // (It may be possible that all input buffer slots except one can be counted to the architectural
235                       // capacity of the FIFO, but this is a relatively small optimization left for future work.)
236        1/1            assign fifo_wready_o = inp_buf_wready && !(sram_full && oup_buf_full);
           Tests:       T1 T2 T3 
237                     
238                       // The current depth of the FIFO represented by this module is the depth of all buffers plus the
239                       // FIFO in the SRAM plus one if there's an entry in transition between SRAM and output buffer.
240        1/1            assign fifo_depth_o = DepthW'(inp_buf_depth) + DepthW'(sram_depth) + DepthW'(oup_buf_depth) +
           Tests:       T1 T2 T3 
241                                             DepthW'(sram_read_in_prev_cyc_q);
242                     
243                       // SRAM write data always comes from the input buffer.
244        1/1            assign sram_wdata_o = inp_buf_rdata;
           Tests:       T1 T2 T3 
245                       assign sram_wmask_o = '1;
246                     
247                       // `sram_rvalid_i` is only used for assertions.
248                       logic unused_sram_rvalid;
249        1/1            assign unused_sram_rvalid = sram_rvalid_i;
           Tests:       T1 T2 T3 

---

Cond Coverage for Instance : tb.dut.i2c_core.u_fifos.u_rx_fifo_sram_adapter

	Total	Covered	Percent
Conditions	51	39	76.47
Logical	51	39	76.47
Non-Logical	0	0
Event	0	0

 LINE       120
 EXPRESSION (fifo_wvalid_i && fifo_wready_o)
             ------1------    ------2------

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Covered	T86,T106,T107
1	1	Covered	T3,T7,T10

 LINE       125
 EXPRESSION (sram_req_o && sram_gnt_i)
             -----1----    -----2----

-1-	-2-	Status	Tests
0	1	Not Covered
1	0	Not Covered
1	1	Covered	T10,T40,T86

 LINE       150
 EXPRESSION (sram_access && sram_write_o)
             -----1-----    ------2-----

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Covered	T86,T42,T87
1	1	Covered	T10,T40,T86

 LINE       151
 EXPRESSION (sram_access && ((!sram_write_o)))
             -----1-----    --------2--------

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Covered	T10,T40,T86
1	1	Covered	T86,T42,T87

 LINE       162
 EXPRESSION (clr_i ? 1'b0 : sram_incr_rd_ptr)
             --1--

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T1,T2,T3

 LINE       196
 EXPRESSION (( ! ((oup_buf_almost_full && oup_buf_wvalid) || oup_buf_full) ) || (fifo_rvalid_o && fifo_rready_i))
             -------------------------------1-------------------------------    ----------------2---------------

-1-	-2-	Status	Tests
0	0	Covered	T10,T40,T86
0	1	Covered	T86,T42,T87
1	0	Not Covered

 LINE       196
 SUB-EXPRESSION ( ! ((oup_buf_almost_full && oup_buf_wvalid) || oup_buf_full) )
                    ----------------------------1----------------------------

-1-	Status	Tests
0	Not Covered
1	Covered	T10,T40,T86

 LINE       196
 SUB-EXPRESSION ((oup_buf_almost_full && oup_buf_wvalid) || oup_buf_full)
                 -------------------1-------------------    ------2-----

-1-	-2-	Status	Tests
0	0	Not Covered
0	1	Covered	T10,T40,T86
1	0	Covered	T86,T42,T87

 LINE       196
 SUB-EXPRESSION (oup_buf_almost_full && oup_buf_wvalid)
                 ---------1---------    -------2------

-1-	-2-	Status	Tests
0	1	Not Covered
1	0	Covered	T10,T40,T86
1	1	Covered	T86,T42,T87

 LINE       196
 SUB-EXPRESSION (fifo_rvalid_o && fifo_rready_i)
                 ------1------    ------2------

-1-	-2-	Status	Tests
0	1	Not Covered
1	0	Covered	T10,T40,T86
1	1	Covered	T86,T42,T87

 LINE       204
 EXPRESSION (((!sram_full)) && inp_buf_rvalid)
             -------1------    -------2------

-1-	-2-	Status	Tests
0	1	Not Covered
1	0	Covered	T10,T40,T86
1	1	Covered	T10,T40,T86

 LINE       207
 EXPRESSION (((!sram_full)) && sram_gnt_i)
             -------1------    -----2----

-1-	-2-	Status	Tests
0	1	Not Covered
1	0	Covered	T10,T40,T86
1	1	Covered	T10,T40,T86

 LINE       212
 EXPRESSION (oup_buf_wready && ((!sram_read_in_prev_cyc_q)))
             -------1------    --------------2-------------

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Covered	T86,T42,T87
1	1	Covered	T1,T2,T3

 LINE       220
 EXPRESSION (((!sram_full)) && inp_buf_rvalid)
             -------1------    -------2------

-1-	-2-	Status	Tests
0	1	Not Covered
1	0	Covered	T1,T2,T3
1	1	Covered	T10,T40,T86

 LINE       223
 EXPRESSION (((!sram_full)) && sram_gnt_i)
             -------1------    -----2----

-1-	-2-	Status	Tests
0	1	Not Covered
1	0	Covered	T1,T2,T3
1	1	Covered	T10,T40,T86

 LINE       236
 EXPRESSION (inp_buf_wready && ( ! (sram_full && oup_buf_full) ))
             -------1------    ----------------2----------------

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Covered	T10,T40,T86
1	1	Covered	T1,T2,T3

 LINE       236
 SUB-EXPRESSION ( ! (sram_full && oup_buf_full) )
                    -------------1-------------

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T10,T40,T86

 LINE       236
 SUB-EXPRESSION (sram_full && oup_buf_full)
                 ----1----    ------2-----

-1-	-2-	Status	Tests
0	1	Covered	T10,T40,T86
1	0	Not Covered
1	1	Covered	T10,T40,T86

---

Branch Coverage for Instance : tb.dut.i2c_core.u_fifos.u_rx_fifo_sram_adapter

	Line No.	Total	Covered	Percent
Branches		10	10	100.00
TERNARY	162	2	2	100.00
IF	164	2	2	100.00
IF	183	2	2	100.00
IF	191	4	4	100.00

162          assign sram_read_in_prev_cyc_d = clr_i ? 1'b0 : sram_incr_rd_ptr;
                                                    -1-  
                                                    ==>  
                                                    ==>  

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T2,T3

164            if (!rst_ni) begin
               -1-  
165              sram_read_in_prev_cyc_q <= 1'b0;
                 ==>
166            end else begin
167              sram_read_in_prev_cyc_q <= sram_read_in_prev_cyc_d;
                 ==>

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T2,T3

183            if (sram_read_in_prev_cyc_q) begin
               -1-  
184              oup_buf_wvalid = 1'b1;
                 ==>
185              oup_buf_wdata = sram_rdata_i;
186              // The output buffer must be ready; otherwise we are in an erroneous state.
187              state_err = !oup_buf_wready;
188            end
               MISSING_ELSE
               ==>

Branches:

-1-	Status	Tests
1	Covered	T86,T42,T87
0	Covered	T1,T2,T3

191            if (!sram_empty) begin
               -1-  
192        
193              // Prioritize refilling of the output buffer: if the output buffer is not being filled to the
194              // last slot in the current cycle or it is being read in the current cycle, read from the SRAM
195              // so the output buffer can be written in the next cycle.
196              if (!((oup_buf_almost_full && oup_buf_wvalid) || oup_buf_full)
                 -2-  
197                  || (fifo_rvalid_o && fifo_rready_i)) begin
198                sram_req_o = 1'b1;
                   ==>
199                sram_write_o = 1'b0;
200                sram_addr_o = sram_rd_addr;
201        
202              // If the output buffer is full (and not being read), drain the input buffer into the SRAM.
203              end else begin
204                sram_req_o = !sram_full && inp_buf_rvalid;
                   ==>
205                sram_write_o = 1'b1;
206                sram_addr_o = sram_wr_addr;
207                inp_buf_rready = !sram_full && sram_gnt_i;
208              end
209        
210            // If the SRAM is empty, data must flow from the input buffer to the output buffer if the output
211            // buffer is ready and is not receiving data read from the SRAM in the previous cycle
212            end else if (oup_buf_wready && !sram_read_in_prev_cyc_q) begin
                        -3-  
213              oup_buf_wvalid = inp_buf_rvalid;
                 ==>
214              oup_buf_wdata = inp_buf_rdata;
215              inp_buf_rready = oup_buf_wready;
216        
217            // Otherwise the SRAM is empty but the output buffer cannot take the data from the input buffer,
218            // so drain the input buffer into the SRAM.
219            end else begin
220              sram_req_o = !sram_full && inp_buf_rvalid;
                 ==>

Branches:

-1-	-2-	-3-	Status	Tests
1	1	-	Covered	T86,T42,T87
1	0	-	Covered	T10,T40,T86
0	-	1	Covered	T1,T2,T3
0	-	0	Covered	T1,T2,T3

---

Assert Coverage for Instance : tb.dut.i2c_core.u_fifos.u_rx_fifo_sram_adapter

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	7	7	100.00	7	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	7	7	100.00	7	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
MinimalSramAw_A	1675	1675	0	0
MinimalSramFifoDepth_A	1675	1675	0	0
NoErr_A	408961761	408787796	0	0
NoSramReadWhenEmpty_A	408961761	384676985	0	0
NoSramWriteWhenFull_A	408961761	228169	0	0
OupBufWreadyAfterSramRead_A	408961761	120156	0	0
SramRvalidAfterRead_A	408961761	120156	0	0

MinimalSramAw_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	1675	1675	0	0
T1	1	1	0	0
T2	1	1	0	0
T3	1	1	0	0
T4	1	1	0	0
T5	1	1	0	0
T6	1	1	0	0
T7	1	1	0	0
T8	1	1	0	0
T9	1	1	0	0
T10	1	1	0	0

MinimalSramFifoDepth_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	1675	1675	0	0
T1	1	1	0	0
T2	1	1	0	0
T3	1	1	0	0
T4	1	1	0	0
T5	1	1	0	0
T6	1	1	0	0
T7	1	1	0	0
T8	1	1	0	0
T9	1	1	0	0
T10	1	1	0	0

NoErr_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	408961761	408787796	0	0
T1	1923	1863	0	0
T2	10306	10241	0	0
T3	13901	13178	0	0
T4	496654	496566	0	0
T5	21213	21144	0	0
T6	9621	9554	0	0
T7	12572	12494	0	0
T8	7344	7249	0	0
T9	9692	9639	0	0
T10	14705	14619	0	0

NoSramReadWhenEmpty_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	408961761	384676985	0	0
T1	1923	1863	0	0
T2	10306	10241	0	0
T3	13901	13178	0	0
T4	496654	496566	0	0
T5	21213	21144	0	0
T6	9621	9554	0	0
T7	12572	12494	0	0
T8	7344	7249	0	0
T9	9692	9639	0	0
T10	14705	2537	0	0

NoSramWriteWhenFull_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	408961761	228169	0	0
T10	14705	4	0	0
T40	0	3	0	0
T42	0	493	0	0
T49	57668	0	0	0
T50	20238	0	0	0
T51	98672	0	0	0
T71	62350	0	0	0
T78	23009	0	0	0
T79	134343	0	0	0
T80	245643	0	0	0
T86	0	2738	0	0
T87	0	626	0	0
T102	1634	0	0	0
T105	2464	0	0	0
T106	0	3519	0	0
T107	0	2128	0	0
T186	0	12	0	0
T187	0	3	0	0
T188	0	4044	0	0

OupBufWreadyAfterSramRead_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	408961761	120156	0	0
T42	0	620	0	0
T74	55698	0	0	0
T77	7746	0	0	0
T86	170699	744	0	0
T87	0	806	0	0
T88	0	620	0	0
T106	0	1054	0	0
T107	0	682	0	0
T169	3970	0	0	0
T170	2357	0	0	0
T171	55351	0	0	0
T172	7750	0	0	0
T173	39984	0	0	0
T174	72922	0	0	0
T175	29871	0	0	0
T188	0	1178	0	0
T189	0	992	0	0
T190	0	620	0	0
T191	0	1116	0	0

SramRvalidAfterRead_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	408961761	120156	0	0
T42	0	620	0	0
T74	55698	0	0	0
T77	7746	0	0	0
T86	170699	744	0	0
T87	0	806	0	0
T88	0	620	0	0
T106	0	1054	0	0
T107	0	682	0	0
T169	3970	0	0	0
T170	2357	0	0	0
T171	55351	0	0	0
T172	7750	0	0	0
T173	39984	0	0	0
T174	72922	0	0	0
T175	29871	0	0	0
T188	0	1178	0	0
T189	0	992	0	0
T190	0	620	0	0
T191	0	1116	0	0

Line Coverage for Instance : tb.dut.i2c_core.u_fifos.u_acq_fifo_sram_adapter

	Line No.	Total	Covered	Percent
TOTAL		44	44	100.00
CONT_ASSIGN	120	1	1	100.00
CONT_ASSIGN	121	1	1	100.00
CONT_ASSIGN	125	1	1	100.00
CONT_ASSIGN	150	1	1	100.00
CONT_ASSIGN	151	1	1	100.00
CONT_ASSIGN	156	1	1	100.00
CONT_ASSIGN	157	1	1	100.00
CONT_ASSIGN	162	1	1	100.00
ALWAYS	164	3	3	100.00
ALWAYS	174	28	28	100.00
CONT_ASSIGN	228	1	1	100.00
CONT_ASSIGN	236	1	1	100.00
CONT_ASSIGN	240	1	1	100.00
CONT_ASSIGN	244	1	1	100.00
CONT_ASSIGN	249	1	1	100.00

119                       );
120        1/1            assign inp_buf_wvalid = fifo_wvalid_i && fifo_wready_o;
           Tests:       T1 T2 T3 
121        1/1            assign oup_buf_almost_full = oup_buf_depth >= OupBufDepthW'(OupBufDepth - 1);
           Tests:       T1 T2 T3 
122                     
123                       // Signal whether we access the SRAM in this cycle
124                       logic sram_access;
125        1/1            assign sram_access = sram_req_o && sram_gnt_i;
           Tests:       T1 T2 T3 
126                     
127                       // SRAM read and write addresses
128                       logic [SramAw-1:0]     sram_wr_addr, sram_rd_addr;
129                       logic [SramPtrW-1:0]   sram_wr_ptr, sram_rd_ptr;
130                       logic [SramDepthW-1:0] sram_depth;
131                       logic                  sram_incr_wr_ptr, sram_incr_rd_ptr;
132                       logic                  sram_full, sram_empty;
133                       logic                  sram_ptrs_err;
134                       prim_fifo_sync_cnt #(
135                         .Depth (SramFifoDepth),
136                         .Secure(1'b0)
137                       ) u_sram_ptrs (
138                         .clk_i,
139                         .rst_ni,
140                         .clr_i,
141                         .incr_wptr_i(sram_incr_wr_ptr),
142                         .incr_rptr_i(sram_incr_rd_ptr),
143                         .wptr_o     (sram_wr_ptr),
144                         .rptr_o     (sram_rd_ptr),
145                         .full_o     (sram_full),
146                         .empty_o    (sram_empty),
147                         .depth_o    (sram_depth),
148                         .err_o      (sram_ptrs_err)
149                       );
150        1/1            assign sram_incr_wr_ptr = sram_access && sram_write_o;
           Tests:       T1 T2 T3 
151        1/1            assign sram_incr_rd_ptr = sram_access && !sram_write_o;
           Tests:       T1 T2 T3 
152                       if (SramAddrLeadingZeros > 0) begin : gen_zero_extend_sram_addrs
153                         assign sram_wr_addr = {{SramAddrLeadingZeros{1'b0}}, sram_wr_ptr} + SramBaseAddr;
154                         assign sram_rd_addr = {{SramAddrLeadingZeros{1'b0}}, sram_rd_ptr} + SramBaseAddr;
155                       end else begin : gen_no_zero_extend_sram_addrs
156        1/1              assign sram_wr_addr = sram_wr_ptr + SramBaseAddr;
           Tests:       T1 T2 T3 
157        1/1              assign sram_rd_addr = sram_rd_ptr + SramBaseAddr;
           Tests:       T1 T2 T3 
158                       end
159                     
160                       // FF to remember whether we read from the SRAM in the previous clock cycle.
161                       logic sram_read_in_prev_cyc_d, sram_read_in_prev_cyc_q;
162        1/1            assign sram_read_in_prev_cyc_d = clr_i ? 1'b0 : sram_incr_rd_ptr;
           Tests:       T1 T2 T3 
163                       always_ff @(posedge clk_i or negedge rst_ni) begin
164        1/1              if (!rst_ni) begin
           Tests:       T1 T2 T3 
165        1/1                sram_read_in_prev_cyc_q <= 1'b0;
           Tests:       T1 T2 T3 
166                         end else begin
167        1/1                sram_read_in_prev_cyc_q <= sram_read_in_prev_cyc_d;
           Tests:       T1 T2 T3 
168                         end
169                       end
170                     
171                       // Control logic for FIFO interface wready, output buffer writes, and SRAM requests
172                       logic state_err;
173                       always_comb begin
174        1/1              inp_buf_rready = 1'b0;
           Tests:       T1 T2 T3 
175        1/1              oup_buf_wvalid = 1'b0;
           Tests:       T1 T2 T3 
176        1/1              oup_buf_wdata = inp_buf_rdata;
           Tests:       T1 T2 T3 
177        1/1              sram_req_o = 1'b0;
           Tests:       T1 T2 T3 
178        1/1              sram_write_o = 1'b0;
           Tests:       T1 T2 T3 
179        1/1              sram_addr_o = sram_wr_addr;
           Tests:       T1 T2 T3 
180        1/1              state_err = 1'b0;
           Tests:       T1 T2 T3 
181                     
182                         // If the SRAM was read in the previous cycle, write the read data to the output buffer.
183        1/1              if (sram_read_in_prev_cyc_q) begin
           Tests:       T1 T2 T3 
184        1/1                oup_buf_wvalid = 1'b1;
           Tests:       T4 T5 T9 
185        1/1                oup_buf_wdata = sram_rdata_i;
           Tests:       T4 T5 T9 
186                           // The output buffer must be ready; otherwise we are in an erroneous state.
187        1/1                state_err = !oup_buf_wready;
           Tests:       T4 T5 T9 
188                         end
                        MISSING_ELSE
189                     
190                         // If the SRAM is not empty, data from the input buffer must flow via the SRAM.
191        1/1              if (!sram_empty) begin
           Tests:       T1 T2 T3 
192                     
193                           // Prioritize refilling of the output buffer: if the output buffer is not being filled to the
194                           // last slot in the current cycle or it is being read in the current cycle, read from the SRAM
195                           // so the output buffer can be written in the next cycle.
196        1/1                if (!((oup_buf_almost_full && oup_buf_wvalid) || oup_buf_full)
           Tests:       T4 T5 T9 
197                               || (fifo_rvalid_o && fifo_rready_i)) begin
198        1/1                  sram_req_o = 1'b1;
           Tests:       T4 T5 T9 
199        1/1                  sram_write_o = 1'b0;
           Tests:       T4 T5 T9 
200        1/1                  sram_addr_o = sram_rd_addr;
           Tests:       T4 T5 T9 
201                     
202                           // If the output buffer is full (and not being read), drain the input buffer into the SRAM.
203                           end else begin
204        1/1                  sram_req_o = !sram_full && inp_buf_rvalid;
           Tests:       T4 T5 T9 
205        1/1                  sram_write_o = 1'b1;
           Tests:       T4 T5 T9 
206        1/1                  sram_addr_o = sram_wr_addr;
           Tests:       T4 T5 T9 
207        1/1                  inp_buf_rready = !sram_full && sram_gnt_i;
           Tests:       T4 T5 T9 
208                           end
209                     
210                         // If the SRAM is empty, data must flow from the input buffer to the output buffer if the output
211                         // buffer is ready and is not receiving data read from the SRAM in the previous cycle
212        1/1              end else if (oup_buf_wready && !sram_read_in_prev_cyc_q) begin
           Tests:       T1 T2 T3 
213        1/1                oup_buf_wvalid = inp_buf_rvalid;
           Tests:       T1 T2 T3 
214        1/1                oup_buf_wdata = inp_buf_rdata;
           Tests:       T1 T2 T3 
215        1/1                inp_buf_rready = oup_buf_wready;
           Tests:       T1 T2 T3 
216                     
217                         // Otherwise the SRAM is empty but the output buffer cannot take the data from the input buffer,
218                         // so drain the input buffer into the SRAM.
219                         end else begin
220        1/1                sram_req_o = !sram_full && inp_buf_rvalid;
           Tests:       T1 T2 T3 
221        1/1                sram_write_o = 1'b1;
           Tests:       T1 T2 T3 
222        1/1                sram_addr_o = sram_wr_addr;
           Tests:       T1 T2 T3 
223        1/1                inp_buf_rready = !sram_full && sram_gnt_i;
           Tests:       T1 T2 T3 
224                         end
225                       end
226                     
227                       // Error output is high if any of the internal errors is high
228        1/1            assign err_o = |{inp_buf_err, oup_buf_err, sram_ptrs_err, state_err};
           Tests:       T1 T2 T3 
229                     
230                       // The SRAM and the output buffer together form the entire architectural capacity of the FIFO.
231                       // Thus, when both are full, the FIFO is no longer ready to receive writes even though the input
232                       // buffer could store one additional entry.  This ensures that in the cycle after an entry has
233                       // been read from the full FIFO, the next entry can be written to the FIFO.
234                       // (It may be possible that all input buffer slots except one can be counted to the architectural
235                       // capacity of the FIFO, but this is a relatively small optimization left for future work.)
236        1/1            assign fifo_wready_o = inp_buf_wready && !(sram_full && oup_buf_full);
           Tests:       T1 T2 T3 
237                     
238                       // The current depth of the FIFO represented by this module is the depth of all buffers plus the
239                       // FIFO in the SRAM plus one if there's an entry in transition between SRAM and output buffer.
240        1/1            assign fifo_depth_o = DepthW'(inp_buf_depth) + DepthW'(sram_depth) + DepthW'(oup_buf_depth) +
           Tests:       T1 T2 T3 
241                                             DepthW'(sram_read_in_prev_cyc_q);
242                     
243                       // SRAM write data always comes from the input buffer.
244        1/1            assign sram_wdata_o = inp_buf_rdata;
           Tests:       T1 T2 T3 
245                       assign sram_wmask_o = '1;
246                     
247                       // `sram_rvalid_i` is only used for assertions.
248                       logic unused_sram_rvalid;
249        1/1            assign unused_sram_rvalid = sram_rvalid_i;
           Tests:       T1 T2 T3 

---

Cond Coverage for Instance : tb.dut.i2c_core.u_fifos.u_acq_fifo_sram_adapter

	Total	Covered	Percent
Conditions	51	42	82.35
Logical	51	42	82.35
Non-Logical	0	0
Event	0	0

 LINE       120
 EXPRESSION (fifo_wvalid_i && fifo_wready_o)
             ------1------    ------2------

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Covered	T55,T57
1	1	Covered	T4,T5,T6

 LINE       125
 EXPRESSION (sram_req_o && sram_gnt_i)
             -----1----    -----2----

-1-	-2-	Status	Tests
0	1	Not Covered
1	0	Not Covered
1	1	Covered	T4,T5,T9

 LINE       150
 EXPRESSION (sram_access && sram_write_o)
             -----1-----    ------2-----

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Covered	T4,T5,T9
1	1	Covered	T4,T5,T9

 LINE       151
 EXPRESSION (sram_access && ((!sram_write_o)))
             -----1-----    --------2--------

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Covered	T4,T5,T9
1	1	Covered	T4,T5,T9

 LINE       162
 EXPRESSION (clr_i ? 1'b0 : sram_incr_rd_ptr)
             --1--

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T1,T2,T3

 LINE       196
 EXPRESSION (( ! ((oup_buf_almost_full && oup_buf_wvalid) || oup_buf_full) ) || (fifo_rvalid_o && fifo_rready_i))
             -------------------------------1-------------------------------    ----------------2---------------

-1-	-2-	Status	Tests
0	0	Covered	T4,T5,T9
0	1	Covered	T4,T5,T9
1	0	Covered	T55,T89,T160

 LINE       196
 SUB-EXPRESSION ( ! ((oup_buf_almost_full && oup_buf_wvalid) || oup_buf_full) )
                    ----------------------------1----------------------------

-1-	Status	Tests
0	Covered	T55,T89,T160
1	Covered	T4,T5,T9

 LINE       196
 SUB-EXPRESSION ((oup_buf_almost_full && oup_buf_wvalid) || oup_buf_full)
                 -------------------1-------------------    ------2-----

-1-	-2-	Status	Tests
0	0	Covered	T55,T89,T160
0	1	Covered	T4,T5,T9
1	0	Covered	T4,T5,T9

 LINE       196
 SUB-EXPRESSION (oup_buf_almost_full && oup_buf_wvalid)
                 ---------1---------    -------2------

-1-	-2-	Status	Tests
0	1	Not Covered
1	0	Covered	T4,T5,T9
1	1	Covered	T4,T5,T9

 LINE       196
 SUB-EXPRESSION (fifo_rvalid_o && fifo_rready_i)
                 ------1------    ------2------

-1-	-2-	Status	Tests
0	1	Not Covered
1	0	Covered	T4,T5,T9
1	1	Covered	T4,T5,T9

 LINE       204
 EXPRESSION (((!sram_full)) && inp_buf_rvalid)
             -------1------    -------2------

-1-	-2-	Status	Tests
0	1	Not Covered
1	0	Covered	T4,T5,T9
1	1	Covered	T4,T5,T9

 LINE       207
 EXPRESSION (((!sram_full)) && sram_gnt_i)
             -------1------    -----2----

-1-	-2-	Status	Tests
0	1	Not Covered
1	0	Covered	T4,T5,T9
1	1	Covered	T4,T5,T9

 LINE       212
 EXPRESSION (oup_buf_wready && ((!sram_read_in_prev_cyc_q)))
             -------1------    --------------2-------------

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Covered	T4,T5,T9
1	1	Covered	T1,T2,T3

 LINE       220
 EXPRESSION (((!sram_full)) && inp_buf_rvalid)
             -------1------    -------2------

-1-	-2-	Status	Tests
0	1	Not Covered
1	0	Covered	T1,T2,T3
1	1	Covered	T4,T5,T9

 LINE       223
 EXPRESSION (((!sram_full)) && sram_gnt_i)
             -------1------    -----2----

-1-	-2-	Status	Tests
0	1	Not Covered
1	0	Covered	T1,T2,T3
1	1	Covered	T4,T5,T9

 LINE       236
 EXPRESSION (inp_buf_wready && ( ! (sram_full && oup_buf_full) ))
             -------1------    ----------------2----------------

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Covered	T68,T69,T55
1	1	Covered	T1,T2,T3

 LINE       236
 SUB-EXPRESSION ( ! (sram_full && oup_buf_full) )
                    -------------1-------------

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T68,T69,T55

 LINE       236
 SUB-EXPRESSION (sram_full && oup_buf_full)
                 ----1----    ------2-----

-1-	-2-	Status	Tests
0	1	Covered	T4,T5,T8
1	0	Not Covered
1	1	Covered	T68,T69,T55

---

Branch Coverage for Instance : tb.dut.i2c_core.u_fifos.u_acq_fifo_sram_adapter

	Line No.	Total	Covered	Percent
Branches		10	10	100.00
TERNARY	162	2	2	100.00
IF	164	2	2	100.00
IF	183	2	2	100.00
IF	191	4	4	100.00

162          assign sram_read_in_prev_cyc_d = clr_i ? 1'b0 : sram_incr_rd_ptr;
                                                    -1-  
                                                    ==>  
                                                    ==>  

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T2,T3

164            if (!rst_ni) begin
               -1-  
165              sram_read_in_prev_cyc_q <= 1'b0;
                 ==>
166            end else begin
167              sram_read_in_prev_cyc_q <= sram_read_in_prev_cyc_d;
                 ==>

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T2,T3

183            if (sram_read_in_prev_cyc_q) begin
               -1-  
184              oup_buf_wvalid = 1'b1;
                 ==>
185              oup_buf_wdata = sram_rdata_i;
186              // The output buffer must be ready; otherwise we are in an erroneous state.
187              state_err = !oup_buf_wready;
188            end
               MISSING_ELSE
               ==>

Branches:

-1-	Status	Tests
1	Covered	T4,T5,T9
0	Covered	T1,T2,T3

191            if (!sram_empty) begin
               -1-  
192        
193              // Prioritize refilling of the output buffer: if the output buffer is not being filled to the
194              // last slot in the current cycle or it is being read in the current cycle, read from the SRAM
195              // so the output buffer can be written in the next cycle.
196              if (!((oup_buf_almost_full && oup_buf_wvalid) || oup_buf_full)
                 -2-  
197                  || (fifo_rvalid_o && fifo_rready_i)) begin
198                sram_req_o = 1'b1;
                   ==>
199                sram_write_o = 1'b0;
200                sram_addr_o = sram_rd_addr;
201        
202              // If the output buffer is full (and not being read), drain the input buffer into the SRAM.
203              end else begin
204                sram_req_o = !sram_full && inp_buf_rvalid;
                   ==>
205                sram_write_o = 1'b1;
206                sram_addr_o = sram_wr_addr;
207                inp_buf_rready = !sram_full && sram_gnt_i;
208              end
209        
210            // If the SRAM is empty, data must flow from the input buffer to the output buffer if the output
211            // buffer is ready and is not receiving data read from the SRAM in the previous cycle
212            end else if (oup_buf_wready && !sram_read_in_prev_cyc_q) begin
                        -3-  
213              oup_buf_wvalid = inp_buf_rvalid;
                 ==>
214              oup_buf_wdata = inp_buf_rdata;
215              inp_buf_rready = oup_buf_wready;
216        
217            // Otherwise the SRAM is empty but the output buffer cannot take the data from the input buffer,
218            // so drain the input buffer into the SRAM.
219            end else begin
220              sram_req_o = !sram_full && inp_buf_rvalid;
                 ==>

Branches:

-1-	-2-	-3-	Status	Tests
1	1	-	Covered	T4,T5,T9
1	0	-	Covered	T4,T5,T9
0	-	1	Covered	T1,T2,T3
0	-	0	Covered	T1,T2,T3

---

Assert Coverage for Instance : tb.dut.i2c_core.u_fifos.u_acq_fifo_sram_adapter

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	7	7	100.00	7	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	7	7	100.00	7	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
MinimalSramAw_A	1675	1675	0	0
MinimalSramFifoDepth_A	1675	1675	0	0
NoErr_A	408961761	408787796	0	0
NoSramReadWhenEmpty_A	408961761	165953611	0	0
NoSramWriteWhenFull_A	408961761	63175	0	0
OupBufWreadyAfterSramRead_A	408961761	245058	0	0
SramRvalidAfterRead_A	408961761	245058	0	0

MinimalSramAw_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	1675	1675	0	0
T1	1	1	0	0
T2	1	1	0	0
T3	1	1	0	0
T4	1	1	0	0
T5	1	1	0	0
T6	1	1	0	0
T7	1	1	0	0
T8	1	1	0	0
T9	1	1	0	0
T10	1	1	0	0

MinimalSramFifoDepth_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	1675	1675	0	0
T1	1	1	0	0
T2	1	1	0	0
T3	1	1	0	0
T4	1	1	0	0
T5	1	1	0	0
T6	1	1	0	0
T7	1	1	0	0
T8	1	1	0	0
T9	1	1	0	0
T10	1	1	0	0

NoErr_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	408961761	408787796	0	0
T1	1923	1863	0	0
T2	10306	10241	0	0
T3	13901	13178	0	0
T4	496654	496566	0	0
T5	21213	21144	0	0
T6	9621	9554	0	0
T7	12572	12494	0	0
T8	7344	7249	0	0
T9	9692	9639	0	0
T10	14705	14619	0	0

NoSramReadWhenEmpty_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	408961761	165953611	0	0
T1	1923	1863	0	0
T2	10306	10241	0	0
T3	13901	13178	0	0
T4	496654	261885	0	0
T5	21213	19389	0	0
T6	9621	9554	0	0
T7	12572	12494	0	0
T8	7344	7249	0	0
T9	9692	1425	0	0
T10	14705	14619	0	0

NoSramWriteWhenFull_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	408961761	63175	0	0
T11	41359	0	0	0
T17	6139	0	0	0
T19	213495	0	0	0
T30	11728	0	0	0
T55	187705	26	0	0
T57	0	21	0	0
T68	45068	1624	0	0
T69	42850	23	0	0
T70	0	8	0	0
T73	0	1360	0	0
T74	0	1527	0	0
T75	10450	0	0	0
T81	105995	0	0	0
T162	0	6	0	0
T163	0	5	0	0
T164	0	765	0	0
T167	129424	0	0	0

OupBufWreadyAfterSramRead_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	408961761	245058	0	0
T4	496654	1435	0	0
T5	21213	6	0	0
T6	9621	0	0	0
T7	12572	0	0	0
T8	7344	0	0	0
T9	9692	52	0	0
T10	14705	0	0	0
T49	57668	272	0	0
T50	20238	0	0	0
T51	0	130	0	0
T69	0	266	0	0
T71	0	144	0	0
T78	23009	44	0	0
T80	0	29	0	0
T167	0	435	0	0

SramRvalidAfterRead_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	408961761	245058	0	0
T4	496654	1435	0	0
T5	21213	6	0	0
T6	9621	0	0	0
T7	12572	0	0	0
T8	7344	0	0	0
T9	9692	52	0	0
T10	14705	0	0	0
T49	57668	272	0	0
T50	20238	0	0	0
T51	0	130	0	0
T69	0	266	0	0
T71	0	144	0	0
T78	23009	44	0	0
T80	0	29	0	0
T167	0	435	0	0