Unified Coverage Report :: Module :: prim_subreg

Module : prim_subreg

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
96.75	100.00	97.40			92.86

Source File(s) :
/workspaces/repo/scratch/os_regression_2024_08_28/i2c-sim-vcs/default/sim-vcs/../src/lowrisc_prim_subreg_0/rtl/prim_subreg.sv

Module self-instances :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
tb.dut.u_reg.u_intr_state_fmt_threshold	65.24	85.71	50.00			60.00
tb.dut.u_reg.u_intr_state_rx_threshold	65.24	85.71	50.00			60.00
tb.dut.u_reg.u_intr_state_acq_threshold	65.24	85.71	50.00			60.00
tb.dut.u_reg.u_intr_state_controller_halt	65.24	85.71	50.00			60.00
tb.dut.u_reg.u_intr_state_tx_stretch	65.24	85.71	50.00			60.00
tb.dut.u_reg.u_intr_state_tx_threshold	65.24	85.71	50.00			60.00
tb.dut.u_reg.u_intr_state_acq_stretch	65.24	85.71	50.00			60.00
tb.dut.u_reg.u_target_nack_count	85.71	100.00	71.43			85.71
tb.dut.u_reg.u_intr_state_rx_overflow	100.00	100.00	100.00			100.00
tb.dut.u_reg.u_intr_state_scl_interference	100.00	100.00	100.00			100.00
tb.dut.u_reg.u_intr_state_sda_interference	100.00	100.00	100.00			100.00
tb.dut.u_reg.u_intr_state_stretch_timeout	100.00	100.00	100.00			100.00
tb.dut.u_reg.u_intr_state_sda_unstable	100.00	100.00	100.00			100.00
tb.dut.u_reg.u_intr_state_cmd_complete	100.00	100.00	100.00			100.00
tb.dut.u_reg.u_intr_state_unexp_stop	100.00	100.00	100.00			100.00
tb.dut.u_reg.u_intr_state_host_timeout	100.00	100.00	100.00			100.00
tb.dut.u_reg.u_intr_enable_fmt_threshold	100.00	100.00	100.00			100.00
tb.dut.u_reg.u_intr_enable_rx_threshold	100.00	100.00	100.00			100.00
tb.dut.u_reg.u_intr_enable_acq_threshold	100.00	100.00	100.00			100.00
tb.dut.u_reg.u_intr_enable_rx_overflow	100.00	100.00	100.00			100.00
tb.dut.u_reg.u_intr_enable_controller_halt	100.00	100.00	100.00			100.00
tb.dut.u_reg.u_intr_enable_scl_interference	100.00	100.00	100.00			100.00
tb.dut.u_reg.u_intr_enable_sda_interference	100.00	100.00	100.00			100.00
tb.dut.u_reg.u_intr_enable_stretch_timeout	100.00	100.00	100.00			100.00
tb.dut.u_reg.u_intr_enable_sda_unstable	100.00	100.00	100.00			100.00
tb.dut.u_reg.u_intr_enable_cmd_complete	100.00	100.00	100.00			100.00
tb.dut.u_reg.u_intr_enable_tx_stretch	100.00	100.00	100.00			100.00
tb.dut.u_reg.u_intr_enable_tx_threshold	100.00	100.00	100.00			100.00
tb.dut.u_reg.u_intr_enable_acq_stretch	100.00	100.00	100.00			100.00
tb.dut.u_reg.u_intr_enable_unexp_stop	100.00	100.00	100.00			100.00
tb.dut.u_reg.u_intr_enable_host_timeout	100.00	100.00	100.00			100.00
tb.dut.u_reg.u_ctrl_enablehost	100.00	100.00	100.00			100.00
tb.dut.u_reg.u_ctrl_enabletarget	100.00	100.00	100.00			100.00
tb.dut.u_reg.u_ctrl_llpbk	100.00	100.00	100.00			100.00
tb.dut.u_reg.u_ctrl_nack_addr_after_timeout	100.00	100.00	100.00			100.00
tb.dut.u_reg.u_ctrl_ack_ctrl_en	100.00	100.00	100.00			100.00
tb.dut.u_reg.u_ctrl_multi_controller_monitor_en	100.00	100.00	100.00			100.00
tb.dut.u_reg.u_ctrl_tx_stretch_ctrl_en	100.00	100.00	100.00			100.00
tb.dut.u_reg.u_fdata_fbyte	100.00	100.00	100.00			100.00
tb.dut.u_reg.u_fdata_start	100.00	100.00	100.00			100.00
tb.dut.u_reg.u_fdata_stop	100.00	100.00	100.00			100.00
tb.dut.u_reg.u_fdata_readb	100.00	100.00	100.00			100.00
tb.dut.u_reg.u_fdata_rcont	100.00	100.00	100.00			100.00
tb.dut.u_reg.u_fdata_nakok	100.00	100.00	100.00			100.00
tb.dut.u_reg.u_fifo_ctrl_rxrst	100.00	100.00	100.00			100.00
tb.dut.u_reg.u_fifo_ctrl_fmtrst	100.00	100.00	100.00			100.00
tb.dut.u_reg.u_fifo_ctrl_acqrst	100.00	100.00	100.00			100.00
tb.dut.u_reg.u_fifo_ctrl_txrst	100.00	100.00	100.00			100.00
tb.dut.u_reg.u_host_fifo_config_rx_thresh	100.00	100.00	100.00			100.00
tb.dut.u_reg.u_host_fifo_config_fmt_thresh	100.00	100.00	100.00			100.00
tb.dut.u_reg.u_target_fifo_config_tx_thresh	100.00	100.00	100.00			100.00
tb.dut.u_reg.u_target_fifo_config_acq_thresh	100.00	100.00	100.00			100.00
tb.dut.u_reg.u_ovrd_txovrden	100.00	100.00	100.00			100.00
tb.dut.u_reg.u_ovrd_sclval	100.00	100.00	100.00			100.00
tb.dut.u_reg.u_ovrd_sdaval	100.00	100.00	100.00			100.00
tb.dut.u_reg.u_timing0_thigh	100.00	100.00	100.00			100.00
tb.dut.u_reg.u_timing0_tlow	100.00	100.00	100.00			100.00
tb.dut.u_reg.u_timing1_t_r	100.00	100.00	100.00			100.00
tb.dut.u_reg.u_timing1_t_f	100.00	100.00	100.00			100.00
tb.dut.u_reg.u_timing2_tsu_sta	100.00	100.00	100.00			100.00
tb.dut.u_reg.u_timing2_thd_sta	100.00	100.00	100.00			100.00
tb.dut.u_reg.u_timing3_tsu_dat	100.00	100.00	100.00			100.00
tb.dut.u_reg.u_timing3_thd_dat	100.00	100.00	100.00			100.00
tb.dut.u_reg.u_timing4_tsu_sto	100.00	100.00	100.00			100.00
tb.dut.u_reg.u_timing4_t_buf	100.00	100.00	100.00			100.00
tb.dut.u_reg.u_timeout_ctrl_val	100.00	100.00	100.00			100.00
tb.dut.u_reg.u_timeout_ctrl_mode	100.00	100.00	100.00			100.00
tb.dut.u_reg.u_timeout_ctrl_en	100.00	100.00	100.00			100.00
tb.dut.u_reg.u_target_id_address0	100.00	100.00	100.00			100.00
tb.dut.u_reg.u_target_id_mask0	100.00	100.00	100.00			100.00
tb.dut.u_reg.u_target_id_address1	100.00	100.00	100.00			100.00
tb.dut.u_reg.u_target_id_mask1	100.00	100.00	100.00			100.00
tb.dut.u_reg.u_txdata	100.00	100.00	100.00			100.00
tb.dut.u_reg.u_host_timeout_ctrl	100.00	100.00	100.00			100.00
tb.dut.u_reg.u_target_timeout_ctrl_val	100.00	100.00	100.00			100.00
tb.dut.u_reg.u_target_timeout_ctrl_en	100.00	100.00	100.00			100.00
tb.dut.u_reg.u_host_nack_handler_timeout_val	100.00	100.00	100.00			100.00
tb.dut.u_reg.u_host_nack_handler_timeout_en	100.00	100.00	100.00			100.00
tb.dut.u_reg.u_controller_events_nack	100.00	100.00	100.00			100.00
tb.dut.u_reg.u_controller_events_unhandled_nack_timeout	100.00	100.00	100.00			100.00
tb.dut.u_reg.u_controller_events_bus_timeout	100.00	100.00	100.00			100.00
tb.dut.u_reg.u_controller_events_arbitration_lost	100.00	100.00	100.00			100.00
tb.dut.u_reg.u_target_events_tx_pending	100.00	100.00	100.00			100.00
tb.dut.u_reg.u_target_events_bus_timeout	100.00	100.00	100.00			100.00
tb.dut.u_reg.u_target_events_arbitration_lost	100.00	100.00	100.00			100.00

Line Coverage for Module : prim_subreg ( parameter DW=1,SwAccess=1,RESVAL=0,Mubi=0 + DW=1,SwAccess=3,RESVAL=0,Mubi=0 + DW=1,SwAccess=0,RESVAL=0,Mubi=0 + DW=8,SwAccess=2,RESVAL=0,Mubi=0 + DW=12,SwAccess=0,RESVAL=0,Mubi=0 + DW=13,SwAccess=0,RESVAL=0,Mubi=0 + DW=10,SwAccess=0,RESVAL=0,Mubi=0 + DW=9,SwAccess=0,RESVAL=0,Mubi=0 + DW=30,SwAccess=0,RESVAL=0,Mubi=0 + DW=7,SwAccess=0,RESVAL=0,Mubi=0 + DW=20,SwAccess=0,RESVAL=0,Mubi=0 + DW=31,SwAccess=0,RESVAL=0,Mubi=0 )
Line Coverage for Module self-instances :

SCORE	LINE
65.24	85.71

tb.dut.u_reg.u_intr_state_fmt_threshold

SCORE	LINE
65.24	85.71

tb.dut.u_reg.u_intr_state_rx_threshold

SCORE	LINE
65.24	85.71

tb.dut.u_reg.u_intr_state_acq_threshold

SCORE	LINE
100.00	100.00

tb.dut.u_reg.u_intr_state_rx_overflow

SCORE	LINE
65.24	85.71

tb.dut.u_reg.u_intr_state_controller_halt

SCORE	LINE
100.00	100.00

tb.dut.u_reg.u_intr_state_scl_interference

SCORE	LINE
100.00	100.00

tb.dut.u_reg.u_intr_state_sda_interference

SCORE	LINE
100.00	100.00

tb.dut.u_reg.u_intr_state_stretch_timeout

SCORE	LINE
100.00	100.00

tb.dut.u_reg.u_intr_state_sda_unstable

SCORE	LINE
100.00	100.00

tb.dut.u_reg.u_intr_state_cmd_complete

SCORE	LINE
65.24	85.71

tb.dut.u_reg.u_intr_state_tx_stretch

SCORE	LINE
65.24	85.71

tb.dut.u_reg.u_intr_state_tx_threshold

SCORE	LINE
65.24	85.71

tb.dut.u_reg.u_intr_state_acq_stretch

SCORE	LINE
100.00	100.00

tb.dut.u_reg.u_intr_state_unexp_stop

SCORE	LINE
100.00	100.00

tb.dut.u_reg.u_intr_state_host_timeout

SCORE	LINE
100.00	100.00

tb.dut.u_reg.u_intr_enable_fmt_threshold

SCORE	LINE
100.00	100.00

tb.dut.u_reg.u_intr_enable_rx_threshold

SCORE	LINE
100.00	100.00

tb.dut.u_reg.u_intr_enable_acq_threshold

SCORE	LINE
100.00	100.00

tb.dut.u_reg.u_intr_enable_rx_overflow

SCORE	LINE
100.00	100.00

tb.dut.u_reg.u_intr_enable_controller_halt

SCORE	LINE
100.00	100.00

tb.dut.u_reg.u_intr_enable_scl_interference

SCORE	LINE
100.00	100.00

tb.dut.u_reg.u_intr_enable_sda_interference

SCORE	LINE
100.00	100.00

tb.dut.u_reg.u_intr_enable_stretch_timeout

SCORE	LINE
100.00	100.00

tb.dut.u_reg.u_intr_enable_sda_unstable

SCORE	LINE
100.00	100.00

tb.dut.u_reg.u_intr_enable_cmd_complete

SCORE	LINE
100.00	100.00

tb.dut.u_reg.u_intr_enable_tx_stretch

SCORE	LINE
100.00	100.00

tb.dut.u_reg.u_intr_enable_tx_threshold

SCORE	LINE
100.00	100.00

tb.dut.u_reg.u_intr_enable_acq_stretch

SCORE	LINE
100.00	100.00

tb.dut.u_reg.u_intr_enable_unexp_stop

SCORE	LINE
100.00	100.00

tb.dut.u_reg.u_intr_enable_host_timeout

SCORE	LINE
100.00	100.00

tb.dut.u_reg.u_ctrl_enablehost

SCORE	LINE
100.00	100.00

tb.dut.u_reg.u_ctrl_enabletarget

SCORE	LINE
100.00	100.00

tb.dut.u_reg.u_ctrl_llpbk

SCORE	LINE
100.00	100.00

tb.dut.u_reg.u_ctrl_nack_addr_after_timeout

SCORE	LINE
100.00	100.00

tb.dut.u_reg.u_ctrl_ack_ctrl_en

SCORE	LINE
100.00	100.00

tb.dut.u_reg.u_ctrl_multi_controller_monitor_en

SCORE	LINE
100.00	100.00

tb.dut.u_reg.u_ctrl_tx_stretch_ctrl_en

SCORE	LINE
100.00	100.00

tb.dut.u_reg.u_fdata_fbyte

SCORE	LINE
100.00	100.00

tb.dut.u_reg.u_fdata_start

SCORE	LINE
100.00	100.00

tb.dut.u_reg.u_fdata_stop

SCORE	LINE
100.00	100.00

tb.dut.u_reg.u_fdata_readb

SCORE	LINE
100.00	100.00

tb.dut.u_reg.u_fdata_rcont

SCORE	LINE
100.00	100.00

tb.dut.u_reg.u_fdata_nakok

SCORE	LINE
100.00	100.00

tb.dut.u_reg.u_fifo_ctrl_rxrst

SCORE	LINE
100.00	100.00

tb.dut.u_reg.u_fifo_ctrl_fmtrst

SCORE	LINE
100.00	100.00

tb.dut.u_reg.u_fifo_ctrl_acqrst

SCORE	LINE
100.00	100.00

tb.dut.u_reg.u_fifo_ctrl_txrst

SCORE	LINE
100.00	100.00

tb.dut.u_reg.u_host_fifo_config_rx_thresh

SCORE	LINE
100.00	100.00

tb.dut.u_reg.u_host_fifo_config_fmt_thresh

SCORE	LINE
100.00	100.00

tb.dut.u_reg.u_target_fifo_config_tx_thresh

SCORE	LINE
100.00	100.00

tb.dut.u_reg.u_target_fifo_config_acq_thresh

SCORE	LINE
100.00	100.00

tb.dut.u_reg.u_ovrd_txovrden

SCORE	LINE
100.00	100.00

tb.dut.u_reg.u_ovrd_sclval

SCORE	LINE
100.00	100.00

tb.dut.u_reg.u_ovrd_sdaval

SCORE	LINE
100.00	100.00

tb.dut.u_reg.u_timing0_thigh

SCORE	LINE
100.00	100.00

tb.dut.u_reg.u_timing0_tlow

SCORE	LINE
100.00	100.00

tb.dut.u_reg.u_timing1_t_r

SCORE	LINE
100.00	100.00

tb.dut.u_reg.u_timing1_t_f

SCORE	LINE
100.00	100.00

tb.dut.u_reg.u_timing2_tsu_sta

SCORE	LINE
100.00	100.00

tb.dut.u_reg.u_timing2_thd_sta

SCORE	LINE
100.00	100.00

tb.dut.u_reg.u_timing3_tsu_dat

SCORE	LINE
100.00	100.00

tb.dut.u_reg.u_timing3_thd_dat

SCORE	LINE
100.00	100.00

tb.dut.u_reg.u_timing4_tsu_sto

SCORE	LINE
100.00	100.00

tb.dut.u_reg.u_timing4_t_buf

SCORE	LINE
100.00	100.00

tb.dut.u_reg.u_timeout_ctrl_val

SCORE	LINE
100.00	100.00

tb.dut.u_reg.u_timeout_ctrl_mode

SCORE	LINE
100.00	100.00

tb.dut.u_reg.u_timeout_ctrl_en

SCORE	LINE
100.00	100.00

tb.dut.u_reg.u_target_id_address0

SCORE	LINE
100.00	100.00

tb.dut.u_reg.u_target_id_mask0

SCORE	LINE
100.00	100.00

tb.dut.u_reg.u_target_id_address1

SCORE	LINE
100.00	100.00

tb.dut.u_reg.u_target_id_mask1

SCORE	LINE
100.00	100.00

tb.dut.u_reg.u_txdata

SCORE	LINE
100.00	100.00

tb.dut.u_reg.u_host_timeout_ctrl

SCORE	LINE
100.00	100.00

tb.dut.u_reg.u_target_timeout_ctrl_val

SCORE	LINE
100.00	100.00

tb.dut.u_reg.u_target_timeout_ctrl_en

SCORE	LINE
100.00	100.00

tb.dut.u_reg.u_host_nack_handler_timeout_val

SCORE	LINE
100.00	100.00

tb.dut.u_reg.u_host_nack_handler_timeout_en

SCORE	LINE
100.00	100.00

tb.dut.u_reg.u_controller_events_nack

SCORE	LINE
100.00	100.00

tb.dut.u_reg.u_controller_events_unhandled_nack_timeout

SCORE	LINE
100.00	100.00

tb.dut.u_reg.u_controller_events_bus_timeout

SCORE	LINE
100.00	100.00

tb.dut.u_reg.u_controller_events_arbitration_lost

SCORE	LINE
100.00	100.00

tb.dut.u_reg.u_target_events_tx_pending

SCORE	LINE
100.00	100.00

tb.dut.u_reg.u_target_events_bus_timeout

SCORE	LINE
100.00	100.00

tb.dut.u_reg.u_target_events_arbitration_lost

	Line No.	Total	Covered	Percent
TOTAL		7	7	100.00
ALWAYS	56	4	4	100.00
CONT_ASSIGN	64	1	1	100.00
CONT_ASSIGN	65	1	1	100.00
CONT_ASSIGN	72	1	1	100.00

55                        always_ff @(posedge clk_i or negedge rst_ni) begin
56         1/1              if (!rst_ni) begin
           Tests:       T1 T2 T3 
57         1/1                q <= RESVAL;
           Tests:       T1 T2 T3 
58         1/1              end else if (wr_en) begin
           Tests:       T1 T2 T3 
59         1/1                q <= wr_data;
           Tests:       T1 T2 T3 
60                          end
                        MISSING_ELSE
61                        end
62                      
63                        // feed back out for consolidation
64         1/1            assign ds = wr_en ? wr_data : qs;
           Tests:       T1 T2 T3 
65         1/1            assign qe = wr_en;
           Tests:       T1 T2 T3 
66                      
67                        if (SwAccess == SwAccessRC) begin : gen_rc
68                          // In case of a SW RC colliding with a HW write, SW gets the value written by HW
69                          // but the register is cleared to 0. See #5416 for a discussion.
70                          assign qs = de && we ? d : q;
71                        end else begin : gen_no_rc
72         1/1              assign qs = q;
           Tests:       T1 T2 T3 

---

Line Coverage for Module : prim_subreg ( parameter DW=8,SwAccess=6,RESVAL=0,Mubi=0 )
Line Coverage for Module self-instances :

SCORE	LINE
85.71	100.00

tb.dut.u_reg.u_target_nack_count

	Line No.	Total	Covered	Percent
TOTAL		7	7	100.00
ALWAYS	56	4	4	100.00
CONT_ASSIGN	64	1	1	100.00
CONT_ASSIGN	65	1	1	100.00
CONT_ASSIGN	70	1	1	100.00

55                        always_ff @(posedge clk_i or negedge rst_ni) begin
56         1/1              if (!rst_ni) begin
           Tests:       T1 T2 T3 
57         1/1                q <= RESVAL;
           Tests:       T1 T2 T3 
58         1/1              end else if (wr_en) begin
           Tests:       T1 T2 T3 
59         1/1                q <= wr_data;
           Tests:       T68 T69 T70 
60                          end
                        MISSING_ELSE
61                        end
62                      
63                        // feed back out for consolidation
64         1/1            assign ds = wr_en ? wr_data : qs;
           Tests:       T1 T2 T3 
65         1/1            assign qe = wr_en;
           Tests:       T1 T2 T3 
66                      
67                        if (SwAccess == SwAccessRC) begin : gen_rc
68                          // In case of a SW RC colliding with a HW write, SW gets the value written by HW
69                          // but the register is cleared to 0. See #5416 for a discussion.
70         1/1              assign qs = de && we ? d : q;
           Tests:       T1 T2 T3 

---

Cond Coverage for Module : prim_subreg ( parameter DW=30,SwAccess=0,RESVAL=0,Mubi=0 )
Cond Coverage for Module self-instances :

SCORE	COND
100.00	100.00

tb.dut.u_reg.u_timeout_ctrl_val

	Total	Covered	Percent
Conditions	2	2	100.00
Logical	2	2	100.00
Non-Logical	0	0
Event	0	0

 LINE       64
 EXPRESSION (wr_en ? wr_data : qs)
             --1--

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T3,T4,T5

---

Cond Coverage for Module : prim_subreg ( parameter DW=20,SwAccess=0,RESVAL=0,Mubi=0 )
Cond Coverage for Module self-instances :

SCORE	COND
100.00	100.00

tb.dut.u_reg.u_host_timeout_ctrl

	Total	Covered	Percent
Conditions	2	2	100.00
Logical	2	2	100.00
Non-Logical	0	0
Event	0	0

 LINE       64
 EXPRESSION (wr_en ? wr_data : qs)
             --1--

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T4,T5,T6

---

Cond Coverage for Module : prim_subreg ( parameter DW=8,SwAccess=2,RESVAL=0,Mubi=0 )
Cond Coverage for Module self-instances :

SCORE	COND
100.00	100.00

tb.dut.u_reg.u_fdata_fbyte

SCORE	COND
100.00	100.00

tb.dut.u_reg.u_txdata

	Total	Covered	Percent
Conditions	2	2	100.00
Logical	2	2	100.00
Non-Logical	0	0
Event	0	0

 LINE       64
 EXPRESSION (wr_en ? wr_data : qs)
             --1--

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T2,T3,T4

---

Cond Coverage for Module : prim_subreg ( parameter DW=1,SwAccess=1,RESVAL=0,Mubi=0 + DW=1,SwAccess=3,RESVAL=0,Mubi=0 + DW=1,SwAccess=0,RESVAL=0,Mubi=0 )
Cond Coverage for Module self-instances :

SCORE	COND
65.24	50.00

tb.dut.u_reg.u_intr_state_fmt_threshold

SCORE	COND
65.24	50.00

tb.dut.u_reg.u_intr_state_rx_threshold

SCORE	COND
65.24	50.00

tb.dut.u_reg.u_intr_state_acq_threshold

SCORE	COND
65.24	50.00

tb.dut.u_reg.u_intr_state_controller_halt

SCORE	COND
65.24	50.00

tb.dut.u_reg.u_intr_state_tx_stretch

SCORE	COND
65.24	50.00

tb.dut.u_reg.u_intr_state_tx_threshold

SCORE	COND
65.24	50.00

tb.dut.u_reg.u_intr_state_acq_stretch

SCORE	COND
100.00	100.00

tb.dut.u_reg.u_intr_state_rx_overflow

SCORE	COND
100.00	100.00

tb.dut.u_reg.u_intr_state_scl_interference

SCORE	COND
100.00	100.00

tb.dut.u_reg.u_intr_state_sda_interference

SCORE	COND
100.00	100.00

tb.dut.u_reg.u_intr_state_stretch_timeout

SCORE	COND
100.00	100.00

tb.dut.u_reg.u_intr_state_sda_unstable

SCORE	COND
100.00	100.00

tb.dut.u_reg.u_intr_state_cmd_complete

SCORE	COND
100.00	100.00

tb.dut.u_reg.u_intr_state_unexp_stop

SCORE	COND
100.00	100.00

tb.dut.u_reg.u_intr_state_host_timeout

SCORE	COND
100.00	100.00

tb.dut.u_reg.u_controller_events_nack

SCORE	COND
100.00	100.00

tb.dut.u_reg.u_controller_events_unhandled_nack_timeout

SCORE	COND
100.00	100.00

tb.dut.u_reg.u_controller_events_bus_timeout

SCORE	COND
100.00	100.00

tb.dut.u_reg.u_controller_events_arbitration_lost

SCORE	COND
100.00	100.00

tb.dut.u_reg.u_target_events_tx_pending

SCORE	COND
100.00	100.00

tb.dut.u_reg.u_target_events_bus_timeout

SCORE	COND
100.00	100.00

tb.dut.u_reg.u_target_events_arbitration_lost

SCORE	COND
100.00	100.00

tb.dut.u_reg.u_intr_enable_fmt_threshold

SCORE	COND
100.00	100.00

tb.dut.u_reg.u_intr_enable_rx_threshold

SCORE	COND
100.00	100.00

tb.dut.u_reg.u_intr_enable_acq_threshold

SCORE	COND
100.00	100.00

tb.dut.u_reg.u_intr_enable_rx_overflow

SCORE	COND
100.00	100.00

tb.dut.u_reg.u_intr_enable_controller_halt

SCORE	COND
100.00	100.00

tb.dut.u_reg.u_intr_enable_scl_interference

SCORE	COND
100.00	100.00

tb.dut.u_reg.u_intr_enable_sda_interference

SCORE	COND
100.00	100.00

tb.dut.u_reg.u_intr_enable_stretch_timeout

SCORE	COND
100.00	100.00

tb.dut.u_reg.u_intr_enable_sda_unstable

SCORE	COND
100.00	100.00

tb.dut.u_reg.u_intr_enable_cmd_complete

SCORE	COND
100.00	100.00

tb.dut.u_reg.u_intr_enable_tx_stretch

SCORE	COND
100.00	100.00

tb.dut.u_reg.u_intr_enable_tx_threshold

SCORE	COND
100.00	100.00

tb.dut.u_reg.u_intr_enable_acq_stretch

SCORE	COND
100.00	100.00

tb.dut.u_reg.u_intr_enable_unexp_stop

SCORE	COND
100.00	100.00

tb.dut.u_reg.u_intr_enable_host_timeout

SCORE	COND
100.00	100.00

tb.dut.u_reg.u_ctrl_enablehost

SCORE	COND
100.00	100.00

tb.dut.u_reg.u_ctrl_enabletarget

SCORE	COND
100.00	100.00

tb.dut.u_reg.u_ctrl_llpbk

SCORE	COND
100.00	100.00

tb.dut.u_reg.u_ctrl_nack_addr_after_timeout

SCORE	COND
100.00	100.00

tb.dut.u_reg.u_ctrl_ack_ctrl_en

SCORE	COND
100.00	100.00

tb.dut.u_reg.u_ctrl_multi_controller_monitor_en

SCORE	COND
100.00	100.00

tb.dut.u_reg.u_ctrl_tx_stretch_ctrl_en

SCORE	COND
100.00	100.00

tb.dut.u_reg.u_fdata_start

SCORE	COND
100.00	100.00

tb.dut.u_reg.u_fdata_stop

SCORE	COND
100.00	100.00

tb.dut.u_reg.u_fdata_readb

SCORE	COND
100.00	100.00

tb.dut.u_reg.u_fdata_rcont

SCORE	COND
100.00	100.00

tb.dut.u_reg.u_fdata_nakok

SCORE	COND
100.00	100.00

tb.dut.u_reg.u_fifo_ctrl_rxrst

SCORE	COND
100.00	100.00

tb.dut.u_reg.u_fifo_ctrl_fmtrst

SCORE	COND
100.00	100.00

tb.dut.u_reg.u_fifo_ctrl_acqrst

SCORE	COND
100.00	100.00

tb.dut.u_reg.u_fifo_ctrl_txrst

SCORE	COND
100.00	100.00

tb.dut.u_reg.u_ovrd_txovrden

SCORE	COND
100.00	100.00

tb.dut.u_reg.u_ovrd_sclval

SCORE	COND
100.00	100.00

tb.dut.u_reg.u_ovrd_sdaval

SCORE	COND
100.00	100.00

tb.dut.u_reg.u_timeout_ctrl_mode

SCORE	COND
100.00	100.00

tb.dut.u_reg.u_timeout_ctrl_en

SCORE	COND
100.00	100.00

tb.dut.u_reg.u_target_timeout_ctrl_en

SCORE	COND
100.00	100.00

tb.dut.u_reg.u_host_nack_handler_timeout_en

	Total	Covered	Percent
Conditions	2	2	100.00
Logical	2	2	100.00
Non-Logical	0	0
Event	0	0

 LINE       64
 EXPRESSION (wr_en ? wr_data : qs)
             --1--

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T1,T2,T3

---

Cond Coverage for Module : prim_subreg ( parameter DW=31,SwAccess=0,RESVAL=0,Mubi=0 )
Cond Coverage for Module self-instances :

SCORE	COND
100.00	100.00

tb.dut.u_reg.u_target_timeout_ctrl_val

SCORE	COND
100.00	100.00

tb.dut.u_reg.u_host_nack_handler_timeout_val

	Total	Covered	Percent
Conditions	2	2	100.00
Logical	2	2	100.00
Non-Logical	0	0
Event	0	0

 LINE       64
 EXPRESSION (wr_en ? wr_data : qs)
             --1--

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T68,T69,T11

---

Cond Coverage for Module : prim_subreg ( parameter DW=8,SwAccess=6,RESVAL=0,Mubi=0 )
Cond Coverage for Module self-instances :

SCORE	COND
85.71	71.43

tb.dut.u_reg.u_target_nack_count

	Total	Covered	Percent
Conditions	7	5	71.43
Logical	7	5	71.43
Non-Logical	0	0
Event	0	0

 LINE       64
 EXPRESSION (wr_en ? wr_data : qs)
             --1--

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T68,T69,T70

 LINE       70
 EXPRESSION ((de && we) ? d : q)
             -----1----

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Not Covered

 LINE       70
 SUB-EXPRESSION (de && we)
                 -1    -2

-1-	-2-	Status	Tests
0	1	Covered	T68,T69,T70
1	0	Covered	T68,T69,T70
1	1	Not Covered

---

Cond Coverage for Module : prim_subreg ( parameter DW=10,SwAccess=0,RESVAL=0,Mubi=0 )
Cond Coverage for Module self-instances :

SCORE	COND
100.00	100.00

tb.dut.u_reg.u_timing1_t_r

	Total	Covered	Percent
Conditions	2	2	100.00
Logical	2	2	100.00
Non-Logical	0	0
Event	0	0

 LINE       64
 EXPRESSION (wr_en ? wr_data : qs)
             --1--

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T3,T4,T5

---

Cond Coverage for Module : prim_subreg ( parameter DW=7,SwAccess=0,RESVAL=0,Mubi=0 )
Cond Coverage for Module self-instances :

SCORE	COND
100.00	100.00

tb.dut.u_reg.u_target_id_address0

SCORE	COND
100.00	100.00

tb.dut.u_reg.u_target_id_mask0

SCORE	COND
100.00	100.00

tb.dut.u_reg.u_target_id_address1

SCORE	COND
100.00	100.00

tb.dut.u_reg.u_target_id_mask1

	Total	Covered	Percent
Conditions	2	2	100.00
Logical	2	2	100.00
Non-Logical	0	0
Event	0	0

 LINE       64
 EXPRESSION (wr_en ? wr_data : qs)
             --1--

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T4,T5,T6

---

Cond Coverage for Module : prim_subreg ( parameter DW=12,SwAccess=0,RESVAL=0,Mubi=0 )
Cond Coverage for Module self-instances :

SCORE	COND
100.00	100.00

tb.dut.u_reg.u_host_fifo_config_rx_thresh

SCORE	COND
100.00	100.00

tb.dut.u_reg.u_host_fifo_config_fmt_thresh

SCORE	COND
100.00	100.00

tb.dut.u_reg.u_target_fifo_config_tx_thresh

SCORE	COND
100.00	100.00

tb.dut.u_reg.u_target_fifo_config_acq_thresh

	Total	Covered	Percent
Conditions	2	2	100.00
Logical	2	2	100.00
Non-Logical	0	0
Event	0	0

 LINE       64
 EXPRESSION (wr_en ? wr_data : qs)
             --1--

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T3,T4,T5

---

Cond Coverage for Module : prim_subreg ( parameter DW=9,SwAccess=0,RESVAL=0,Mubi=0 )
Cond Coverage for Module self-instances :

SCORE	COND
100.00	100.00

tb.dut.u_reg.u_timing1_t_f

SCORE	COND
100.00	100.00

tb.dut.u_reg.u_timing3_tsu_dat

	Total	Covered	Percent
Conditions	2	2	100.00
Logical	2	2	100.00
Non-Logical	0	0
Event	0	0

 LINE       64
 EXPRESSION (wr_en ? wr_data : qs)
             --1--

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T3,T4,T5

---

Cond Coverage for Module : prim_subreg ( parameter DW=13,SwAccess=0,RESVAL=0,Mubi=0 )
Cond Coverage for Module self-instances :

SCORE	COND
100.00	100.00

tb.dut.u_reg.u_timing0_thigh

SCORE	COND
100.00	100.00

tb.dut.u_reg.u_timing0_tlow

SCORE	COND
100.00	100.00

tb.dut.u_reg.u_timing2_tsu_sta

SCORE	COND
100.00	100.00

tb.dut.u_reg.u_timing2_thd_sta

SCORE	COND
100.00	100.00

tb.dut.u_reg.u_timing3_thd_dat

SCORE	COND
100.00	100.00

tb.dut.u_reg.u_timing4_tsu_sto

SCORE	COND
100.00	100.00

tb.dut.u_reg.u_timing4_t_buf

	Total	Covered	Percent
Conditions	2	2	100.00
Logical	2	2	100.00
Non-Logical	0	0
Event	0	0

 LINE       64
 EXPRESSION (wr_en ? wr_data : qs)
             --1--

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T3,T4,T5

---

Branch Coverage for Module : prim_subreg ( parameter DW=1,SwAccess=1,RESVAL=0,Mubi=0 + DW=1,SwAccess=3,RESVAL=0,Mubi=0 + DW=1,SwAccess=0,RESVAL=0,Mubi=0 + DW=8,SwAccess=2,RESVAL=0,Mubi=0 + DW=12,SwAccess=0,RESVAL=0,Mubi=0 + DW=13,SwAccess=0,RESVAL=0,Mubi=0 + DW=10,SwAccess=0,RESVAL=0,Mubi=0 + DW=9,SwAccess=0,RESVAL=0,Mubi=0 + DW=30,SwAccess=0,RESVAL=0,Mubi=0 + DW=7,SwAccess=0,RESVAL=0,Mubi=0 + DW=20,SwAccess=0,RESVAL=0,Mubi=0 + DW=31,SwAccess=0,RESVAL=0,Mubi=0 )
Branch Coverage for Module self-instances :

SCORE	BRANCH
65.24	60.00

tb.dut.u_reg.u_intr_state_fmt_threshold

SCORE	BRANCH
65.24	60.00

tb.dut.u_reg.u_intr_state_rx_threshold

SCORE	BRANCH
65.24	60.00

tb.dut.u_reg.u_intr_state_acq_threshold

SCORE	BRANCH
65.24	60.00

tb.dut.u_reg.u_intr_state_controller_halt

SCORE	BRANCH
65.24	60.00

tb.dut.u_reg.u_intr_state_tx_stretch

SCORE	BRANCH
65.24	60.00

tb.dut.u_reg.u_intr_state_tx_threshold

SCORE	BRANCH
65.24	60.00

tb.dut.u_reg.u_intr_state_acq_stretch

SCORE	BRANCH
100.00	100.00

tb.dut.u_reg.u_intr_state_rx_overflow

SCORE	BRANCH
100.00	100.00

tb.dut.u_reg.u_intr_state_scl_interference

SCORE	BRANCH
100.00	100.00

tb.dut.u_reg.u_intr_state_sda_interference

SCORE	BRANCH
100.00	100.00

tb.dut.u_reg.u_intr_state_stretch_timeout

SCORE	BRANCH
100.00	100.00

tb.dut.u_reg.u_intr_state_sda_unstable

SCORE	BRANCH
100.00	100.00

tb.dut.u_reg.u_intr_state_cmd_complete

SCORE	BRANCH
100.00	100.00

tb.dut.u_reg.u_intr_state_unexp_stop

SCORE	BRANCH
100.00	100.00

tb.dut.u_reg.u_intr_state_host_timeout

SCORE	BRANCH
100.00	100.00

tb.dut.u_reg.u_controller_events_nack

SCORE	BRANCH
100.00	100.00

tb.dut.u_reg.u_controller_events_unhandled_nack_timeout

SCORE	BRANCH
100.00	100.00

tb.dut.u_reg.u_controller_events_bus_timeout

SCORE	BRANCH
100.00	100.00

tb.dut.u_reg.u_controller_events_arbitration_lost

SCORE	BRANCH
100.00	100.00

tb.dut.u_reg.u_target_events_tx_pending

SCORE	BRANCH
100.00	100.00

tb.dut.u_reg.u_target_events_bus_timeout

SCORE	BRANCH
100.00	100.00

tb.dut.u_reg.u_target_events_arbitration_lost

SCORE	BRANCH
100.00	100.00

tb.dut.u_reg.u_intr_enable_fmt_threshold

SCORE	BRANCH
100.00	100.00

tb.dut.u_reg.u_intr_enable_rx_threshold

SCORE	BRANCH
100.00	100.00

tb.dut.u_reg.u_intr_enable_acq_threshold

SCORE	BRANCH
100.00	100.00

tb.dut.u_reg.u_intr_enable_rx_overflow

SCORE	BRANCH
100.00	100.00

tb.dut.u_reg.u_intr_enable_controller_halt

SCORE	BRANCH
100.00	100.00

tb.dut.u_reg.u_intr_enable_scl_interference

SCORE	BRANCH
100.00	100.00

tb.dut.u_reg.u_intr_enable_sda_interference

SCORE	BRANCH
100.00	100.00

tb.dut.u_reg.u_intr_enable_stretch_timeout

SCORE	BRANCH
100.00	100.00

tb.dut.u_reg.u_intr_enable_sda_unstable

SCORE	BRANCH
100.00	100.00

tb.dut.u_reg.u_intr_enable_cmd_complete

SCORE	BRANCH
100.00	100.00

tb.dut.u_reg.u_intr_enable_tx_stretch

SCORE	BRANCH
100.00	100.00

tb.dut.u_reg.u_intr_enable_tx_threshold

SCORE	BRANCH
100.00	100.00

tb.dut.u_reg.u_intr_enable_acq_stretch

SCORE	BRANCH
100.00	100.00

tb.dut.u_reg.u_intr_enable_unexp_stop

SCORE	BRANCH
100.00	100.00

tb.dut.u_reg.u_intr_enable_host_timeout

SCORE	BRANCH
100.00	100.00

tb.dut.u_reg.u_ctrl_enablehost

SCORE	BRANCH
100.00	100.00

tb.dut.u_reg.u_ctrl_enabletarget

SCORE	BRANCH
100.00	100.00

tb.dut.u_reg.u_ctrl_llpbk

SCORE	BRANCH
100.00	100.00

tb.dut.u_reg.u_ctrl_nack_addr_after_timeout

SCORE	BRANCH
100.00	100.00

tb.dut.u_reg.u_ctrl_ack_ctrl_en

SCORE	BRANCH
100.00	100.00

tb.dut.u_reg.u_ctrl_multi_controller_monitor_en

SCORE	BRANCH
100.00	100.00

tb.dut.u_reg.u_ctrl_tx_stretch_ctrl_en

SCORE	BRANCH
100.00	100.00

tb.dut.u_reg.u_fdata_start

SCORE	BRANCH
100.00	100.00

tb.dut.u_reg.u_fdata_stop

SCORE	BRANCH
100.00	100.00

tb.dut.u_reg.u_fdata_readb

SCORE	BRANCH
100.00	100.00

tb.dut.u_reg.u_fdata_rcont

SCORE	BRANCH
100.00	100.00

tb.dut.u_reg.u_fdata_nakok

SCORE	BRANCH
100.00	100.00

tb.dut.u_reg.u_fifo_ctrl_rxrst

SCORE	BRANCH
100.00	100.00

tb.dut.u_reg.u_fifo_ctrl_fmtrst

SCORE	BRANCH
100.00	100.00

tb.dut.u_reg.u_fifo_ctrl_acqrst

SCORE	BRANCH
100.00	100.00

tb.dut.u_reg.u_fifo_ctrl_txrst

SCORE	BRANCH
100.00	100.00

tb.dut.u_reg.u_ovrd_txovrden

SCORE	BRANCH
100.00	100.00

tb.dut.u_reg.u_ovrd_sclval

SCORE	BRANCH
100.00	100.00

tb.dut.u_reg.u_ovrd_sdaval

SCORE	BRANCH
100.00	100.00

tb.dut.u_reg.u_timeout_ctrl_mode

SCORE	BRANCH
100.00	100.00

tb.dut.u_reg.u_timeout_ctrl_en

SCORE	BRANCH
100.00	100.00

tb.dut.u_reg.u_target_timeout_ctrl_en

SCORE	BRANCH
100.00	100.00

tb.dut.u_reg.u_host_nack_handler_timeout_en

SCORE	BRANCH
100.00	100.00

tb.dut.u_reg.u_fdata_fbyte

SCORE	BRANCH
100.00	100.00

tb.dut.u_reg.u_txdata

SCORE	BRANCH
100.00	100.00

tb.dut.u_reg.u_host_fifo_config_rx_thresh

SCORE	BRANCH
100.00	100.00

tb.dut.u_reg.u_host_fifo_config_fmt_thresh

SCORE	BRANCH
100.00	100.00

tb.dut.u_reg.u_target_fifo_config_tx_thresh

SCORE	BRANCH
100.00	100.00

tb.dut.u_reg.u_target_fifo_config_acq_thresh

SCORE	BRANCH
100.00	100.00

tb.dut.u_reg.u_timing0_thigh

SCORE	BRANCH
100.00	100.00

tb.dut.u_reg.u_timing0_tlow

SCORE	BRANCH
100.00	100.00

tb.dut.u_reg.u_timing2_tsu_sta

SCORE	BRANCH
100.00	100.00

tb.dut.u_reg.u_timing2_thd_sta

SCORE	BRANCH
100.00	100.00

tb.dut.u_reg.u_timing3_thd_dat

SCORE	BRANCH
100.00	100.00

tb.dut.u_reg.u_timing4_tsu_sto

SCORE	BRANCH
100.00	100.00

tb.dut.u_reg.u_timing4_t_buf

SCORE	BRANCH
100.00	100.00

tb.dut.u_reg.u_timing1_t_r

SCORE	BRANCH
100.00	100.00

tb.dut.u_reg.u_timing1_t_f

SCORE	BRANCH
100.00	100.00

tb.dut.u_reg.u_timing3_tsu_dat

SCORE	BRANCH
100.00	100.00

tb.dut.u_reg.u_timeout_ctrl_val

SCORE	BRANCH
100.00	100.00

tb.dut.u_reg.u_target_id_address0

SCORE	BRANCH
100.00	100.00

tb.dut.u_reg.u_target_id_mask0

SCORE	BRANCH
100.00	100.00

tb.dut.u_reg.u_target_id_address1

SCORE	BRANCH
100.00	100.00

tb.dut.u_reg.u_target_id_mask1

SCORE	BRANCH
100.00	100.00

tb.dut.u_reg.u_host_timeout_ctrl

SCORE	BRANCH
100.00	100.00

tb.dut.u_reg.u_target_timeout_ctrl_val

SCORE	BRANCH
100.00	100.00

tb.dut.u_reg.u_host_nack_handler_timeout_val

	Line No.	Total	Covered	Percent
Branches		5	5	100.00
TERNARY	64	2	2	100.00
IF	56	3	3	100.00

64           assign ds = wr_en ? wr_data : qs;
                               -1-  
                               ==>  
                               ==>  

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T2,T3

56             if (!rst_ni) begin
               -1-  
57               q <= RESVAL;
                 ==>
58             end else if (wr_en) begin
                        -2-  
59               q <= wr_data;
                 ==>
60             end
               MISSING_ELSE
               ==>

Branches:

-1-	-2-	Status	Tests
1	-	Covered	T1,T2,T3
0	1	Covered	T1,T2,T3
0	0	Covered	T1,T2,T3

---

Branch Coverage for Module : prim_subreg ( parameter DW=8,SwAccess=6,RESVAL=0,Mubi=0 )
Branch Coverage for Module self-instances :

SCORE	BRANCH
85.71	85.71

tb.dut.u_reg.u_target_nack_count

	Line No.	Total	Covered	Percent
Branches		7	6	85.71
TERNARY	64	2	2	100.00
TERNARY	70	2	1	50.00
IF	56	3	3	100.00

64           assign ds = wr_en ? wr_data : qs;
                               -1-  
                               ==>  
                               ==>  

Branches:

-1-	Status	Tests
1	Covered	T68,T69,T70
0	Covered	T1,T2,T3

70             assign qs = de && we ? d : q;
                                    -1-  
                                    ==>  
                                    ==>  

Branches:

-1-	Status	Tests
1	Not Covered
0	Covered	T1,T2,T3

56             if (!rst_ni) begin
               -1-  
57               q <= RESVAL;
                 ==>
58             end else if (wr_en) begin
                        -2-  
59               q <= wr_data;
                 ==>
60             end
               MISSING_ELSE
               ==>

Branches:

-1-	-2-	Status	Tests
1	-	Covered	T1,T2,T3
0	1	Covered	T68,T69,T70
0	0	Covered	T1,T2,T3