Unified Coverage Report :: Group :: tl_agent_pkg::tl_a_chan_cov_cg::SHAPE{(2 << ((valid_source_width - 1) - 1))=128}

Group : tl_agent_pkg::tl_a_chan_cov_cg::SHAPE{(2 << ((valid_source_width - 1) - 1))=128}

SCORE	INSTANCES	WEIGHT	GOAL	AT LEAST	PER INSTANCE	AUTO BIN MAX	PRINT MISSING
100.00	100.00	1	100	1	1	64	64

Source File(s) :
/workspaces/repo/scratch/os_regression_2024_08_31/i2c-sim-vcs/default/sim-vcs/../src/lowrisc_dv_tl_agent_0/tl_agent_cov.sv

1 Instances:

NAME	SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
tl_agent_pkg.uvm_test_top.env.m_tl_agent_i2c_reg_block.cov::m_tl_a_chan_cov_cg	100.00	1	100	1	64	64

---

Group Instance : tl_agent_pkg.uvm_test_top.env.m_tl_agent_i2c_reg_block.cov::m_tl_a_chan_cov_cg

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
100.00	1	100	1	64	64

---

Summary for Group Instance tl_agent_pkg.uvm_test_top.env.m_tl_agent_i2c_reg_block.cov::m_tl_a_chan_cov_cg

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	134	0	134	100.00
Crosses	3	0	3	100.00

Variables for Group Instance tl_agent_pkg.uvm_test_top.env.m_tl_agent_i2c_reg_block.cov::m_tl_a_chan_cov_cg

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
cp_mask	1	0	1	100.00	100	1	1	0
cp_opcode	3	0	3	100.00	100	1	1	0
cp_size	1	0	1	100.00	100	1	1	0
cp_source	129	0	129	100.00	100	1	1	0

Crosses for Group Instance tl_agent_pkg.uvm_test_top.env.m_tl_agent_i2c_reg_block.cov::m_tl_a_chan_cov_cg

CROSS	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	PRINT MISSING	COMMENT
tl_a_chan_cov_cg_cc	3	0	3	100.00	100	1	1	0

Summary for Variable cp_mask

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	1	0	1	100.00

User Defined Bins for cp_mask

Excluded/Illegal bins

NAME	COUNT	STATUS
others	29349755	Excluded

Covered bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

all_enables

8261178

1

T1

14

T2

20

T3

23

---

Summary for Variable cp_opcode

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	3	0	3	100.00

User Defined Bins for cp_opcode

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
values[0x4]	36816278	1			T1	13		T2	67		T3	45
values[0x0]	397116	1			T1	9		T2	34		T3	9
values[0x1]	397539	1			T1	8		T2	30		T3	10

---

Summary for Variable cp_size

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	1	0	1	100.00

User Defined Bins for cp_size

Excluded/Illegal bins

NAME	COUNT	STATUS
others	20570436	Excluded

Covered bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

biggest_size

17040497

1

T1

17

T2

48

T3

34

---

Summary for Variable cp_source

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	129	0	129	100.00

User Defined Bins for cp_source

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
valid_sources[0x00]	151667	1			T2	2		T4	3		T7	33
valid_sources[0x01]	151006	1			T2	1		T4	5		T7	42
valid_sources[0x02]	138059	1			T3	1		T4	2		T7	30
valid_sources[0x03]	141705	1			T4	2		T7	57		T10	120
valid_sources[0x04]	135812	1			T1	1		T4	6		T7	28
valid_sources[0x05]	135530	1			T4	8		T7	45		T10	32
valid_sources[0x06]	158812	1			T2	1		T4	6		T7	50
valid_sources[0x07]	162770	1			T4	2		T7	41		T10	63
valid_sources[0x08]	146768	1			T4	1		T7	45		T10	41
valid_sources[0x09]	158722	1			T2	1		T4	4		T7	38
valid_sources[0x0a]	159247	1			T4	3		T7	27		T10	122
valid_sources[0x0b]	139347	1			T1	1		T2	3		T4	6
valid_sources[0x0c]	142187	1			T2	2		T4	5		T7	38
valid_sources[0x0d]	140693	1			T2	2		T4	6		T7	36
valid_sources[0x0e]	142448	1			T2	1		T4	5		T7	39
valid_sources[0x0f]	144515	1			T4	6		T7	31		T10	122
valid_sources[0x10]	142139	1			T2	2		T4	5		T7	43
valid_sources[0x11]	139427	1			T1	1		T3	1		T4	4
valid_sources[0x12]	144110	1			T2	1		T4	3		T7	32
valid_sources[0x13]	166395	1			T4	3		T7	35		T10	74
valid_sources[0x14]	141328	1			T4	2		T7	62		T10	101
valid_sources[0x15]	140038	1			T4	3		T7	28		T10	21
valid_sources[0x16]	142672	1			T2	2		T4	3		T7	33
valid_sources[0x17]	145595	1			T1	1		T3	5		T4	7
valid_sources[0x18]	150268	1			T4	5		T7	39		T10	77
valid_sources[0x19]	135596	1			T4	3		T7	36		T10	109
valid_sources[0x1a]	140959	1			T4	7		T7	40		T10	84
valid_sources[0x1b]	145662	1			T2	1		T4	1		T7	52
valid_sources[0x1c]	146585	1			T2	2		T7	27		T10	85
valid_sources[0x1d]	156491	1			T2	3		T3	1		T4	6
valid_sources[0x1e]	150802	1			T2	1		T3	1		T4	3
valid_sources[0x1f]	138985	1			T2	1		T4	4		T7	41
valid_sources[0x20]	133742	1			T3	3		T4	7		T7	38
valid_sources[0x21]	138766	1			T2	1		T4	8		T7	37
valid_sources[0x22]	142602	1			T4	9		T7	44		T10	35
valid_sources[0x23]	143437	1			T4	8		T7	27		T10	63
valid_sources[0x24]	136226	1			T4	7		T7	45		T10	84
valid_sources[0x25]	138352	1			T7	30		T10	82		T41	26
valid_sources[0x26]	143713	1			T2	1		T4	5		T6	1989
valid_sources[0x27]	137578	1			T4	4		T7	43		T10	86
valid_sources[0x28]	151276	1			T1	2		T2	2		T4	2
valid_sources[0x29]	154015	1			T4	3		T7	12		T10	68
valid_sources[0x2a]	137103	1			T4	6		T7	33		T10	56
valid_sources[0x2b]	135179	1			T7	29		T10	58		T41	3
valid_sources[0x2c]	145826	1			T2	1		T4	8		T7	26
valid_sources[0x2d]	153627	1			T4	5		T7	43		T10	39
valid_sources[0x2e]	146769	1			T2	2		T3	1		T4	1
valid_sources[0x2f]	139980	1			T2	1		T7	48		T10	56
valid_sources[0x30]	137282	1			T4	8		T6	1999		T7	28
valid_sources[0x31]	152072	1			T4	7		T7	26		T10	102
valid_sources[0x32]	152059	1			T4	4		T7	52		T10	104
valid_sources[0x33]	133943	1			T3	1		T7	42		T10	42
valid_sources[0x34]	155234	1			T4	4		T7	53		T10	45
valid_sources[0x35]	151522	1			T2	1		T4	6		T7	45
valid_sources[0x36]	146096	1			T4	9		T7	59		T10	78
valid_sources[0x37]	140576	1			T4	9		T7	41		T10	90
valid_sources[0x38]	132545	1			T4	4		T7	41		T10	74
valid_sources[0x39]	166338	1			T3	2		T4	3		T7	16
valid_sources[0x3a]	140050	1			T4	2		T7	29		T10	80
valid_sources[0x3b]	170752	1			T4	7		T7	35		T10	47
valid_sources[0x3c]	147883	1			T4	5		T7	36		T10	42
valid_sources[0x3d]	160490	1			T2	2		T4	4		T7	40
valid_sources[0x3e]	154156	1			T4	9		T7	38		T10	83
valid_sources[0x3f]	138969	1			T4	3		T7	51		T10	84
valid_sources[0x40]	144348	1			T3	1		T4	8		T7	35
valid_sources[0x41]	151975	1			T4	4		T7	35		T10	92
valid_sources[0x42]	139219	1			T4	8		T7	40		T10	69
valid_sources[0x43]	146448	1			T2	1		T4	3		T7	36
valid_sources[0x44]	135381	1			T4	3		T7	33		T10	77
valid_sources[0x45]	161853	1			T1	2		T4	2		T7	22
valid_sources[0x46]	149695	1			T4	5		T7	55		T10	72
valid_sources[0x47]	139489	1			T4	4		T7	48		T10	72
valid_sources[0x48]	138421	1			T4	8		T7	45		T10	69
valid_sources[0x49]	138952	1			T4	5		T7	36		T10	26
valid_sources[0x4a]	156400	1			T2	1		T4	6		T7	42
valid_sources[0x4b]	150590	1			T4	5		T7	43		T10	52
valid_sources[0x4c]	138354	1			T2	1		T4	2		T7	45
valid_sources[0x4d]	138038	1			T3	3		T4	4		T7	38
valid_sources[0x4e]	135124	1			T1	2		T2	2		T4	6
valid_sources[0x4f]	144664	1			T4	3		T7	38		T10	99
valid_sources[0x50]	155948	1			T4	2		T7	54		T10	123
valid_sources[0x51]	150277	1			T2	1		T4	9		T7	36
valid_sources[0x52]	145911	1			T2	2		T4	7		T7	28
valid_sources[0x53]	142192	1			T4	5		T7	39		T10	51
valid_sources[0x54]	157574	1			T4	2		T6	2749		T7	49
valid_sources[0x55]	137900	1			T3	2		T4	5		T7	35
valid_sources[0x56]	139447	1			T4	6		T7	37		T10	66
valid_sources[0x57]	147215	1			T2	2		T4	5		T7	50
valid_sources[0x58]	155951	1			T2	1		T4	4		T7	34
valid_sources[0x59]	154163	1			T4	3		T7	55		T10	35
valid_sources[0x5a]	138266	1			T3	2		T4	7		T7	28
valid_sources[0x5b]	151600	1			T3	2		T4	2		T7	40
valid_sources[0x5c]	141905	1			T2	4		T4	2		T7	28
valid_sources[0x5d]	148099	1			T4	10		T6	69		T7	33
valid_sources[0x5e]	136142	1			T4	7		T7	48		T10	84
valid_sources[0x5f]	139307	1			T2	1		T4	2		T7	53
valid_sources[0x60]	142468	1			T4	3		T7	32		T10	94
valid_sources[0x61]	145285	1			T4	6		T7	16		T10	29
valid_sources[0x62]	139255	1			T3	3		T4	2		T7	38
valid_sources[0x63]	147543	1			T4	4		T7	29		T10	37
valid_sources[0x64]	137027	1			T1	2		T3	1		T4	9
valid_sources[0x65]	152583	1			T2	1		T4	4		T7	24
valid_sources[0x66]	134083	1			T7	38		T10	14		T41	11
valid_sources[0x67]	141271	1			T4	10		T7	25		T10	51
valid_sources[0x68]	143700	1			T4	4		T7	24		T10	45
valid_sources[0x69]	146361	1			T4	3		T7	74		T10	59
valid_sources[0x6a]	146770	1			T4	3		T7	35		T10	53
valid_sources[0x6b]	158367	1			T4	5		T7	32		T10	101
valid_sources[0x6c]	154772	1			T2	1		T4	10		T7	33
valid_sources[0x6d]	141958	1			T4	5		T7	19		T10	112
valid_sources[0x6e]	132660	1			T4	1		T7	53		T10	82
valid_sources[0x6f]	143189	1			T4	5		T7	31		T10	86
valid_sources[0x70]	140475	1			T2	1		T4	3		T7	28
valid_sources[0x71]	160931	1			T4	4		T7	26		T10	84
valid_sources[0x72]	142132	1			T7	39		T10	131		T41	1
valid_sources[0x73]	147929	1			T4	9		T7	46		T10	61
valid_sources[0x74]	180864	1			T2	2		T4	1		T7	34
valid_sources[0x75]	141960	1			T4	4		T7	37		T10	148
valid_sources[0x76]	138829	1			T4	3		T7	42		T10	47
valid_sources[0x77]	136760	1			T2	3		T4	3		T7	35
valid_sources[0x78]	150292	1			T4	2		T7	37		T10	14
valid_sources[0x79]	147560	1			T4	6		T7	34		T10	38
valid_sources[0x7a]	146884	1			T2	1		T4	5		T7	39
valid_sources[0x7b]	182008	1			T4	6		T7	26		T10	57
valid_sources[0x7c]	144460	1			T4	2		T7	42		T10	63
valid_sources[0x7d]	136081	1			T4	2		T7	41		T10	100
valid_sources[0x7e]	175140	1			T4	2		T7	25		T10	124
valid_sources[0x7f]	144965	1			T4	4		T7	38		T10	85
valid_sources[0x80]	153667	1			T2	1		T4	8		T7	33

---

Summary for Cross tl_a_chan_cov_cg_cc

Samples crossed: cp_opcode cp_mask cp_size

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	3	0	3	100.00

Automatically Generated Cross Bins for tl_a_chan_cov_cg_cc

Bins

cp_opcode

cp_mask

cp_size

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

values[0x4]

all_enables

biggest_size

7910016

1

T1

5

T3

12

T4

431

values[0x0]

all_enables

biggest_size

208726

1

T1

5

T2

11

T3

6

values[0x1]

all_enables

biggest_size

142436

1

T1

4

T2

9

T3

5