Unified Coverage Report :: Module :: i2c_csr_assert_fpv

Module : i2c_csr_assert_fpv

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
93.75						93.75

Source File(s) :
/workspaces/repo/scratch/os_regression_2024_08_31/i2c-sim-vcs/default/sim-vcs/../src/lowrisc_fpv_i2c_csr_assert_0/i2c_csr_assert_fpv.sv

Module self-instances :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
tb.dut.i2c_csr_assert	93.75						93.75

---

Module Instance : tb.dut.i2c_csr_assert

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
93.75						93.75

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
93.75						93.75

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
98.48	100.00	100.00	93.91			100.00	dut

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Since this is the module's only instance, the coverage report is the same as for the module.

Assert Coverage for Module : i2c_csr_assert_fpv

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	16	16	100.00	15	93.75
Cover properties	0	0		0
Cover sequences	0	0		0
Total	16	16	100.00	15	93.75

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
TlulOOBAddrErr_A	388982286	0	0	0
ctrl_rd_A	388982286	2504	0	0
host_fifo_config_rd_A	388982286	3490	0	0
host_nack_handler_timeout_rd_A	388982286	1525	0	0
host_timeout_ctrl_rd_A	388982286	1527	0	0
intr_enable_rd_A	388982286	4325	0	0
ovrd_rd_A	388982286	2631	0	0
target_fifo_config_rd_A	388982286	1562	0	0
target_id_rd_A	388982286	1865	0	0
target_timeout_ctrl_rd_A	388982286	1564	0	0
timeout_ctrl_rd_A	388982286	1712	0	0
timing0_rd_A	388982286	1702	0	0
timing1_rd_A	388982286	1469	0	0
timing2_rd_A	388982286	1607	0	0
timing3_rd_A	388982286	1582	0	0
timing4_rd_A	388982286	1615	0	0

TlulOOBAddrErr_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	388982286	0	0	0

ctrl_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	388982286	2504	0	0
T96	7757	233	0	0
T97	3669	39	0	0
T98	10807	101	0	0
T99	2901	23	0	0
T100	5791	68	0	0
T101	5807	40	0	0
T102	26349	262	0	0
T103	3325	24	0	0
T104	13953	33	0	0
T105	12906	8	0	0

host_fifo_config_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	388982286	3490	0	0
T44	51764	0	0	0
T56	17629	0	0	0
T63	93790	0	0	0
T70	114030	0	0	0
T75	429106	218	0	0
T78	0	180	0	0
T94	1240	0	0	0
T106	0	149	0	0
T107	0	89	0	0
T108	0	109	0	0
T109	0	126	0	0
T110	0	168	0	0
T111	0	250	0	0
T112	0	124	0	0
T113	0	192	0	0
T114	67572	0	0	0
T115	59941	0	0	0
T116	72485	0	0	0
T117	56118	0	0	0

host_nack_handler_timeout_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	388982286	1525	0	0
T96	7757	45	0	0
T97	3669	11	0	0
T98	10807	135	0	0
T100	5791	72	0	0
T101	5807	41	0	0
T102	26349	230	0	0
T103	3325	17	0	0
T104	13953	47	0	0
T105	12906	21	0	0
T118	1678	5	0	0

host_timeout_ctrl_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	388982286	1527	0	0
T96	7757	28	0	0
T97	3669	17	0	0
T98	10807	122	0	0
T99	2901	31	0	0
T100	5791	67	0	0
T101	5807	51	0	0
T102	26349	220	0	0
T103	3325	12	0	0
T104	13953	37	0	0
T105	12906	16	0	0

intr_enable_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	388982286	4325	0	0
T21	318325	12	0	0
T96	0	332	0	0
T97	0	129	0	0
T98	0	114	0	0
T99	0	4	0	0
T100	0	61	0	0
T119	139156	22	0	0
T120	0	16	0	0
T121	0	5	0	0
T122	0	11	0	0
T123	75090	0	0	0
T124	16354	0	0	0
T125	290956	0	0	0
T126	21543	0	0	0
T127	130677	0	0	0
T128	59652	0	0	0
T129	9561	0	0	0
T130	28043	0	0	0

ovrd_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	388982286	2631	0	0
T12	40909	0	0	0
T19	228900	0	0	0
T20	12258	0	0	0
T34	10462	0	0	0
T75	429106	0	0	0
T131	3021	59	0	0
T132	0	31	0	0
T133	0	60	0	0
T134	0	71	0	0
T135	0	44	0	0
T136	0	37	0	0
T137	0	40	0	0
T138	0	4	0	0
T139	0	36	0	0
T140	0	74	0	0
T141	110171	0	0	0
T142	11058	0	0	0
T143	14749	0	0	0
T144	92225	0	0	0

target_fifo_config_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	388982286	1562	0	0
T96	7757	69	0	0
T97	3669	16	0	0
T98	10807	124	0	0
T99	2901	46	0	0
T100	5791	100	0	0
T101	5807	21	0	0
T102	26349	224	0	0
T103	3325	22	0	0
T104	13953	7	0	0
T105	12906	37	0	0

target_id_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	388982286	1865	0	0
T96	7757	77	0	0
T97	3669	24	0	0
T98	10807	134	0	0
T99	2901	1	0	0
T100	5791	47	0	0
T101	5807	40	0	0
T102	26349	232	0	0
T103	3325	55	0	0
T104	13953	31	0	0
T105	12906	8	0	0

target_timeout_ctrl_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	388982286	1564	0	0
T96	7757	68	0	0
T97	3669	28	0	0
T98	10807	120	0	0
T99	2901	25	0	0
T100	5791	38	0	0
T101	5807	22	0	0
T102	26349	207	0	0
T103	3325	19	0	0
T104	13953	21	0	0
T105	12906	15	0	0

timeout_ctrl_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	388982286	1712	0	0
T96	7757	60	0	0
T97	3669	16	0	0
T98	10807	121	0	0
T99	2901	20	0	0
T100	5791	63	0	0
T101	5807	30	0	0
T102	26349	238	0	0
T103	3325	15	0	0
T104	13953	78	0	0
T105	12906	15	0	0

timing0_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	388982286	1702	0	0
T96	7757	53	0	0
T97	3669	12	0	0
T98	10807	166	0	0
T99	2901	2	0	0
T100	5791	60	0	0
T101	5807	44	0	0
T102	26349	225	0	0
T103	3325	16	0	0
T104	13953	62	0	0
T105	12906	20	0	0

timing1_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	388982286	1469	0	0
T96	7757	84	0	0
T97	3669	22	0	0
T98	10807	111	0	0
T99	2901	16	0	0
T100	5791	38	0	0
T101	5807	58	0	0
T102	26349	223	0	0
T103	3325	24	0	0
T104	13953	19	0	0
T105	12906	27	0	0

timing2_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	388982286	1607	0	0
T96	7757	78	0	0
T97	3669	7	0	0
T98	10807	98	0	0
T99	2901	19	0	0
T100	5791	25	0	0
T101	5807	15	0	0
T102	26349	197	0	0
T103	3325	17	0	0
T104	13953	43	0	0
T105	12906	6	0	0

timing3_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	388982286	1582	0	0
T96	7757	66	0	0
T97	3669	22	0	0
T98	10807	124	0	0
T99	2901	32	0	0
T100	5791	50	0	0
T101	5807	69	0	0
T102	26349	245	0	0
T103	3325	26	0	0
T104	13953	29	0	0
T105	12906	9	0	0

timing4_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	388982286	1615	0	0
T96	7757	52	0	0
T97	3669	34	0	0
T98	10807	125	0	0
T99	2901	46	0	0
T100	5791	54	0	0
T101	5807	41	0	0
T102	26349	213	0	0
T103	3325	13	0	0
T104	13953	56	0	0
T105	12906	26	0	0