Group : i2c_env_pkg::i2c_status_cg
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Group : i2c_env_pkg::i2c_status_cg
SCOREINSTANCESWEIGHTGOALAT LEASTPER INSTANCEAUTO BIN MAXPRINT MISSING
100.00 100.00 1 100 1 1 64 64


Source File(s) :
/workspaces/repo/scratch/os_regression_2024_09_03/i2c-sim-vcs/default/sim-vcs/../src/lowrisc_dv_i2c_env_0.1/i2c_env_cov.sv

1 Instances:
NAMESCOREWEIGHTGOALAT LEASTAUTO BIN MAXPRINT MISSING
i2c_env_pkg.status_cg 100.00 1 100 1 64 64




Group Instance : i2c_env_pkg.status_cg
SCOREWEIGHTGOALAT LEASTAUTO BIN MAXPRINT MISSING
100.00 1 100 1 64 64




Summary for Group Instance i2c_env_pkg.status_cg

CATEGORYEXPECTEDUNCOVEREDCOVEREDPERCENT
Variables 20 0 20 100.00


Variables for Group Instance i2c_env_pkg.status_cg
VARIABLE   EXPECTED   UNCOVERED   COVERED   PERCENT   GOAL   WEIGHT   AT LEAST   AUTO BIN MAX   COMMENT   
cp_acqempty 2 0 2 100.00 100 1 1 2
cp_acqfull 2 0 2 100.00 100 1 1 2
cp_fmtempty 2 0 2 100.00 100 1 1 2
cp_fmtfull 2 0 2 100.00 100 1 1 2
cp_hostidle 2 0 2 100.00 100 1 1 2
cp_rxempty 2 0 2 100.00 100 1 1 2
cp_rxfull 2 0 2 100.00 100 1 1 2
cp_targetidle 2 0 2 100.00 100 1 1 2
cp_txempty 2 0 2 100.00 100 1 1 2
cp_txfull 2 0 2 100.00 100 1 1 2


Summary for Variable cp_acqempty

CATEGORYEXPECTEDUNCOVEREDCOVEREDPERCENT
Automatically Generated Bins 2 0 2 100.00


Automatically Generated Bins for cp_acqempty

Bins
NAME   COUNT   AT LEAST   STATUS   TEST   COUNT   TEST   COUNT   TEST   COUNT   
auto[0] 1232487 1 T7 216 T43 5 T46 1
auto[1] 30713305 1 T2 60 T3 1047 T4 1429



Summary for Variable cp_acqfull

CATEGORYEXPECTEDUNCOVEREDCOVEREDPERCENT
Automatically Generated Bins 2 0 2 100.00


Automatically Generated Bins for cp_acqfull

Bins
NAME   COUNT   AT LEAST   STATUS   TEST   COUNT   TEST   COUNT   TEST   COUNT   
auto[0] 31922799 1 T2 60 T3 1047 T4 1429
auto[1] 22993 1 T68 40 T298 19 T50 358



Summary for Variable cp_fmtempty

CATEGORYEXPECTEDUNCOVEREDCOVEREDPERCENT
Automatically Generated Bins 2 0 2 100.00


Automatically Generated Bins for cp_fmtempty

Bins
NAME   COUNT   AT LEAST   STATUS   TEST   COUNT   TEST   COUNT   TEST   COUNT   
auto[0] 29881329 1 T2 42 T3 1034 T4 1426
auto[1] 2064463 1 T2 18 T3 13 T4 3



Summary for Variable cp_fmtfull

CATEGORYEXPECTEDUNCOVEREDCOVEREDPERCENT
Automatically Generated Bins 2 0 2 100.00


Automatically Generated Bins for cp_fmtfull

Bins
NAME   COUNT   AT LEAST   STATUS   TEST   COUNT   TEST   COUNT   TEST   COUNT   
auto[0] 26988937 1 T2 60 T3 1047 T4 1429
auto[1] 4956855 1 T154 2430 T165 832 T16 40428



Summary for Variable cp_hostidle

CATEGORYEXPECTEDUNCOVEREDCOVEREDPERCENT
Automatically Generated Bins 2 0 2 100.00


Automatically Generated Bins for cp_hostidle

Bins
NAME   COUNT   AT LEAST   STATUS   TEST   COUNT   TEST   COUNT   TEST   COUNT   
auto[0] 29879781 1 T2 59 T3 1034 T4 1426
auto[1] 2066011 1 T2 1 T3 13 T4 3



Summary for Variable cp_rxempty

CATEGORYEXPECTEDUNCOVEREDCOVEREDPERCENT
Automatically Generated Bins 2 0 2 100.00


Automatically Generated Bins for cp_rxempty

Bins
NAME   COUNT   AT LEAST   STATUS   TEST   COUNT   TEST   COUNT   TEST   COUNT   
auto[0] 5252714 1 T3 10 T4 1376 T9 17878
auto[1] 26693078 1 T2 60 T3 1037 T4 53



Summary for Variable cp_rxfull

CATEGORYEXPECTEDUNCOVEREDCOVEREDPERCENT
Automatically Generated Bins 2 0 2 100.00


Automatically Generated Bins for cp_rxfull

Bins
NAME   COUNT   AT LEAST   STATUS   TEST   COUNT   TEST   COUNT   TEST   COUNT   
auto[0] 31904886 1 T2 60 T3 1047 T4 1428
auto[1] 40906 1 T4 1 T9 280 T102 312



Summary for Variable cp_targetidle

CATEGORYEXPECTEDUNCOVEREDCOVEREDPERCENT
Automatically Generated Bins 2 0 2 100.00


Automatically Generated Bins for cp_targetidle

Bins
NAME   COUNT   AT LEAST   STATUS   TEST   COUNT   TEST   COUNT   TEST   COUNT   
auto[0] 1741829 1 T7 230 T8 1 T43 5
auto[1] 30203963 1 T2 60 T3 1047 T4 1429



Summary for Variable cp_txempty

CATEGORYEXPECTEDUNCOVEREDCOVEREDPERCENT
Automatically Generated Bins 2 0 2 100.00


Automatically Generated Bins for cp_txempty

Bins
NAME   COUNT   AT LEAST   STATUS   TEST   COUNT   TEST   COUNT   TEST   COUNT   
auto[0] 1610331 1 T7 131 T8 1 T42 62
auto[1] 30335461 1 T2 60 T3 1047 T4 1429



Summary for Variable cp_txfull

CATEGORYEXPECTEDUNCOVEREDCOVEREDPERCENT
Automatically Generated Bins 2 0 2 100.00


Automatically Generated Bins for cp_txfull

Bins
NAME   COUNT   AT LEAST   STATUS   TEST   COUNT   TEST   COUNT   TEST   COUNT   
auto[0] 31945783 1 T2 60 T3 1047 T4 1429
auto[1] 9 1 T104 1 T299 4 T300 1