Unified Coverage Report :: Group :: tl_agent_pkg::tl_a_chan_cov_cg::SHAPE{(2 << ((valid_source_width - 1) - 1))=128}

Group : tl_agent_pkg::tl_a_chan_cov_cg::SHAPE{(2 << ((valid_source_width - 1) - 1))=128}

SCORE	INSTANCES	WEIGHT	GOAL	AT LEAST	PER INSTANCE	AUTO BIN MAX	PRINT MISSING
100.00	100.00	1	100	1	1	64	64

Source File(s) :
/workspaces/repo/scratch/os_regression_2024_09_03/i2c-sim-vcs/default/sim-vcs/../src/lowrisc_dv_tl_agent_0/tl_agent_cov.sv

1 Instances:

NAME	SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
tl_agent_pkg.uvm_test_top.env.m_tl_agent_i2c_reg_block.cov::m_tl_a_chan_cov_cg	100.00	1	100	1	64	64

---

Group Instance : tl_agent_pkg.uvm_test_top.env.m_tl_agent_i2c_reg_block.cov::m_tl_a_chan_cov_cg

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
100.00	1	100	1	64	64

---

Summary for Group Instance tl_agent_pkg.uvm_test_top.env.m_tl_agent_i2c_reg_block.cov::m_tl_a_chan_cov_cg

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	134	0	134	100.00
Crosses	3	0	3	100.00

Variables for Group Instance tl_agent_pkg.uvm_test_top.env.m_tl_agent_i2c_reg_block.cov::m_tl_a_chan_cov_cg

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
cp_mask	1	0	1	100.00	100	1	1	0
cp_opcode	3	0	3	100.00	100	1	1	0
cp_size	1	0	1	100.00	100	1	1	0
cp_source	129	0	129	100.00	100	1	1	0

Crosses for Group Instance tl_agent_pkg.uvm_test_top.env.m_tl_agent_i2c_reg_block.cov::m_tl_a_chan_cov_cg

CROSS	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	PRINT MISSING	COMMENT
tl_a_chan_cov_cg_cc	3	0	3	100.00	100	1	1	0

Summary for Variable cp_mask

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	1	0	1	100.00

User Defined Bins for cp_mask

Excluded/Illegal bins

NAME	COUNT	STATUS
others	28017547	Excluded

Covered bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

all_enables

7596497

1

T1

11

T2

30

T3

287

---

Summary for Variable cp_opcode

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	3	0	3	100.00

User Defined Bins for cp_opcode

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
values[0x4]	34756011	1			T1	15		T2	71		T3	1077
values[0x0]	427764	1			T1	8		T2	28		T3	30
values[0x1]	430269	1			T1	8		T2	36		T3	20

---

Summary for Variable cp_size

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	1	0	1	100.00

User Defined Bins for cp_size

Excluded/Illegal bins

NAME	COUNT	STATUS
others	19578328	Excluded

Covered bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

biggest_size

16035716

1

T1

12

T2

63

T3

529

---

Summary for Variable cp_source

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	129	0	129	100.00

User Defined Bins for cp_source

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
valid_sources[0x00]	183790	1			T3	10		T5	7		T6	1
valid_sources[0x01]	137220	1			T3	8		T5	16		T7	6
valid_sources[0x02]	127685	1			T3	5		T5	20		T7	19
valid_sources[0x03]	131314	1			T5	17		T9	74		T34	1
valid_sources[0x04]	128524	1			T3	4		T5	15		T6	3
valid_sources[0x05]	145848	1			T3	9		T5	14		T6	3
valid_sources[0x06]	174234	1			T3	5		T5	5		T7	5
valid_sources[0x07]	129343	1			T3	5		T5	9		T6	2
valid_sources[0x08]	132800	1			T3	7		T5	11		T7	5
valid_sources[0x09]	143780	1			T5	12		T7	8		T9	60
valid_sources[0x0a]	131213	1			T3	14		T5	18		T9	75
valid_sources[0x0b]	144187	1			T3	6		T5	11		T7	5
valid_sources[0x0c]	132244	1			T3	17		T5	10		T7	7
valid_sources[0x0d]	143638	1			T3	3		T5	14		T7	4
valid_sources[0x0e]	127237	1			T3	5		T5	14		T7	10
valid_sources[0x0f]	133818	1			T5	29		T6	2		T7	6
valid_sources[0x10]	138219	1			T5	17		T7	3		T9	106
valid_sources[0x11]	131357	1			T5	39		T7	8		T9	72
valid_sources[0x12]	127155	1			T3	9		T5	23		T7	2
valid_sources[0x13]	134618	1			T3	2		T5	18		T6	1
valid_sources[0x14]	127771	1			T3	3		T5	12		T9	75
valid_sources[0x15]	133496	1			T3	7		T5	29		T9	76
valid_sources[0x16]	127249	1			T5	11		T9	66		T75	1
valid_sources[0x17]	125319	1			T5	4		T7	5		T8	1
valid_sources[0x18]	135868	1			T5	20		T6	1		T7	1
valid_sources[0x19]	131232	1			T3	12		T5	1		T7	10
valid_sources[0x1a]	132830	1			T5	5		T9	88		T17	1
valid_sources[0x1b]	123697	1			T5	9		T7	3		T9	90
valid_sources[0x1c]	149939	1			T3	1		T5	11		T7	3
valid_sources[0x1d]	142927	1			T3	7		T5	15		T9	81
valid_sources[0x1e]	133477	1			T5	3		T7	7		T9	90
valid_sources[0x1f]	132207	1			T3	1		T5	14		T7	5
valid_sources[0x20]	125934	1			T3	3		T5	12		T6	1
valid_sources[0x21]	151297	1			T3	28		T5	8		T6	1
valid_sources[0x22]	139251	1			T5	5		T6	5		T8	4
valid_sources[0x23]	153641	1			T5	13		T7	13		T9	90
valid_sources[0x24]	136443	1			T5	10		T7	7		T9	66
valid_sources[0x25]	127711	1			T3	1		T5	17		T7	11
valid_sources[0x26]	144719	1			T5	5		T7	2		T9	32
valid_sources[0x27]	134573	1			T3	5		T5	5		T7	1
valid_sources[0x28]	129820	1			T5	16		T6	2		T7	2
valid_sources[0x29]	136750	1			T3	15		T5	7		T6	2
valid_sources[0x2a]	138280	1			T5	4		T7	10		T9	54
valid_sources[0x2b]	130401	1			T5	18		T7	4		T8	1
valid_sources[0x2c]	121331	1			T5	11		T6	2		T7	4
valid_sources[0x2d]	131907	1			T5	14		T7	1		T9	72
valid_sources[0x2e]	125985	1			T5	24		T9	59		T153	5
valid_sources[0x2f]	166641	1			T3	2		T5	11		T6	2
valid_sources[0x30]	156228	1			T3	2		T5	22		T6	2
valid_sources[0x31]	142452	1			T5	20		T9	100		T75	1
valid_sources[0x32]	167749	1			T3	19		T5	18		T9	85
valid_sources[0x33]	125463	1			T3	20		T5	6		T6	1
valid_sources[0x34]	129172	1			T3	4		T5	5		T6	1
valid_sources[0x35]	120280	1			T3	6		T5	12		T7	17
valid_sources[0x36]	131383	1			T3	1		T5	13		T6	1
valid_sources[0x37]	128480	1			T3	9		T5	38		T6	1
valid_sources[0x38]	145767	1			T5	9		T6	2		T7	22
valid_sources[0x39]	157106	1			T3	10		T5	12		T6	1
valid_sources[0x3a]	139908	1			T5	8		T6	3		T7	1
valid_sources[0x3b]	139762	1			T3	8		T5	13		T9	65
valid_sources[0x3c]	144942	1			T3	9		T5	18		T7	4
valid_sources[0x3d]	130915	1			T5	11		T6	3		T9	90
valid_sources[0x3e]	145586	1			T3	10		T5	9		T6	1
valid_sources[0x3f]	150818	1			T5	4		T6	6		T7	3
valid_sources[0x40]	155498	1			T3	3		T5	7		T6	2
valid_sources[0x41]	135001	1			T3	1		T5	12		T7	2
valid_sources[0x42]	128058	1			T3	5		T5	13		T7	6
valid_sources[0x43]	141214	1			T5	7		T6	7		T7	5
valid_sources[0x44]	131875	1			T3	4		T5	10		T6	3
valid_sources[0x45]	141239	1			T5	6		T6	3		T7	3
valid_sources[0x46]	133120	1			T5	34		T7	7		T9	56
valid_sources[0x47]	126972	1			T5	10		T6	2		T7	1
valid_sources[0x48]	140080	1			T3	25		T5	11		T7	7
valid_sources[0x49]	140075	1			T3	11		T5	14		T8	3
valid_sources[0x4a]	129308	1			T5	12		T6	3		T9	71
valid_sources[0x4b]	138539	1			T5	16		T7	1		T9	63
valid_sources[0x4c]	123707	1			T3	14		T5	5		T6	3
valid_sources[0x4d]	127738	1			T3	3		T5	12		T7	2
valid_sources[0x4e]	132895	1			T3	21		T5	12		T9	80
valid_sources[0x4f]	122475	1			T3	3		T5	12		T9	78
valid_sources[0x50]	138684	1			T5	10		T6	5		T7	6
valid_sources[0x51]	133431	1			T3	25		T5	17		T6	1
valid_sources[0x52]	158239	1			T5	8		T6	2		T7	3
valid_sources[0x53]	122113	1			T3	6		T5	10		T7	1
valid_sources[0x54]	152515	1			T5	9		T6	2		T7	3
valid_sources[0x55]	139139	1			T3	14		T5	5		T6	1
valid_sources[0x56]	136597	1			T5	18		T7	1		T9	58
valid_sources[0x57]	137112	1			T3	4		T5	7		T7	7
valid_sources[0x58]	137674	1			T4	1448		T5	9		T6	1
valid_sources[0x59]	130454	1			T5	15		T6	3		T7	4
valid_sources[0x5a]	155645	1			T3	23		T5	14		T7	5
valid_sources[0x5b]	135135	1			T3	13		T5	12		T6	7
valid_sources[0x5c]	156560	1			T3	3		T5	16		T9	58
valid_sources[0x5d]	134565	1			T3	2		T5	14		T7	6
valid_sources[0x5e]	129820	1			T5	23		T6	2		T7	7
valid_sources[0x5f]	125228	1			T3	9		T5	6		T6	1
valid_sources[0x60]	138687	1			T5	8		T9	109		T46	7
valid_sources[0x61]	126937	1			T5	7		T8	1		T9	65
valid_sources[0x62]	144171	1			T5	10		T6	2		T7	12
valid_sources[0x63]	133172	1			T5	25		T6	2		T7	2
valid_sources[0x64]	134063	1			T3	2		T5	27		T7	5
valid_sources[0x65]	121677	1			T3	1		T5	15		T6	1
valid_sources[0x66]	138247	1			T5	19		T6	1		T7	2
valid_sources[0x67]	159664	1			T3	1		T5	13		T6	2
valid_sources[0x68]	125225	1			T3	3		T5	18		T9	72
valid_sources[0x69]	139636	1			T5	12		T6	8		T9	78
valid_sources[0x6a]	132940	1			T5	11		T6	1		T7	1
valid_sources[0x6b]	140972	1			T5	4		T9	90		T44	3
valid_sources[0x6c]	132652	1			T3	7		T5	8		T7	3
valid_sources[0x6d]	129434	1			T3	5		T5	14		T8	2
valid_sources[0x6e]	147356	1			T5	9		T6	7		T7	8
valid_sources[0x6f]	135571	1			T5	14		T6	7		T7	1
valid_sources[0x70]	128136	1			T5	9		T6	2		T7	3
valid_sources[0x71]	156281	1			T3	10		T5	5		T7	1
valid_sources[0x72]	128847	1			T3	24		T5	8		T7	6
valid_sources[0x73]	132538	1			T5	10		T6	2		T7	3
valid_sources[0x74]	206882	1			T5	15		T6	1		T7	3
valid_sources[0x75]	128845	1			T3	5		T5	8		T7	8
valid_sources[0x76]	123042	1			T3	1		T5	14		T7	1
valid_sources[0x77]	129833	1			T3	5		T5	14		T9	56
valid_sources[0x78]	141346	1			T5	10		T7	7		T9	69
valid_sources[0x79]	140485	1			T4	2		T5	9		T6	3
valid_sources[0x7a]	130965	1			T5	19		T6	2		T9	57
valid_sources[0x7b]	146212	1			T3	1		T5	18		T6	1
valid_sources[0x7c]	129214	1			T3	1		T5	15		T7	3
valid_sources[0x7d]	151863	1			T3	11		T5	9		T7	1
valid_sources[0x7e]	137492	1			T5	11		T7	6		T9	81
valid_sources[0x7f]	153643	1			T3	3		T5	23		T6	1
valid_sources[0x80]	137726	1			T5	4		T7	3		T9	84

---

Summary for Cross tl_a_chan_cov_cg_cc

Samples crossed: cp_opcode cp_mask cp_size

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	3	0	3	100.00

Automatically Generated Cross Bins for tl_a_chan_cov_cg_cc

Bins

cp_opcode

cp_mask

cp_size

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

values[0x4]

all_enables

biggest_size

7220662

1

T1

7

T2

2

T3

264

values[0x0]

all_enables

biggest_size

223568

1

T1

3

T2

19

T3

15

values[0x1]

all_enables

biggest_size

152267

1

T1

1

T2

9

T3

8