Unified Coverage Report :: Module :: i2c_reg_top

Module : i2c_reg_top

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
99.71	100.00	98.85			100.00	100.00

Source File(s) :
/workspaces/repo/scratch/os_regression_2024_09_03/i2c-sim-vcs/default/sim-vcs/../src/lowrisc_ip_i2c_0.1/rtl/i2c_reg_top.sv

Module self-instances :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
tb.dut.u_reg	99.71	100.00	98.85			100.00	100.00

---

Module Instance : tb.dut.u_reg

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
99.71	100.00	98.85			100.00	100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
98.67	98.59	97.16	100.00		97.58	100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
98.48	100.00	100.00	93.91			100.00	dut

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
u_acq_fifo_next_data	66.67	66.67
u_acqdata_abyte	100.00	100.00
u_acqdata_signal	100.00	100.00
u_alert_test	100.00	100.00
u_chk	100.00	100.00		100.00			100.00
u_controller_events_arbitration_lost	97.22	100.00	91.67			100.00
u_controller_events_bus_timeout	88.89	100.00	66.67			100.00
u_controller_events_nack	100.00	100.00	100.00			100.00
u_controller_events_unhandled_nack_timeout	88.89	100.00	66.67			100.00
u_ctrl_ack_ctrl_en	100.00	100.00	100.00			100.00
u_ctrl_enablehost	100.00	100.00	100.00			100.00
u_ctrl_enabletarget	100.00	100.00	100.00			100.00
u_ctrl_llpbk	100.00	100.00	100.00			100.00
u_ctrl_multi_controller_monitor_en	100.00	100.00	100.00			100.00
u_ctrl_nack_addr_after_timeout	100.00	100.00	100.00			100.00
u_ctrl_tx_stretch_ctrl_en	100.00	100.00	100.00			100.00
u_fdata0_qe	100.00	100.00				100.00
u_fdata_fbyte	100.00	100.00	100.00			100.00
u_fdata_nakok	100.00	100.00	100.00			100.00
u_fdata_rcont	100.00	100.00	100.00			100.00
u_fdata_readb	100.00	100.00	100.00			100.00
u_fdata_start	100.00	100.00	100.00			100.00
u_fdata_stop	100.00	100.00	100.00			100.00
u_fifo_ctrl0_qe	100.00	100.00				100.00
u_fifo_ctrl_acqrst	100.00	100.00	100.00			100.00
u_fifo_ctrl_fmtrst	100.00	100.00	100.00			100.00
u_fifo_ctrl_rxrst	100.00	100.00	100.00			100.00
u_fifo_ctrl_txrst	100.00	100.00	100.00			100.00
u_host_fifo_config0_qe	100.00	100.00				100.00
u_host_fifo_config_fmt_thresh	100.00	100.00	100.00			100.00
u_host_fifo_config_rx_thresh	100.00	100.00	100.00			100.00
u_host_fifo_status_fmtlvl	100.00	100.00
u_host_fifo_status_rxlvl	100.00	100.00
u_host_nack_handler_timeout_en	100.00	100.00	100.00			100.00
u_host_nack_handler_timeout_val	100.00	100.00	100.00			100.00
u_host_timeout_ctrl	100.00	100.00	100.00			100.00
u_intr_enable_acq_stretch	100.00	100.00	100.00			100.00
u_intr_enable_acq_threshold	100.00	100.00	100.00			100.00
u_intr_enable_cmd_complete	100.00	100.00	100.00			100.00
u_intr_enable_controller_halt	100.00	100.00	100.00			100.00
u_intr_enable_fmt_threshold	100.00	100.00	100.00			100.00
u_intr_enable_host_timeout	100.00	100.00	100.00			100.00
u_intr_enable_rx_overflow	100.00	100.00	100.00			100.00
u_intr_enable_rx_threshold	100.00	100.00	100.00			100.00
u_intr_enable_scl_interference	100.00	100.00	100.00			100.00
u_intr_enable_sda_interference	100.00	100.00	100.00			100.00
u_intr_enable_sda_unstable	100.00	100.00	100.00			100.00
u_intr_enable_stretch_timeout	100.00	100.00	100.00			100.00
u_intr_enable_tx_stretch	100.00	100.00	100.00			100.00
u_intr_enable_tx_threshold	100.00	100.00	100.00			100.00
u_intr_enable_unexp_stop	100.00	100.00	100.00			100.00
u_intr_state_acq_stretch	62.59	77.78	50.00			60.00
u_intr_state_acq_threshold	62.59	77.78	50.00			60.00
u_intr_state_cmd_complete	100.00	100.00	100.00			100.00
u_intr_state_controller_halt	62.59	77.78	50.00			60.00
u_intr_state_fmt_threshold	62.59	77.78	50.00			60.00
u_intr_state_host_timeout	100.00	100.00	100.00			100.00
u_intr_state_rx_overflow	100.00	100.00	100.00			100.00
u_intr_state_rx_threshold	62.59	77.78	50.00			60.00
u_intr_state_scl_interference	100.00	100.00	100.00			100.00
u_intr_state_sda_interference	100.00	100.00	100.00			100.00
u_intr_state_sda_unstable	100.00	100.00	100.00			100.00
u_intr_state_stretch_timeout	100.00	100.00	100.00			100.00
u_intr_state_tx_stretch	62.59	77.78	50.00			60.00
u_intr_state_tx_threshold	62.59	77.78	50.00			60.00
u_intr_state_unexp_stop	100.00	100.00	100.00			100.00
u_intr_test_acq_stretch	100.00	100.00
u_intr_test_acq_threshold	100.00	100.00
u_intr_test_cmd_complete	100.00	100.00
u_intr_test_controller_halt	100.00	100.00
u_intr_test_fmt_threshold	100.00	100.00
u_intr_test_host_timeout	100.00	100.00
u_intr_test_rx_overflow	100.00	100.00
u_intr_test_rx_threshold	100.00	100.00
u_intr_test_scl_interference	100.00	100.00
u_intr_test_sda_interference	100.00	100.00
u_intr_test_sda_unstable	100.00	100.00
u_intr_test_stretch_timeout	100.00	100.00
u_intr_test_tx_stretch	100.00	100.00
u_intr_test_tx_threshold	100.00	100.00
u_intr_test_unexp_stop	100.00	100.00
u_ovrd_sclval	100.00	100.00	100.00			100.00
u_ovrd_sdaval	100.00	100.00	100.00			100.00
u_ovrd_txovrden	100.00	100.00	100.00			100.00
u_prim_reg_we_check	100.00	100.00		100.00
u_rdata	100.00	100.00
u_reg_if	98.67	97.14	97.53			100.00	100.00
u_rsp_intg_gen	100.00	100.00					100.00
u_status_ack_ctrl_stretch	100.00	100.00
u_status_acqempty	100.00	100.00
u_status_acqfull	100.00	100.00
u_status_fmtempty	100.00	100.00
u_status_fmtfull	100.00	100.00
u_status_hostidle	100.00	100.00
u_status_rxempty	100.00	100.00
u_status_rxfull	100.00	100.00
u_status_targetidle	100.00	100.00
u_status_txempty	100.00	100.00
u_status_txfull	100.00	100.00
u_target_ack_ctrl_nack	100.00	100.00
u_target_ack_ctrl_nbytes	100.00	100.00
u_target_events_arbitration_lost	88.89	100.00	66.67			100.00
u_target_events_bus_timeout	88.89	100.00	66.67			100.00
u_target_events_tx_pending	100.00	100.00	100.00			100.00
u_target_fifo_config0_qe	100.00	100.00				100.00
u_target_fifo_config_acq_thresh	100.00	100.00	100.00			100.00
u_target_fifo_config_tx_thresh	100.00	100.00	100.00			100.00
u_target_fifo_status_acqlvl	100.00	100.00
u_target_fifo_status_txlvl	100.00	100.00
u_target_id_address0	100.00	100.00	100.00			100.00
u_target_id_address1	100.00	100.00	100.00			100.00
u_target_id_mask0	100.00	100.00	100.00			100.00
u_target_id_mask1	100.00	100.00	100.00			100.00
u_target_nack_count	88.57	100.00	80.00			85.71
u_target_timeout_ctrl_en	100.00	100.00	100.00			100.00
u_target_timeout_ctrl_val	100.00	100.00	100.00			100.00
u_timeout_ctrl_en	100.00	100.00	100.00			100.00
u_timeout_ctrl_mode	100.00	100.00	100.00			100.00
u_timeout_ctrl_val	100.00	100.00	100.00			100.00
u_timing0_thigh	100.00	100.00	100.00			100.00
u_timing0_tlow	100.00	100.00	100.00			100.00
u_timing1_t_f	100.00	100.00	100.00			100.00
u_timing1_t_r	100.00	100.00	100.00			100.00
u_timing2_thd_sta	100.00	100.00	100.00			100.00
u_timing2_tsu_sta	100.00	100.00	100.00			100.00
u_timing3_thd_dat	100.00	100.00	100.00			100.00
u_timing3_tsu_dat	100.00	100.00	100.00			100.00
u_timing4_t_buf	100.00	100.00	100.00			100.00
u_timing4_tsu_sto	100.00	100.00	100.00			100.00
u_txdata	100.00	100.00	100.00			100.00
u_txdata0_qe	100.00	100.00				100.00
u_val_scl_rx	66.67	66.67
u_val_sda_rx	66.67	66.67

---

Since this is the module's only instance, the coverage report is the same as for the module.

Line Coverage for Module : i2c_reg_top

	Line No.	Total	Covered	Percent
TOTAL		369	369	100.00
ALWAYS	68	4	4	100.00
CONT_ASSIGN	77	1	1	100.00
CONT_ASSIGN	89	1	1	100.00
CONT_ASSIGN	90	1	1	100.00
CONT_ASSIGN	118	1	1	100.00
CONT_ASSIGN	119	1	1	100.00
CONT_ASSIGN	1168	1	1	100.00
CONT_ASSIGN	1183	1	1	100.00
CONT_ASSIGN	1199	1	1	100.00
CONT_ASSIGN	1215	1	1	100.00
CONT_ASSIGN	1231	1	1	100.00
CONT_ASSIGN	1247	1	1	100.00
CONT_ASSIGN	1263	1	1	100.00
CONT_ASSIGN	1279	1	1	100.00
CONT_ASSIGN	1295	1	1	100.00
CONT_ASSIGN	1311	1	1	100.00
CONT_ASSIGN	1327	1	1	100.00
CONT_ASSIGN	1343	1	1	100.00
CONT_ASSIGN	1359	1	1	100.00
CONT_ASSIGN	1375	1	1	100.00
CONT_ASSIGN	1391	1	1	100.00
CONT_ASSIGN	1407	1	1	100.00
CONT_ASSIGN	1413	1	1	100.00
CONT_ASSIGN	1427	1	1	100.00
CONT_ASSIGN	1842	1	1	100.00
CONT_ASSIGN	1870	1	1	100.00
CONT_ASSIGN	1898	1	1	100.00
CONT_ASSIGN	1926	1	1	100.00
CONT_ASSIGN	1954	1	1	100.00
CONT_ASSIGN	1982	1	1	100.00
CONT_ASSIGN	2023	1	1	100.00
CONT_ASSIGN	2051	1	1	100.00
CONT_ASSIGN	2079	1	1	100.00
CONT_ASSIGN	2107	1	1	100.00
CONT_ASSIGN	2148	1	1	100.00
CONT_ASSIGN	2176	1	1	100.00
CONT_ASSIGN	2217	1	1	100.00
CONT_ASSIGN	2245	1	1	100.00
CONT_ASSIGN	2969	1	1	100.00
CONT_ASSIGN	3087	1	1	100.00
CONT_ASSIGN	3102	1	1	100.00
CONT_ASSIGN	3118	1	1	100.00
ALWAYS	3389	33	33	100.00
CONT_ASSIGN	3424	1	1	100.00
ALWAYS	3428	1	1	100.00
CONT_ASSIGN	3464	1	1	100.00
CONT_ASSIGN	3466	1	1	100.00
CONT_ASSIGN	3468	1	1	100.00
CONT_ASSIGN	3470	1	1	100.00
CONT_ASSIGN	3472	1	1	100.00
CONT_ASSIGN	3474	1	1	100.00
CONT_ASSIGN	3476	1	1	100.00
CONT_ASSIGN	3478	1	1	100.00
CONT_ASSIGN	3480	1	1	100.00
CONT_ASSIGN	3481	1	1	100.00
CONT_ASSIGN	3483	1	1	100.00
CONT_ASSIGN	3485	1	1	100.00
CONT_ASSIGN	3487	1	1	100.00
CONT_ASSIGN	3489	1	1	100.00
CONT_ASSIGN	3491	1	1	100.00
CONT_ASSIGN	3493	1	1	100.00
CONT_ASSIGN	3495	1	1	100.00
CONT_ASSIGN	3497	1	1	100.00
CONT_ASSIGN	3499	1	1	100.00
CONT_ASSIGN	3501	1	1	100.00
CONT_ASSIGN	3503	1	1	100.00
CONT_ASSIGN	3505	1	1	100.00
CONT_ASSIGN	3507	1	1	100.00
CONT_ASSIGN	3509	1	1	100.00
CONT_ASSIGN	3511	1	1	100.00
CONT_ASSIGN	3512	1	1	100.00
CONT_ASSIGN	3514	1	1	100.00
CONT_ASSIGN	3516	1	1	100.00
CONT_ASSIGN	3518	1	1	100.00
CONT_ASSIGN	3520	1	1	100.00
CONT_ASSIGN	3522	1	1	100.00
CONT_ASSIGN	3524	1	1	100.00
CONT_ASSIGN	3526	1	1	100.00
CONT_ASSIGN	3528	1	1	100.00
CONT_ASSIGN	3530	1	1	100.00
CONT_ASSIGN	3532	1	1	100.00
CONT_ASSIGN	3534	1	1	100.00
CONT_ASSIGN	3536	1	1	100.00
CONT_ASSIGN	3538	1	1	100.00
CONT_ASSIGN	3540	1	1	100.00
CONT_ASSIGN	3542	1	1	100.00
CONT_ASSIGN	3543	1	1	100.00
CONT_ASSIGN	3545	1	1	100.00
CONT_ASSIGN	3546	1	1	100.00
CONT_ASSIGN	3548	1	1	100.00
CONT_ASSIGN	3550	1	1	100.00
CONT_ASSIGN	3552	1	1	100.00
CONT_ASSIGN	3554	1	1	100.00
CONT_ASSIGN	3556	1	1	100.00
CONT_ASSIGN	3558	1	1	100.00
CONT_ASSIGN	3560	1	1	100.00
CONT_ASSIGN	3561	1	1	100.00
CONT_ASSIGN	3562	1	1	100.00
CONT_ASSIGN	3563	1	1	100.00
CONT_ASSIGN	3565	1	1	100.00
CONT_ASSIGN	3567	1	1	100.00
CONT_ASSIGN	3569	1	1	100.00
CONT_ASSIGN	3571	1	1	100.00
CONT_ASSIGN	3573	1	1	100.00
CONT_ASSIGN	3575	1	1	100.00
CONT_ASSIGN	3576	1	1	100.00
CONT_ASSIGN	3578	1	1	100.00
CONT_ASSIGN	3580	1	1	100.00
CONT_ASSIGN	3582	1	1	100.00
CONT_ASSIGN	3584	1	1	100.00
CONT_ASSIGN	3585	1	1	100.00
CONT_ASSIGN	3587	1	1	100.00
CONT_ASSIGN	3589	1	1	100.00
CONT_ASSIGN	3590	1	1	100.00
CONT_ASSIGN	3592	1	1	100.00
CONT_ASSIGN	3594	1	1	100.00
CONT_ASSIGN	3595	1	1	100.00
CONT_ASSIGN	3596	1	1	100.00
CONT_ASSIGN	3597	1	1	100.00
CONT_ASSIGN	3599	1	1	100.00
CONT_ASSIGN	3601	1	1	100.00
CONT_ASSIGN	3603	1	1	100.00
CONT_ASSIGN	3604	1	1	100.00
CONT_ASSIGN	3605	1	1	100.00
CONT_ASSIGN	3607	1	1	100.00
CONT_ASSIGN	3609	1	1	100.00
CONT_ASSIGN	3610	1	1	100.00
CONT_ASSIGN	3612	1	1	100.00
CONT_ASSIGN	3614	1	1	100.00
CONT_ASSIGN	3615	1	1	100.00
CONT_ASSIGN	3617	1	1	100.00
CONT_ASSIGN	3619	1	1	100.00
CONT_ASSIGN	3620	1	1	100.00
CONT_ASSIGN	3622	1	1	100.00
CONT_ASSIGN	3624	1	1	100.00
CONT_ASSIGN	3625	1	1	100.00
CONT_ASSIGN	3627	1	1	100.00
CONT_ASSIGN	3629	1	1	100.00
CONT_ASSIGN	3630	1	1	100.00
CONT_ASSIGN	3632	1	1	100.00
CONT_ASSIGN	3634	1	1	100.00
CONT_ASSIGN	3636	1	1	100.00
CONT_ASSIGN	3637	1	1	100.00
CONT_ASSIGN	3639	1	1	100.00
CONT_ASSIGN	3641	1	1	100.00
CONT_ASSIGN	3643	1	1	100.00
CONT_ASSIGN	3645	1	1	100.00
CONT_ASSIGN	3646	1	1	100.00
CONT_ASSIGN	3647	1	1	100.00
CONT_ASSIGN	3649	1	1	100.00
CONT_ASSIGN	3650	1	1	100.00
CONT_ASSIGN	3652	1	1	100.00
CONT_ASSIGN	3653	1	1	100.00
CONT_ASSIGN	3655	1	1	100.00
CONT_ASSIGN	3657	1	1	100.00
CONT_ASSIGN	3658	1	1	100.00
CONT_ASSIGN	3661	1	1	100.00
CONT_ASSIGN	3662	1	1	100.00
CONT_ASSIGN	3664	1	1	100.00
CONT_ASSIGN	3666	1	1	100.00
CONT_ASSIGN	3667	1	1	100.00
CONT_ASSIGN	3668	1	1	100.00
CONT_ASSIGN	3670	1	1	100.00
CONT_ASSIGN	3672	1	1	100.00
CONT_ASSIGN	3673	1	1	100.00
CONT_ASSIGN	3675	1	1	100.00
CONT_ASSIGN	3677	1	1	100.00
CONT_ASSIGN	3679	1	1	100.00
CONT_ASSIGN	3681	1	1	100.00
CONT_ASSIGN	3682	1	1	100.00
CONT_ASSIGN	3684	1	1	100.00
CONT_ASSIGN	3686	1	1	100.00
CONT_ASSIGN	3688	1	1	100.00
ALWAYS	3692	33	33	100.00
ALWAYS	3729	126	126	100.00
CONT_ASSIGN	3962	0	0
CONT_ASSIGN	3970	1	1	100.00
CONT_ASSIGN	3971	1	1	100.00

Click here to see the source line report.

---

Cond Coverage for Module : i2c_reg_top

	Total	Covered	Percent
Conditions	347	343	98.85
Logical	347	343	98.85
Non-Logical	0	0
Event	0	0

This module contains a very large number of conditions, so the report has been split into multiple pages, by source line number. Click on the line number range in the table below to see the condition coverage for that section of the module.

Line numbers	Percent
58-3658	99.07
3661-3682	95.83

---

Branch Coverage for Module : i2c_reg_top

	Line No.	Total	Covered	Percent
Branches		38	38	100.00
TERNARY	3424	2	2	100.00
IF	68	3	3	100.00
CASE	3730	33	33	100.00

3424         assign addrmiss = (reg_re || reg_we) ? ~|addr_hit : 1'b0 ;
                                                  -1-  
                                                  ==>  
                                                  ==>  

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T2,T3

68             if (!rst_ni) begin
               -1-  
69               err_q <= '0;
                 ==>
70             end else if (intg_err || reg_we_err) begin
                        -2-  
71               err_q <= 1'b1;
                 ==>
72             end
               MISSING_ELSE
               ==>

Branches:

-1-	-2-	Status	Tests
1	-	Covered	T1,T2,T3
0	1	Covered	T10,T41,T191
0	0	Covered	T1,T2,T3

3730           unique case (1'b1)
                      -1-  
3731             addr_hit[0]: begin
3732               reg_rdata_next[0] = intr_state_fmt_threshold_qs;
                   ==>
3733               reg_rdata_next[1] = intr_state_rx_threshold_qs;
3734               reg_rdata_next[2] = intr_state_acq_threshold_qs;
3735               reg_rdata_next[3] = intr_state_rx_overflow_qs;
3736               reg_rdata_next[4] = intr_state_controller_halt_qs;
3737               reg_rdata_next[5] = intr_state_scl_interference_qs;
3738               reg_rdata_next[6] = intr_state_sda_interference_qs;
3739               reg_rdata_next[7] = intr_state_stretch_timeout_qs;
3740               reg_rdata_next[8] = intr_state_sda_unstable_qs;
3741               reg_rdata_next[9] = intr_state_cmd_complete_qs;
3742               reg_rdata_next[10] = intr_state_tx_stretch_qs;
3743               reg_rdata_next[11] = intr_state_tx_threshold_qs;
3744               reg_rdata_next[12] = intr_state_acq_stretch_qs;
3745               reg_rdata_next[13] = intr_state_unexp_stop_qs;
3746               reg_rdata_next[14] = intr_state_host_timeout_qs;
3747             end
3748       
3749             addr_hit[1]: begin
3750               reg_rdata_next[0] = intr_enable_fmt_threshold_qs;
                   ==>
3751               reg_rdata_next[1] = intr_enable_rx_threshold_qs;
3752               reg_rdata_next[2] = intr_enable_acq_threshold_qs;
3753               reg_rdata_next[3] = intr_enable_rx_overflow_qs;
3754               reg_rdata_next[4] = intr_enable_controller_halt_qs;
3755               reg_rdata_next[5] = intr_enable_scl_interference_qs;
3756               reg_rdata_next[6] = intr_enable_sda_interference_qs;
3757               reg_rdata_next[7] = intr_enable_stretch_timeout_qs;
3758               reg_rdata_next[8] = intr_enable_sda_unstable_qs;
3759               reg_rdata_next[9] = intr_enable_cmd_complete_qs;
3760               reg_rdata_next[10] = intr_enable_tx_stretch_qs;
3761               reg_rdata_next[11] = intr_enable_tx_threshold_qs;
3762               reg_rdata_next[12] = intr_enable_acq_stretch_qs;
3763               reg_rdata_next[13] = intr_enable_unexp_stop_qs;
3764               reg_rdata_next[14] = intr_enable_host_timeout_qs;
3765             end
3766       
3767             addr_hit[2]: begin
3768               reg_rdata_next[0] = '0;
                   ==>
3769               reg_rdata_next[1] = '0;
3770               reg_rdata_next[2] = '0;
3771               reg_rdata_next[3] = '0;
3772               reg_rdata_next[4] = '0;
3773               reg_rdata_next[5] = '0;
3774               reg_rdata_next[6] = '0;
3775               reg_rdata_next[7] = '0;
3776               reg_rdata_next[8] = '0;
3777               reg_rdata_next[9] = '0;
3778               reg_rdata_next[10] = '0;
3779               reg_rdata_next[11] = '0;
3780               reg_rdata_next[12] = '0;
3781               reg_rdata_next[13] = '0;
3782               reg_rdata_next[14] = '0;
3783             end
3784       
3785             addr_hit[3]: begin
3786               reg_rdata_next[0] = '0;
                   ==>
3787             end
3788       
3789             addr_hit[4]: begin
3790               reg_rdata_next[0] = ctrl_enablehost_qs;
                   ==>
3791               reg_rdata_next[1] = ctrl_enabletarget_qs;
3792               reg_rdata_next[2] = ctrl_llpbk_qs;
3793               reg_rdata_next[3] = ctrl_nack_addr_after_timeout_qs;
3794               reg_rdata_next[4] = ctrl_ack_ctrl_en_qs;
3795               reg_rdata_next[5] = ctrl_multi_controller_monitor_en_qs;
3796               reg_rdata_next[6] = ctrl_tx_stretch_ctrl_en_qs;
3797             end
3798       
3799             addr_hit[5]: begin
3800               reg_rdata_next[0] = status_fmtfull_qs;
                   ==>
3801               reg_rdata_next[1] = status_rxfull_qs;
3802               reg_rdata_next[2] = status_fmtempty_qs;
3803               reg_rdata_next[3] = status_hostidle_qs;
3804               reg_rdata_next[4] = status_targetidle_qs;
3805               reg_rdata_next[5] = status_rxempty_qs;
3806               reg_rdata_next[6] = status_txfull_qs;
3807               reg_rdata_next[7] = status_acqfull_qs;
3808               reg_rdata_next[8] = status_txempty_qs;
3809               reg_rdata_next[9] = status_acqempty_qs;
3810               reg_rdata_next[10] = status_ack_ctrl_stretch_qs;
3811             end
3812       
3813             addr_hit[6]: begin
3814               reg_rdata_next[7:0] = rdata_qs;
                   ==>
3815             end
3816       
3817             addr_hit[7]: begin
3818               reg_rdata_next[7:0] = '0;
                   ==>
3819               reg_rdata_next[8] = '0;
3820               reg_rdata_next[9] = '0;
3821               reg_rdata_next[10] = '0;
3822               reg_rdata_next[11] = '0;
3823               reg_rdata_next[12] = '0;
3824             end
3825       
3826             addr_hit[8]: begin
3827               reg_rdata_next[0] = '0;
                   ==>
3828               reg_rdata_next[1] = '0;
3829               reg_rdata_next[7] = '0;
3830               reg_rdata_next[8] = '0;
3831             end
3832       
3833             addr_hit[9]: begin
3834               reg_rdata_next[11:0] = host_fifo_config_rx_thresh_qs;
                   ==>
3835               reg_rdata_next[27:16] = host_fifo_config_fmt_thresh_qs;
3836             end
3837       
3838             addr_hit[10]: begin
3839               reg_rdata_next[11:0] = target_fifo_config_tx_thresh_qs;
                   ==>
3840               reg_rdata_next[27:16] = target_fifo_config_acq_thresh_qs;
3841             end
3842       
3843             addr_hit[11]: begin
3844               reg_rdata_next[11:0] = host_fifo_status_fmtlvl_qs;
                   ==>
3845               reg_rdata_next[27:16] = host_fifo_status_rxlvl_qs;
3846             end
3847       
3848             addr_hit[12]: begin
3849               reg_rdata_next[11:0] = target_fifo_status_txlvl_qs;
                   ==>
3850               reg_rdata_next[27:16] = target_fifo_status_acqlvl_qs;
3851             end
3852       
3853             addr_hit[13]: begin
3854               reg_rdata_next[0] = ovrd_txovrden_qs;
                   ==>
3855               reg_rdata_next[1] = ovrd_sclval_qs;
3856               reg_rdata_next[2] = ovrd_sdaval_qs;
3857             end
3858       
3859             addr_hit[14]: begin
3860               reg_rdata_next[15:0] = val_scl_rx_qs;
                   ==>
3861               reg_rdata_next[31:16] = val_sda_rx_qs;
3862             end
3863       
3864             addr_hit[15]: begin
3865               reg_rdata_next[12:0] = timing0_thigh_qs;
                   ==>
3866               reg_rdata_next[28:16] = timing0_tlow_qs;
3867             end
3868       
3869             addr_hit[16]: begin
3870               reg_rdata_next[9:0] = timing1_t_r_qs;
                   ==>
3871               reg_rdata_next[24:16] = timing1_t_f_qs;
3872             end
3873       
3874             addr_hit[17]: begin
3875               reg_rdata_next[12:0] = timing2_tsu_sta_qs;
                   ==>
3876               reg_rdata_next[28:16] = timing2_thd_sta_qs;
3877             end
3878       
3879             addr_hit[18]: begin
3880               reg_rdata_next[8:0] = timing3_tsu_dat_qs;
                   ==>
3881               reg_rdata_next[28:16] = timing3_thd_dat_qs;
3882             end
3883       
3884             addr_hit[19]: begin
3885               reg_rdata_next[12:0] = timing4_tsu_sto_qs;
                   ==>
3886               reg_rdata_next[28:16] = timing4_t_buf_qs;
3887             end
3888       
3889             addr_hit[20]: begin
3890               reg_rdata_next[29:0] = timeout_ctrl_val_qs;
                   ==>
3891               reg_rdata_next[30] = timeout_ctrl_mode_qs;
3892               reg_rdata_next[31] = timeout_ctrl_en_qs;
3893             end
3894       
3895             addr_hit[21]: begin
3896               reg_rdata_next[6:0] = target_id_address0_qs;
                   ==>
3897               reg_rdata_next[13:7] = target_id_mask0_qs;
3898               reg_rdata_next[20:14] = target_id_address1_qs;
3899               reg_rdata_next[27:21] = target_id_mask1_qs;
3900             end
3901       
3902             addr_hit[22]: begin
3903               reg_rdata_next[7:0] = acqdata_abyte_qs;
                   ==>
3904               reg_rdata_next[10:8] = acqdata_signal_qs;
3905             end
3906       
3907             addr_hit[23]: begin
3908               reg_rdata_next[7:0] = '0;
                   ==>
3909             end
3910       
3911             addr_hit[24]: begin
3912               reg_rdata_next[19:0] = host_timeout_ctrl_qs;
                   ==>
3913             end
3914       
3915             addr_hit[25]: begin
3916               reg_rdata_next[30:0] = target_timeout_ctrl_val_qs;
                   ==>
3917               reg_rdata_next[31] = target_timeout_ctrl_en_qs;
3918             end
3919       
3920             addr_hit[26]: begin
3921               reg_rdata_next[7:0] = target_nack_count_qs;
                   ==>
3922             end
3923       
3924             addr_hit[27]: begin
3925               reg_rdata_next[8:0] = target_ack_ctrl_nbytes_qs;
                   ==>
3926               reg_rdata_next[31] = '0;
3927             end
3928       
3929             addr_hit[28]: begin
3930               reg_rdata_next[7:0] = acq_fifo_next_data_qs;
                   ==>
3931             end
3932       
3933             addr_hit[29]: begin
3934               reg_rdata_next[30:0] = host_nack_handler_timeout_val_qs;
                   ==>
3935               reg_rdata_next[31] = host_nack_handler_timeout_en_qs;
3936             end
3937       
3938             addr_hit[30]: begin
3939               reg_rdata_next[0] = controller_events_nack_qs;
                   ==>
3940               reg_rdata_next[1] = controller_events_unhandled_nack_timeout_qs;
3941               reg_rdata_next[2] = controller_events_bus_timeout_qs;
3942               reg_rdata_next[3] = controller_events_arbitration_lost_qs;
3943             end
3944       
3945             addr_hit[31]: begin
3946               reg_rdata_next[0] = target_events_tx_pending_qs;
                   ==>
3947               reg_rdata_next[1] = target_events_bus_timeout_qs;
3948               reg_rdata_next[2] = target_events_arbitration_lost_qs;
3949             end
3950       
3951             default: begin
3952               reg_rdata_next = '1;
                   ==>

Branches:

-1-	Status	Tests
addr_hit[0]	Covered	T1,T2,T3
addr_hit[1]	Covered	T1,T2,T3
addr_hit[2]	Covered	T1,T2,T3
addr_hit[3]	Covered	T1,T2,T3
addr_hit[4]	Covered	T1,T2,T3
addr_hit[5]	Covered	T1,T2,T3
addr_hit[6]	Covered	T1,T2,T3
addr_hit[7]	Covered	T1,T2,T3
addr_hit[8]	Covered	T1,T2,T3
addr_hit[9]	Covered	T1,T2,T3
addr_hit[10]	Covered	T1,T2,T3
addr_hit[11]	Covered	T1,T2,T3
addr_hit[12]	Covered	T1,T2,T3
addr_hit[13]	Covered	T1,T2,T3
addr_hit[14]	Covered	T1,T2,T3
addr_hit[15]	Covered	T1,T2,T3
addr_hit[16]	Covered	T1,T2,T3
addr_hit[17]	Covered	T1,T2,T3
addr_hit[18]	Covered	T1,T2,T3
addr_hit[19]	Covered	T1,T2,T3
addr_hit[20]	Covered	T1,T2,T3
addr_hit[21]	Covered	T1,T2,T3
addr_hit[22]	Covered	T1,T2,T3
addr_hit[23]	Covered	T1,T2,T3
addr_hit[24]	Covered	T1,T2,T3
addr_hit[25]	Covered	T1,T2,T3
addr_hit[26]	Covered	T1,T2,T3
addr_hit[27]	Covered	T1,T2,T3
addr_hit[28]	Covered	T1,T2,T3
addr_hit[29]	Covered	T1,T2,T3
addr_hit[30]	Covered	T1,T2,T3
addr_hit[31]	Covered	T1,T2,T3
default	Covered	T1,T3,T7

---

Assert Coverage for Module : i2c_reg_top

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	4	4	100.00	4	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	4	4	100.00	4	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
en2addrHit	410258125	35605751	0	0
reAfterRv	410258125	35605614	0	0
rePulse	410258125	34753980	0	0
wePulse	410258125	851634	0	0

en2addrHit

Name	Attempts	Real Successes	Failures	Incomplete
Total	410258125	35605751	0	0
T1	1296	31	0	0
T2	9974	135	0	0
T3	12945	1127	0	0
T4	11981	1450	0	0
T5	30777	3216	0	0
T6	7561	275	0	0
T7	59395	1111	0	0
T8	10772	77	0	0
T9	136420	19252	0	0
T10	5882	1	0	0

reAfterRv

Name	Attempts	Real Successes	Failures	Incomplete
Total	410258125	35605614	0	0
T1	1296	31	0	0
T2	9974	135	0	0
T3	12945	1127	0	0
T4	11981	1450	0	0
T5	30777	3216	0	0
T6	7561	274	0	0
T7	59395	1111	0	0
T8	10772	77	0	0
T9	136420	19252	0	0
T10	5882	1	0	0

rePulse

Name	Attempts	Real Successes	Failures	Incomplete
Total	410258125	34753980	0	0
T1	1296	15	0	0
T2	9974	71	0	0
T3	12945	1077	0	0
T4	11981	1432	0	0
T5	30777	2949	0	0
T6	7561	170	0	0
T7	59395	839	0	0
T8	10772	11	0	0
T9	136420	19131	0	0
T10	5882	1	0	0

wePulse

Name	Attempts	Real Successes	Failures	Incomplete
Total	410258125	851634	0	0
T1	1296	16	0	0
T2	9974	64	0	0
T3	12945	50	0	0
T4	11981	18	0	0
T5	30777	267	0	0
T6	7561	104	0	0
T7	59395	272	0	0
T8	10772	66	0	0
T9	136420	121	0	0
T10	5882	0	0	0
T40	0	6	0	0