Unified Coverage Report :: Module :: i2c_csr_assert_fpv

Module : i2c_csr_assert_fpv

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
93.75						93.75

Source File(s) :
/workspaces/repo/scratch/os_regression_2024_09_03/i2c-sim-vcs/default/sim-vcs/../src/lowrisc_fpv_i2c_csr_assert_0/i2c_csr_assert_fpv.sv

Module self-instances :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
tb.dut.i2c_csr_assert	93.75						93.75

---

Module Instance : tb.dut.i2c_csr_assert

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
93.75						93.75

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
93.75						93.75

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
98.48	100.00	100.00	93.91			100.00	dut

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Since this is the module's only instance, the coverage report is the same as for the module.

Assert Coverage for Module : i2c_csr_assert_fpv

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	16	16	100.00	15	93.75
Cover properties	0	0		0
Cover sequences	0	0		0
Total	16	16	100.00	15	93.75

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
TlulOOBAddrErr_A	410258125	0	0	0
ctrl_rd_A	410258125	1952	0	0
host_fifo_config_rd_A	410258125	5726	0	0
host_nack_handler_timeout_rd_A	410258125	1081	0	0
host_timeout_ctrl_rd_A	410258125	1008	0	0
intr_enable_rd_A	410258125	3799	0	0
ovrd_rd_A	410258125	2112	0	0
target_fifo_config_rd_A	410258125	1121	0	0
target_id_rd_A	410258125	1524	0	0
target_timeout_ctrl_rd_A	410258125	1116	0	0
timeout_ctrl_rd_A	410258125	1290	0	0
timing0_rd_A	410258125	1137	0	0
timing1_rd_A	410258125	1143	0	0
timing2_rd_A	410258125	1212	0	0
timing3_rd_A	410258125	1197	0	0
timing4_rd_A	410258125	1079	0	0

TlulOOBAddrErr_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	410258125	0	0	0

ctrl_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	410258125	1952	0	0
T105	5767	3	0	0
T106	1849	3	0	0
T107	6359	5	0	0
T108	10794	181	0	0
T109	1636	9	0	0
T110	1994	8	0	0
T111	13925	54	0	0
T112	2547	24	0	0
T113	7044	25	0	0
T114	2303	18	0	0

host_fifo_config_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	410258125	5726	0	0
T15	486967	0	0	0
T16	229099	0	0	0
T37	0	95	0	0
T84	453201	137	0	0
T103	204827	0	0	0
T115	0	127	0	0
T116	0	214	0	0
T117	0	184	0	0
T118	0	86	0	0
T119	0	68	0	0
T120	0	146	0	0
T121	0	146	0	0
T122	0	153	0	0
T123	83870	0	0	0
T124	22530	0	0	0
T125	10320	0	0	0
T126	31630	0	0	0
T127	120045	0	0	0
T128	46435	0	0	0

host_nack_handler_timeout_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	410258125	1081	0	0
T106	1849	14	0	0
T108	10794	221	0	0
T109	1636	7	0	0
T110	1994	2	0	0
T111	13925	27	0	0
T113	7044	7	0	0
T114	2303	2	0	0
T129	26329	244	0	0
T130	16692	112	0	0
T131	1939	12	0	0

host_timeout_ctrl_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	410258125	1008	0	0
T106	1849	3	0	0
T107	6359	4	0	0
T108	10794	206	0	0
T111	13925	17	0	0
T112	2547	6	0	0
T113	7044	26	0	0
T114	2303	9	0	0
T129	26329	247	0	0
T130	16692	79	0	0
T131	1939	6	0	0

intr_enable_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	410258125	3799	0	0
T37	135726	40	0	0
T106	0	14	0	0
T107	0	12	0	0
T108	0	233	0	0
T109	0	36	0	0
T110	0	8	0	0
T111	0	33	0	0
T132	0	17	0	0
T133	0	11	0	0
T134	0	22	0	0
T135	54707	0	0	0
T136	44670	0	0	0
T137	989831	0	0	0
T138	7424	0	0	0
T139	12598	0	0	0
T140	196585	0	0	0
T141	67985	0	0	0
T142	12374	0	0	0
T143	27504	0	0	0

ovrd_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	410258125	2112	0	0
T17	12955	0	0	0
T18	12660	0	0	0
T34	8189	0	0	0
T42	13330	0	0	0
T43	23755	0	0	0
T44	12875	0	0	0
T46	23549	0	0	0
T69	14280	0	0	0
T75	2437	28	0	0
T144	0	41	0	0
T145	0	44	0	0
T146	0	28	0	0
T147	0	61	0	0
T148	0	56	0	0
T149	0	33	0	0
T150	0	39	0	0
T151	0	42	0	0
T152	0	69	0	0
T153	221414	0	0	0

target_fifo_config_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	410258125	1121	0	0
T106	1849	8	0	0
T107	6359	14	0	0
T108	10794	210	0	0
T109	1636	2	0	0
T111	13925	61	0	0
T112	2547	24	0	0
T113	7044	15	0	0
T114	2303	7	0	0
T129	26329	238	0	0
T130	16692	104	0	0

target_id_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	410258125	1524	0	0
T105	5767	5	0	0
T106	1849	10	0	0
T107	6359	11	0	0
T108	10794	200	0	0
T110	1994	7	0	0
T111	13925	12	0	0
T112	2547	18	0	0
T113	7044	22	0	0
T114	2303	1	0	0
T129	26329	236	0	0

target_timeout_ctrl_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	410258125	1116	0	0
T105	5767	9	0	0
T106	1849	2	0	0
T107	6359	7	0	0
T108	10794	185	0	0
T109	1636	5	0	0
T111	13925	38	0	0
T112	2547	12	0	0
T113	7044	3	0	0
T114	2303	16	0	0
T129	26329	227	0	0

timeout_ctrl_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	410258125	1290	0	0
T105	5767	2	0	0
T106	1849	8	0	0
T107	6359	13	0	0
T108	10794	206	0	0
T110	1994	5	0	0
T111	13925	23	0	0
T112	2547	13	0	0
T113	7044	11	0	0
T114	2303	14	0	0
T129	26329	229	0	0

timing0_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	410258125	1137	0	0
T105	5767	7	0	0
T106	1849	4	0	0
T108	10794	246	0	0
T109	1636	1	0	0
T110	1994	6	0	0
T111	13925	40	0	0
T112	2547	10	0	0
T113	7044	8	0	0
T114	2303	6	0	0
T129	26329	213	0	0

timing1_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	410258125	1143	0	0
T105	5767	3	0	0
T106	1849	13	0	0
T108	10794	239	0	0
T109	1636	3	0	0
T110	1994	2	0	0
T111	13925	34	0	0
T112	2547	2	0	0
T113	7044	9	0	0
T114	2303	5	0	0
T129	26329	267	0	0

timing2_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	410258125	1212	0	0
T106	1849	9	0	0
T108	10794	236	0	0
T109	1636	2	0	0
T110	1994	2	0	0
T111	13925	55	0	0
T112	2547	33	0	0
T113	7044	28	0	0
T114	2303	17	0	0
T129	26329	237	0	0
T130	16692	137	0	0

timing3_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	410258125	1197	0	0
T105	5767	6	0	0
T106	1849	2	0	0
T107	6359	13	0	0
T108	10794	214	0	0
T110	1994	1	0	0
T111	13925	42	0	0
T112	2547	9	0	0
T113	7044	13	0	0
T114	2303	10	0	0
T129	26329	245	0	0

timing4_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	410258125	1079	0	0
T105	5767	11	0	0
T106	1849	3	0	0
T107	6359	10	0	0
T108	10794	224	0	0
T109	1636	1	0	0
T110	1994	8	0	0
T111	13925	22	0	0
T112	2547	36	0	0
T113	7044	11	0	0
T114	2303	6	0	0