Unified Coverage Report :: Group :: tl_agent_pkg::tl_a_chan_cov_cg::SHAPE{(2 << ((valid_source_width - 1) - 1))=128}

Group : tl_agent_pkg::tl_a_chan_cov_cg::SHAPE{(2 << ((valid_source_width - 1) - 1))=128}

SCORE	INSTANCES	WEIGHT	GOAL	AT LEAST	PER INSTANCE	AUTO BIN MAX	PRINT MISSING
100.00	100.00	1	100	1	1	64	64

Source File(s) :
/workspaces/repo/scratch/os_regression_2024_09_08/i2c-sim-vcs/default/sim-vcs/../src/lowrisc_dv_tl_agent_0/tl_agent_cov.sv

1 Instances:

NAME	SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
tl_agent_pkg.uvm_test_top.env.m_tl_agent_i2c_reg_block.cov::m_tl_a_chan_cov_cg	100.00	1	100	1	64	64

---

Group Instance : tl_agent_pkg.uvm_test_top.env.m_tl_agent_i2c_reg_block.cov::m_tl_a_chan_cov_cg

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
100.00	1	100	1	64	64

---

Summary for Group Instance tl_agent_pkg.uvm_test_top.env.m_tl_agent_i2c_reg_block.cov::m_tl_a_chan_cov_cg

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	134	0	134	100.00
Crosses	3	0	3	100.00

Variables for Group Instance tl_agent_pkg.uvm_test_top.env.m_tl_agent_i2c_reg_block.cov::m_tl_a_chan_cov_cg

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
cp_mask	1	0	1	100.00	100	1	1	0
cp_opcode	3	0	3	100.00	100	1	1	0
cp_size	1	0	1	100.00	100	1	1	0
cp_source	129	0	129	100.00	100	1	1	0

Crosses for Group Instance tl_agent_pkg.uvm_test_top.env.m_tl_agent_i2c_reg_block.cov::m_tl_a_chan_cov_cg

CROSS	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	PRINT MISSING	COMMENT
tl_a_chan_cov_cg_cc	3	0	3	100.00	100	1	1	0

Summary for Variable cp_mask

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	1	0	1	100.00

User Defined Bins for cp_mask

Excluded/Illegal bins

NAME	COUNT	STATUS
others	33239178	Excluded

Covered bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

all_enables

8460009

1

T1

65

T2

258

T3

14

---

Summary for Variable cp_opcode

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	3	0	3	100.00

User Defined Bins for cp_opcode

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
values[0x4]	40846438	1			T1	118		T2	7157		T3	843
values[0x0]	425680	1			T1	41		T2	130		T3	16
values[0x1]	427069	1			T1	41		T2	109		T3	12

---

Summary for Variable cp_size

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	1	0	1	100.00

User Defined Bins for cp_size

Excluded/Illegal bins

NAME	COUNT	STATUS
others	23224490	Excluded

Covered bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

biggest_size

18474697

1

T1

112

T2

3741

T3

222

---

Summary for Variable cp_source

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	129	0	129	100.00

User Defined Bins for cp_source

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
valid_sources[0x00]	151726	1			T2	28		T3	3		T5	2
valid_sources[0x01]	151777	1			T1	1		T2	29		T3	4
valid_sources[0x02]	157095	1			T1	1		T2	27		T3	4
valid_sources[0x03]	149534	1			T2	28		T9	8		T10	63
valid_sources[0x04]	156928	1			T1	1		T2	25		T3	5
valid_sources[0x05]	177685	1			T1	1		T2	33		T3	1
valid_sources[0x06]	156749	1			T2	40		T3	3		T5	2
valid_sources[0x07]	182942	1			T2	29		T3	7		T9	4
valid_sources[0x08]	152587	1			T1	1		T2	24		T3	1
valid_sources[0x09]	159759	1			T2	31		T3	2		T4	1
valid_sources[0x0a]	149776	1			T2	25		T3	4		T5	1
valid_sources[0x0b]	181357	1			T2	36		T3	8		T5	3
valid_sources[0x0c]	155420	1			T1	2		T2	32		T3	3
valid_sources[0x0d]	162804	1			T1	1		T2	36		T3	1
valid_sources[0x0e]	154319	1			T1	4		T2	31		T3	2
valid_sources[0x0f]	167804	1			T1	2		T2	36		T3	5
valid_sources[0x10]	178657	1			T1	1		T2	30		T3	2
valid_sources[0x11]	141091	1			T2	23		T3	2		T7	5
valid_sources[0x12]	162457	1			T2	26		T3	4		T5	2
valid_sources[0x13]	154995	1			T2	24		T3	3		T4	1
valid_sources[0x14]	171061	1			T1	1		T2	35		T3	4
valid_sources[0x15]	168576	1			T2	22		T3	1		T9	4
valid_sources[0x16]	157246	1			T2	20		T3	5		T4	1
valid_sources[0x17]	162537	1			T2	29		T3	8		T5	1
valid_sources[0x18]	159660	1			T2	35		T3	3		T4	1
valid_sources[0x19]	158237	1			T2	29		T3	2		T5	1
valid_sources[0x1a]	166926	1			T2	33		T3	7		T6	1
valid_sources[0x1b]	165732	1			T1	2		T2	41		T3	5
valid_sources[0x1c]	159720	1			T2	31		T3	5		T5	4
valid_sources[0x1d]	186061	1			T2	24		T3	7		T5	3
valid_sources[0x1e]	167409	1			T1	1		T2	42		T3	3
valid_sources[0x1f]	177934	1			T1	2		T2	44		T3	2
valid_sources[0x20]	192145	1			T1	1		T2	32		T3	7
valid_sources[0x21]	163338	1			T1	1		T2	30		T3	2
valid_sources[0x22]	154026	1			T1	1		T2	26		T3	6
valid_sources[0x23]	152030	1			T1	1		T2	30		T3	6
valid_sources[0x24]	171492	1			T2	32		T5	1		T9	1
valid_sources[0x25]	240810	1			T1	1		T2	31		T3	2
valid_sources[0x26]	150304	1			T2	16		T3	4		T5	2
valid_sources[0x27]	178513	1			T2	29		T3	1		T4	2
valid_sources[0x28]	177677	1			T2	33		T3	5		T5	3
valid_sources[0x29]	407436	1			T2	30		T3	1		T9	6
valid_sources[0x2a]	175763	1			T2	29		T3	2		T5	2
valid_sources[0x2b]	154878	1			T2	28		T3	4		T9	3
valid_sources[0x2c]	162440	1			T2	33		T3	6		T5	2
valid_sources[0x2d]	152015	1			T1	3		T2	29		T3	4
valid_sources[0x2e]	175805	1			T2	36		T3	4		T5	3
valid_sources[0x2f]	175449	1			T1	1		T2	41		T3	4
valid_sources[0x30]	152161	1			T1	2		T2	25		T3	4
valid_sources[0x31]	170204	1			T2	36		T3	6		T9	4
valid_sources[0x32]	144733	1			T1	2		T2	31		T3	3
valid_sources[0x33]	156491	1			T1	2		T2	32		T3	5
valid_sources[0x34]	159751	1			T2	39		T3	1		T5	1
valid_sources[0x35]	175788	1			T1	1		T2	18		T3	3
valid_sources[0x36]	151494	1			T2	25		T3	4		T5	1
valid_sources[0x37]	156048	1			T2	38		T3	1		T9	6
valid_sources[0x38]	161156	1			T2	25		T3	3		T9	4
valid_sources[0x39]	155749	1			T1	1		T2	24		T3	3
valid_sources[0x3a]	166460	1			T2	29		T3	2		T5	2
valid_sources[0x3b]	158300	1			T2	31		T3	1		T5	1
valid_sources[0x3c]	168571	1			T2	32		T3	1		T4	1
valid_sources[0x3d]	171872	1			T2	41		T3	1		T9	2
valid_sources[0x3e]	159113	1			T2	35		T3	5		T9	9
valid_sources[0x3f]	157754	1			T2	20		T3	5		T5	2
valid_sources[0x40]	152521	1			T1	1		T2	25		T3	1
valid_sources[0x41]	164609	1			T2	39		T3	4		T6	2
valid_sources[0x42]	161923	1			T2	32		T3	5		T5	4
valid_sources[0x43]	158309	1			T2	37		T3	4		T9	8
valid_sources[0x44]	151539	1			T1	1		T2	31		T3	6
valid_sources[0x45]	155363	1			T1	2		T2	27		T3	5
valid_sources[0x46]	155156	1			T2	20		T5	3		T6	1
valid_sources[0x47]	160113	1			T1	1		T2	37		T3	5
valid_sources[0x48]	178712	1			T1	2		T2	36		T3	4
valid_sources[0x49]	161045	1			T1	1		T2	27		T3	2
valid_sources[0x4a]	174299	1			T2	31		T3	1		T6	2
valid_sources[0x4b]	156447	1			T1	2		T2	17		T3	5
valid_sources[0x4c]	181820	1			T1	4		T2	28		T3	5
valid_sources[0x4d]	176689	1			T2	29		T3	3		T5	1
valid_sources[0x4e]	156038	1			T1	2		T2	26		T3	3
valid_sources[0x4f]	162903	1			T2	23		T3	5		T6	1
valid_sources[0x50]	170684	1			T2	35		T3	4		T5	1
valid_sources[0x51]	152024	1			T1	1		T2	33		T5	1
valid_sources[0x52]	165625	1			T2	32		T3	6		T5	2
valid_sources[0x53]	162625	1			T2	32		T3	3		T5	1
valid_sources[0x54]	170879	1			T1	1		T2	32		T3	5
valid_sources[0x55]	163061	1			T2	37		T3	2		T5	1
valid_sources[0x56]	148279	1			T2	31		T3	1		T5	2
valid_sources[0x57]	164558	1			T2	21		T3	4		T5	2
valid_sources[0x58]	155984	1			T2	33		T3	3		T4	2
valid_sources[0x59]	164055	1			T2	31		T3	6		T5	2
valid_sources[0x5a]	146808	1			T1	5		T2	19		T3	1
valid_sources[0x5b]	154274	1			T1	1		T2	30		T3	3
valid_sources[0x5c]	162125	1			T2	37		T3	5		T5	1
valid_sources[0x5d]	151076	1			T2	38		T3	5		T5	1
valid_sources[0x5e]	169849	1			T1	3		T2	29		T3	2
valid_sources[0x5f]	154975	1			T1	1		T2	17		T3	2
valid_sources[0x60]	167491	1			T1	3		T2	26		T3	7
valid_sources[0x61]	185876	1			T2	37		T5	4		T6	1
valid_sources[0x62]	161922	1			T1	1		T2	19		T3	8
valid_sources[0x63]	166686	1			T2	29		T3	3		T6	2
valid_sources[0x64]	163313	1			T1	2		T2	25		T3	6
valid_sources[0x65]	150141	1			T2	25		T3	3		T5	3
valid_sources[0x66]	173712	1			T1	1		T2	26		T3	3
valid_sources[0x67]	157154	1			T2	45		T3	2		T5	2
valid_sources[0x68]	154267	1			T1	2		T2	19		T3	1
valid_sources[0x69]	148193	1			T2	31		T3	3		T9	2
valid_sources[0x6a]	192406	1			T1	3		T2	24		T5	2
valid_sources[0x6b]	156212	1			T1	2		T2	19		T3	2
valid_sources[0x6c]	167575	1			T2	33		T3	2		T5	1
valid_sources[0x6d]	150177	1			T2	25		T3	6		T4	1
valid_sources[0x6e]	167775	1			T2	33		T3	8		T4	2
valid_sources[0x6f]	158679	1			T2	15		T3	7		T5	1
valid_sources[0x70]	155411	1			T1	1		T2	43		T3	3
valid_sources[0x71]	151854	1			T1	1		T2	19		T3	4
valid_sources[0x72]	155817	1			T2	34		T3	2		T4	1
valid_sources[0x73]	151729	1			T2	29		T3	2		T4	1
valid_sources[0x74]	152540	1			T1	1		T2	31		T3	4
valid_sources[0x75]	163345	1			T2	23		T3	4		T4	1
valid_sources[0x76]	162285	1			T1	2		T2	33		T3	9
valid_sources[0x77]	163537	1			T1	1		T2	35		T3	2
valid_sources[0x78]	159069	1			T1	1		T2	37		T3	3
valid_sources[0x79]	163453	1			T2	26		T3	2		T5	1
valid_sources[0x7a]	170190	1			T2	28		T3	8		T5	1
valid_sources[0x7b]	176105	1			T1	3		T2	24		T3	1
valid_sources[0x7c]	160594	1			T2	29		T3	5		T5	1
valid_sources[0x7d]	154628	1			T2	32		T3	2		T5	3
valid_sources[0x7e]	169320	1			T2	32		T3	1		T5	2
valid_sources[0x7f]	166173	1			T1	2		T2	25		T3	5
valid_sources[0x80]	161250	1			T1	2		T2	21		T3	1

---

Summary for Cross tl_a_chan_cov_cg_cc

Samples crossed: cp_opcode cp_mask cp_size

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	3	0	3	100.00

Automatically Generated Cross Bins for tl_a_chan_cov_cg_cc

Bins

cp_opcode

cp_mask

cp_size

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

values[0x4]

all_enables

biggest_size

8085925

1

T1

13

T2

183

T3

2

values[0x0]

all_enables

biggest_size

222872

1

T1

28

T2

52

T3

7

values[0x1]

all_enables

biggest_size

151212

1

T1

24

T2

23

T3

5