Line Coverage for Module :
i2c_bus_monitor
| Line No. | Total | Covered | Percent |
|---|
| TOTAL | | 107 | 103 | 96.26 |
| CONT_ASSIGN | 37 | 1 | 1 | 100.00 |
| ALWAYS | 40 | 3 | 3 | 100.00 |
| ALWAYS | 50 | 5 | 5 | 100.00 |
| ALWAYS | 82 | 6 | 6 | 100.00 |
| ALWAYS | 92 | 6 | 6 | 100.00 |
| ALWAYS | 102 | 6 | 6 | 100.00 |
| CONT_ASSIGN | 112 | 1 | 1 | 100.00 |
| CONT_ASSIGN | 113 | 1 | 1 | 100.00 |
| CONT_ASSIGN | 114 | 1 | 1 | 100.00 |
| CONT_ASSIGN | 117 | 1 | 1 | 100.00 |
| CONT_ASSIGN | 118 | 1 | 1 | 100.00 |
| CONT_ASSIGN | 119 | 1 | 1 | 100.00 |
| CONT_ASSIGN | 127 | 1 | 1 | 100.00 |
| CONT_ASSIGN | 137 | 1 | 1 | 100.00 |
| ALWAYS | 147 | 3 | 3 | 100.00 |
| ALWAYS | 158 | 9 | 8 | 88.89 |
| ALWAYS | 189 | 46 | 45 | 97.83 |
| ALWAYS | 275 | 9 | 8 | 88.89 |
| ALWAYS | 293 | 3 | 2 | 66.67 |
| CONT_ASSIGN | 303 | 1 | 1 | 100.00 |
| CONT_ASSIGN | 304 | 1 | 1 | 100.00 |
36 logic monitor_enable, monitor_enable_q;
37 1/1 assign monitor_enable = controller_enable_i | target_enable_i | multi_controller_enable_i;
Tests: T1 T2 T3
38
39 always_ff @ (posedge clk_i or negedge rst_ni) begin
40 1/1 if (!rst_ni) begin
Tests: T1 T2 T3
41 1/1 monitor_enable_q <= 1'b0;
Tests: T1 T2 T3
42 end else begin
43 1/1 monitor_enable_q <= monitor_enable;
Tests: T1 T2 T3
44 end
45 end
46
47 // SDA and SCL at the previous clock edge
48 logic scl_i_q, sda_i_q;
49 always_ff @ (posedge clk_i or negedge rst_ni) begin : bus_prev
50 1/1 if (!rst_ni) begin
Tests: T1 T2 T3
51 1/1 scl_i_q <= 1'b1;
Tests: T1 T2 T3
52 1/1 sda_i_q <= 1'b1;
Tests: T1 T2 T3
53 end else begin
54 1/1 scl_i_q <= scl_i;
Tests: T1 T2 T3
55 1/1 sda_i_q <= sda_i;
Tests: T1 T2 T3
56 end
57 end
58
59 // Start and Stop detection
60 //
61 // To resolve ambiguity with early SDA arrival, reject control symbols when
62 // SCL goes low too soon. The hold time for ordinary data/ACK bits is too
63 // short to reliably see SCL change before SDA. Use the hold time for
64 // control signals to ensure a Start or Stop symbol was actually received.
65 // Requirements: thd_dat + 1 < thd_sta
66 // The extra (+1) here is to account for a late SDA arrival due to CDC
67 // skew.
68 //
69 // Note that this counter combines Start and Stop detection into one
70 // counter. A controller-only reset scenario could end up with a Stop
71 // following shortly after a Start, with the requisite setup time not
72 // observed.
73 logic start_det_trigger, start_det_pending;
74 logic start_det; // indicates start or repeated start is detected on the bus
75 logic stop_det_trigger, stop_det_pending;
76 logic stop_det; // indicates stop is detected on the bus
77
78 // Stop / Start detection counter
79 logic [13:0] ctrl_det_count;
80
81 always_ff @(posedge clk_i or negedge rst_ni) begin
82 1/1 if (!rst_ni) begin
Tests: T1 T2 T3
83 1/1 ctrl_det_count <= '0;
Tests: T1 T2 T3
84 1/1 end else if (start_det_trigger || stop_det_trigger) begin
Tests: T1 T2 T3
85 1/1 ctrl_det_count <= 14'd1;
Tests: T1 T2 T3
86 1/1 end else if (start_det_pending || stop_det_pending) begin
Tests: T1 T2 T3
87 1/1 ctrl_det_count <= ctrl_det_count + 1'b1;
Tests: T1 T2 T3
88 end
MISSING_ELSE
89 end
90
91 always_ff @(posedge clk_i or negedge rst_ni) begin
92 1/1 if (!rst_ni) begin
Tests: T1 T2 T3
93 1/1 start_det_pending <= 1'b0;
Tests: T1 T2 T3
94 1/1 end else if (start_det_trigger) begin
Tests: T1 T2 T3
95 1/1 start_det_pending <= 1'b1;
Tests: T1 T2 T3
96 1/1 end else if (!monitor_enable || !scl_i || start_det || stop_det_trigger) begin
Tests: T1 T2 T3
97 1/1 start_det_pending <= 1'b0;
Tests: T1 T2 T3
98 end
MISSING_ELSE
99 end
100
101 always_ff @(posedge clk_i or negedge rst_ni) begin
102 1/1 if (!rst_ni) begin
Tests: T1 T2 T3
103 1/1 stop_det_pending <= 1'b0;
Tests: T1 T2 T3
104 1/1 end else if (stop_det_trigger) begin
Tests: T1 T2 T3
105 1/1 stop_det_pending <= 1'b1;
Tests: T2 T3 T5
106 1/1 end else if (!monitor_enable || !scl_i || stop_det || start_det_trigger) begin
Tests: T1 T2 T3
107 1/1 stop_det_pending <= 1'b0;
Tests: T1 T2 T3
108 end
MISSING_ELSE
109 end
110
111 // (Repeated) Start condition detection by target
112 1/1 assign start_det_trigger = monitor_enable && (scl_i_q && scl_i) & (sda_i_q && !sda_i);
Tests: T1 T2 T3
113 1/1 assign start_det = monitor_enable && start_det_pending && (ctrl_det_count >= 14'(thd_dat_i));
Tests: T1 T2 T3
114 1/1 assign start_detect_o = start_det;
Tests: T1 T2 T3
115
116 // Stop condition detection by target
117 1/1 assign stop_det_trigger = monitor_enable && (scl_i_q && scl_i) & (!sda_i_q && sda_i);
Tests: T1 T2 T3
118 1/1 assign stop_det = monitor_enable && stop_det_pending && (ctrl_det_count >= 14'(thd_dat_i));
Tests: T1 T2 T3
119 1/1 assign stop_detect_o = stop_det;
Tests: T1 T2 T3
120
121 //
122 // Bus timeout logic
123 //
124
125 // Detection of bus in a released state.
126 logic bus_idling;
127 1/1 assign bus_idling = scl_i && (sda_i == sda_i_q);
Tests: T1 T2 T3
128
129 logic [29:0] bus_release_cnt, bus_release_cnt_sel;
130 logic bus_release_cnt_load, bus_release_cnt_dec;
131
132 // bus_inactive_timeout_det is only high for the case where the bus release
133 // counter reaches zero for bus idling, not the wait after a Stop condition.
134 logic bus_inactive_timeout_det;
135
136 logic bus_inactive_timeout_en;
137 1/1 assign bus_inactive_timeout_en = (bus_inactive_timeout_i > '0);
Tests: T1 T2 T3
138
139 // bus_active_timeout latches high when SCL has been held low for too long.
140 // This can be done intentionally or unintentionally, as the response for
141 // target devices should be to abort the current transaction and release any
142 // hold on the bus. Note that the bus doesn't immediately transition to
143 // "free" status, since the controller can continue holding SCL low for some
144 // time.
145 logic bus_active_timeout_det_d, bus_active_timeout_det_q;
146 always_ff @(posedge clk_i or negedge rst_ni) begin
147 1/1 if (!rst_ni) begin
Tests: T1 T2 T3
148 1/1 bus_active_timeout_det_q <= 1'b0;
Tests: T1 T2 T3
149 end else begin
150 1/1 bus_active_timeout_det_q <= bus_active_timeout_det_d;
Tests: T1 T2 T3
151 end
152 end
153
154 // Bus release counter.
155 // Together with the FSM below, this counter detects bus timeouts and the end
156 // of the bus free time following a Stop condition.
157 always_ff @ (posedge clk_i or negedge rst_ni) begin : bus_idle
158 1/1 if (!rst_ni) begin
Tests: T1 T2 T3
159 1/1 bus_release_cnt <= '0;
Tests: T1 T2 T3
160 1/1 end else if (monitor_enable && !monitor_enable_q) begin
Tests: T1 T2 T3
161 // The rising edge of monitor enable resets the counter for
162 // multi-controller mode.
163 1/1 if (multi_controller_enable_i) begin
Tests: T1 T2 T3
164 // For the multi-controller case, wait until the bus isn't busy before
165 // transmitting.
166 0/1 ==> bus_release_cnt <= 30'(bus_inactive_timeout_i);
167 end
MISSING_ELSE
168 1/1 end else if (bus_release_cnt_load) begin
Tests: T1 T2 T3
169 1/1 bus_release_cnt <= bus_release_cnt_sel;
Tests: T1 T2 T3
170 1/1 end else if (bus_release_cnt_dec && (bus_release_cnt != '0)) begin
Tests: T1 T2 T3
171 1/1 bus_release_cnt <= bus_release_cnt - 1'b1;
Tests: T1 T2 T3
172 end
MISSING_ELSE
173 end
174
175 typedef enum logic [1:0] {
176 // Bus is currently free. Can transmit.
177 StBusFree,
178 // Bus is busy and not held with SCL high.
179 StBusBusyLow,
180 // Bus is currently busy, but SCL is held high.
181 StBusBusyHigh,
182 // Bus is currently busy, but saw a Stop. Count down to Bus Free.
183 StBusBusyStop
184 } bus_state_e;
185
186 bus_state_e state_q, state_d;
187
188 always_comb begin
189 1/1 state_d = state_q;
Tests: T1 T2 T3
190 1/1 bus_release_cnt_load = 1'b0;
Tests: T1 T2 T3
191 1/1 bus_release_cnt_sel = 30'(t_buf_i);
Tests: T1 T2 T3
192 1/1 bus_release_cnt_dec = 1'b0;
Tests: T1 T2 T3
193 1/1 bus_inactive_timeout_det = 1'b0;
Tests: T1 T2 T3
194 1/1 bus_active_timeout_det_d = bus_active_timeout_det_q;
Tests: T1 T2 T3
195
196 1/1 unique case (state_q)
Tests: T1 T2 T3
197 StBusFree: begin
198 1/1 bus_active_timeout_det_d = 1'b0;
Tests: T1 T2 T3
199
200 1/1 if (!scl_i || !sda_i) begin
Tests: T1 T2 T3
201 1/1 state_d = StBusBusyLow;
Tests: T1 T2 T3
202 1/1 bus_release_cnt_load = 1'b1;
Tests: T1 T2 T3
203 1/1 bus_release_cnt_sel = bus_active_timeout_i;
Tests: T1 T2 T3
204 end
MISSING_ELSE
205 end
206
207 StBusBusyLow: begin
208 1/1 bus_release_cnt_dec = !scl_i;
Tests: T1 T2 T3
209
210 1/1 if (stop_det) begin
Tests: T1 T2 T3
211 1/1 state_d = StBusBusyStop;
Tests: T2 T3 T5
212 1/1 bus_release_cnt_load = 1'b1;
Tests: T2 T3 T5
213 1/1 bus_release_cnt_sel = 30'(t_buf_i);
Tests: T2 T3 T5
214 1/1 end else if (bus_idling && bus_inactive_timeout_en) begin
Tests: T1 T2 T3
215 1/1 state_d = StBusBusyHigh;
Tests: T2 T3 T5
216 1/1 bus_release_cnt_load = 1'b1;
Tests: T2 T3 T5
217 1/1 bus_release_cnt_sel = 30'(bus_inactive_timeout_i);
Tests: T2 T3 T5
218 1/1 end else if (scl_i) begin
Tests: T1 T2 T3
219 1/1 bus_release_cnt_load = 1'b1;
Tests: T1 T4 T8
220 1/1 bus_release_cnt_sel = bus_active_timeout_i;
Tests: T1 T4 T8
221 1/1 if (bus_active_timeout_det_q) begin
Tests: T1 T4 T8
222 // SCL was released due to the bus timeout, so go to BusFree.
223 0/1 ==> state_d = StBusFree;
224 end
MISSING_ELSE
225 1/1 end else if (bus_release_cnt == 30'd1) begin
Tests: T1 T2 T3
226 // The active timeout occurs when SCL has been held continuously low
227 // for too long. Both the controller and target should respond to
228 // this timeout and release the bus. We don't consider the bus free
229 // yet, though: SCL must be released first.
230 1/1 bus_active_timeout_det_d = bus_active_timeout_en_i;
Tests: T1 T2 T3
231 end
MISSING_ELSE
232 end
233
234 StBusBusyHigh: begin
235 1/1 bus_release_cnt_dec = 1'b1;
Tests: T2 T3 T5
236
237 1/1 if (stop_det) begin
Tests: T2 T3 T5
238 1/1 state_d = StBusBusyStop;
Tests: T49 T50
239 1/1 bus_release_cnt_load = 1'b1;
Tests: T49 T50
240 1/1 bus_release_cnt_sel = 30'(t_buf_i);
Tests: T49 T50
241 1/1 end else if (!bus_idling) begin
Tests: T2 T3 T5
242 1/1 state_d = StBusBusyLow;
Tests: T2 T3 T5
243 1/1 bus_release_cnt_load = 1'b1;
Tests: T2 T3 T5
244 1/1 bus_release_cnt_sel = bus_active_timeout_i;
Tests: T2 T3 T5
245 1/1 end else if (bus_release_cnt == 30'd1) begin
Tests: T2 T3 T5
246 // The host_timeout interrupt occurs regardless of which value of
247 // SDA was present, but only transition to StBusFree if we entered
248 // this state with SDA high. If SDA is low, a change to SCL will
249 // cause a transition back to StBusBusyLow. If SDA changes from low
250 // to high, we get a Stop condition and transition to StBusBusyStop.
251 1/1 bus_inactive_timeout_det = bus_inactive_timeout_en;
Tests: T45 T77 T78
252 1/1 if (sda_i) begin
Tests: T45 T77 T78
253 1/1 state_d = StBusFree;
Tests: T45 T77 T78
254 end
MISSING_ELSE
255 end
MISSING_ELSE
256 end
257
258 StBusBusyStop: begin
259 1/1 bus_release_cnt_dec = 1'b1;
Tests: T2 T3 T5
260
261 1/1 if (!scl_i || !sda_i) begin
Tests: T2 T3 T5
262 1/1 state_d = StBusBusyLow;
Tests: T2 T9 T45
263 1/1 end else if (bus_release_cnt == 30'd1) begin
Tests: T2 T3 T5
264 1/1 state_d = StBusFree;
Tests: T2 T3 T5
265 end
MISSING_ELSE
266 end
267
268 default: begin
269 state_d = StBusFree;
270 end
271 endcase
272 end
273
274 always_ff @(posedge clk_i or negedge rst_ni) begin
275 1/1 if (!rst_ni) begin
Tests: T1 T2 T3
276 1/1 state_q <= StBusFree;
Tests: T1 T2 T3
277 1/1 end else if (!monitor_enable) begin
Tests: T1 T2 T3
278 1/1 state_q <= StBusFree;
Tests: T1 T2 T3
279 1/1 end else if (monitor_enable && !monitor_enable_q) begin
Tests: T1 T2 T3
280 1/1 if (multi_controller_enable_i) begin
Tests: T1 T2 T3
281 // For the multi-controller case, wait until the bus isn't busy before
282 // transmitting.
283 0/1 ==> state_q <= StBusBusyHigh;
284 end else begin
285 1/1 state_q <= StBusFree;
Tests: T1 T2 T3
286 end
287 end else begin
288 1/1 state_q <= state_d;
Tests: T1 T2 T3
289 end
290 end
291
292 always_comb begin
293 1/1 if (multi_controller_enable_i) begin
Tests: T1 T2 T3
294 0/1 ==> bus_free_o = (state_q == StBusFree);
295 end else begin
296 // For single-controller cases, the bus is only "busy" while waiting for the "bus free" time
297 // after a Stop condition. In other words, that is the only time our controller can't
298 // continue to the next transaction.
299 1/1 bus_free_o = (state_q != StBusBusyStop);
Tests: T1 T2 T3
300 end
301 end
302
303 1/1 assign event_bus_active_timeout_o = bus_active_timeout_det_d && !bus_active_timeout_det_q;
Tests: T1 T2 T3
304 1/1 assign event_host_timeout_o = !target_idle_i && bus_inactive_timeout_det;
Tests: T1 T2 T3
Cond Coverage for Module :
i2c_bus_monitor
| Total | Covered | Percent |
|---|
| Conditions | 93 | 83 | 89.25 |
| Logical | 93 | 83 | 89.25 |
| Non-Logical | 0 | 0 | |
| Event | 0 | 0 | |
LINE 37
EXPRESSION (controller_enable_i | target_enable_i | multi_controller_enable_i)
---------1--------- -------2------- ------------3------------
| -1- | -2- | -3- | Status | Tests |
|---|
| 0 | 0 | 0 | Covered | T1,T2,T3 |
| 0 | 0 | 1 | Not Covered | |
| 0 | 1 | 0 | Covered | T2,T3,T5 |
| 1 | 0 | 0 | Covered | T1,T4,T6 |
LINE 84
EXPRESSION (start_det_trigger || stop_det_trigger)
--------1-------- --------2-------
| -1- | -2- | Status | Tests |
|---|
| 0 | 0 | Covered | T1,T2,T3 |
| 0 | 1 | Covered | T2,T3,T5 |
| 1 | 0 | Covered | T1,T2,T3 |
LINE 86
EXPRESSION (start_det_pending || stop_det_pending)
--------1-------- --------2-------
| -1- | -2- | Status | Tests |
|---|
| 0 | 0 | Covered | T1,T2,T3 |
| 0 | 1 | Covered | T2,T3,T5 |
| 1 | 0 | Covered | T1,T2,T3 |
LINE 96
EXPRESSION (((!monitor_enable)) || ((!scl_i)) || start_det || stop_det_trigger)
---------1--------- -----2---- ----3---- --------4-------
| -1- | -2- | -3- | -4- | Status | Tests |
|---|
| 0 | 0 | 0 | 0 | Covered | T1,T2,T3 |
| 0 | 0 | 0 | 1 | Covered | T2,T3,T5 |
| 0 | 0 | 1 | 0 | Covered | T1,T2,T3 |
| 0 | 1 | 0 | 0 | Covered | T1,T2,T3 |
| 1 | 0 | 0 | 0 | Covered | T1,T2,T3 |
LINE 106
EXPRESSION (((!monitor_enable)) || ((!scl_i)) || stop_det || start_det_trigger)
---------1--------- -----2---- ----3--- --------4--------
| -1- | -2- | -3- | -4- | Status | Tests |
|---|
| 0 | 0 | 0 | 0 | Covered | T1,T2,T3 |
| 0 | 0 | 0 | 1 | Covered | T1,T2,T3 |
| 0 | 0 | 1 | 0 | Covered | T2,T3,T5 |
| 0 | 1 | 0 | 0 | Covered | T1,T2,T3 |
| 1 | 0 | 0 | 0 | Covered | T1,T2,T3 |
LINE 112
EXPRESSION (monitor_enable && ((scl_i_q && scl_i) & (sda_i_q && ((!sda_i)))))
-------1------ -----------------------2----------------------
| -1- | -2- | Status | Tests |
|---|
| 0 | 1 | Not Covered | |
| 1 | 0 | Covered | T1,T2,T3 |
| 1 | 1 | Covered | T1,T2,T3 |
LINE 112
SUB-EXPRESSION ((scl_i_q && scl_i) & (sda_i_q && ((!sda_i))))
---------1-------- -----------2-----------
| -1- | -2- | Status | Tests |
|---|
| 0 | 1 | Covered | T1,T2,T3 |
| 1 | 0 | Covered | T1,T2,T3 |
| 1 | 1 | Covered | T1,T2,T3 |
LINE 112
SUB-EXPRESSION (scl_i_q && scl_i)
---1--- --2--
| -1- | -2- | Status | Tests |
|---|
| 0 | 1 | Covered | T1,T2,T3 |
| 1 | 0 | Covered | T1,T2,T3 |
| 1 | 1 | Covered | T1,T2,T3 |
LINE 112
SUB-EXPRESSION (sda_i_q && ((!sda_i)))
---1--- -----2----
| -1- | -2- | Status | Tests |
|---|
| 0 | 1 | Covered | T1,T2,T3 |
| 1 | 0 | Covered | T1,T2,T3 |
| 1 | 1 | Covered | T1,T2,T3 |
LINE 113
EXPRESSION (monitor_enable && start_det_pending && (ctrl_det_count >= 14'(thd_dat_i)))
-------1------ --------2-------- -----------------3----------------
| -1- | -2- | -3- | Status | Tests |
|---|
| 0 | 1 | 1 | Not Covered | |
| 1 | 0 | 1 | Covered | T1,T2,T3 |
| 1 | 1 | 0 | Covered | T1,T10,T11 |
| 1 | 1 | 1 | Covered | T1,T2,T3 |
LINE 117
EXPRESSION (monitor_enable && ((scl_i_q && scl_i) & (((!sda_i_q)) && sda_i)))
-------1------ -----------------------2----------------------
| -1- | -2- | Status | Tests |
|---|
| 0 | 1 | Covered | T26,T27,T79 |
| 1 | 0 | Covered | T1,T2,T3 |
| 1 | 1 | Covered | T2,T3,T5 |
LINE 117
SUB-EXPRESSION ((scl_i_q && scl_i) & (((!sda_i_q)) && sda_i))
---------1-------- -----------2-----------
| -1- | -2- | Status | Tests |
|---|
| 0 | 1 | Covered | T1,T2,T3 |
| 1 | 0 | Covered | T1,T2,T3 |
| 1 | 1 | Covered | T2,T3,T5 |
LINE 117
SUB-EXPRESSION (scl_i_q && scl_i)
---1--- --2--
| -1- | -2- | Status | Tests |
|---|
| 0 | 1 | Covered | T1,T2,T3 |
| 1 | 0 | Covered | T1,T2,T3 |
| 1 | 1 | Covered | T1,T2,T3 |
LINE 117
SUB-EXPRESSION (((!sda_i_q)) && sda_i)
------1----- --2--
| -1- | -2- | Status | Tests |
|---|
| 0 | 1 | Covered | T1,T2,T3 |
| 1 | 0 | Covered | T1,T2,T3 |
| 1 | 1 | Covered | T1,T2,T3 |
LINE 118
EXPRESSION (monitor_enable && stop_det_pending && (ctrl_det_count >= 14'(thd_dat_i)))
-------1------ --------2------- -----------------3----------------
| -1- | -2- | -3- | Status | Tests |
|---|
| 0 | 1 | 1 | Not Covered | |
| 1 | 0 | 1 | Covered | T1,T2,T3 |
| 1 | 1 | 0 | Covered | T10,T11,T25 |
| 1 | 1 | 1 | Covered | T2,T3,T5 |
LINE 127
EXPRESSION (scl_i && (sda_i == sda_i_q))
--1-- ---------2--------
| -1- | -2- | Status | Tests |
|---|
| 0 | 1 | Covered | T1,T2,T3 |
| 1 | 0 | Covered | T1,T2,T3 |
| 1 | 1 | Covered | T1,T2,T3 |
LINE 127
SUB-EXPRESSION (sda_i == sda_i_q)
---------1--------
| -1- | Status | Tests |
|---|
| 0 | Covered | T1,T2,T3 |
| 1 | Covered | T1,T2,T3 |
LINE 160
EXPRESSION (monitor_enable && ((!monitor_enable_q)))
-------1------ ----------2----------
| -1- | -2- | Status | Tests |
|---|
| 0 | 1 | Covered | T1,T2,T3 |
| 1 | 0 | Covered | T1,T2,T3 |
| 1 | 1 | Covered | T1,T2,T3 |
LINE 170
EXPRESSION (bus_release_cnt_dec && (bus_release_cnt != '0))
---------1--------- -----------2-----------
| -1- | -2- | Status | Tests |
|---|
| 0 | 1 | Covered | T26,T27,T28 |
| 1 | 0 | Covered | T1,T2,T3 |
| 1 | 1 | Covered | T1,T2,T3 |
LINE 170
SUB-EXPRESSION (bus_release_cnt != '0)
-----------1-----------
| -1- | Status | Tests |
|---|
| 0 | Covered | T1,T2,T3 |
| 1 | Covered | T1,T2,T3 |
LINE 200
EXPRESSION (((!scl_i)) || ((!sda_i)))
-----1---- -----2----
| -1- | -2- | Status | Tests |
|---|
| 0 | 0 | Covered | T1,T2,T3 |
| 0 | 1 | Covered | T1,T2,T3 |
| 1 | 0 | Covered | T6,T45,T37 |
LINE 214
EXPRESSION (bus_idling && bus_inactive_timeout_en)
-----1---- -----------2-----------
| -1- | -2- | Status | Tests |
|---|
| 0 | 1 | Covered | T2,T3,T5 |
| 1 | 0 | Covered | T1,T4,T8 |
| 1 | 1 | Covered | T2,T3,T5 |
LINE 225
EXPRESSION (bus_release_cnt == 30'b1)
-------------1------------
| -1- | Status | Tests |
|---|
| 0 | Covered | T1,T2,T3 |
| 1 | Covered | T1,T2,T3 |
LINE 245
EXPRESSION (bus_release_cnt == 30'b1)
-------------1------------
| -1- | Status | Tests |
|---|
| 0 | Covered | T2,T3,T5 |
| 1 | Covered | T45,T77,T78 |
LINE 261
EXPRESSION (((!scl_i)) || ((!sda_i)))
-----1---- -----2----
| -1- | -2- | Status | Tests |
|---|
| 0 | 0 | Covered | T2,T3,T5 |
| 0 | 1 | Covered | T2,T9,T45 |
| 1 | 0 | Covered | T49,T50,T80 |
LINE 263
EXPRESSION (bus_release_cnt == 30'b1)
-------------1------------
| -1- | Status | Tests |
|---|
| 0 | Covered | T2,T3,T5 |
| 1 | Covered | T2,T3,T5 |
LINE 279
EXPRESSION (monitor_enable && ((!monitor_enable_q)))
-------1------ ----------2----------
| -1- | -2- | Status | Tests |
|---|
| 0 | 1 | Not Covered | |
| 1 | 0 | Covered | T1,T2,T3 |
| 1 | 1 | Covered | T1,T2,T3 |
LINE 294
EXPRESSION (state_q == StBusFree)
-----------1----------
| -1- | Status | Tests |
|---|
| 0 | Not Covered | |
| 1 | Not Covered | |
LINE 299
EXPRESSION (state_q != StBusBusyStop)
-------------1------------
| -1- | Status | Tests |
|---|
| 0 | Covered | T2,T3,T5 |
| 1 | Covered | T1,T2,T3 |
LINE 303
EXPRESSION (bus_active_timeout_det_d && ((!bus_active_timeout_det_q)))
------------1----------- --------------2--------------
| -1- | -2- | Status | Tests |
|---|
| 0 | 1 | Covered | T1,T2,T3 |
| 1 | 0 | Not Covered | |
| 1 | 1 | Not Covered | |
LINE 304
EXPRESSION (((!target_idle_i)) && bus_inactive_timeout_det)
---------1-------- ------------2-----------
| -1- | -2- | Status | Tests |
|---|
| 0 | 1 | Not Covered | |
| 1 | 0 | Covered | T2,T3,T5 |
| 1 | 1 | Covered | T45,T77,T78 |
FSM Coverage for Module :
i2c_bus_monitor
Summary for FSM :: state_q
| Total | Covered | Percent | |
| States |
4 |
4 |
100.00 |
(Not included in score) |
| Transitions |
11 |
9 |
81.82 |
|
| Sequences |
0 |
0 |
|
|
State, Transition and Sequence Details for FSM :: state_q
| states | Line No. | Covered | Tests |
| StBusBusyHigh |
283 |
Covered |
T2,T3,T5 |
| StBusBusyLow |
201 |
Covered |
T1,T2,T3 |
| StBusBusyStop |
211 |
Covered |
T2,T3,T5 |
| StBusFree |
278 |
Covered |
T1,T2,T3 |
| transitions | Line No. | Covered | Tests |
| StBusBusyHigh->StBusBusyLow |
242 |
Covered |
T2,T3,T5 |
| StBusBusyHigh->StBusBusyStop |
238 |
Covered |
T49,T50 |
| StBusBusyHigh->StBusFree |
278 |
Covered |
T45,T77,T78 |
| StBusBusyLow->StBusBusyHigh |
283 |
Covered |
T2,T3,T5 |
| StBusBusyLow->StBusBusyStop |
211 |
Covered |
T2,T3,T5 |
| StBusBusyLow->StBusFree |
278 |
Covered |
T1,T19,T20 |
| StBusBusyStop->StBusBusyHigh |
283 |
Not Covered |
|
| StBusBusyStop->StBusBusyLow |
262 |
Covered |
T2,T9,T45 |
| StBusBusyStop->StBusFree |
278 |
Covered |
T2,T3,T5 |
| StBusFree->StBusBusyHigh |
283 |
Not Covered |
|
| StBusFree->StBusBusyLow |
201 |
Covered |
T1,T2,T3 |
Branch Coverage for Module :
i2c_bus_monitor
| Line No. | Total | Covered | Percent |
| Branches |
|
48 |
43 |
89.58 |
| IF |
40 |
2 |
2 |
100.00 |
| IF |
50 |
2 |
2 |
100.00 |
| IF |
82 |
4 |
4 |
100.00 |
| IF |
92 |
4 |
4 |
100.00 |
| IF |
102 |
4 |
4 |
100.00 |
| IF |
147 |
2 |
2 |
100.00 |
| IF |
158 |
6 |
5 |
83.33 |
| CASE |
196 |
17 |
15 |
88.24 |
| IF |
275 |
5 |
4 |
80.00 |
| IF |
293 |
2 |
1 |
50.00 |
40 if (!rst_ni) begin
-1-
41 monitor_enable_q <= 1'b0;
==>
42 end else begin
43 monitor_enable_q <= monitor_enable;
==>
Branches:
| -1- | Status | Tests |
| 1 |
Covered |
T1,T2,T3 |
| 0 |
Covered |
T1,T2,T3 |
50 if (!rst_ni) begin
-1-
51 scl_i_q <= 1'b1;
==>
52 sda_i_q <= 1'b1;
53 end else begin
54 scl_i_q <= scl_i;
==>
Branches:
| -1- | Status | Tests |
| 1 |
Covered |
T1,T2,T3 |
| 0 |
Covered |
T1,T2,T3 |
82 if (!rst_ni) begin
-1-
83 ctrl_det_count <= '0;
==>
84 end else if (start_det_trigger || stop_det_trigger) begin
-2-
85 ctrl_det_count <= 14'd1;
==>
86 end else if (start_det_pending || stop_det_pending) begin
-3-
87 ctrl_det_count <= ctrl_det_count + 1'b1;
==>
88 end
MISSING_ELSE
==>
Branches:
| -1- | -2- | -3- | Status | Tests |
| 1 |
- |
- |
Covered |
T1,T2,T3 |
| 0 |
1 |
- |
Covered |
T1,T2,T3 |
| 0 |
0 |
1 |
Covered |
T1,T2,T3 |
| 0 |
0 |
0 |
Covered |
T1,T2,T3 |
92 if (!rst_ni) begin
-1-
93 start_det_pending <= 1'b0;
==>
94 end else if (start_det_trigger) begin
-2-
95 start_det_pending <= 1'b1;
==>
96 end else if (!monitor_enable || !scl_i || start_det || stop_det_trigger) begin
-3-
97 start_det_pending <= 1'b0;
==>
98 end
MISSING_ELSE
==>
Branches:
| -1- | -2- | -3- | Status | Tests |
| 1 |
- |
- |
Covered |
T1,T2,T3 |
| 0 |
1 |
- |
Covered |
T1,T2,T3 |
| 0 |
0 |
1 |
Covered |
T1,T2,T3 |
| 0 |
0 |
0 |
Covered |
T1,T2,T3 |
102 if (!rst_ni) begin
-1-
103 stop_det_pending <= 1'b0;
==>
104 end else if (stop_det_trigger) begin
-2-
105 stop_det_pending <= 1'b1;
==>
106 end else if (!monitor_enable || !scl_i || stop_det || start_det_trigger) begin
-3-
107 stop_det_pending <= 1'b0;
==>
108 end
MISSING_ELSE
==>
Branches:
| -1- | -2- | -3- | Status | Tests |
| 1 |
- |
- |
Covered |
T1,T2,T3 |
| 0 |
1 |
- |
Covered |
T2,T3,T5 |
| 0 |
0 |
1 |
Covered |
T1,T2,T3 |
| 0 |
0 |
0 |
Covered |
T1,T2,T3 |
147 if (!rst_ni) begin
-1-
148 bus_active_timeout_det_q <= 1'b0;
==>
149 end else begin
150 bus_active_timeout_det_q <= bus_active_timeout_det_d;
==>
Branches:
| -1- | Status | Tests |
| 1 |
Covered |
T1,T2,T3 |
| 0 |
Covered |
T1,T2,T3 |
158 if (!rst_ni) begin
-1-
159 bus_release_cnt <= '0;
==>
160 end else if (monitor_enable && !monitor_enable_q) begin
-2-
161 // The rising edge of monitor enable resets the counter for
162 // multi-controller mode.
163 if (multi_controller_enable_i) begin
-3-
164 // For the multi-controller case, wait until the bus isn't busy before
165 // transmitting.
166 bus_release_cnt <= 30'(bus_inactive_timeout_i);
==>
167 end
MISSING_ELSE
==>
168 end else if (bus_release_cnt_load) begin
-4-
169 bus_release_cnt <= bus_release_cnt_sel;
==>
170 end else if (bus_release_cnt_dec && (bus_release_cnt != '0)) begin
-5-
171 bus_release_cnt <= bus_release_cnt - 1'b1;
==>
172 end
MISSING_ELSE
==>
Branches:
| -1- | -2- | -3- | -4- | -5- | Status | Tests |
| 1 |
- |
- |
- |
- |
Covered |
T1,T2,T3 |
| 0 |
1 |
1 |
- |
- |
Not Covered |
|
| 0 |
1 |
0 |
- |
- |
Covered |
T1,T2,T3 |
| 0 |
0 |
- |
1 |
- |
Covered |
T1,T2,T3 |
| 0 |
0 |
- |
0 |
1 |
Covered |
T1,T2,T3 |
| 0 |
0 |
- |
0 |
0 |
Covered |
T1,T2,T3 |
196 unique case (state_q)
-1-
197 StBusFree: begin
198 bus_active_timeout_det_d = 1'b0;
199
200 if (!scl_i || !sda_i) begin
-2-
201 state_d = StBusBusyLow;
==>
202 bus_release_cnt_load = 1'b1;
203 bus_release_cnt_sel = bus_active_timeout_i;
204 end
MISSING_ELSE
==>
205 end
206
207 StBusBusyLow: begin
208 bus_release_cnt_dec = !scl_i;
209
210 if (stop_det) begin
-3-
211 state_d = StBusBusyStop;
==>
212 bus_release_cnt_load = 1'b1;
213 bus_release_cnt_sel = 30'(t_buf_i);
214 end else if (bus_idling && bus_inactive_timeout_en) begin
-4-
215 state_d = StBusBusyHigh;
==>
216 bus_release_cnt_load = 1'b1;
217 bus_release_cnt_sel = 30'(bus_inactive_timeout_i);
218 end else if (scl_i) begin
-5-
219 bus_release_cnt_load = 1'b1;
220 bus_release_cnt_sel = bus_active_timeout_i;
221 if (bus_active_timeout_det_q) begin
-6-
222 // SCL was released due to the bus timeout, so go to BusFree.
223 state_d = StBusFree;
==>
224 end
MISSING_ELSE
==>
225 end else if (bus_release_cnt == 30'd1) begin
-7-
226 // The active timeout occurs when SCL has been held continuously low
227 // for too long. Both the controller and target should respond to
228 // this timeout and release the bus. We don't consider the bus free
229 // yet, though: SCL must be released first.
230 bus_active_timeout_det_d = bus_active_timeout_en_i;
==>
231 end
MISSING_ELSE
==>
232 end
233
234 StBusBusyHigh: begin
235 bus_release_cnt_dec = 1'b1;
236
237 if (stop_det) begin
-8-
238 state_d = StBusBusyStop;
==>
239 bus_release_cnt_load = 1'b1;
240 bus_release_cnt_sel = 30'(t_buf_i);
241 end else if (!bus_idling) begin
-9-
242 state_d = StBusBusyLow;
==>
243 bus_release_cnt_load = 1'b1;
244 bus_release_cnt_sel = bus_active_timeout_i;
245 end else if (bus_release_cnt == 30'd1) begin
-10-
246 // The host_timeout interrupt occurs regardless of which value of
247 // SDA was present, but only transition to StBusFree if we entered
248 // this state with SDA high. If SDA is low, a change to SCL will
249 // cause a transition back to StBusBusyLow. If SDA changes from low
250 // to high, we get a Stop condition and transition to StBusBusyStop.
251 bus_inactive_timeout_det = bus_inactive_timeout_en;
252 if (sda_i) begin
-11-
253 state_d = StBusFree;
==>
254 end
MISSING_ELSE
==>
255 end
MISSING_ELSE
==>
256 end
257
258 StBusBusyStop: begin
259 bus_release_cnt_dec = 1'b1;
260
261 if (!scl_i || !sda_i) begin
-12-
262 state_d = StBusBusyLow;
==>
263 end else if (bus_release_cnt == 30'd1) begin
-13-
264 state_d = StBusFree;
==>
265 end
MISSING_ELSE
==>
266 end
267
268 default: begin
269 state_d = StBusFree;
==>
Branches:
| -1- | -2- | -3- | -4- | -5- | -6- | -7- | -8- | -9- | -10- | -11- | -12- | -13- | Status | Tests |
| StBusFree |
1 |
- |
- |
- |
- |
- |
- |
- |
- |
- |
- |
- |
Covered |
T1,T2,T3 |
| StBusFree |
0 |
- |
- |
- |
- |
- |
- |
- |
- |
- |
- |
- |
Covered |
T1,T2,T3 |
| StBusBusyLow |
- |
1 |
- |
- |
- |
- |
- |
- |
- |
- |
- |
- |
Covered |
T2,T3,T5 |
| StBusBusyLow |
- |
0 |
1 |
- |
- |
- |
- |
- |
- |
- |
- |
- |
Covered |
T2,T3,T5 |
| StBusBusyLow |
- |
0 |
0 |
1 |
1 |
- |
- |
- |
- |
- |
- |
- |
Not Covered |
|
| StBusBusyLow |
- |
0 |
0 |
1 |
0 |
- |
- |
- |
- |
- |
- |
- |
Covered |
T1,T4,T8 |
| StBusBusyLow |
- |
0 |
0 |
0 |
- |
1 |
- |
- |
- |
- |
- |
- |
Covered |
T1,T2,T3 |
| StBusBusyLow |
- |
0 |
0 |
0 |
- |
0 |
- |
- |
- |
- |
- |
- |
Covered |
T1,T2,T3 |
| StBusBusyHigh |
- |
- |
- |
- |
- |
- |
1 |
- |
- |
- |
- |
- |
Covered |
T49,T50 |
| StBusBusyHigh |
- |
- |
- |
- |
- |
- |
0 |
1 |
- |
- |
- |
- |
Covered |
T2,T3,T5 |
| StBusBusyHigh |
- |
- |
- |
- |
- |
- |
0 |
0 |
1 |
1 |
- |
- |
Covered |
T45,T77,T78 |
| StBusBusyHigh |
- |
- |
- |
- |
- |
- |
0 |
0 |
1 |
0 |
- |
- |
Covered |
T45,T77,T78 |
| StBusBusyHigh |
- |
- |
- |
- |
- |
- |
0 |
0 |
0 |
- |
- |
- |
Covered |
T2,T3,T5 |
| StBusBusyStop |
- |
- |
- |
- |
- |
- |
- |
- |
- |
- |
1 |
- |
Covered |
T2,T9,T45 |
| StBusBusyStop |
- |
- |
- |
- |
- |
- |
- |
- |
- |
- |
0 |
1 |
Covered |
T2,T3,T5 |
| StBusBusyStop |
- |
- |
- |
- |
- |
- |
- |
- |
- |
- |
0 |
0 |
Covered |
T2,T3,T5 |
| default |
- |
- |
- |
- |
- |
- |
- |
- |
- |
- |
- |
- |
Not Covered |
|
275 if (!rst_ni) begin
-1-
276 state_q <= StBusFree;
==>
277 end else if (!monitor_enable) begin
-2-
278 state_q <= StBusFree;
==>
279 end else if (monitor_enable && !monitor_enable_q) begin
-3-
280 if (multi_controller_enable_i) begin
-4-
281 // For the multi-controller case, wait until the bus isn't busy before
282 // transmitting.
283 state_q <= StBusBusyHigh;
==>
284 end else begin
285 state_q <= StBusFree;
==>
286 end
287 end else begin
288 state_q <= state_d;
==>
Branches:
| -1- | -2- | -3- | -4- | Status | Tests |
| 1 |
- |
- |
- |
Covered |
T1,T2,T3 |
| 0 |
1 |
- |
- |
Covered |
T1,T2,T3 |
| 0 |
0 |
1 |
1 |
Not Covered |
|
| 0 |
0 |
1 |
0 |
Covered |
T1,T2,T3 |
| 0 |
0 |
0 |
- |
Covered |
T1,T2,T3 |
293 if (multi_controller_enable_i) begin
-1-
294 bus_free_o = (state_q == StBusFree);
==>
295 end else begin
296 // For single-controller cases, the bus is only "busy" while waiting for the "bus free" time
297 // after a Stop condition. In other words, that is the only time our controller can't
298 // continue to the next transaction.
299 bus_free_o = (state_q != StBusBusyStop);
==>
Branches:
| -1- | Status | Tests |
| 1 |
Not Covered |
|
| 0 |
Covered |
T1,T2,T3 |