Module Definition
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Module : prim_subreg_arb
SCORELINECONDTOGGLEFSMBRANCHASSERT
95.83 87.50 100.00 100.00

Source File(s) :
/workspaces/repo/scratch/os_regression_2024_09_08/i2c-sim-vcs/default/sim-vcs/../src/lowrisc_prim_subreg_0/rtl/prim_subreg_arb.sv

Module self-instances :
NAME   SCORE   LINE   COND   TOGGLE   FSM   BRANCH   ASSERT   
tb.dut.u_reg.u_intr_state_fmt_threshold.wr_en_data_arb 50.00 50.00
tb.dut.u_reg.u_intr_state_rx_threshold.wr_en_data_arb 50.00 50.00
tb.dut.u_reg.u_intr_state_acq_threshold.wr_en_data_arb 50.00 50.00
tb.dut.u_reg.u_intr_state_controller_halt.wr_en_data_arb 50.00 50.00
tb.dut.u_reg.u_intr_state_tx_stretch.wr_en_data_arb 50.00 50.00
tb.dut.u_reg.u_intr_state_tx_threshold.wr_en_data_arb 50.00 50.00
tb.dut.u_reg.u_intr_state_acq_stretch.wr_en_data_arb 50.00 50.00
tb.dut.u_reg.u_controller_events_unhandled_nack_timeout.wr_en_data_arb 80.00 100.00 60.00
tb.dut.u_reg.u_controller_events_bus_timeout.wr_en_data_arb 80.00 100.00 60.00
tb.dut.u_reg.u_target_events_bus_timeout.wr_en_data_arb 80.00 100.00 60.00
tb.dut.u_reg.u_target_events_arbitration_lost.wr_en_data_arb 80.00 100.00 60.00
tb.dut.u_reg.u_controller_events_arbitration_lost.wr_en_data_arb 95.00 100.00 90.00
tb.dut.u_reg.u_intr_state_rx_overflow.wr_en_data_arb 100.00 100.00 100.00
tb.dut.u_reg.u_intr_state_scl_interference.wr_en_data_arb 100.00 100.00 100.00
tb.dut.u_reg.u_intr_state_sda_interference.wr_en_data_arb 100.00 100.00 100.00
tb.dut.u_reg.u_intr_state_stretch_timeout.wr_en_data_arb 100.00 100.00 100.00
tb.dut.u_reg.u_intr_state_sda_unstable.wr_en_data_arb 100.00 100.00 100.00
tb.dut.u_reg.u_intr_state_cmd_complete.wr_en_data_arb 100.00 100.00 100.00
tb.dut.u_reg.u_intr_state_unexp_stop.wr_en_data_arb 100.00 100.00 100.00
tb.dut.u_reg.u_intr_state_host_timeout.wr_en_data_arb 100.00 100.00 100.00
tb.dut.u_reg.u_intr_enable_fmt_threshold.wr_en_data_arb 100.00 100.00 100.00 100.00
tb.dut.u_reg.u_intr_enable_rx_threshold.wr_en_data_arb 100.00 100.00 100.00 100.00
tb.dut.u_reg.u_intr_enable_acq_threshold.wr_en_data_arb 100.00 100.00 100.00 100.00
tb.dut.u_reg.u_intr_enable_rx_overflow.wr_en_data_arb 100.00 100.00 100.00 100.00
tb.dut.u_reg.u_intr_enable_controller_halt.wr_en_data_arb 100.00 100.00 100.00 100.00
tb.dut.u_reg.u_intr_enable_scl_interference.wr_en_data_arb 100.00 100.00 100.00 100.00
tb.dut.u_reg.u_intr_enable_sda_interference.wr_en_data_arb 100.00 100.00 100.00 100.00
tb.dut.u_reg.u_intr_enable_stretch_timeout.wr_en_data_arb 100.00 100.00 100.00 100.00
tb.dut.u_reg.u_intr_enable_sda_unstable.wr_en_data_arb 100.00 100.00 100.00 100.00
tb.dut.u_reg.u_intr_enable_cmd_complete.wr_en_data_arb 100.00 100.00 100.00 100.00
tb.dut.u_reg.u_intr_enable_tx_stretch.wr_en_data_arb 100.00 100.00 100.00 100.00
tb.dut.u_reg.u_intr_enable_tx_threshold.wr_en_data_arb 100.00 100.00 100.00 100.00
tb.dut.u_reg.u_intr_enable_acq_stretch.wr_en_data_arb 100.00 100.00 100.00 100.00
tb.dut.u_reg.u_intr_enable_unexp_stop.wr_en_data_arb 100.00 100.00 100.00 100.00
tb.dut.u_reg.u_intr_enable_host_timeout.wr_en_data_arb 100.00 100.00 100.00 100.00
tb.dut.u_reg.u_ctrl_enablehost.wr_en_data_arb 100.00 100.00 100.00 100.00
tb.dut.u_reg.u_ctrl_enabletarget.wr_en_data_arb 100.00 100.00 100.00 100.00
tb.dut.u_reg.u_ctrl_llpbk.wr_en_data_arb 100.00 100.00 100.00 100.00
tb.dut.u_reg.u_ctrl_nack_addr_after_timeout.wr_en_data_arb 100.00 100.00 100.00 100.00
tb.dut.u_reg.u_ctrl_ack_ctrl_en.wr_en_data_arb 100.00 100.00 100.00 100.00
tb.dut.u_reg.u_ctrl_multi_controller_monitor_en.wr_en_data_arb 100.00 100.00 100.00 100.00
tb.dut.u_reg.u_ctrl_tx_stretch_ctrl_en.wr_en_data_arb 100.00 100.00 100.00 100.00
tb.dut.u_reg.u_fdata_fbyte.wr_en_data_arb 100.00 100.00 100.00 100.00
tb.dut.u_reg.u_fdata_start.wr_en_data_arb 100.00 100.00 100.00 100.00
tb.dut.u_reg.u_fdata_stop.wr_en_data_arb 100.00 100.00 100.00 100.00
tb.dut.u_reg.u_fdata_readb.wr_en_data_arb 100.00 100.00 100.00 100.00
tb.dut.u_reg.u_fdata_rcont.wr_en_data_arb 100.00 100.00 100.00 100.00
tb.dut.u_reg.u_fdata_nakok.wr_en_data_arb 100.00 100.00 100.00 100.00
tb.dut.u_reg.u_fifo_ctrl_rxrst.wr_en_data_arb 100.00 100.00 100.00 100.00
tb.dut.u_reg.u_fifo_ctrl_fmtrst.wr_en_data_arb 100.00 100.00 100.00 100.00
tb.dut.u_reg.u_fifo_ctrl_acqrst.wr_en_data_arb 100.00 100.00 100.00 100.00
tb.dut.u_reg.u_fifo_ctrl_txrst.wr_en_data_arb 100.00 100.00 100.00 100.00
tb.dut.u_reg.u_host_fifo_config_rx_thresh.wr_en_data_arb 100.00 100.00 100.00 100.00
tb.dut.u_reg.u_host_fifo_config_fmt_thresh.wr_en_data_arb 100.00 100.00 100.00 100.00
tb.dut.u_reg.u_target_fifo_config_tx_thresh.wr_en_data_arb 100.00 100.00 100.00 100.00
tb.dut.u_reg.u_target_fifo_config_acq_thresh.wr_en_data_arb 100.00 100.00 100.00 100.00
tb.dut.u_reg.u_ovrd_txovrden.wr_en_data_arb 100.00 100.00 100.00 100.00
tb.dut.u_reg.u_ovrd_sclval.wr_en_data_arb 100.00 100.00 100.00 100.00
tb.dut.u_reg.u_ovrd_sdaval.wr_en_data_arb 100.00 100.00 100.00 100.00
tb.dut.u_reg.u_timing0_thigh.wr_en_data_arb 100.00 100.00 100.00 100.00
tb.dut.u_reg.u_timing0_tlow.wr_en_data_arb 100.00 100.00 100.00 100.00
tb.dut.u_reg.u_timing1_t_r.wr_en_data_arb 100.00 100.00 100.00 100.00
tb.dut.u_reg.u_timing1_t_f.wr_en_data_arb 100.00 100.00 100.00 100.00
tb.dut.u_reg.u_timing2_tsu_sta.wr_en_data_arb 100.00 100.00 100.00 100.00
tb.dut.u_reg.u_timing2_thd_sta.wr_en_data_arb 100.00 100.00 100.00 100.00
tb.dut.u_reg.u_timing3_tsu_dat.wr_en_data_arb 100.00 100.00 100.00 100.00
tb.dut.u_reg.u_timing3_thd_dat.wr_en_data_arb 100.00 100.00 100.00 100.00
tb.dut.u_reg.u_timing4_tsu_sto.wr_en_data_arb 100.00 100.00 100.00 100.00
tb.dut.u_reg.u_timing4_t_buf.wr_en_data_arb 100.00 100.00 100.00 100.00
tb.dut.u_reg.u_timeout_ctrl_val.wr_en_data_arb 100.00 100.00 100.00 100.00
tb.dut.u_reg.u_timeout_ctrl_mode.wr_en_data_arb 100.00 100.00 100.00 100.00
tb.dut.u_reg.u_timeout_ctrl_en.wr_en_data_arb 100.00 100.00 100.00 100.00
tb.dut.u_reg.u_target_id_address0.wr_en_data_arb 100.00 100.00 100.00 100.00
tb.dut.u_reg.u_target_id_mask0.wr_en_data_arb 100.00 100.00 100.00 100.00
tb.dut.u_reg.u_target_id_address1.wr_en_data_arb 100.00 100.00 100.00 100.00
tb.dut.u_reg.u_target_id_mask1.wr_en_data_arb 100.00 100.00 100.00 100.00
tb.dut.u_reg.u_txdata.wr_en_data_arb 100.00 100.00 100.00 100.00
tb.dut.u_reg.u_host_timeout_ctrl.wr_en_data_arb 100.00 100.00 100.00 100.00
tb.dut.u_reg.u_target_timeout_ctrl_val.wr_en_data_arb 100.00 100.00 100.00 100.00
tb.dut.u_reg.u_target_timeout_ctrl_en.wr_en_data_arb 100.00 100.00 100.00 100.00
tb.dut.u_reg.u_target_nack_count.wr_en_data_arb 100.00 100.00 100.00
tb.dut.u_reg.u_host_nack_handler_timeout_val.wr_en_data_arb 100.00 100.00 100.00 100.00
tb.dut.u_reg.u_host_nack_handler_timeout_en.wr_en_data_arb 100.00 100.00 100.00 100.00
tb.dut.u_reg.u_controller_events_nack.wr_en_data_arb 100.00 100.00 100.00
tb.dut.u_reg.u_target_events_tx_pending.wr_en_data_arb 100.00 100.00 100.00

Line Coverage for Module : prim_subreg_arb ( parameter DW=1,SwAccess=1,Mubi=0 )
Line Coverage for Module self-instances :
SCORELINE
50.00 50.00
tb.dut.u_reg.u_intr_state_fmt_threshold.wr_en_data_arb

SCORELINE
50.00 50.00
tb.dut.u_reg.u_intr_state_rx_threshold.wr_en_data_arb

SCORELINE
50.00 50.00
tb.dut.u_reg.u_intr_state_acq_threshold.wr_en_data_arb

SCORELINE
50.00 50.00
tb.dut.u_reg.u_intr_state_controller_halt.wr_en_data_arb

SCORELINE
50.00 50.00
tb.dut.u_reg.u_intr_state_tx_stretch.wr_en_data_arb

SCORELINE
50.00 50.00
tb.dut.u_reg.u_intr_state_tx_threshold.wr_en_data_arb

SCORELINE
50.00 50.00
tb.dut.u_reg.u_intr_state_acq_stretch.wr_en_data_arb

Line No.TotalCoveredPercent
TOTAL2150.00
CONT_ASSIGN43100.00
CONT_ASSIGN4411100.00
CONT_ASSIGN5100
CONT_ASSIGN5200
CONT_ASSIGN5300

42 end else if (SwAccess == SwAccessRO) begin : gen_ro 43 0/1 ==> assign wr_en = de; 44 1/1 assign wr_data = d; Tests: T1 T2 T3  45 // Unused we, wd, q - Prevent lint errors. 46 logic unused_we; 47 logic [DW-1:0] unused_wd; 48 logic [DW-1:0] unused_q; 49 //VCS coverage off 50 // pragma coverage off 51 unreachable assign unused_we = we; 52 unreachable assign unused_wd = wd; 53 unreachable assign unused_q = q;

Line Coverage for Module : prim_subreg_arb ( parameter DW=1,SwAccess=3,Mubi=0 )
Line Coverage for Module self-instances :
SCORELINE
100.00 100.00
tb.dut.u_reg.u_intr_state_rx_overflow.wr_en_data_arb

SCORELINE
100.00 100.00
tb.dut.u_reg.u_intr_state_scl_interference.wr_en_data_arb

SCORELINE
100.00 100.00
tb.dut.u_reg.u_intr_state_sda_interference.wr_en_data_arb

SCORELINE
100.00 100.00
tb.dut.u_reg.u_intr_state_stretch_timeout.wr_en_data_arb

SCORELINE
100.00 100.00
tb.dut.u_reg.u_intr_state_sda_unstable.wr_en_data_arb

SCORELINE
100.00 100.00
tb.dut.u_reg.u_intr_state_cmd_complete.wr_en_data_arb

SCORELINE
100.00 100.00
tb.dut.u_reg.u_intr_state_unexp_stop.wr_en_data_arb

SCORELINE
100.00 100.00
tb.dut.u_reg.u_intr_state_host_timeout.wr_en_data_arb

SCORELINE
100.00 100.00
tb.dut.u_reg.u_controller_events_nack.wr_en_data_arb

SCORELINE
80.00 100.00
tb.dut.u_reg.u_controller_events_unhandled_nack_timeout.wr_en_data_arb

SCORELINE
80.00 100.00
tb.dut.u_reg.u_controller_events_bus_timeout.wr_en_data_arb

SCORELINE
95.00 100.00
tb.dut.u_reg.u_controller_events_arbitration_lost.wr_en_data_arb

SCORELINE
100.00 100.00
tb.dut.u_reg.u_target_events_tx_pending.wr_en_data_arb

SCORELINE
80.00 100.00
tb.dut.u_reg.u_target_events_bus_timeout.wr_en_data_arb

SCORELINE
80.00 100.00
tb.dut.u_reg.u_target_events_arbitration_lost.wr_en_data_arb

Line No.TotalCoveredPercent
TOTAL22100.00
CONT_ASSIGN8811100.00
CONT_ASSIGN11011100.00

87 // If both try to set/clr at the same bit pos, SW wins. 88 1/1 assign wr_en = we | de; Tests: T1 T2 T3  89 if (Mubi) begin : gen_mubi 90 if (DW == 4) begin : gen_mubi4 91 assign wr_data = prim_mubi_pkg::mubi4_and_hi(prim_mubi_pkg::mubi4_t'(de ? d : q), 92 (we ? prim_mubi_pkg::mubi4_t'(~wd) : 93 prim_mubi_pkg::MuBi4True)); 94 end else if (DW == 8) begin : gen_mubi8 95 assign wr_data = prim_mubi_pkg::mubi8_and_hi(prim_mubi_pkg::mubi8_t'(de ? d : q), 96 (we ? prim_mubi_pkg::mubi8_t'(~wd) : 97 prim_mubi_pkg::MuBi8True)); 98 end else if (DW == 12) begin : gen_mubi12 99 assign wr_data = prim_mubi_pkg::mubi12_and_hi(prim_mubi_pkg::mubi12_t'(de ? d : q), 100 (we ? prim_mubi_pkg::mubi12_t'(~wd) : 101 prim_mubi_pkg::MuBi12True)); 102 end else if (DW == 16) begin : gen_mubi16 103 assign wr_data = prim_mubi_pkg::mubi16_and_hi(prim_mubi_pkg::mubi16_t'(de ? d : q), 104 (we ? prim_mubi_pkg::mubi16_t'(~wd) : 105 prim_mubi_pkg::MuBi16True)); 106 end else begin : gen_invalid_mubi 107 $error("%m: Invalid width for MuBi"); 108 end 109 end else begin : gen_non_mubi 110 1/1 assign wr_data = (de ? d : q) & (we ? ~wd : '1); Tests: T1 T2 T3 

Line Coverage for Module : prim_subreg_arb ( parameter DW=1,SwAccess=0,Mubi=0 + DW=8,SwAccess=2,Mubi=0 + DW=12,SwAccess=0,Mubi=0 + DW=13,SwAccess=0,Mubi=0 + DW=10,SwAccess=0,Mubi=0 + DW=9,SwAccess=0,Mubi=0 + DW=30,SwAccess=0,Mubi=0 + DW=7,SwAccess=0,Mubi=0 + DW=20,SwAccess=0,Mubi=0 + DW=31,SwAccess=0,Mubi=0 )
Line Coverage for Module self-instances :
SCORELINE
100.00 100.00
tb.dut.u_reg.u_intr_enable_fmt_threshold.wr_en_data_arb

SCORELINE
100.00 100.00
tb.dut.u_reg.u_intr_enable_rx_threshold.wr_en_data_arb

SCORELINE
100.00 100.00
tb.dut.u_reg.u_intr_enable_acq_threshold.wr_en_data_arb

SCORELINE
100.00 100.00
tb.dut.u_reg.u_intr_enable_rx_overflow.wr_en_data_arb

SCORELINE
100.00 100.00
tb.dut.u_reg.u_intr_enable_controller_halt.wr_en_data_arb

SCORELINE
100.00 100.00
tb.dut.u_reg.u_intr_enable_scl_interference.wr_en_data_arb

SCORELINE
100.00 100.00
tb.dut.u_reg.u_intr_enable_sda_interference.wr_en_data_arb

SCORELINE
100.00 100.00
tb.dut.u_reg.u_intr_enable_stretch_timeout.wr_en_data_arb

SCORELINE
100.00 100.00
tb.dut.u_reg.u_intr_enable_sda_unstable.wr_en_data_arb

SCORELINE
100.00 100.00
tb.dut.u_reg.u_intr_enable_cmd_complete.wr_en_data_arb

SCORELINE
100.00 100.00
tb.dut.u_reg.u_intr_enable_tx_stretch.wr_en_data_arb

SCORELINE
100.00 100.00
tb.dut.u_reg.u_intr_enable_tx_threshold.wr_en_data_arb

SCORELINE
100.00 100.00
tb.dut.u_reg.u_intr_enable_acq_stretch.wr_en_data_arb

SCORELINE
100.00 100.00
tb.dut.u_reg.u_intr_enable_unexp_stop.wr_en_data_arb

SCORELINE
100.00 100.00
tb.dut.u_reg.u_intr_enable_host_timeout.wr_en_data_arb

SCORELINE
100.00 100.00
tb.dut.u_reg.u_ctrl_enablehost.wr_en_data_arb

SCORELINE
100.00 100.00
tb.dut.u_reg.u_ctrl_enabletarget.wr_en_data_arb

SCORELINE
100.00 100.00
tb.dut.u_reg.u_ctrl_llpbk.wr_en_data_arb

SCORELINE
100.00 100.00
tb.dut.u_reg.u_ctrl_nack_addr_after_timeout.wr_en_data_arb

SCORELINE
100.00 100.00
tb.dut.u_reg.u_ctrl_ack_ctrl_en.wr_en_data_arb

SCORELINE
100.00 100.00
tb.dut.u_reg.u_ctrl_multi_controller_monitor_en.wr_en_data_arb

SCORELINE
100.00 100.00
tb.dut.u_reg.u_ctrl_tx_stretch_ctrl_en.wr_en_data_arb

SCORELINE
100.00 100.00
tb.dut.u_reg.u_fdata_fbyte.wr_en_data_arb

SCORELINE
100.00 100.00
tb.dut.u_reg.u_fdata_start.wr_en_data_arb

SCORELINE
100.00 100.00
tb.dut.u_reg.u_fdata_stop.wr_en_data_arb

SCORELINE
100.00 100.00
tb.dut.u_reg.u_fdata_readb.wr_en_data_arb

SCORELINE
100.00 100.00
tb.dut.u_reg.u_fdata_rcont.wr_en_data_arb

SCORELINE
100.00 100.00
tb.dut.u_reg.u_fdata_nakok.wr_en_data_arb

SCORELINE
100.00 100.00
tb.dut.u_reg.u_fifo_ctrl_rxrst.wr_en_data_arb

SCORELINE
100.00 100.00
tb.dut.u_reg.u_fifo_ctrl_fmtrst.wr_en_data_arb

SCORELINE
100.00 100.00
tb.dut.u_reg.u_fifo_ctrl_acqrst.wr_en_data_arb

SCORELINE
100.00 100.00
tb.dut.u_reg.u_fifo_ctrl_txrst.wr_en_data_arb

SCORELINE
100.00 100.00
tb.dut.u_reg.u_host_fifo_config_rx_thresh.wr_en_data_arb

SCORELINE
100.00 100.00
tb.dut.u_reg.u_host_fifo_config_fmt_thresh.wr_en_data_arb

SCORELINE
100.00 100.00
tb.dut.u_reg.u_target_fifo_config_tx_thresh.wr_en_data_arb

SCORELINE
100.00 100.00
tb.dut.u_reg.u_target_fifo_config_acq_thresh.wr_en_data_arb

SCORELINE
100.00 100.00
tb.dut.u_reg.u_ovrd_txovrden.wr_en_data_arb

SCORELINE
100.00 100.00
tb.dut.u_reg.u_ovrd_sclval.wr_en_data_arb

SCORELINE
100.00 100.00
tb.dut.u_reg.u_ovrd_sdaval.wr_en_data_arb

SCORELINE
100.00 100.00
tb.dut.u_reg.u_timing0_thigh.wr_en_data_arb

SCORELINE
100.00 100.00
tb.dut.u_reg.u_timing0_tlow.wr_en_data_arb

SCORELINE
100.00 100.00
tb.dut.u_reg.u_timing1_t_r.wr_en_data_arb

SCORELINE
100.00 100.00
tb.dut.u_reg.u_timing1_t_f.wr_en_data_arb

SCORELINE
100.00 100.00
tb.dut.u_reg.u_timing2_tsu_sta.wr_en_data_arb

SCORELINE
100.00 100.00
tb.dut.u_reg.u_timing2_thd_sta.wr_en_data_arb

SCORELINE
100.00 100.00
tb.dut.u_reg.u_timing3_tsu_dat.wr_en_data_arb

SCORELINE
100.00 100.00
tb.dut.u_reg.u_timing3_thd_dat.wr_en_data_arb

SCORELINE
100.00 100.00
tb.dut.u_reg.u_timing4_tsu_sto.wr_en_data_arb

SCORELINE
100.00 100.00
tb.dut.u_reg.u_timing4_t_buf.wr_en_data_arb

SCORELINE
100.00 100.00
tb.dut.u_reg.u_timeout_ctrl_val.wr_en_data_arb

SCORELINE
100.00 100.00
tb.dut.u_reg.u_timeout_ctrl_mode.wr_en_data_arb

SCORELINE
100.00 100.00
tb.dut.u_reg.u_timeout_ctrl_en.wr_en_data_arb

SCORELINE
100.00 100.00
tb.dut.u_reg.u_target_id_address0.wr_en_data_arb

SCORELINE
100.00 100.00
tb.dut.u_reg.u_target_id_mask0.wr_en_data_arb

SCORELINE
100.00 100.00
tb.dut.u_reg.u_target_id_address1.wr_en_data_arb

SCORELINE
100.00 100.00
tb.dut.u_reg.u_target_id_mask1.wr_en_data_arb

SCORELINE
100.00 100.00
tb.dut.u_reg.u_txdata.wr_en_data_arb

SCORELINE
100.00 100.00
tb.dut.u_reg.u_host_timeout_ctrl.wr_en_data_arb

SCORELINE
100.00 100.00
tb.dut.u_reg.u_target_timeout_ctrl_val.wr_en_data_arb

SCORELINE
100.00 100.00
tb.dut.u_reg.u_target_timeout_ctrl_en.wr_en_data_arb

SCORELINE
100.00 100.00
tb.dut.u_reg.u_host_nack_handler_timeout_val.wr_en_data_arb

SCORELINE
100.00 100.00
tb.dut.u_reg.u_host_nack_handler_timeout_en.wr_en_data_arb

Line No.TotalCoveredPercent
TOTAL22100.00
CONT_ASSIGN3311100.00
CONT_ASSIGN3411100.00
CONT_ASSIGN3900

32 if (SwAccess inside {SwAccessRW, SwAccessWO}) begin : gen_w 33 1/1 assign wr_en = we | de; Tests: T1 T2 T3  34 1/1 assign wr_data = (we == 1'b1) ? wd : d; // SW higher priority Tests: T1 T2 T3  35 // Unused q - Prevent lint errors. 36 logic [DW-1:0] unused_q; 37 //VCS coverage off 38 // pragma coverage off 39 unreachable assign unused_q = q;

Line Coverage for Module : prim_subreg_arb ( parameter DW=8,SwAccess=6,Mubi=0 )
Line Coverage for Module self-instances :
SCORELINE
100.00 100.00
tb.dut.u_reg.u_target_nack_count.wr_en_data_arb

Line No.TotalCoveredPercent
TOTAL22100.00
CONT_ASSIGN14011100.00
CONT_ASSIGN16211100.00
CONT_ASSIGN16800

139 // WARN: we signal is actually read signal not write enable. 140 1/1 assign wr_en = we | de; Tests: T1 T2 T3  141 if (Mubi) begin : gen_mubi 142 if (DW == 4) begin : gen_mubi4 143 assign wr_data = prim_mubi_pkg::mubi4_and_hi(prim_mubi_pkg::mubi4_t'(de ? d : q), 144 (we ? prim_mubi_pkg::MuBi4False : 145 prim_mubi_pkg::MuBi4True)); 146 end else if (DW == 8) begin : gen_mubi8 147 assign wr_data = prim_mubi_pkg::mubi8_and_hi(prim_mubi_pkg::mubi8_t'(de ? d : q), 148 (we ? prim_mubi_pkg::MuBi8False : 149 prim_mubi_pkg::MuBi8True)); 150 end else if (DW == 12) begin : gen_mubi12 151 assign wr_data = prim_mubi_pkg::mubi12_and_hi(prim_mubi_pkg::mubi12_t'(de ? d : q), 152 (we ? prim_mubi_pkg::MuBi12False : 153 prim_mubi_pkg::MuBi12True)); 154 end else if (DW == 16) begin : gen_mubi16 155 assign wr_data = prim_mubi_pkg::mubi16_and_hi(prim_mubi_pkg::mubi16_t'(de ? d : q), 156 (we ? prim_mubi_pkg::mubi16_t'(wd) : 157 prim_mubi_pkg::MuBi16True)); 158 end else begin : gen_invalid_mubi 159 $error("%m: Invalid width for MuBi"); 160 end 161 end else begin : gen_non_mubi 162 1/1 assign wr_data = (de ? d : q) & (we ? '0 : '1); Tests: T1 T2 T3  163 end 164 // Unused wd - Prevent lint errors. 165 logic [DW-1:0] unused_wd; 166 //VCS coverage off 167 // pragma coverage off 168 unreachable assign unused_wd = wd;

Cond Coverage for Module : prim_subreg_arb ( parameter DW=8,SwAccess=6,Mubi=0 )
Cond Coverage for Module self-instances :
SCORECOND
100.00 100.00
tb.dut.u_reg.u_target_nack_count.wr_en_data_arb

TotalCoveredPercent
Conditions33100.00
Logical33100.00
Non-Logical00
Event00

 LINE       140
 EXPRESSION (we | de)
             -1   -2
-1--2-StatusTests
00CoveredT1,T2,T3
01CoveredT62,T63,T59
10CoveredT62,T63,T59

Cond Coverage for Module : prim_subreg_arb ( parameter DW=10,SwAccess=0,Mubi=0 )
Cond Coverage for Module self-instances :
SCORECOND
100.00 100.00
tb.dut.u_reg.u_timing1_t_r.wr_en_data_arb

TotalCoveredPercent
Conditions66100.00
Logical66100.00
Non-Logical00
Event00

 LINE       33
 EXPRESSION (we | de)
             -1   -2
-1--2-StatusTests
00CoveredT1,T2,T3
01Unreachable
10CoveredT1,T2,T3

 LINE       34
 EXPRESSION ((we == 1'b1) ? wd : d)
             ------1-----
-1-StatusTests
0CoveredT1,T2,T3
1CoveredT1,T2,T3

 LINE       34
 SUB-EXPRESSION (we == 1'b1)
                ------1-----
-1-StatusTests
0CoveredT1,T2,T3
1CoveredT1,T2,T3

Cond Coverage for Module : prim_subreg_arb ( parameter DW=9,SwAccess=0,Mubi=0 )
Cond Coverage for Module self-instances :
SCORECOND
100.00 100.00
tb.dut.u_reg.u_timing1_t_f.wr_en_data_arb

SCORECOND
100.00 100.00
tb.dut.u_reg.u_timing3_tsu_dat.wr_en_data_arb

TotalCoveredPercent
Conditions66100.00
Logical66100.00
Non-Logical00
Event00

 LINE       33
 EXPRESSION (we | de)
             -1   -2
-1--2-StatusTests
00CoveredT1,T2,T3
01Unreachable
10CoveredT1,T2,T3

 LINE       34
 EXPRESSION ((we == 1'b1) ? wd : d)
             ------1-----
-1-StatusTests
0CoveredT1,T2,T3
1CoveredT1,T2,T3

 LINE       34
 SUB-EXPRESSION (we == 1'b1)
                ------1-----
-1-StatusTests
0CoveredT1,T2,T3
1CoveredT1,T2,T3

Cond Coverage for Module : prim_subreg_arb ( parameter DW=1,SwAccess=3,Mubi=0 )
Cond Coverage for Module self-instances :
SCORECOND
100.00 100.00
tb.dut.u_reg.u_intr_state_rx_overflow.wr_en_data_arb

SCORECOND
100.00 100.00
tb.dut.u_reg.u_intr_state_scl_interference.wr_en_data_arb

SCORECOND
100.00 100.00
tb.dut.u_reg.u_intr_state_sda_interference.wr_en_data_arb

SCORECOND
100.00 100.00
tb.dut.u_reg.u_intr_state_stretch_timeout.wr_en_data_arb

SCORECOND
100.00 100.00
tb.dut.u_reg.u_intr_state_sda_unstable.wr_en_data_arb

SCORECOND
100.00 100.00
tb.dut.u_reg.u_intr_state_cmd_complete.wr_en_data_arb

SCORECOND
100.00 100.00
tb.dut.u_reg.u_intr_state_unexp_stop.wr_en_data_arb

SCORECOND
100.00 100.00
tb.dut.u_reg.u_intr_state_host_timeout.wr_en_data_arb

SCORECOND
100.00 100.00
tb.dut.u_reg.u_controller_events_nack.wr_en_data_arb

SCORECOND
80.00 60.00
tb.dut.u_reg.u_controller_events_unhandled_nack_timeout.wr_en_data_arb

SCORECOND
80.00 60.00
tb.dut.u_reg.u_controller_events_bus_timeout.wr_en_data_arb

SCORECOND
95.00 90.00
tb.dut.u_reg.u_controller_events_arbitration_lost.wr_en_data_arb

SCORECOND
100.00 100.00
tb.dut.u_reg.u_target_events_tx_pending.wr_en_data_arb

SCORECOND
80.00 60.00
tb.dut.u_reg.u_target_events_bus_timeout.wr_en_data_arb

SCORECOND
80.00 60.00
tb.dut.u_reg.u_target_events_arbitration_lost.wr_en_data_arb

TotalCoveredPercent
Conditions1010100.00
Logical1010100.00
Non-Logical00
Event00

 LINE       88
 EXPRESSION (we | de)
             -1   -2
-1--2-StatusTests
00CoveredT1,T2,T3
01CoveredT1,T19,T20
10CoveredT1,T2,T3

 LINE       110
 EXPRESSION ((de ? d : q) & (we ? ((~wd)) : '1))
             ------1-----   ---------2---------
-1--2-StatusTests
01CoveredT1,T2,T3
10CoveredT8,T83,T36
11CoveredT1,T19,T20

 LINE       110
 SUB-EXPRESSION (de ? d : q)
                 -1
-1-StatusTests
0CoveredT1,T2,T3
1CoveredT1,T19,T20

 LINE       110
 SUB-EXPRESSION (we ? ((~wd)) : '1)
                 -1
-1-StatusTests
0CoveredT1,T2,T3
1CoveredT1,T2,T3

Cond Coverage for Module : prim_subreg_arb ( parameter DW=1,SwAccess=0,Mubi=0 )
Cond Coverage for Module self-instances :
SCORECOND
100.00 100.00
tb.dut.u_reg.u_intr_enable_fmt_threshold.wr_en_data_arb

SCORECOND
100.00 100.00
tb.dut.u_reg.u_intr_enable_rx_threshold.wr_en_data_arb

SCORECOND
100.00 100.00
tb.dut.u_reg.u_intr_enable_acq_threshold.wr_en_data_arb

SCORECOND
100.00 100.00
tb.dut.u_reg.u_intr_enable_rx_overflow.wr_en_data_arb

SCORECOND
100.00 100.00
tb.dut.u_reg.u_intr_enable_controller_halt.wr_en_data_arb

SCORECOND
100.00 100.00
tb.dut.u_reg.u_intr_enable_scl_interference.wr_en_data_arb

SCORECOND
100.00 100.00
tb.dut.u_reg.u_intr_enable_sda_interference.wr_en_data_arb

SCORECOND
100.00 100.00
tb.dut.u_reg.u_intr_enable_stretch_timeout.wr_en_data_arb

SCORECOND
100.00 100.00
tb.dut.u_reg.u_intr_enable_sda_unstable.wr_en_data_arb

SCORECOND
100.00 100.00
tb.dut.u_reg.u_intr_enable_cmd_complete.wr_en_data_arb

SCORECOND
100.00 100.00
tb.dut.u_reg.u_intr_enable_tx_stretch.wr_en_data_arb

SCORECOND
100.00 100.00
tb.dut.u_reg.u_intr_enable_tx_threshold.wr_en_data_arb

SCORECOND
100.00 100.00
tb.dut.u_reg.u_intr_enable_acq_stretch.wr_en_data_arb

SCORECOND
100.00 100.00
tb.dut.u_reg.u_intr_enable_unexp_stop.wr_en_data_arb

SCORECOND
100.00 100.00
tb.dut.u_reg.u_intr_enable_host_timeout.wr_en_data_arb

SCORECOND
100.00 100.00
tb.dut.u_reg.u_ctrl_enablehost.wr_en_data_arb

SCORECOND
100.00 100.00
tb.dut.u_reg.u_ctrl_enabletarget.wr_en_data_arb

SCORECOND
100.00 100.00
tb.dut.u_reg.u_ctrl_llpbk.wr_en_data_arb

SCORECOND
100.00 100.00
tb.dut.u_reg.u_ctrl_nack_addr_after_timeout.wr_en_data_arb

SCORECOND
100.00 100.00
tb.dut.u_reg.u_ctrl_ack_ctrl_en.wr_en_data_arb

SCORECOND
100.00 100.00
tb.dut.u_reg.u_ctrl_multi_controller_monitor_en.wr_en_data_arb

SCORECOND
100.00 100.00
tb.dut.u_reg.u_ctrl_tx_stretch_ctrl_en.wr_en_data_arb

SCORECOND
100.00 100.00
tb.dut.u_reg.u_fdata_start.wr_en_data_arb

SCORECOND
100.00 100.00
tb.dut.u_reg.u_fdata_stop.wr_en_data_arb

SCORECOND
100.00 100.00
tb.dut.u_reg.u_fdata_readb.wr_en_data_arb

SCORECOND
100.00 100.00
tb.dut.u_reg.u_fdata_rcont.wr_en_data_arb

SCORECOND
100.00 100.00
tb.dut.u_reg.u_fdata_nakok.wr_en_data_arb

SCORECOND
100.00 100.00
tb.dut.u_reg.u_fifo_ctrl_rxrst.wr_en_data_arb

SCORECOND
100.00 100.00
tb.dut.u_reg.u_fifo_ctrl_fmtrst.wr_en_data_arb

SCORECOND
100.00 100.00
tb.dut.u_reg.u_fifo_ctrl_acqrst.wr_en_data_arb

SCORECOND
100.00 100.00
tb.dut.u_reg.u_fifo_ctrl_txrst.wr_en_data_arb

SCORECOND
100.00 100.00
tb.dut.u_reg.u_ovrd_txovrden.wr_en_data_arb

SCORECOND
100.00 100.00
tb.dut.u_reg.u_ovrd_sclval.wr_en_data_arb

SCORECOND
100.00 100.00
tb.dut.u_reg.u_ovrd_sdaval.wr_en_data_arb

SCORECOND
100.00 100.00
tb.dut.u_reg.u_timeout_ctrl_mode.wr_en_data_arb

SCORECOND
100.00 100.00
tb.dut.u_reg.u_timeout_ctrl_en.wr_en_data_arb

SCORECOND
100.00 100.00
tb.dut.u_reg.u_target_timeout_ctrl_en.wr_en_data_arb

SCORECOND
100.00 100.00
tb.dut.u_reg.u_host_nack_handler_timeout_en.wr_en_data_arb

TotalCoveredPercent
Conditions66100.00
Logical66100.00
Non-Logical00
Event00

 LINE       33
 EXPRESSION (we | de)
             -1   -2
-1--2-StatusTests
00CoveredT1,T2,T3
01Unreachable
10CoveredT1,T2,T3

 LINE       34
 EXPRESSION ((we == 1'b1) ? wd : d)
             ------1-----
-1-StatusTests
0CoveredT1,T2,T3
1CoveredT1,T2,T3

 LINE       34
 SUB-EXPRESSION (we == 1'b1)
                ------1-----
-1-StatusTests
0CoveredT1,T2,T3
1CoveredT1,T2,T3

Cond Coverage for Module : prim_subreg_arb ( parameter DW=13,SwAccess=0,Mubi=0 )
Cond Coverage for Module self-instances :
SCORECOND
100.00 100.00
tb.dut.u_reg.u_timing0_thigh.wr_en_data_arb

SCORECOND
100.00 100.00
tb.dut.u_reg.u_timing0_tlow.wr_en_data_arb

SCORECOND
100.00 100.00
tb.dut.u_reg.u_timing2_tsu_sta.wr_en_data_arb

SCORECOND
100.00 100.00
tb.dut.u_reg.u_timing2_thd_sta.wr_en_data_arb

SCORECOND
100.00 100.00
tb.dut.u_reg.u_timing3_thd_dat.wr_en_data_arb

SCORECOND
100.00 100.00
tb.dut.u_reg.u_timing4_tsu_sto.wr_en_data_arb

SCORECOND
100.00 100.00
tb.dut.u_reg.u_timing4_t_buf.wr_en_data_arb

TotalCoveredPercent
Conditions66100.00
Logical66100.00
Non-Logical00
Event00

 LINE       33
 EXPRESSION (we | de)
             -1   -2
-1--2-StatusTests
00CoveredT1,T2,T3
01Unreachable
10CoveredT1,T2,T3

 LINE       34
 EXPRESSION ((we == 1'b1) ? wd : d)
             ------1-----
-1-StatusTests
0CoveredT1,T2,T3
1CoveredT1,T2,T3

 LINE       34
 SUB-EXPRESSION (we == 1'b1)
                ------1-----
-1-StatusTests
0CoveredT1,T2,T3
1CoveredT1,T2,T3

Cond Coverage for Module : prim_subreg_arb ( parameter DW=31,SwAccess=0,Mubi=0 )
Cond Coverage for Module self-instances :
SCORECOND
100.00 100.00
tb.dut.u_reg.u_target_timeout_ctrl_val.wr_en_data_arb

SCORECOND
100.00 100.00
tb.dut.u_reg.u_host_nack_handler_timeout_val.wr_en_data_arb

TotalCoveredPercent
Conditions66100.00
Logical66100.00
Non-Logical00
Event00

 LINE       33
 EXPRESSION (we | de)
             -1   -2
-1--2-StatusTests
00CoveredT1,T2,T3
01Unreachable
10CoveredT12,T62,T13

 LINE       34
 EXPRESSION ((we == 1'b1) ? wd : d)
             ------1-----
-1-StatusTests
0CoveredT1,T2,T3
1CoveredT12,T62,T13

 LINE       34
 SUB-EXPRESSION (we == 1'b1)
                ------1-----
-1-StatusTests
0CoveredT1,T2,T3
1CoveredT12,T62,T13

Cond Coverage for Module : prim_subreg_arb ( parameter DW=7,SwAccess=0,Mubi=0 )
Cond Coverage for Module self-instances :
SCORECOND
100.00 100.00
tb.dut.u_reg.u_target_id_address0.wr_en_data_arb

SCORECOND
100.00 100.00
tb.dut.u_reg.u_target_id_mask0.wr_en_data_arb

SCORECOND
100.00 100.00
tb.dut.u_reg.u_target_id_address1.wr_en_data_arb

SCORECOND
100.00 100.00
tb.dut.u_reg.u_target_id_mask1.wr_en_data_arb

TotalCoveredPercent
Conditions66100.00
Logical66100.00
Non-Logical00
Event00

 LINE       33
 EXPRESSION (we | de)
             -1   -2
-1--2-StatusTests
00CoveredT1,T2,T3
01Unreachable
10CoveredT2,T3,T5

 LINE       34
 EXPRESSION ((we == 1'b1) ? wd : d)
             ------1-----
-1-StatusTests
0CoveredT1,T2,T3
1CoveredT2,T3,T5

 LINE       34
 SUB-EXPRESSION (we == 1'b1)
                ------1-----
-1-StatusTests
0CoveredT1,T2,T3
1CoveredT2,T3,T5

Cond Coverage for Module : prim_subreg_arb ( parameter DW=20,SwAccess=0,Mubi=0 )
Cond Coverage for Module self-instances :
SCORECOND
100.00 100.00
tb.dut.u_reg.u_host_timeout_ctrl.wr_en_data_arb

TotalCoveredPercent
Conditions66100.00
Logical66100.00
Non-Logical00
Event00

 LINE       33
 EXPRESSION (we | de)
             -1   -2
-1--2-StatusTests
00CoveredT1,T2,T3
01Unreachable
10CoveredT2,T3,T5

 LINE       34
 EXPRESSION ((we == 1'b1) ? wd : d)
             ------1-----
-1-StatusTests
0CoveredT1,T2,T3
1CoveredT2,T3,T5

 LINE       34
 SUB-EXPRESSION (we == 1'b1)
                ------1-----
-1-StatusTests
0CoveredT1,T2,T3
1CoveredT2,T3,T5

Cond Coverage for Module : prim_subreg_arb ( parameter DW=8,SwAccess=2,Mubi=0 )
Cond Coverage for Module self-instances :
SCORECOND
100.00 100.00
tb.dut.u_reg.u_fdata_fbyte.wr_en_data_arb

SCORECOND
100.00 100.00
tb.dut.u_reg.u_txdata.wr_en_data_arb

TotalCoveredPercent
Conditions66100.00
Logical66100.00
Non-Logical00
Event00

 LINE       33
 EXPRESSION (we | de)
             -1   -2
-1--2-StatusTests
00CoveredT1,T2,T3
01Unreachable
10CoveredT1,T2,T3

 LINE       34
 EXPRESSION ((we == 1'b1) ? wd : d)
             ------1-----
-1-StatusTests
0CoveredT1,T2,T3
1CoveredT1,T2,T3

 LINE       34
 SUB-EXPRESSION (we == 1'b1)
                ------1-----
-1-StatusTests
0CoveredT1,T2,T3
1CoveredT1,T2,T3

Cond Coverage for Module : prim_subreg_arb ( parameter DW=12,SwAccess=0,Mubi=0 )
Cond Coverage for Module self-instances :
SCORECOND
100.00 100.00
tb.dut.u_reg.u_host_fifo_config_rx_thresh.wr_en_data_arb

SCORECOND
100.00 100.00
tb.dut.u_reg.u_host_fifo_config_fmt_thresh.wr_en_data_arb

SCORECOND
100.00 100.00
tb.dut.u_reg.u_target_fifo_config_tx_thresh.wr_en_data_arb

SCORECOND
100.00 100.00
tb.dut.u_reg.u_target_fifo_config_acq_thresh.wr_en_data_arb

TotalCoveredPercent
Conditions66100.00
Logical66100.00
Non-Logical00
Event00

 LINE       33
 EXPRESSION (we | de)
             -1   -2
-1--2-StatusTests
00CoveredT1,T2,T3
01Unreachable
10CoveredT1,T2,T3

 LINE       34
 EXPRESSION ((we == 1'b1) ? wd : d)
             ------1-----
-1-StatusTests
0CoveredT1,T2,T3
1CoveredT1,T2,T3

 LINE       34
 SUB-EXPRESSION (we == 1'b1)
                ------1-----
-1-StatusTests
0CoveredT1,T2,T3
1CoveredT1,T2,T3

Cond Coverage for Module : prim_subreg_arb ( parameter DW=30,SwAccess=0,Mubi=0 )
Cond Coverage for Module self-instances :
SCORECOND
100.00 100.00
tb.dut.u_reg.u_timeout_ctrl_val.wr_en_data_arb

TotalCoveredPercent
Conditions66100.00
Logical66100.00
Non-Logical00
Event00

 LINE       33
 EXPRESSION (we | de)
             -1   -2
-1--2-StatusTests
00CoveredT1,T2,T3
01Unreachable
10CoveredT1,T2,T3

 LINE       34
 EXPRESSION ((we == 1'b1) ? wd : d)
             ------1-----
-1-StatusTests
0CoveredT1,T2,T3
1CoveredT1,T2,T3

 LINE       34
 SUB-EXPRESSION (we == 1'b1)
                ------1-----
-1-StatusTests
0CoveredT1,T2,T3
1CoveredT1,T2,T3

Branch Coverage for Module : prim_subreg_arb
Line No.TotalCoveredPercent
Branches 2 2 100.00
TERNARY 34 2 2 100.00


34 assign wr_data = (we == 1'b1) ? wd : d; // SW higher priority -1- ==> ==>

Branches:
-1-StatusTests
1 Covered T1,T2,T3
0 Covered T1,T2,T3