Unified Coverage Report :: Group :: tl_agent_pkg::tl_a_chan_cov_cg::SHAPE{(2 << ((valid_source_width - 1) - 1))=128}

Group : tl_agent_pkg::tl_a_chan_cov_cg::SHAPE{(2 << ((valid_source_width - 1) - 1))=128}

SCORE	INSTANCES	WEIGHT	GOAL	AT LEAST	PER INSTANCE	AUTO BIN MAX	PRINT MISSING
100.00	100.00	1	100	1	1	64	64

Source File(s) :
/workspaces/repo/scratch/os_regression_2024_09_10/i2c-sim-vcs/default/sim-vcs/../src/lowrisc_dv_tl_agent_0/tl_agent_cov.sv

1 Instances:

NAME	SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
tl_agent_pkg.uvm_test_top.env.m_tl_agent_i2c_reg_block.cov::m_tl_a_chan_cov_cg	100.00	1	100	1	64	64

---

Group Instance : tl_agent_pkg.uvm_test_top.env.m_tl_agent_i2c_reg_block.cov::m_tl_a_chan_cov_cg

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
100.00	1	100	1	64	64

---

Summary for Group Instance tl_agent_pkg.uvm_test_top.env.m_tl_agent_i2c_reg_block.cov::m_tl_a_chan_cov_cg

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	134	0	134	100.00
Crosses	3	0	3	100.00

Variables for Group Instance tl_agent_pkg.uvm_test_top.env.m_tl_agent_i2c_reg_block.cov::m_tl_a_chan_cov_cg

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
cp_mask	1	0	1	100.00	100	1	1	0
cp_opcode	3	0	3	100.00	100	1	1	0
cp_size	1	0	1	100.00	100	1	1	0
cp_source	129	0	129	100.00	100	1	1	0

Crosses for Group Instance tl_agent_pkg.uvm_test_top.env.m_tl_agent_i2c_reg_block.cov::m_tl_a_chan_cov_cg

CROSS	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	PRINT MISSING	COMMENT
tl_a_chan_cov_cg_cc	3	0	3	100.00	100	1	1	0

Summary for Variable cp_mask

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	1	0	1	100.00

User Defined Bins for cp_mask

Excluded/Illegal bins

NAME	COUNT	STATUS
others	29140341	Excluded

Covered bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

all_enables

7714584

1

T1

13

T2

41

T3

177

---

Summary for Variable cp_opcode

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	3	0	3	100.00

User Defined Bins for cp_opcode

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
values[0x4]	36027423	1			T1	14		T2	97		T3	680
values[0x0]	413179	1			T1	9		T2	51		T3	14
values[0x1]	414323	1			T1	8		T2	40		T3	14

---

Summary for Variable cp_size

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	1	0	1	100.00

User Defined Bins for cp_size

Excluded/Illegal bins

NAME	COUNT	STATUS
others	20378548	Excluded

Covered bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

biggest_size

16476377

1

T1

15

T2

83

T3

343

---

Summary for Variable cp_source

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	129	0	129	100.00

User Defined Bins for cp_source

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
valid_sources[0x00]	159359	1			T3	2		T4	10		T8	34
valid_sources[0x01]	137849	1			T3	4		T4	6		T8	24
valid_sources[0x02]	135703	1			T3	2		T4	9		T8	24
valid_sources[0x03]	152600	1			T3	4		T4	7		T7	37
valid_sources[0x04]	136399	1			T3	1		T4	5		T8	33
valid_sources[0x05]	141809	1			T3	2		T4	4		T7	2
valid_sources[0x06]	138508	1			T3	4		T4	4		T8	17
valid_sources[0x07]	151033	1			T3	4		T4	6		T7	13
valid_sources[0x08]	145319	1			T1	31		T3	2		T4	6
valid_sources[0x09]	134502	1			T3	4		T4	4		T7	12
valid_sources[0x0a]	158200	1			T3	1		T4	4		T7	1
valid_sources[0x0b]	144132	1			T3	1		T4	6		T8	31
valid_sources[0x0c]	146085	1			T3	2		T4	9		T8	21
valid_sources[0x0d]	152145	1			T3	5		T4	5		T8	28
valid_sources[0x0e]	140432	1			T3	1		T4	6		T8	29
valid_sources[0x0f]	144821	1			T4	6		T8	41		T10	4
valid_sources[0x10]	149591	1			T3	2		T4	8		T7	28
valid_sources[0x11]	132600	1			T3	3		T4	9		T7	72
valid_sources[0x12]	152095	1			T3	2		T4	13		T7	8
valid_sources[0x13]	138171	1			T3	1		T4	6		T7	12
valid_sources[0x14]	159522	1			T3	2		T4	7		T7	23
valid_sources[0x15]	162412	1			T3	4		T4	6		T8	29
valid_sources[0x16]	142038	1			T3	1		T4	8		T8	28
valid_sources[0x17]	141594	1			T3	3		T4	5		T7	15
valid_sources[0x18]	160152	1			T3	4		T4	7		T8	42
valid_sources[0x19]	134023	1			T3	4		T4	4		T8	22
valid_sources[0x1a]	135155	1			T3	5		T4	10		T8	39
valid_sources[0x1b]	156606	1			T3	5		T4	5		T8	38
valid_sources[0x1c]	137186	1			T3	3		T4	5		T7	15
valid_sources[0x1d]	157127	1			T3	3		T4	6		T8	35
valid_sources[0x1e]	131724	1			T3	3		T4	8		T8	25
valid_sources[0x1f]	137754	1			T3	4		T4	13		T7	7
valid_sources[0x20]	137692	1			T3	3		T4	5		T8	24
valid_sources[0x21]	143158	1			T3	4		T4	6		T6	3
valid_sources[0x22]	136983	1			T3	5		T4	11		T8	31
valid_sources[0x23]	136376	1			T3	6		T4	8		T8	31
valid_sources[0x24]	147185	1			T3	4		T4	10		T7	4
valid_sources[0x25]	153673	1			T4	6		T8	27		T10	2
valid_sources[0x26]	138586	1			T3	3		T4	12		T7	8
valid_sources[0x27]	141977	1			T3	3		T4	7		T8	30
valid_sources[0x28]	153470	1			T3	5		T4	8		T7	2
valid_sources[0x29]	132230	1			T3	3		T4	8		T7	15
valid_sources[0x2a]	142194	1			T3	2		T4	12		T7	48
valid_sources[0x2b]	156952	1			T3	1		T4	10		T8	33
valid_sources[0x2c]	134899	1			T3	3		T4	5		T8	22
valid_sources[0x2d]	139070	1			T3	5		T4	12		T8	33
valid_sources[0x2e]	147374	1			T4	4		T8	29		T10	1
valid_sources[0x2f]	144961	1			T3	4		T4	8		T8	25
valid_sources[0x30]	141791	1			T3	3		T4	6		T8	28
valid_sources[0x31]	133750	1			T3	1		T4	9		T7	8
valid_sources[0x32]	145205	1			T3	4		T4	10		T8	33
valid_sources[0x33]	145024	1			T3	6		T4	12		T7	6
valid_sources[0x34]	138804	1			T3	4		T4	2		T8	41
valid_sources[0x35]	142947	1			T3	3		T4	13		T7	6
valid_sources[0x36]	128850	1			T3	7		T4	6		T8	27
valid_sources[0x37]	153944	1			T3	2		T4	5		T7	17
valid_sources[0x38]	145317	1			T3	3		T4	10		T7	11
valid_sources[0x39]	160641	1			T4	8		T8	27		T17	12
valid_sources[0x3a]	145820	1			T3	3		T4	12		T8	36
valid_sources[0x3b]	155545	1			T3	4		T4	8		T8	39
valid_sources[0x3c]	136510	1			T4	9		T7	12		T8	23
valid_sources[0x3d]	134454	1			T3	4		T4	7		T8	31
valid_sources[0x3e]	155975	1			T3	2		T4	9		T8	38
valid_sources[0x3f]	151866	1			T3	4		T4	7		T8	33
valid_sources[0x40]	135360	1			T3	1		T4	8		T7	2
valid_sources[0x41]	138258	1			T3	5		T4	8		T7	29
valid_sources[0x42]	142447	1			T3	2		T4	5		T8	30
valid_sources[0x43]	133325	1			T3	4		T4	8		T8	34
valid_sources[0x44]	133795	1			T3	2		T4	2		T8	35
valid_sources[0x45]	149609	1			T3	3		T4	7		T7	3
valid_sources[0x46]	135665	1			T2	188		T3	3		T4	4
valid_sources[0x47]	134454	1			T4	8		T7	21		T8	25
valid_sources[0x48]	146219	1			T3	5		T4	10		T7	12
valid_sources[0x49]	130966	1			T3	3		T4	12		T7	25
valid_sources[0x4a]	138829	1			T3	2		T4	8		T8	27
valid_sources[0x4b]	142425	1			T3	3		T4	4		T7	8
valid_sources[0x4c]	134733	1			T3	2		T4	10		T8	33
valid_sources[0x4d]	139149	1			T3	3		T4	8		T8	41
valid_sources[0x4e]	140618	1			T3	1		T4	9		T8	28
valid_sources[0x4f]	139900	1			T3	2		T4	5		T8	38
valid_sources[0x50]	140480	1			T3	4		T4	12		T8	27
valid_sources[0x51]	151151	1			T3	2		T4	5		T8	24
valid_sources[0x52]	139688	1			T3	3		T4	7		T8	19
valid_sources[0x53]	143316	1			T3	1		T4	6		T6	9
valid_sources[0x54]	142678	1			T4	7		T8	22		T10	1
valid_sources[0x55]	156619	1			T3	3		T4	8		T7	6
valid_sources[0x56]	138689	1			T3	5		T4	4		T8	32
valid_sources[0x57]	134527	1			T3	5		T4	7		T7	5
valid_sources[0x58]	134383	1			T3	2		T4	4		T8	34
valid_sources[0x59]	142019	1			T3	1		T4	6		T8	28
valid_sources[0x5a]	153680	1			T3	1		T4	10		T7	17
valid_sources[0x5b]	148988	1			T3	2		T4	11		T8	30
valid_sources[0x5c]	133657	1			T3	1		T4	5		T8	31
valid_sources[0x5d]	183498	1			T3	3		T4	6		T8	27
valid_sources[0x5e]	148319	1			T3	3		T4	10		T8	22
valid_sources[0x5f]	144801	1			T3	5		T4	5		T8	30
valid_sources[0x60]	140748	1			T3	3		T4	7		T8	43
valid_sources[0x61]	147676	1			T3	3		T4	6		T7	12
valid_sources[0x62]	144621	1			T3	3		T4	8		T7	17
valid_sources[0x63]	147389	1			T3	4		T4	10		T7	3
valid_sources[0x64]	148420	1			T3	4		T4	2		T7	20
valid_sources[0x65]	142729	1			T3	2		T4	13		T8	45
valid_sources[0x66]	133499	1			T3	5		T4	6		T7	2
valid_sources[0x67]	151472	1			T3	2		T4	9		T7	24
valid_sources[0x68]	145379	1			T3	2		T4	2		T7	14
valid_sources[0x69]	132228	1			T3	5		T4	8		T8	22
valid_sources[0x6a]	141846	1			T3	6		T4	5		T7	20
valid_sources[0x6b]	163881	1			T3	3		T4	6		T8	24
valid_sources[0x6c]	138386	1			T3	3		T4	7		T7	16
valid_sources[0x6d]	151269	1			T3	4		T4	5		T7	9
valid_sources[0x6e]	138570	1			T3	1		T4	4		T8	27
valid_sources[0x6f]	144000	1			T3	2		T4	16		T8	21
valid_sources[0x70]	130453	1			T3	3		T4	4		T8	26
valid_sources[0x71]	148249	1			T3	1		T4	8		T7	31
valid_sources[0x72]	135577	1			T3	2		T4	8		T8	26
valid_sources[0x73]	141121	1			T3	2		T4	4		T8	23
valid_sources[0x74]	143243	1			T3	3		T4	6		T7	1
valid_sources[0x75]	158489	1			T3	3		T4	9		T7	28
valid_sources[0x76]	157957	1			T3	3		T4	6		T7	12
valid_sources[0x77]	143947	1			T3	3		T4	8		T7	8
valid_sources[0x78]	133674	1			T3	4		T4	6		T8	23
valid_sources[0x79]	153132	1			T3	2		T4	14		T8	29
valid_sources[0x7a]	153201	1			T3	3		T4	11		T8	40
valid_sources[0x7b]	137643	1			T4	8		T8	27		T10	2
valid_sources[0x7c]	127505	1			T3	4		T4	9		T8	39
valid_sources[0x7d]	155783	1			T4	13		T7	5		T8	30
valid_sources[0x7e]	135261	1			T3	6		T4	3		T7	3
valid_sources[0x7f]	142252	1			T3	4		T4	7		T7	2
valid_sources[0x80]	134764	1			T3	3		T4	15		T8	40

---

Summary for Cross tl_a_chan_cov_cg_cc

Samples crossed: cp_opcode cp_mask cp_size

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	3	0	3	100.00

Automatically Generated Cross Bins for tl_a_chan_cov_cg_cc

Bins

cp_opcode

cp_mask

cp_size

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

values[0x4]

all_enables

biggest_size

7350796

1

T1

6

T2

2

T3

165

values[0x0]

all_enables

biggest_size

216863

1

T1

5

T2

31

T3

7

values[0x1]

all_enables

biggest_size

146925

1

T1

2

T2

8

T3

5