Unified Coverage Report :: Module :: i2c_csr_assert_fpv

Module : i2c_csr_assert_fpv

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
93.75						93.75

Source File(s) :
/workspaces/repo/scratch/os_regression_2024_09_10/i2c-sim-vcs/default/sim-vcs/../src/lowrisc_fpv_i2c_csr_assert_0/i2c_csr_assert_fpv.sv

Module self-instances :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
tb.dut.i2c_csr_assert	93.75						93.75

---

Module Instance : tb.dut.i2c_csr_assert

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
93.75						93.75

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
93.75						93.75

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
98.48	100.00	100.00	93.91			100.00	dut

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Since this is the module's only instance, the coverage report is the same as for the module.

Assert Coverage for Module : i2c_csr_assert_fpv

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	16	16	100.00	15	93.75
Cover properties	0	0		0
Cover sequences	0	0		0
Total	16	16	100.00	15	93.75

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
TlulOOBAddrErr_A	413684813	0	0	0
ctrl_rd_A	413684813	2461	0	0
host_fifo_config_rd_A	413684813	4020	0	0
host_nack_handler_timeout_rd_A	413684813	1758	0	0
host_timeout_ctrl_rd_A	413684813	1307	0	0
intr_enable_rd_A	413684813	4149	0	0
ovrd_rd_A	413684813	2859	0	0
target_fifo_config_rd_A	413684813	1714	0	0
target_id_rd_A	413684813	2010	0	0
target_timeout_ctrl_rd_A	413684813	1628	0	0
timeout_ctrl_rd_A	413684813	2094	0	0
timing0_rd_A	413684813	1648	0	0
timing1_rd_A	413684813	1648	0	0
timing2_rd_A	413684813	1689	0	0
timing3_rd_A	413684813	1798	0	0
timing4_rd_A	413684813	1563	0	0

TlulOOBAddrErr_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	413684813	0	0	0

ctrl_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	413684813	2461	0	0
T105	6715	73	0	0
T106	1862	47	0	0
T107	5862	5	0	0
T108	3229	21	0	0
T109	26402	214	0	0
T110	1787	11	0	0
T111	14523	229	0	0
T112	9476	5	0	0
T113	5608	110	0	0
T114	44822	275	0	0

host_fifo_config_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	413684813	4020	0	0
T35	0	78	0	0
T42	0	334	0	0
T115	429031	72	0	0
T116	0	200	0	0
T117	0	230	0	0
T118	0	59	0	0
T119	0	97	0	0
T120	0	90	0	0
T121	0	209	0	0
T122	0	191	0	0
T123	68007	0	0	0
T124	148899	0	0	0
T125	234508	0	0	0
T126	12530	0	0	0
T127	88306	0	0	0
T128	22276	0	0	0
T129	163160	0	0	0
T130	46495	0	0	0
T131	238067	0	0	0

host_nack_handler_timeout_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	413684813	1758	0	0
T105	6715	36	0	0
T106	1862	7	0	0
T107	5862	21	0	0
T108	3229	29	0	0
T109	26402	170	0	0
T110	1787	5	0	0
T111	14523	199	0	0
T112	9476	62	0	0
T113	5608	105	0	0
T114	44822	315	0	0

host_timeout_ctrl_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	413684813	1307	0	0
T105	6715	26	0	0
T106	1862	4	0	0
T108	3229	18	0	0
T109	26402	241	0	0
T110	1787	8	0	0
T111	14523	188	0	0
T112	9476	15	0	0
T113	5608	76	0	0
T114	44822	266	0	0
T132	1881	2	0	0

intr_enable_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	413684813	4149	0	0
T35	144559	7	0	0
T42	0	5	0	0
T105	0	78	0	0
T106	0	50	0	0
T107	0	6	0	0
T108	0	28	0	0
T109	0	216	0	0
T133	0	37	0	0
T134	0	18	0	0
T135	0	7	0	0
T136	60665	0	0	0
T137	306503	0	0	0
T138	15027	0	0	0
T139	106961	0	0	0
T140	61012	0	0	0
T141	57167	0	0	0
T142	33462	0	0	0
T143	18768	0	0	0
T144	141952	0	0	0

ovrd_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	413684813	2859	0	0
T25	159430	0	0	0
T38	11147	0	0	0
T46	14103	0	0	0
T52	57000	0	0	0
T53	220661	0	0	0
T62	57893	0	0	0
T74	93630	0	0	0
T75	63317	0	0	0
T81	0	55	0	0
T102	1388	41	0	0
T145	0	43	0	0
T146	0	39	0	0
T147	0	19	0	0
T148	0	82	0	0
T149	0	62	0	0
T150	0	48	0	0
T151	0	36	0	0
T152	0	77	0	0
T153	48655	0	0	0

target_fifo_config_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	413684813	1714	0	0
T105	6715	56	0	0
T106	1862	16	0	0
T107	5862	9	0	0
T108	3229	6	0	0
T109	26402	227	0	0
T110	1787	4	0	0
T111	14523	229	0	0
T112	9476	42	0	0
T113	5608	122	0	0
T154	1971	1	0	0

target_id_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	413684813	2010	0	0
T105	6715	31	0	0
T106	1862	22	0	0
T107	5862	11	0	0
T108	3229	10	0	0
T109	26402	257	0	0
T110	1787	8	0	0
T111	14523	208	0	0
T112	9476	14	0	0
T113	5608	114	0	0
T154	1971	7	0	0

target_timeout_ctrl_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	413684813	1628	0	0
T105	6715	56	0	0
T107	5862	9	0	0
T108	3229	42	0	0
T109	26402	257	0	0
T110	1787	14	0	0
T111	14523	182	0	0
T112	9476	12	0	0
T113	5608	100	0	0
T114	44822	255	0	0
T132	1881	2	0	0

timeout_ctrl_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	413684813	2094	0	0
T105	6715	77	0	0
T106	1862	4	0	0
T107	5862	17	0	0
T108	3229	39	0	0
T109	26402	227	0	0
T110	1787	9	0	0
T111	14523	226	0	0
T112	9476	37	0	0
T113	5608	139	0	0
T154	1971	12	0	0

timing0_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	413684813	1648	0	0
T105	6715	36	0	0
T106	1862	20	0	0
T107	5862	19	0	0
T108	3229	28	0	0
T109	26402	213	0	0
T110	1787	4	0	0
T111	14523	214	0	0
T112	9476	35	0	0
T113	5608	111	0	0
T154	1971	13	0	0

timing1_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	413684813	1648	0	0
T105	6715	58	0	0
T106	1862	11	0	0
T107	5862	9	0	0
T109	26402	213	0	0
T110	1787	7	0	0
T111	14523	215	0	0
T112	9476	27	0	0
T113	5608	130	0	0
T114	44822	266	0	0
T154	1971	10	0	0

timing2_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	413684813	1689	0	0
T105	6715	37	0	0
T106	1862	4	0	0
T107	5862	4	0	0
T108	3229	36	0	0
T109	26402	233	0	0
T110	1787	11	0	0
T111	14523	231	0	0
T112	9476	9	0	0
T113	5608	134	0	0
T154	1971	5	0	0

timing3_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	413684813	1798	0	0
T105	6715	28	0	0
T106	1862	12	0	0
T107	5862	14	0	0
T108	3229	12	0	0
T109	26402	218	0	0
T110	1787	9	0	0
T111	14523	215	0	0
T112	9476	9	0	0
T113	5608	121	0	0
T154	1971	11	0	0

timing4_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	413684813	1563	0	0
T105	6715	22	0	0
T106	1862	9	0	0
T107	5862	12	0	0
T108	3229	22	0	0
T109	26402	200	0	0
T110	1787	11	0	0
T111	14523	188	0	0
T112	9476	22	0	0
T113	5608	132	0	0
T154	1971	8	0	0