Unified Coverage Report :: Group :: cip_base_pkg::intr_cg::SHAPE{(num_interrupts - 1)=14}

Group : cip_base_pkg::intr_cg::SHAPE{(num_interrupts - 1)=14}

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
91.14	1	100	1	64	64

Source File(s) :
/workspaces/repo/scratch/os_regression_2024_09_23/i2c-sim-vcs/default/sim-vcs/../src/lowrisc_dv_cip_lib_0/cip_base_env_cov.sv

---

Summary for Group cip_base_pkg::intr_cg::SHAPE{(num_interrupts - 1)=14}

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	19	0	19	100.00
Crosses	60	7	53	88.33

Variables for Group cip_base_pkg::intr_cg::SHAPE{(num_interrupts - 1)=14}

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
cp_intr	15	0	15	100.00	100	1	1	0
cp_intr_en	2	0	2	100.00	100	1	1	2
cp_intr_state	2	0	2	100.00	100	1	1	2

Crosses for Group cip_base_pkg::intr_cg::SHAPE{(num_interrupts - 1)=14}

CROSS	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	PRINT MISSING	COMMENT
intr_cg_cc	60	7	53	88.33	100	1	1	0

Summary for Variable cp_intr

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	15	0	15	100.00

User Defined Bins for cp_intr

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
all_values[0]	627620	1			T1	1		T2	2		T3	8
all_values[1]	627620	1			T1	1		T2	2		T3	8
all_values[2]	627620	1			T1	1		T2	2		T3	8
all_values[3]	627620	1			T1	1		T2	2		T3	8
all_values[4]	627620	1			T1	1		T2	2		T3	8
all_values[5]	627620	1			T1	1		T2	2		T3	8
all_values[6]	627620	1			T1	1		T2	2		T3	8
all_values[7]	627620	1			T1	1		T2	2		T3	8
all_values[8]	627620	1			T1	1		T2	2		T3	8
all_values[9]	627620	1			T1	1		T2	2		T3	8
all_values[10]	627620	1			T1	1		T2	2		T3	8
all_values[11]	627620	1			T1	1		T2	2		T3	8
all_values[12]	627620	1			T1	1		T2	2		T3	8
all_values[13]	627620	1			T1	1		T2	2		T3	8
all_values[14]	627620	1			T1	1		T2	2		T3	8

---

Summary for Variable cp_intr_en

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cp_intr_en

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

7787099

1

T1

15

T2

30

T3

120

auto[1]

1627201

1

T5

4

T6

4

T7

4

---

Summary for Variable cp_intr_state

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cp_intr_state

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

9239737

1

T1

15

T2

30

T3

120

auto[1]

174563

1

T118

124

T128

290

T129

5182

---

Summary for Cross intr_cg_cc

Samples crossed: cp_intr cp_intr_en cp_intr_state

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	60	7	53	88.33	7

Automatically Generated Cross Bins for intr_cg_cc

Uncovered bins

cp_intr	cp_intr_en	cp_intr_state	COUNT	AT LEAST	NUMBER	STATUS
[all_values[3]]	[auto[1]]	[auto[0]]	0	1	1
[all_values[5] , all_values[6]]	[auto[1]]	[auto[0]]	--	--	2
[all_values[8]]	[auto[1]]	[auto[0]]	0	1	1
[all_values[10]]	[auto[1]]	[auto[0]]	0	1	1
[all_values[13] , all_values[14]]	[auto[1]]	[auto[0]]	--	--	2

Covered bins

cp_intr	cp_intr_en	cp_intr_state	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
all_values[0]	auto[0]	auto[0]	115836	1			T1	1		T2	2		T3	8
all_values[0]	auto[0]	auto[1]	828	1			T118	5		T128	5		T129	13
all_values[0]	auto[1]	auto[0]	500141	1			T5	2		T6	2		T7	2
all_values[0]	auto[1]	auto[1]	10815	1			T118	4		T128	14		T129	332
all_values[1]	auto[0]	auto[0]	615729	1			T1	1		T2	2		T3	8
all_values[1]	auto[0]	auto[1]	11512	1			T118	4		T128	16		T129	340
all_values[1]	auto[1]	auto[0]	263	1			T30	57		T181	1		T272	7
all_values[1]	auto[1]	auto[1]	116	1			T118	5		T128	4		T129	5
all_values[2]	auto[0]	auto[0]	615795	1			T1	1		T2	2		T3	8
all_values[2]	auto[0]	auto[1]	11508	1			T118	4		T128	13		T129	337
all_values[2]	auto[1]	auto[0]	194	1			T72	1		T197	2		T64	1
all_values[2]	auto[1]	auto[1]	123	1			T118	4		T128	4		T129	6
all_values[3]	auto[0]	auto[0]	615994	1			T1	1		T2	2		T3	8
all_values[3]	auto[0]	auto[1]	11476	1			T118	5		T128	13		T129	341
all_values[3]	auto[1]	auto[1]	150	1			T118	4		T128	7		T129	5
all_values[4]	auto[0]	auto[0]	615952	1			T1	1		T2	2		T3	8
all_values[4]	auto[0]	auto[1]	11521	1			T118	5		T128	15		T129	340
all_values[4]	auto[1]	auto[0]	18	1			T12	1		T261	1		T255	1
all_values[4]	auto[1]	auto[1]	129	1			T118	2		T128	5		T129	5
all_values[5]	auto[0]	auto[0]	615984	1			T1	1		T2	2		T3	8
all_values[5]	auto[0]	auto[1]	11496	1			T118	6		T128	9		T129	335
all_values[5]	auto[1]	auto[1]	140	1			T118	3		T128	10		T129	11
all_values[6]	auto[0]	auto[0]	615977	1			T1	1		T2	2		T3	8
all_values[6]	auto[0]	auto[1]	11502	1			T118	7		T128	15		T129	342
all_values[6]	auto[1]	auto[1]	141	1			T118	2		T128	5		T129	4
all_values[7]	auto[0]	auto[0]	589429	1			T1	1		T2	2		T3	8
all_values[7]	auto[0]	auto[1]	11275	1			T118	5		T128	15		T129	288
all_values[7]	auto[1]	auto[0]	26549	1			T9	2		T23	1		T11	17
all_values[7]	auto[1]	auto[1]	367	1			T118	4		T128	5		T129	57
all_values[8]	auto[0]	auto[0]	615988	1			T1	1		T2	2		T3	8
all_values[8]	auto[0]	auto[1]	11461	1			T118	4		T128	11		T129	338
all_values[8]	auto[1]	auto[1]	171	1			T118	5		T128	8		T129	8
all_values[9]	auto[0]	auto[0]	164631	1			T1	1		T2	2		T3	8
all_values[9]	auto[0]	auto[1]	1005	1			T118	4		T128	14		T129	319
all_values[9]	auto[1]	auto[0]	451337	1			T8	1		T9	2		T10	1
all_values[9]	auto[1]	auto[1]	10647	1			T118	2		T128	6		T129	27
all_values[10]	auto[0]	auto[0]	615987	1			T1	1		T2	2		T3	8
all_values[10]	auto[0]	auto[1]	11516	1			T118	4		T128	16		T129	336
all_values[10]	auto[1]	auto[1]	117	1			T118	2		T128	4		T129	9
all_values[11]	auto[0]	auto[0]	2124	1			T1	1		T2	2		T3	8
all_values[11]	auto[0]	auto[1]	189	1			T118	5		T128	7		T129	13
all_values[11]	auto[1]	auto[0]	613865	1			T5	2		T6	2		T7	2
all_values[11]	auto[1]	auto[1]	11442	1			T118	4		T128	12		T129	333
all_values[12]	auto[0]	auto[0]	615903	1			T1	1		T2	2		T3	8
all_values[12]	auto[0]	auto[1]	11521	1			T118	6		T128	15		T129	341
all_values[12]	auto[1]	auto[0]	66	1			T64	1		T68	1		T69	1
all_values[12]	auto[1]	auto[1]	130	1			T118	3		T128	5		T129	5
all_values[13]	auto[0]	auto[0]	615982	1			T1	1		T2	2		T3	8
all_values[13]	auto[0]	auto[1]	11492	1			T118	2		T128	13		T129	339
all_values[13]	auto[1]	auto[1]	146	1			T118	6		T128	6		T129	7
all_values[14]	auto[0]	auto[0]	615993	1			T1	1		T2	2		T3	8
all_values[14]	auto[0]	auto[1]	11493	1			T118	4		T128	13		T129	340
all_values[14]	auto[1]	auto[1]	134	1			T118	4		T128	5		T129	6