Tests
dashboard | hierarchy | modlist | groups | tests | asserts
Total Coverage Summary 
SCORELINECONDTOGGLEFSMBRANCHASSERTGROUP
91.26 97.26 89.54 97.22 72.02 94.30 98.47 90.00


Total tests in report: 1829
Tests are in graded order

Scores are accumulated (Total) and incremental (Incr) for each test.

SCORE LINE COND TOGGLE FSM BRANCH ASSERT GROUP  
TOTAL INCRTOTALINCRTOTALINCRTOTALINCRTOTALINCRTOTALINCRTOTALINCRTOTALINCRNAME
65.33 65.33 84.43 84.43 63.83 63.83 89.10 89.10 19.64 19.64 76.19 76.19 87.77 87.77 36.32 36.32 /workspaces/repo/scratch/os_regression_2024_09_23/i2c-sim-vcs/coverage/default/0.i2c_host_mode_toggle.2026697802
74.47 9.15 92.43 8.00 73.88 10.05 90.72 1.62 39.88 20.24 86.74 10.55 90.83 3.06 46.84 10.53 /workspaces/repo/scratch/os_regression_2024_09_23/i2c-sim-vcs/coverage/default/0.i2c_target_perf.2021916290
78.51 4.04 92.80 0.37 74.86 0.98 90.95 0.23 64.29 24.40 87.31 0.57 91.05 0.22 48.32 1.47 /workspaces/repo/scratch/os_regression_2024_09_23/i2c-sim-vcs/coverage/default/1.i2c_target_glitch.487899282
81.55 3.04 93.97 1.17 76.85 1.99 91.18 0.23 64.29 0.00 87.81 0.50 91.27 0.22 65.47 17.16 /workspaces/repo/scratch/os_regression_2024_09_23/i2c-sim-vcs/coverage/default/36.i2c_host_stress_all.1835482549
82.83 1.28 94.00 0.03 78.06 1.20 92.11 0.93 64.29 0.00 87.88 0.07 94.76 3.49 68.74 3.26 /workspaces/repo/scratch/os_regression_2024_09_23/i2c-sim-vcs/coverage/cover_reg_top/2.i2c_tl_errors.2512834294
84.04 1.21 94.49 0.49 79.86 1.81 92.58 0.46 64.88 0.60 88.88 1.00 94.98 0.22 72.63 3.89 /workspaces/repo/scratch/os_regression_2024_09_23/i2c-sim-vcs/coverage/default/0.i2c_host_may_nack.302867335
84.81 0.77 95.01 0.52 82.09 2.22 92.81 0.23 64.88 0.00 89.67 0.78 95.85 0.87 73.37 0.74 /workspaces/repo/scratch/os_regression_2024_09_23/i2c-sim-vcs/coverage/default/0.i2c_host_fifo_watermark.2133094151
85.50 0.69 95.20 0.18 83.70 1.62 93.50 0.70 66.67 1.79 90.09 0.43 95.85 0.00 73.47 0.11 /workspaces/repo/scratch/os_regression_2024_09_23/i2c-sim-vcs/coverage/default/10.i2c_host_error_intr.1010473746
86.16 0.66 95.60 0.40 85.36 1.66 93.97 0.46 67.26 0.60 91.38 1.28 96.07 0.22 73.47 0.00 /workspaces/repo/scratch/os_regression_2024_09_23/i2c-sim-vcs/coverage/default/1.i2c_target_nack_txstretch.728934281
86.67 0.51 95.88 0.28 85.92 0.56 94.20 0.23 67.26 0.00 92.16 0.78 96.29 0.22 74.95 1.47 /workspaces/repo/scratch/os_regression_2024_09_23/i2c-sim-vcs/coverage/default/1.i2c_host_override.381802836
87.10 0.44 95.91 0.03 86.04 0.11 96.29 2.09 67.26 0.00 92.23 0.07 96.51 0.22 75.47 0.53 /workspaces/repo/scratch/os_regression_2024_09_23/i2c-sim-vcs/coverage/default/0.i2c_sec_cm.1535272988
87.52 0.42 96.15 0.25 86.53 0.49 96.52 0.23 68.45 1.19 92.59 0.36 96.51 0.00 75.89 0.42 /workspaces/repo/scratch/os_regression_2024_09_23/i2c-sim-vcs/coverage/default/3.i2c_target_stress_all.556215413
87.92 0.40 96.21 0.06 87.05 0.53 96.75 0.23 68.45 0.00 92.87 0.29 96.72 0.22 77.37 1.47 /workspaces/repo/scratch/os_regression_2024_09_23/i2c-sim-vcs/coverage/default/2.i2c_host_fifo_reset_rx.3276999275
88.29 0.37 96.65 0.43 87.05 0.00 96.75 0.00 69.64 1.19 93.30 0.43 96.72 0.00 77.89 0.53 /workspaces/repo/scratch/os_regression_2024_09_23/i2c-sim-vcs/coverage/default/6.i2c_target_nack_acqfull_addr.320635278
88.57 0.28 96.65 0.00 87.13 0.08 96.75 0.00 69.64 0.00 93.30 0.00 96.72 0.00 79.79 1.89 /workspaces/repo/scratch/os_regression_2024_09_23/i2c-sim-vcs/coverage/default/1.i2c_host_fifo_reset_fmt.3312641653
88.80 0.23 96.68 0.03 87.17 0.04 96.75 0.00 69.64 0.00 93.30 0.00 98.25 1.53 79.79 0.00 /workspaces/repo/scratch/os_regression_2024_09_23/i2c-sim-vcs/coverage/cover_reg_top/1.i2c_csr_rw.880526785
89.01 0.21 96.83 0.15 87.39 0.23 96.75 0.00 70.24 0.60 93.51 0.21 98.25 0.00 80.11 0.32 /workspaces/repo/scratch/os_regression_2024_09_23/i2c-sim-vcs/coverage/default/0.i2c_target_nack_acqfull.2975799640
89.19 0.17 96.83 0.00 87.77 0.38 96.75 0.00 70.24 0.00 93.51 0.00 98.25 0.00 80.95 0.84 /workspaces/repo/scratch/os_regression_2024_09_23/i2c-sim-vcs/coverage/cover_reg_top/1.i2c_tl_intg_err.46362042
89.36 0.17 96.86 0.03 87.77 0.00 96.75 0.00 70.83 0.60 93.66 0.14 98.25 0.00 81.37 0.42 /workspaces/repo/scratch/os_regression_2024_09_23/i2c-sim-vcs/coverage/default/1.i2c_target_bad_addr.2277887072
89.52 0.17 96.86 0.00 87.77 0.00 96.75 0.00 70.83 0.00 93.66 0.00 98.25 0.00 82.53 1.16 /workspaces/repo/scratch/os_regression_2024_09_23/i2c-sim-vcs/coverage/cover_reg_top/14.i2c_intr_test.723198161
89.67 0.15 96.98 0.12 87.88 0.11 96.75 0.00 71.43 0.60 93.87 0.21 98.25 0.00 82.53 0.00 /workspaces/repo/scratch/os_regression_2024_09_23/i2c-sim-vcs/coverage/default/32.i2c_host_error_intr.3676234830
89.81 0.14 96.98 0.00 87.88 0.00 96.75 0.00 71.43 0.00 93.87 0.00 98.25 0.00 83.47 0.95 /workspaces/repo/scratch/os_regression_2024_09_23/i2c-sim-vcs/coverage/default/23.i2c_host_stress_all.3470015842
89.93 0.12 97.11 0.12 87.88 0.00 96.75 0.00 72.02 0.60 94.01 0.14 98.25 0.00 83.47 0.00 /workspaces/repo/scratch/os_regression_2024_09_23/i2c-sim-vcs/coverage/default/19.i2c_target_nack_acqfull.621171804
90.04 0.11 97.11 0.00 88.41 0.53 96.98 0.23 72.02 0.00 94.01 0.00 98.25 0.00 83.47 0.00 /workspaces/repo/scratch/os_regression_2024_09_23/i2c-sim-vcs/coverage/default/2.i2c_host_fifo_overflow.3941463460
90.14 0.11 97.11 0.00 88.41 0.00 96.98 0.00 72.02 0.00 94.01 0.00 98.25 0.00 84.21 0.74 /workspaces/repo/scratch/os_regression_2024_09_23/i2c-sim-vcs/coverage/default/0.i2c_target_stress_all.3938802092
90.25 0.11 97.11 0.00 88.41 0.00 96.98 0.00 72.02 0.00 94.01 0.00 98.25 0.00 84.95 0.74 /workspaces/repo/scratch/os_regression_2024_09_23/i2c-sim-vcs/coverage/default/1.i2c_host_perf_precise.1392135284
90.32 0.08 97.11 0.00 88.41 0.00 96.98 0.00 72.02 0.00 94.01 0.00 98.25 0.00 85.47 0.53 /workspaces/repo/scratch/os_regression_2024_09_23/i2c-sim-vcs/coverage/cover_reg_top/10.i2c_intr_test.2791122152
90.40 0.08 97.11 0.00 88.41 0.00 96.98 0.00 72.02 0.00 94.01 0.00 98.25 0.00 86.00 0.53 /workspaces/repo/scratch/os_regression_2024_09_23/i2c-sim-vcs/coverage/default/0.i2c_target_fifo_watermarks_acq.1342053675
90.47 0.08 97.11 0.00 88.41 0.00 96.98 0.00 72.02 0.00 94.01 0.00 98.25 0.00 86.53 0.53 /workspaces/repo/scratch/os_regression_2024_09_23/i2c-sim-vcs/coverage/default/14.i2c_host_stretch_timeout.2598407092
90.54 0.07 97.11 0.00 88.48 0.08 96.98 0.00 72.02 0.00 94.01 0.00 98.25 0.00 86.95 0.42 /workspaces/repo/scratch/os_regression_2024_09_23/i2c-sim-vcs/coverage/default/3.i2c_host_may_nack.2710852294
90.61 0.07 97.23 0.12 88.60 0.11 97.22 0.23 72.02 0.00 94.01 0.00 98.25 0.00 86.95 0.00 /workspaces/repo/scratch/os_regression_2024_09_23/i2c-sim-vcs/coverage/default/0.i2c_alert_test.2136136360
90.67 0.06 97.23 0.00 88.75 0.15 97.22 0.00 72.02 0.00 94.08 0.07 98.47 0.22 86.95 0.00 /workspaces/repo/scratch/os_regression_2024_09_23/i2c-sim-vcs/coverage/default/5.i2c_target_smoke.3538056579
90.73 0.06 97.23 0.00 88.75 0.00 97.22 0.00 72.02 0.00 94.08 0.00 98.47 0.00 87.37 0.42 /workspaces/repo/scratch/os_regression_2024_09_23/i2c-sim-vcs/coverage/default/11.i2c_host_fifo_reset_rx.3090182736
90.79 0.06 97.23 0.00 88.93 0.19 97.22 0.00 72.02 0.00 94.08 0.00 98.47 0.00 87.58 0.21 /workspaces/repo/scratch/os_regression_2024_09_23/i2c-sim-vcs/coverage/cover_reg_top/6.i2c_tl_intg_err.3228786713
90.84 0.05 97.23 0.00 88.93 0.00 97.22 0.00 72.02 0.00 94.08 0.00 98.47 0.00 87.89 0.32 /workspaces/repo/scratch/os_regression_2024_09_23/i2c-sim-vcs/coverage/default/22.i2c_host_may_nack.125110679
90.87 0.04 97.23 0.00 89.01 0.08 97.22 0.00 72.02 0.00 94.16 0.07 98.47 0.00 88.00 0.11 /workspaces/repo/scratch/os_regression_2024_09_23/i2c-sim-vcs/coverage/default/4.i2c_target_stress_all.2647707851
90.90 0.03 97.23 0.00 89.01 0.00 97.22 0.00 72.02 0.00 94.16 0.00 98.47 0.00 88.21 0.21 /workspaces/repo/scratch/os_regression_2024_09_23/i2c-sim-vcs/coverage/cover_reg_top/0.i2c_intr_test.2796509678
90.93 0.03 97.23 0.00 89.01 0.00 97.22 0.00 72.02 0.00 94.16 0.00 98.47 0.00 88.42 0.21 /workspaces/repo/scratch/os_regression_2024_09_23/i2c-sim-vcs/coverage/default/11.i2c_host_fifo_reset_fmt.77600495
90.96 0.03 97.23 0.00 89.01 0.00 97.22 0.00 72.02 0.00 94.16 0.00 98.47 0.00 88.63 0.21 /workspaces/repo/scratch/os_regression_2024_09_23/i2c-sim-vcs/coverage/default/23.i2c_host_may_nack.2921208232
90.99 0.03 97.23 0.00 89.01 0.00 97.22 0.00 72.02 0.00 94.16 0.00 98.47 0.00 88.84 0.21 /workspaces/repo/scratch/os_regression_2024_09_23/i2c-sim-vcs/coverage/default/35.i2c_host_override.724963550
91.02 0.03 97.23 0.00 89.01 0.00 97.22 0.00 72.02 0.00 94.16 0.00 98.47 0.00 89.05 0.21 /workspaces/repo/scratch/os_regression_2024_09_23/i2c-sim-vcs/coverage/default/41.i2c_target_fifo_reset_tx.3839407005
91.04 0.02 97.26 0.03 89.05 0.04 97.22 0.00 72.02 0.00 94.23 0.07 98.47 0.00 89.05 0.00 /workspaces/repo/scratch/os_regression_2024_09_23/i2c-sim-vcs/coverage/default/11.i2c_host_perf.1617636500
91.06 0.02 97.26 0.00 89.09 0.04 97.22 0.00 72.02 0.00 94.30 0.07 98.47 0.00 89.05 0.00 /workspaces/repo/scratch/os_regression_2024_09_23/i2c-sim-vcs/coverage/default/2.i2c_host_perf.1661788194
91.07 0.02 97.26 0.00 89.09 0.00 97.22 0.00 72.02 0.00 94.30 0.00 98.47 0.00 89.16 0.11 /workspaces/repo/scratch/os_regression_2024_09_23/i2c-sim-vcs/coverage/cover_reg_top/1.i2c_intr_test.2916651608
91.09 0.02 97.26 0.00 89.09 0.00 97.22 0.00 72.02 0.00 94.30 0.00 98.47 0.00 89.26 0.11 /workspaces/repo/scratch/os_regression_2024_09_23/i2c-sim-vcs/coverage/default/0.i2c_target_fifo_reset_acq.2013092478
91.10 0.02 97.26 0.00 89.09 0.00 97.22 0.00 72.02 0.00 94.30 0.00 98.47 0.00 89.37 0.11 /workspaces/repo/scratch/os_regression_2024_09_23/i2c-sim-vcs/coverage/default/0.i2c_target_stress_rd.3415696464
91.12 0.02 97.26 0.00 89.09 0.00 97.22 0.00 72.02 0.00 94.30 0.00 98.47 0.00 89.47 0.11 /workspaces/repo/scratch/os_regression_2024_09_23/i2c-sim-vcs/coverage/default/0.i2c_target_tx_stretch_ctrl.3801738653
91.13 0.02 97.26 0.00 89.09 0.00 97.22 0.00 72.02 0.00 94.30 0.00 98.47 0.00 89.58 0.11 /workspaces/repo/scratch/os_regression_2024_09_23/i2c-sim-vcs/coverage/default/11.i2c_host_may_nack.2563235958
91.15 0.02 97.26 0.00 89.09 0.00 97.22 0.00 72.02 0.00 94.30 0.00 98.47 0.00 89.68 0.11 /workspaces/repo/scratch/os_regression_2024_09_23/i2c-sim-vcs/coverage/default/12.i2c_host_mode_toggle.1409867440
91.16 0.02 97.26 0.00 89.09 0.00 97.22 0.00 72.02 0.00 94.30 0.00 98.47 0.00 89.79 0.11 /workspaces/repo/scratch/os_regression_2024_09_23/i2c-sim-vcs/coverage/default/12.i2c_target_fifo_reset_acq.3781843833
91.18 0.02 97.26 0.00 89.09 0.00 97.22 0.00 72.02 0.00 94.30 0.00 98.47 0.00 89.89 0.11 /workspaces/repo/scratch/os_regression_2024_09_23/i2c-sim-vcs/coverage/default/12.i2c_target_intr_smoke.576113932
91.19 0.02 97.26 0.00 89.09 0.00 97.22 0.00 72.02 0.00 94.30 0.00 98.47 0.00 90.00 0.11 /workspaces/repo/scratch/os_regression_2024_09_23/i2c-sim-vcs/coverage/default/2.i2c_target_smoke.447113131
91.20 0.01 97.26 0.00 89.16 0.08 97.22 0.00 72.02 0.00 94.30 0.00 98.47 0.00 90.00 0.00 /workspaces/repo/scratch/os_regression_2024_09_23/i2c-sim-vcs/coverage/cover_reg_top/10.i2c_tl_intg_err.2388344137
91.22 0.01 97.26 0.00 89.24 0.08 97.22 0.00 72.02 0.00 94.30 0.00 98.47 0.00 90.00 0.00 /workspaces/repo/scratch/os_regression_2024_09_23/i2c-sim-vcs/coverage/cover_reg_top/11.i2c_tl_errors.3741571826
91.23 0.01 97.26 0.00 89.31 0.08 97.22 0.00 72.02 0.00 94.30 0.00 98.47 0.00 90.00 0.00 /workspaces/repo/scratch/os_regression_2024_09_23/i2c-sim-vcs/coverage/default/42.i2c_host_error_intr.484339055
91.23 0.01 97.26 0.00 89.35 0.04 97.22 0.00 72.02 0.00 94.30 0.00 98.47 0.00 90.00 0.00 /workspaces/repo/scratch/os_regression_2024_09_23/i2c-sim-vcs/coverage/cover_reg_top/1.i2c_same_csr_outstanding.3330707967
91.24 0.01 97.26 0.00 89.39 0.04 97.22 0.00 72.02 0.00 94.30 0.00 98.47 0.00 90.00 0.00 /workspaces/repo/scratch/os_regression_2024_09_23/i2c-sim-vcs/coverage/cover_reg_top/17.i2c_tl_intg_err.540104495
91.24 0.01 97.26 0.00 89.42 0.04 97.22 0.00 72.02 0.00 94.30 0.00 98.47 0.00 90.00 0.00 /workspaces/repo/scratch/os_regression_2024_09_23/i2c-sim-vcs/coverage/default/1.i2c_host_fifo_full.3852597485
91.25 0.01 97.26 0.00 89.46 0.04 97.22 0.00 72.02 0.00 94.30 0.00 98.47 0.00 90.00 0.00 /workspaces/repo/scratch/os_regression_2024_09_23/i2c-sim-vcs/coverage/default/1.i2c_target_hrst.1312024435
91.25 0.01 97.26 0.00 89.50 0.04 97.22 0.00 72.02 0.00 94.30 0.00 98.47 0.00 90.00 0.00 /workspaces/repo/scratch/os_regression_2024_09_23/i2c-sim-vcs/coverage/default/11.i2c_host_error_intr.2293719203
91.26 0.01 97.26 0.00 89.54 0.04 97.22 0.00 72.02 0.00 94.30 0.00 98.47 0.00 90.00 0.00 /workspaces/repo/scratch/os_regression_2024_09_23/i2c-sim-vcs/coverage/default/16.i2c_host_mode_toggle.1896215818

Tests that do not contribute to grading

Name
/workspaces/repo/scratch/os_regression_2024_09_23/i2c-sim-vcs/coverage/cover_reg_top/0.i2c_csr_aliasing.4206325874
/workspaces/repo/scratch/os_regression_2024_09_23/i2c-sim-vcs/coverage/cover_reg_top/0.i2c_csr_bit_bash.2614920509
/workspaces/repo/scratch/os_regression_2024_09_23/i2c-sim-vcs/coverage/cover_reg_top/0.i2c_csr_hw_reset.2505535295
/workspaces/repo/scratch/os_regression_2024_09_23/i2c-sim-vcs/coverage/cover_reg_top/0.i2c_csr_mem_rw_with_rand_reset.1540684372
/workspaces/repo/scratch/os_regression_2024_09_23/i2c-sim-vcs/coverage/cover_reg_top/0.i2c_csr_rw.2319708394
/workspaces/repo/scratch/os_regression_2024_09_23/i2c-sim-vcs/coverage/cover_reg_top/0.i2c_same_csr_outstanding.2074475230
/workspaces/repo/scratch/os_regression_2024_09_23/i2c-sim-vcs/coverage/cover_reg_top/0.i2c_tl_errors.2789473442
/workspaces/repo/scratch/os_regression_2024_09_23/i2c-sim-vcs/coverage/cover_reg_top/0.i2c_tl_intg_err.2219918681
/workspaces/repo/scratch/os_regression_2024_09_23/i2c-sim-vcs/coverage/cover_reg_top/1.i2c_csr_aliasing.4200244862
/workspaces/repo/scratch/os_regression_2024_09_23/i2c-sim-vcs/coverage/cover_reg_top/1.i2c_csr_bit_bash.3374112289
/workspaces/repo/scratch/os_regression_2024_09_23/i2c-sim-vcs/coverage/cover_reg_top/1.i2c_csr_hw_reset.3216668810
/workspaces/repo/scratch/os_regression_2024_09_23/i2c-sim-vcs/coverage/cover_reg_top/1.i2c_csr_mem_rw_with_rand_reset.151220331
/workspaces/repo/scratch/os_regression_2024_09_23/i2c-sim-vcs/coverage/cover_reg_top/1.i2c_tl_errors.3542340085
/workspaces/repo/scratch/os_regression_2024_09_23/i2c-sim-vcs/coverage/cover_reg_top/10.i2c_csr_mem_rw_with_rand_reset.1311643746
/workspaces/repo/scratch/os_regression_2024_09_23/i2c-sim-vcs/coverage/cover_reg_top/10.i2c_csr_rw.4177860610
/workspaces/repo/scratch/os_regression_2024_09_23/i2c-sim-vcs/coverage/cover_reg_top/10.i2c_same_csr_outstanding.3607090272
/workspaces/repo/scratch/os_regression_2024_09_23/i2c-sim-vcs/coverage/cover_reg_top/10.i2c_tl_errors.3017027590
/workspaces/repo/scratch/os_regression_2024_09_23/i2c-sim-vcs/coverage/cover_reg_top/11.i2c_csr_mem_rw_with_rand_reset.2117976768
/workspaces/repo/scratch/os_regression_2024_09_23/i2c-sim-vcs/coverage/cover_reg_top/11.i2c_csr_rw.2178341419
/workspaces/repo/scratch/os_regression_2024_09_23/i2c-sim-vcs/coverage/cover_reg_top/11.i2c_intr_test.3587465954
/workspaces/repo/scratch/os_regression_2024_09_23/i2c-sim-vcs/coverage/cover_reg_top/11.i2c_same_csr_outstanding.2477033234
/workspaces/repo/scratch/os_regression_2024_09_23/i2c-sim-vcs/coverage/cover_reg_top/11.i2c_tl_intg_err.2239862796
/workspaces/repo/scratch/os_regression_2024_09_23/i2c-sim-vcs/coverage/cover_reg_top/12.i2c_csr_mem_rw_with_rand_reset.652539
/workspaces/repo/scratch/os_regression_2024_09_23/i2c-sim-vcs/coverage/cover_reg_top/12.i2c_csr_rw.3540717317
/workspaces/repo/scratch/os_regression_2024_09_23/i2c-sim-vcs/coverage/cover_reg_top/12.i2c_intr_test.977142862
/workspaces/repo/scratch/os_regression_2024_09_23/i2c-sim-vcs/coverage/cover_reg_top/12.i2c_same_csr_outstanding.2232936075
/workspaces/repo/scratch/os_regression_2024_09_23/i2c-sim-vcs/coverage/cover_reg_top/12.i2c_tl_errors.4261924156
/workspaces/repo/scratch/os_regression_2024_09_23/i2c-sim-vcs/coverage/cover_reg_top/12.i2c_tl_intg_err.714873621
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/workspaces/repo/scratch/os_regression_2024_09_23/i2c-sim-vcs/coverage/default/9.i2c_target_tx_stretch_ctrl.2733108792



Total test records in report: 1829
tests.html | tests1.html | tests2.html | tests3.html | tests4.html | tests5.html | tests6.html | tests7.html | tests8.html | tests9.html | tests10.html | tests11.html | tests12.html | tests13.html | tests14.html | tests15.html | tests16.html | tests17.html | tests18.html | tests19.html | tests20.html | tests21.html | tests22.html | tests23.html | tests24.html | tests25.html | tests26.html | tests27.html | tests28.html | tests29.html | tests30.html | tests31.html | tests32.html | tests33.html | tests34.html | tests35.html | tests36.html | tests37.html | tests38.html
TEST NOTEST LOCATIONTEST NAMESTATUSSTARTEDFINISHEDSIMULATION TIME
T1 /workspaces/repo/scratch/os_regression_2024_09_23/i2c-sim-vcs/coverage/default/0.i2c_host_override.2832595425 Sep 24 08:14:31 AM UTC 24 Sep 24 08:14:33 AM UTC 24 29186996 ps
T2 /workspaces/repo/scratch/os_regression_2024_09_23/i2c-sim-vcs/coverage/default/0.i2c_host_fifo_reset_fmt.184901129 Sep 24 08:14:31 AM UTC 24 Sep 24 08:14:33 AM UTC 24 80105873 ps
T3 /workspaces/repo/scratch/os_regression_2024_09_23/i2c-sim-vcs/coverage/default/0.i2c_host_error_intr.3290816443 Sep 24 08:14:34 AM UTC 24 Sep 24 08:14:36 AM UTC 24 83493846 ps
T4 /workspaces/repo/scratch/os_regression_2024_09_23/i2c-sim-vcs/coverage/default/3.i2c_host_override.46191208 Sep 24 08:15:25 AM UTC 24 Sep 24 08:15:28 AM UTC 24 27699505 ps
T5 /workspaces/repo/scratch/os_regression_2024_09_23/i2c-sim-vcs/coverage/default/0.i2c_target_stretch.3306527114 Sep 24 08:14:34 AM UTC 24 Sep 24 08:14:39 AM UTC 24 4402772870 ps
T6 /workspaces/repo/scratch/os_regression_2024_09_23/i2c-sim-vcs/coverage/default/0.i2c_target_fifo_reset_tx.1543228440 Sep 24 08:14:37 AM UTC 24 Sep 24 08:14:39 AM UTC 24 509980354 ps
T7 /workspaces/repo/scratch/os_regression_2024_09_23/i2c-sim-vcs/coverage/default/0.i2c_target_fifo_reset_acq.2013092478 Sep 24 08:14:37 AM UTC 24 Sep 24 08:14:40 AM UTC 24 253903495 ps
T8 /workspaces/repo/scratch/os_regression_2024_09_23/i2c-sim-vcs/coverage/default/0.i2c_host_fifo_reset_rx.3890660220 Sep 24 08:14:32 AM UTC 24 Sep 24 08:14:40 AM UTC 24 146878185 ps
T9 /workspaces/repo/scratch/os_regression_2024_09_23/i2c-sim-vcs/coverage/default/0.i2c_host_perf.3728420241 Sep 24 08:14:32 AM UTC 24 Sep 24 08:14:43 AM UTC 24 246120515 ps
T10 /workspaces/repo/scratch/os_regression_2024_09_23/i2c-sim-vcs/coverage/default/0.i2c_host_mode_toggle.2026697802 Sep 24 08:14:40 AM UTC 24 Sep 24 08:14:44 AM UTC 24 89025250 ps
T44 /workspaces/repo/scratch/os_regression_2024_09_23/i2c-sim-vcs/coverage/default/0.i2c_target_perf.2021916290 Sep 24 08:14:38 AM UTC 24 Sep 24 08:14:44 AM UTC 24 404862461 ps
T23 /workspaces/repo/scratch/os_regression_2024_09_23/i2c-sim-vcs/coverage/default/0.i2c_host_fifo_fmt_empty.2417518536 Sep 24 08:14:32 AM UTC 24 Sep 24 08:14:47 AM UTC 24 434729113 ps
T47 /workspaces/repo/scratch/os_regression_2024_09_23/i2c-sim-vcs/coverage/default/0.i2c_target_timeout.2027014984 Sep 24 08:14:36 AM UTC 24 Sep 24 08:14:47 AM UTC 24 1258184353 ps
T72 /workspaces/repo/scratch/os_regression_2024_09_23/i2c-sim-vcs/coverage/default/0.i2c_target_fifo_watermarks_acq.1342053675 Sep 24 08:14:44 AM UTC 24 Sep 24 08:14:48 AM UTC 24 1689362933 ps
T73 /workspaces/repo/scratch/os_regression_2024_09_23/i2c-sim-vcs/coverage/default/0.i2c_target_fifo_watermarks_tx.2307920392 Sep 24 08:14:45 AM UTC 24 Sep 24 08:14:48 AM UTC 24 476490584 ps
T11 /workspaces/repo/scratch/os_regression_2024_09_23/i2c-sim-vcs/coverage/default/0.i2c_host_may_nack.302867335 Sep 24 08:14:42 AM UTC 24 Sep 24 08:14:48 AM UTC 24 730955600 ps
T74 /workspaces/repo/scratch/os_regression_2024_09_23/i2c-sim-vcs/coverage/default/0.i2c_target_intr_smoke.2434122851 Sep 24 08:14:35 AM UTC 24 Sep 24 08:14:48 AM UTC 24 1437006906 ps
T75 /workspaces/repo/scratch/os_regression_2024_09_23/i2c-sim-vcs/coverage/default/0.i2c_target_stress_rd.3415696464 Sep 24 08:14:34 AM UTC 24 Sep 24 08:14:49 AM UTC 24 5584864039 ps
T45 /workspaces/repo/scratch/os_regression_2024_09_23/i2c-sim-vcs/coverage/default/0.i2c_target_bad_addr.4225490856 Sep 24 08:14:39 AM UTC 24 Sep 24 08:14:49 AM UTC 24 4052655834 ps
T97 /workspaces/repo/scratch/os_regression_2024_09_23/i2c-sim-vcs/coverage/default/0.i2c_alert_test.2136136360 Sep 24 08:14:48 AM UTC 24 Sep 24 08:14:50 AM UTC 24 31602525 ps
T41 /workspaces/repo/scratch/os_regression_2024_09_23/i2c-sim-vcs/coverage/default/0.i2c_host_perf_precise.4165423981 Sep 24 08:14:32 AM UTC 24 Sep 24 08:14:50 AM UTC 24 437120406 ps
T191 /workspaces/repo/scratch/os_regression_2024_09_23/i2c-sim-vcs/coverage/default/0.i2c_sec_cm.1535272988 Sep 24 08:14:48 AM UTC 24 Sep 24 08:14:50 AM UTC 24 143292417 ps
T197 /workspaces/repo/scratch/os_regression_2024_09_23/i2c-sim-vcs/coverage/default/0.i2c_target_smbus_maxlen.2675182198 Sep 24 08:14:46 AM UTC 24 Sep 24 08:14:51 AM UTC 24 2222722247 ps
T76 /workspaces/repo/scratch/os_regression_2024_09_23/i2c-sim-vcs/coverage/default/2.i2c_target_timeout.2786094683 Sep 24 08:15:13 AM UTC 24 Sep 24 08:15:25 AM UTC 24 1060044375 ps
T63 /workspaces/repo/scratch/os_regression_2024_09_23/i2c-sim-vcs/coverage/default/0.i2c_target_nack_acqfull.2975799640 Sep 24 08:14:47 AM UTC 24 Sep 24 08:14:51 AM UTC 24 1119760466 ps
T50 /workspaces/repo/scratch/os_regression_2024_09_23/i2c-sim-vcs/coverage/default/0.i2c_target_glitch.1016355343 Sep 24 08:14:34 AM UTC 24 Sep 24 08:14:51 AM UTC 24 10435261123 ps
T100 /workspaces/repo/scratch/os_regression_2024_09_23/i2c-sim-vcs/coverage/default/1.i2c_host_override.381802836 Sep 24 08:14:49 AM UTC 24 Sep 24 08:14:51 AM UTC 24 237570554 ps
T42 /workspaces/repo/scratch/os_regression_2024_09_23/i2c-sim-vcs/coverage/default/2.i2c_host_fifo_reset_rx.3276999275 Sep 24 08:15:10 AM UTC 24 Sep 24 08:15:17 AM UTC 24 373166449 ps
T34 /workspaces/repo/scratch/os_regression_2024_09_23/i2c-sim-vcs/coverage/default/1.i2c_host_fifo_reset_fmt.3312641653 Sep 24 08:14:49 AM UTC 24 Sep 24 08:14:52 AM UTC 24 1733830324 ps
T64 /workspaces/repo/scratch/os_regression_2024_09_23/i2c-sim-vcs/coverage/default/0.i2c_target_nack_acqfull_addr.1448448863 Sep 24 08:14:47 AM UTC 24 Sep 24 08:14:52 AM UTC 24 1214062002 ps
T70 /workspaces/repo/scratch/os_regression_2024_09_23/i2c-sim-vcs/coverage/default/0.i2c_target_tx_stretch_ctrl.3801738653 Sep 24 08:14:45 AM UTC 24 Sep 24 08:14:55 AM UTC 24 581200266 ps
T30 /workspaces/repo/scratch/os_regression_2024_09_23/i2c-sim-vcs/coverage/default/0.i2c_host_stretch_timeout.2359530335 Sep 24 08:14:32 AM UTC 24 Sep 24 08:14:55 AM UTC 24 2342511201 ps
T98 /workspaces/repo/scratch/os_regression_2024_09_23/i2c-sim-vcs/coverage/default/2.i2c_alert_test.3258612865 Sep 24 08:15:25 AM UTC 24 Sep 24 08:15:27 AM UTC 24 50887196 ps
T43 /workspaces/repo/scratch/os_regression_2024_09_23/i2c-sim-vcs/coverage/default/1.i2c_host_perf_precise.1392135284 Sep 24 08:14:51 AM UTC 24 Sep 24 08:15:00 AM UTC 24 242052404 ps
T148 /workspaces/repo/scratch/os_regression_2024_09_23/i2c-sim-vcs/coverage/default/1.i2c_target_intr_smoke.1108948204 Sep 24 08:14:54 AM UTC 24 Sep 24 08:15:00 AM UTC 24 690895152 ps
T31 /workspaces/repo/scratch/os_regression_2024_09_23/i2c-sim-vcs/coverage/default/2.i2c_host_smoke.1229735087 Sep 24 08:15:08 AM UTC 24 Sep 24 08:15:32 AM UTC 24 1142039046 ps
T40 /workspaces/repo/scratch/os_regression_2024_09_23/i2c-sim-vcs/coverage/default/1.i2c_host_fifo_fmt_empty.3304596683 Sep 24 08:14:50 AM UTC 24 Sep 24 08:15:00 AM UTC 24 2130326340 ps
T242 /workspaces/repo/scratch/os_regression_2024_09_23/i2c-sim-vcs/coverage/default/1.i2c_target_fifo_reset_acq.65614125 Sep 24 08:14:58 AM UTC 24 Sep 24 08:15:01 AM UTC 24 203040501 ps
T274 /workspaces/repo/scratch/os_regression_2024_09_23/i2c-sim-vcs/coverage/default/0.i2c_target_smoke.1093034191 Sep 24 08:14:34 AM UTC 24 Sep 24 08:15:01 AM UTC 24 859942214 ps
T184 /workspaces/repo/scratch/os_regression_2024_09_23/i2c-sim-vcs/coverage/default/1.i2c_target_fifo_reset_tx.178268123 Sep 24 08:14:59 AM UTC 24 Sep 24 08:15:02 AM UTC 24 178915503 ps
T149 /workspaces/repo/scratch/os_regression_2024_09_23/i2c-sim-vcs/coverage/default/1.i2c_host_fifo_reset_rx.902431793 Sep 24 08:14:50 AM UTC 24 Sep 24 08:15:03 AM UTC 24 210576118 ps
T181 /workspaces/repo/scratch/os_regression_2024_09_23/i2c-sim-vcs/coverage/default/0.i2c_host_smoke.2264759379 Sep 24 08:14:31 AM UTC 24 Sep 24 08:15:03 AM UTC 24 2167309974 ps
T187 /workspaces/repo/scratch/os_regression_2024_09_23/i2c-sim-vcs/coverage/default/1.i2c_target_hrst.1312024435 Sep 24 08:15:00 AM UTC 24 Sep 24 08:15:06 AM UTC 24 1318262043 ps
T303 /workspaces/repo/scratch/os_regression_2024_09_23/i2c-sim-vcs/coverage/default/1.i2c_target_fifo_watermarks_tx.1760545408 Sep 24 08:15:03 AM UTC 24 Sep 24 08:15:06 AM UTC 24 1124230636 ps
T269 /workspaces/repo/scratch/os_regression_2024_09_23/i2c-sim-vcs/coverage/default/0.i2c_target_stress_wr.878987481 Sep 24 08:14:34 AM UTC 24 Sep 24 08:15:06 AM UTC 24 10166423772 ps
T182 /workspaces/repo/scratch/os_regression_2024_09_23/i2c-sim-vcs/coverage/default/1.i2c_host_smoke.877039882 Sep 24 08:14:49 AM UTC 24 Sep 24 08:15:07 AM UTC 24 972393576 ps
T51 /workspaces/repo/scratch/os_regression_2024_09_23/i2c-sim-vcs/coverage/default/0.i2c_target_intr_stress_wr.3298022744 Sep 24 08:14:35 AM UTC 24 Sep 24 08:15:07 AM UTC 24 9607780830 ps
T282 /workspaces/repo/scratch/os_regression_2024_09_23/i2c-sim-vcs/coverage/default/1.i2c_target_fifo_watermarks_acq.3351404961 Sep 24 08:15:02 AM UTC 24 Sep 24 08:15:07 AM UTC 24 519320974 ps
T193 /workspaces/repo/scratch/os_regression_2024_09_23/i2c-sim-vcs/coverage/default/2.i2c_sec_cm.155498996 Sep 24 08:15:25 AM UTC 24 Sep 24 08:15:28 AM UTC 24 133024818 ps
T71 /workspaces/repo/scratch/os_regression_2024_09_23/i2c-sim-vcs/coverage/default/1.i2c_target_tx_stretch_ctrl.1734053590 Sep 24 08:15:04 AM UTC 24 Sep 24 08:15:08 AM UTC 24 114067869 ps
T46 /workspaces/repo/scratch/os_regression_2024_09_23/i2c-sim-vcs/coverage/default/1.i2c_target_timeout.4237244171 Sep 24 08:14:56 AM UTC 24 Sep 24 08:15:08 AM UTC 24 4515806224 ps
T52 /workspaces/repo/scratch/os_regression_2024_09_23/i2c-sim-vcs/coverage/default/1.i2c_target_glitch.487899282 Sep 24 08:14:53 AM UTC 24 Sep 24 08:15:08 AM UTC 24 7717848159 ps
T304 /workspaces/repo/scratch/os_regression_2024_09_23/i2c-sim-vcs/coverage/default/1.i2c_target_smbus_maxlen.1367103663 Sep 24 08:15:04 AM UTC 24 Sep 24 08:15:09 AM UTC 24 1939280435 ps
T267 /workspaces/repo/scratch/os_regression_2024_09_23/i2c-sim-vcs/coverage/default/1.i2c_target_stress_rd.1731645475 Sep 24 08:14:53 AM UTC 24 Sep 24 08:15:09 AM UTC 24 1017393397 ps
T12 /workspaces/repo/scratch/os_regression_2024_09_23/i2c-sim-vcs/coverage/default/1.i2c_host_may_nack.2852040577 Sep 24 08:15:02 AM UTC 24 Sep 24 08:15:09 AM UTC 24 1346220226 ps
T66 /workspaces/repo/scratch/os_regression_2024_09_23/i2c-sim-vcs/coverage/default/1.i2c_target_bad_addr.2277887072 Sep 24 08:15:00 AM UTC 24 Sep 24 08:15:09 AM UTC 24 7965228590 ps
T99 /workspaces/repo/scratch/os_regression_2024_09_23/i2c-sim-vcs/coverage/default/1.i2c_alert_test.1536618073 Sep 24 08:15:07 AM UTC 24 Sep 24 08:15:09 AM UTC 24 17937123 ps
T194 /workspaces/repo/scratch/os_regression_2024_09_23/i2c-sim-vcs/coverage/default/1.i2c_sec_cm.2025133600 Sep 24 08:15:07 AM UTC 24 Sep 24 08:15:10 AM UTC 24 67813949 ps
T60 /workspaces/repo/scratch/os_regression_2024_09_23/i2c-sim-vcs/coverage/default/1.i2c_target_nack_txstretch.728934281 Sep 24 08:15:07 AM UTC 24 Sep 24 08:15:10 AM UTC 24 166499048 ps
T169 /workspaces/repo/scratch/os_regression_2024_09_23/i2c-sim-vcs/coverage/default/2.i2c_host_override.118477588 Sep 24 08:15:08 AM UTC 24 Sep 24 08:15:10 AM UTC 24 29515210 ps
T65 /workspaces/repo/scratch/os_regression_2024_09_23/i2c-sim-vcs/coverage/default/1.i2c_target_nack_acqfull.4083767529 Sep 24 08:15:06 AM UTC 24 Sep 24 08:15:10 AM UTC 24 2910265445 ps
T68 /workspaces/repo/scratch/os_regression_2024_09_23/i2c-sim-vcs/coverage/default/1.i2c_target_nack_acqfull_addr.2287288322 Sep 24 08:15:06 AM UTC 24 Sep 24 08:15:11 AM UTC 24 1699270682 ps
T170 /workspaces/repo/scratch/os_regression_2024_09_23/i2c-sim-vcs/coverage/default/1.i2c_target_perf.3020745592 Sep 24 08:15:00 AM UTC 24 Sep 24 08:15:12 AM UTC 24 846930269 ps
T35 /workspaces/repo/scratch/os_regression_2024_09_23/i2c-sim-vcs/coverage/default/2.i2c_host_fifo_reset_fmt.154531930 Sep 24 08:15:09 AM UTC 24 Sep 24 08:15:12 AM UTC 24 555375578 ps
T171 /workspaces/repo/scratch/os_regression_2024_09_23/i2c-sim-vcs/coverage/default/2.i2c_host_perf_precise.2961951448 Sep 24 08:15:10 AM UTC 24 Sep 24 08:15:12 AM UTC 24 323123606 ps
T172 /workspaces/repo/scratch/os_regression_2024_09_23/i2c-sim-vcs/coverage/default/0.i2c_target_stress_all.3938802092 Sep 24 08:14:38 AM UTC 24 Sep 24 08:15:13 AM UTC 24 5828548718 ps
T173 /workspaces/repo/scratch/os_regression_2024_09_23/i2c-sim-vcs/coverage/default/1.i2c_host_stretch_timeout.1280607438 Sep 24 08:14:52 AM UTC 24 Sep 24 08:15:13 AM UTC 24 4243565885 ps
T174 /workspaces/repo/scratch/os_regression_2024_09_23/i2c-sim-vcs/coverage/default/1.i2c_target_stretch.1553978245 Sep 24 08:14:53 AM UTC 24 Sep 24 08:15:14 AM UTC 24 2482321444 ps
T305 /workspaces/repo/scratch/os_regression_2024_09_23/i2c-sim-vcs/coverage/default/2.i2c_host_fifo_fmt_empty.2463217357 Sep 24 08:15:09 AM UTC 24 Sep 24 08:15:16 AM UTC 24 189086513 ps
T218 /workspaces/repo/scratch/os_regression_2024_09_23/i2c-sim-vcs/coverage/default/1.i2c_target_smoke.67560217 Sep 24 08:14:53 AM UTC 24 Sep 24 08:15:16 AM UTC 24 5582997267 ps
T244 /workspaces/repo/scratch/os_regression_2024_09_23/i2c-sim-vcs/coverage/default/2.i2c_target_fifo_reset_acq.1044708382 Sep 24 08:15:14 AM UTC 24 Sep 24 08:15:16 AM UTC 24 725162091 ps
T306 /workspaces/repo/scratch/os_regression_2024_09_23/i2c-sim-vcs/coverage/default/2.i2c_target_fifo_reset_tx.1984532775 Sep 24 08:15:14 AM UTC 24 Sep 24 08:15:17 AM UTC 24 404066970 ps
T307 /workspaces/repo/scratch/os_regression_2024_09_23/i2c-sim-vcs/coverage/default/2.i2c_target_intr_smoke.1518480302 Sep 24 08:15:13 AM UTC 24 Sep 24 08:15:20 AM UTC 24 786951112 ps
T188 /workspaces/repo/scratch/os_regression_2024_09_23/i2c-sim-vcs/coverage/default/2.i2c_target_hrst.268185736 Sep 24 08:15:17 AM UTC 24 Sep 24 08:15:21 AM UTC 24 260930806 ps
T150 /workspaces/repo/scratch/os_regression_2024_09_23/i2c-sim-vcs/coverage/default/2.i2c_target_nack_acqfull.2687122439 Sep 24 08:15:23 AM UTC 24 Sep 24 08:15:29 AM UTC 24 532279839 ps
T308 /workspaces/repo/scratch/os_regression_2024_09_23/i2c-sim-vcs/coverage/default/2.i2c_target_perf.1580128504 Sep 24 08:15:14 AM UTC 24 Sep 24 08:15:21 AM UTC 24 508980487 ps
T151 /workspaces/repo/scratch/os_regression_2024_09_23/i2c-sim-vcs/coverage/default/1.i2c_host_perf.1853195279 Sep 24 08:14:51 AM UTC 24 Sep 24 08:15:23 AM UTC 24 2714958713 ps
T183 /workspaces/repo/scratch/os_regression_2024_09_23/i2c-sim-vcs/coverage/default/2.i2c_host_stretch_timeout.2207536447 Sep 24 08:15:10 AM UTC 24 Sep 24 08:15:23 AM UTC 24 4374041776 ps
T309 /workspaces/repo/scratch/os_regression_2024_09_23/i2c-sim-vcs/coverage/default/2.i2c_target_stretch.2492290020 Sep 24 08:15:12 AM UTC 24 Sep 24 08:15:24 AM UTC 24 3329141518 ps
T310 /workspaces/repo/scratch/os_regression_2024_09_23/i2c-sim-vcs/coverage/default/2.i2c_target_fifo_watermarks_tx.2029425545 Sep 24 08:15:21 AM UTC 24 Sep 24 08:15:24 AM UTC 24 240376094 ps
T67 /workspaces/repo/scratch/os_regression_2024_09_23/i2c-sim-vcs/coverage/default/2.i2c_target_bad_addr.4221296912 Sep 24 08:15:17 AM UTC 24 Sep 24 08:15:24 AM UTC 24 1783698892 ps
T311 /workspaces/repo/scratch/os_regression_2024_09_23/i2c-sim-vcs/coverage/default/2.i2c_target_smbus_maxlen.1524780615 Sep 24 08:15:22 AM UTC 24 Sep 24 08:15:26 AM UTC 24 1434080682 ps
T195 /workspaces/repo/scratch/os_regression_2024_09_23/i2c-sim-vcs/coverage/default/4.i2c_sec_cm.330813 Sep 24 08:16:28 AM UTC 24 Sep 24 08:16:31 AM UTC 24 123375005 ps
T283 /workspaces/repo/scratch/os_regression_2024_09_23/i2c-sim-vcs/coverage/default/2.i2c_target_fifo_watermarks_acq.450400095 Sep 24 08:15:21 AM UTC 24 Sep 24 08:15:25 AM UTC 24 4132846104 ps
T246 /workspaces/repo/scratch/os_regression_2024_09_23/i2c-sim-vcs/coverage/default/3.i2c_host_fifo_reset_fmt.4074436386 Sep 24 08:15:27 AM UTC 24 Sep 24 08:15:30 AM UTC 24 179647093 ps
T69 /workspaces/repo/scratch/os_regression_2024_09_23/i2c-sim-vcs/coverage/default/2.i2c_target_nack_acqfull_addr.457034342 Sep 24 08:15:24 AM UTC 24 Sep 24 08:15:30 AM UTC 24 9233924233 ps
T56 /workspaces/repo/scratch/os_regression_2024_09_23/i2c-sim-vcs/coverage/default/3.i2c_target_stress_wr.3390086957 Sep 24 08:15:33 AM UTC 24 Sep 24 08:16:39 AM UTC 24 21253375221 ps
T13 /workspaces/repo/scratch/os_regression_2024_09_23/i2c-sim-vcs/coverage/default/2.i2c_host_may_nack.2374894206 Sep 24 08:15:20 AM UTC 24 Sep 24 08:15:32 AM UTC 24 783109205 ps
T312 /workspaces/repo/scratch/os_regression_2024_09_23/i2c-sim-vcs/coverage/default/3.i2c_host_perf_precise.2310837703 Sep 24 08:15:29 AM UTC 24 Sep 24 08:15:33 AM UTC 24 65893570 ps
T297 /workspaces/repo/scratch/os_regression_2024_09_23/i2c-sim-vcs/coverage/default/2.i2c_target_smoke.447113131 Sep 24 08:15:11 AM UTC 24 Sep 24 08:15:34 AM UTC 24 840022921 ps
T313 /workspaces/repo/scratch/os_regression_2024_09_23/i2c-sim-vcs/coverage/default/5.i2c_target_perf.3369532772 Sep 24 08:16:42 AM UTC 24 Sep 24 08:16:49 AM UTC 24 1991172436 ps
T301 /workspaces/repo/scratch/os_regression_2024_09_23/i2c-sim-vcs/coverage/default/2.i2c_target_tx_stretch_ctrl.3976485271 Sep 24 08:15:22 AM UTC 24 Sep 24 08:15:34 AM UTC 24 895583303 ps
T219 /workspaces/repo/scratch/os_regression_2024_09_23/i2c-sim-vcs/coverage/default/2.i2c_target_stress_rd.2526909747 Sep 24 08:15:11 AM UTC 24 Sep 24 08:15:34 AM UTC 24 1204817633 ps
T17 /workspaces/repo/scratch/os_regression_2024_09_23/i2c-sim-vcs/coverage/default/3.i2c_host_error_intr.1006962343 Sep 24 08:15:31 AM UTC 24 Sep 24 08:15:36 AM UTC 24 122553726 ps
T152 /workspaces/repo/scratch/os_regression_2024_09_23/i2c-sim-vcs/coverage/default/3.i2c_host_fifo_reset_rx.4180335859 Sep 24 08:15:28 AM UTC 24 Sep 24 08:15:36 AM UTC 24 235034453 ps
T314 /workspaces/repo/scratch/os_regression_2024_09_23/i2c-sim-vcs/coverage/default/5.i2c_host_perf.789967774 Sep 24 08:16:31 AM UTC 24 Sep 24 08:16:44 AM UTC 24 1120888657 ps
T315 /workspaces/repo/scratch/os_regression_2024_09_23/i2c-sim-vcs/coverage/default/3.i2c_target_fifo_reset_acq.1172085343 Sep 24 08:15:38 AM UTC 24 Sep 24 08:15:40 AM UTC 24 236225242 ps
T57 /workspaces/repo/scratch/os_regression_2024_09_23/i2c-sim-vcs/coverage/default/1.i2c_target_intr_stress_wr.1352174966 Sep 24 08:14:56 AM UTC 24 Sep 24 08:15:41 AM UTC 24 10120559161 ps
T316 /workspaces/repo/scratch/os_regression_2024_09_23/i2c-sim-vcs/coverage/default/3.i2c_target_stress_rd.1386411788 Sep 24 08:15:33 AM UTC 24 Sep 24 08:15:41 AM UTC 24 551832689 ps
T317 /workspaces/repo/scratch/os_regression_2024_09_23/i2c-sim-vcs/coverage/default/3.i2c_target_intr_smoke.1658265718 Sep 24 08:15:34 AM UTC 24 Sep 24 08:15:43 AM UTC 24 661943968 ps
T318 /workspaces/repo/scratch/os_regression_2024_09_23/i2c-sim-vcs/coverage/default/3.i2c_target_fifo_reset_tx.892660963 Sep 24 08:15:41 AM UTC 24 Sep 24 08:15:44 AM UTC 24 845801527 ps
T296 /workspaces/repo/scratch/os_regression_2024_09_23/i2c-sim-vcs/coverage/default/3.i2c_host_stretch_timeout.3184069385 Sep 24 08:15:30 AM UTC 24 Sep 24 08:15:45 AM UTC 24 752603078 ps
T189 /workspaces/repo/scratch/os_regression_2024_09_23/i2c-sim-vcs/coverage/default/3.i2c_target_hrst.3968846434 Sep 24 08:15:44 AM UTC 24 Sep 24 08:15:48 AM UTC 24 1063524539 ps
T319 /workspaces/repo/scratch/os_regression_2024_09_23/i2c-sim-vcs/coverage/default/3.i2c_target_timeout.2502676022 Sep 24 08:15:35 AM UTC 24 Sep 24 08:15:50 AM UTC 24 1491716061 ps
T320 /workspaces/repo/scratch/os_regression_2024_09_23/i2c-sim-vcs/coverage/default/3.i2c_target_perf.3334382906 Sep 24 08:15:42 AM UTC 24 Sep 24 08:15:51 AM UTC 24 602345455 ps
T321 /workspaces/repo/scratch/os_regression_2024_09_23/i2c-sim-vcs/coverage/default/3.i2c_target_smoke.689631265 Sep 24 08:15:32 AM UTC 24 Sep 24 08:15:53 AM UTC 24 4262394588 ps
T322 /workspaces/repo/scratch/os_regression_2024_09_23/i2c-sim-vcs/coverage/default/3.i2c_host_fifo_fmt_empty.2623369518 Sep 24 08:15:28 AM UTC 24 Sep 24 08:15:53 AM UTC 24 998215264 ps
T323 /workspaces/repo/scratch/os_regression_2024_09_23/i2c-sim-vcs/coverage/default/3.i2c_target_bad_addr.970744092 Sep 24 08:15:43 AM UTC 24 Sep 24 08:15:54 AM UTC 24 4308181906 ps
T324 /workspaces/repo/scratch/os_regression_2024_09_23/i2c-sim-vcs/coverage/default/5.i2c_target_stretch.748105043 Sep 24 08:16:36 AM UTC 24 Sep 24 08:16:41 AM UTC 24 1273422909 ps
T325 /workspaces/repo/scratch/os_regression_2024_09_23/i2c-sim-vcs/coverage/default/3.i2c_target_fifo_watermarks_tx.2134807967 Sep 24 08:15:53 AM UTC 24 Sep 24 08:15:56 AM UTC 24 92210618 ps
T326 /workspaces/repo/scratch/os_regression_2024_09_23/i2c-sim-vcs/coverage/default/3.i2c_target_fifo_watermarks_acq.3533096262 Sep 24 08:15:51 AM UTC 24 Sep 24 08:15:56 AM UTC 24 5718454053 ps
T153 /workspaces/repo/scratch/os_regression_2024_09_23/i2c-sim-vcs/coverage/default/3.i2c_target_nack_acqfull_addr.1907577992 Sep 24 08:15:54 AM UTC 24 Sep 24 08:15:58 AM UTC 24 494246941 ps
T327 /workspaces/repo/scratch/os_regression_2024_09_23/i2c-sim-vcs/coverage/default/3.i2c_alert_test.1496527565 Sep 24 08:15:57 AM UTC 24 Sep 24 08:15:59 AM UTC 24 46742490 ps
T26 /workspaces/repo/scratch/os_regression_2024_09_23/i2c-sim-vcs/coverage/default/3.i2c_host_may_nack.2710852294 Sep 24 08:15:50 AM UTC 24 Sep 24 08:15:59 AM UTC 24 783835837 ps
T196 /workspaces/repo/scratch/os_regression_2024_09_23/i2c-sim-vcs/coverage/default/3.i2c_sec_cm.1326853198 Sep 24 08:15:56 AM UTC 24 Sep 24 08:15:59 AM UTC 24 348744481 ps
T61 /workspaces/repo/scratch/os_regression_2024_09_23/i2c-sim-vcs/coverage/default/3.i2c_target_nack_txstretch.3613827890 Sep 24 08:15:55 AM UTC 24 Sep 24 08:15:59 AM UTC 24 1198443984 ps
T268 /workspaces/repo/scratch/os_regression_2024_09_23/i2c-sim-vcs/coverage/default/3.i2c_host_smoke.1647324116 Sep 24 08:15:25 AM UTC 24 Sep 24 08:15:59 AM UTC 24 3112180188 ps
T79 /workspaces/repo/scratch/os_regression_2024_09_23/i2c-sim-vcs/coverage/default/3.i2c_host_fifo_watermark.3785726619 Sep 24 08:15:25 AM UTC 24 Sep 24 08:16:41 AM UTC 24 41392973980 ps
T158 /workspaces/repo/scratch/os_regression_2024_09_23/i2c-sim-vcs/coverage/default/3.i2c_target_smbus_maxlen.2850153484 Sep 24 08:15:54 AM UTC 24 Sep 24 08:16:00 AM UTC 24 1929211777 ps
T159 /workspaces/repo/scratch/os_regression_2024_09_23/i2c-sim-vcs/coverage/default/3.i2c_target_tx_stretch_ctrl.3278098820 Sep 24 08:15:54 AM UTC 24 Sep 24 08:16:00 AM UTC 24 150775963 ps
T154 /workspaces/repo/scratch/os_regression_2024_09_23/i2c-sim-vcs/coverage/default/3.i2c_target_nack_acqfull.395888164 Sep 24 08:15:54 AM UTC 24 Sep 24 08:16:00 AM UTC 24 547629532 ps
T80 /workspaces/repo/scratch/os_regression_2024_09_23/i2c-sim-vcs/coverage/default/1.i2c_host_fifo_overflow.349066055 Sep 24 08:14:49 AM UTC 24 Sep 24 08:16:02 AM UTC 24 11091543920 ps
T160 /workspaces/repo/scratch/os_regression_2024_09_23/i2c-sim-vcs/coverage/default/4.i2c_host_override.4289463556 Sep 24 08:16:00 AM UTC 24 Sep 24 08:16:02 AM UTC 24 54266269 ps
T161 /workspaces/repo/scratch/os_regression_2024_09_23/i2c-sim-vcs/coverage/default/1.i2c_target_stress_all.1290551881 Sep 24 08:15:00 AM UTC 24 Sep 24 08:16:03 AM UTC 24 6520897047 ps
T162 /workspaces/repo/scratch/os_regression_2024_09_23/i2c-sim-vcs/coverage/default/4.i2c_host_fifo_reset_fmt.1443240052 Sep 24 08:16:01 AM UTC 24 Sep 24 08:16:04 AM UTC 24 102394427 ps
T178 /workspaces/repo/scratch/os_regression_2024_09_23/i2c-sim-vcs/coverage/default/4.i2c_host_fifo_fmt_empty.1015700495 Sep 24 08:16:01 AM UTC 24 Sep 24 08:16:10 AM UTC 24 1063046719 ps
T155 /workspaces/repo/scratch/os_regression_2024_09_23/i2c-sim-vcs/coverage/default/4.i2c_host_fifo_reset_rx.3432483400 Sep 24 08:16:01 AM UTC 24 Sep 24 08:16:10 AM UTC 24 3166521249 ps
T272 /workspaces/repo/scratch/os_regression_2024_09_23/i2c-sim-vcs/coverage/default/4.i2c_host_stretch_timeout.2868148042 Sep 24 08:16:01 AM UTC 24 Sep 24 08:16:10 AM UTC 24 369638187 ps
T27 /workspaces/repo/scratch/os_regression_2024_09_23/i2c-sim-vcs/coverage/default/3.i2c_host_fifo_full.2924388994 Sep 24 08:15:28 AM UTC 24 Sep 24 08:16:14 AM UTC 24 1958769433 ps
T328 /workspaces/repo/scratch/os_regression_2024_09_23/i2c-sim-vcs/coverage/default/4.i2c_host_perf.2901262470 Sep 24 08:16:01 AM UTC 24 Sep 24 08:16:16 AM UTC 24 1190273542 ps
T329 /workspaces/repo/scratch/os_regression_2024_09_23/i2c-sim-vcs/coverage/default/4.i2c_host_perf_precise.901627028 Sep 24 08:16:01 AM UTC 24 Sep 24 08:16:45 AM UTC 24 732242873 ps
T330 /workspaces/repo/scratch/os_regression_2024_09_23/i2c-sim-vcs/coverage/default/4.i2c_target_smoke.2642428769 Sep 24 08:16:03 AM UTC 24 Sep 24 08:16:19 AM UTC 24 915625854 ps
T185 /workspaces/repo/scratch/os_regression_2024_09_23/i2c-sim-vcs/coverage/default/5.i2c_target_fifo_reset_acq.410215976 Sep 24 08:16:40 AM UTC 24 Sep 24 08:16:43 AM UTC 24 673451648 ps
T245 /workspaces/repo/scratch/os_regression_2024_09_23/i2c-sim-vcs/coverage/default/4.i2c_target_fifo_reset_acq.1368736653 Sep 24 08:16:17 AM UTC 24 Sep 24 08:16:20 AM UTC 24 160325766 ps
T81 /workspaces/repo/scratch/os_regression_2024_09_23/i2c-sim-vcs/coverage/default/0.i2c_host_fifo_watermark.2133094151 Sep 24 08:14:31 AM UTC 24 Sep 24 08:16:20 AM UTC 24 18745812452 ps
T121 /workspaces/repo/scratch/os_regression_2024_09_23/i2c-sim-vcs/coverage/default/4.i2c_target_intr_smoke.4262181874 Sep 24 08:16:10 AM UTC 24 Sep 24 08:16:20 AM UTC 24 1798981298 ps
T122 /workspaces/repo/scratch/os_regression_2024_09_23/i2c-sim-vcs/coverage/default/4.i2c_target_fifo_reset_tx.3268722797 Sep 24 08:16:18 AM UTC 24 Sep 24 08:16:21 AM UTC 24 293372687 ps
T123 /workspaces/repo/scratch/os_regression_2024_09_23/i2c-sim-vcs/coverage/default/4.i2c_target_intr_stress_wr.2430169785 Sep 24 08:16:11 AM UTC 24 Sep 24 08:16:21 AM UTC 24 8471210277 ps
T14 /workspaces/repo/scratch/os_regression_2024_09_23/i2c-sim-vcs/coverage/default/3.i2c_host_perf.3931466837 Sep 24 08:15:29 AM UTC 24 Sep 24 08:16:48 AM UTC 24 7923416798 ps
T58 /workspaces/repo/scratch/os_regression_2024_09_23/i2c-sim-vcs/coverage/default/3.i2c_target_intr_stress_wr.2740679915 Sep 24 08:15:35 AM UTC 24 Sep 24 08:16:22 AM UTC 24 15632746867 ps
T124 /workspaces/repo/scratch/os_regression_2024_09_23/i2c-sim-vcs/coverage/default/4.i2c_target_timeout.1584386814 Sep 24 08:16:12 AM UTC 24 Sep 24 08:16:22 AM UTC 24 1183837979 ps
T125 /workspaces/repo/scratch/os_regression_2024_09_23/i2c-sim-vcs/coverage/default/4.i2c_target_stress_rd.2602941249 Sep 24 08:16:04 AM UTC 24 Sep 24 08:16:22 AM UTC 24 628580477 ps
T32 /workspaces/repo/scratch/os_regression_2024_09_23/i2c-sim-vcs/coverage/default/2.i2c_host_fifo_overflow.3941463460 Sep 24 08:15:08 AM UTC 24 Sep 24 08:16:22 AM UTC 24 2623977394 ps
T126 /workspaces/repo/scratch/os_regression_2024_09_23/i2c-sim-vcs/coverage/default/4.i2c_host_smoke.4095008020 Sep 24 08:15:58 AM UTC 24 Sep 24 08:16:25 AM UTC 24 4295482188 ps
T24 /workspaces/repo/scratch/os_regression_2024_09_23/i2c-sim-vcs/coverage/default/4.i2c_host_mode_toggle.2618447137 Sep 24 08:16:22 AM UTC 24 Sep 24 08:16:26 AM UTC 24 209019108 ps
T331 /workspaces/repo/scratch/os_regression_2024_09_23/i2c-sim-vcs/coverage/default/4.i2c_target_fifo_watermarks_acq.868578564 Sep 24 08:16:22 AM UTC 24 Sep 24 08:16:26 AM UTC 24 911258940 ps
T332 /workspaces/repo/scratch/os_regression_2024_09_23/i2c-sim-vcs/coverage/default/4.i2c_target_fifo_watermarks_tx.2506188277 Sep 24 08:16:23 AM UTC 24 Sep 24 08:16:26 AM UTC 24 518410865 ps
T275 /workspaces/repo/scratch/os_regression_2024_09_23/i2c-sim-vcs/coverage/default/4.i2c_target_bad_addr.3478840832 Sep 24 08:16:20 AM UTC 24 Sep 24 08:16:28 AM UTC 24 2192345240 ps
T333 /workspaces/repo/scratch/os_regression_2024_09_23/i2c-sim-vcs/coverage/default/4.i2c_target_perf.1435673815 Sep 24 08:16:20 AM UTC 24 Sep 24 08:16:29 AM UTC 24 954408053 ps
T334 /workspaces/repo/scratch/os_regression_2024_09_23/i2c-sim-vcs/coverage/default/4.i2c_target_smbus_maxlen.3701512656 Sep 24 08:16:23 AM UTC 24 Sep 24 08:16:29 AM UTC 24 1098586511 ps
T335 /workspaces/repo/scratch/os_regression_2024_09_23/i2c-sim-vcs/coverage/default/4.i2c_target_nack_acqfull.2580897886 Sep 24 08:16:25 AM UTC 24 Sep 24 08:16:29 AM UTC 24 1946053716 ps
T336 /workspaces/repo/scratch/os_regression_2024_09_23/i2c-sim-vcs/coverage/default/4.i2c_alert_test.3980147816 Sep 24 08:16:28 AM UTC 24 Sep 24 08:16:30 AM UTC 24 15905768 ps
T62 /workspaces/repo/scratch/os_regression_2024_09_23/i2c-sim-vcs/coverage/default/4.i2c_target_nack_txstretch.2306513858 Sep 24 08:16:27 AM UTC 24 Sep 24 08:16:30 AM UTC 24 141940586 ps
T101 /workspaces/repo/scratch/os_regression_2024_09_23/i2c-sim-vcs/coverage/default/0.i2c_host_fifo_overflow.467269702 Sep 24 08:14:31 AM UTC 24 Sep 24 08:16:31 AM UTC 24 8525973089 ps
T139 /workspaces/repo/scratch/os_regression_2024_09_23/i2c-sim-vcs/coverage/default/5.i2c_host_override.38099906 Sep 24 08:16:29 AM UTC 24 Sep 24 08:16:31 AM UTC 24 17643332 ps
T337 /workspaces/repo/scratch/os_regression_2024_09_23/i2c-sim-vcs/coverage/default/4.i2c_target_nack_acqfull_addr.2444140116 Sep 24 08:16:27 AM UTC 24 Sep 24 08:16:33 AM UTC 24 2143097522 ps
T338 /workspaces/repo/scratch/os_regression_2024_09_23/i2c-sim-vcs/coverage/default/5.i2c_host_fifo_reset_fmt.2017764794 Sep 24 08:16:30 AM UTC 24 Sep 24 08:16:33 AM UTC 24 472283499 ps
T339 /workspaces/repo/scratch/os_regression_2024_09_23/i2c-sim-vcs/coverage/default/3.i2c_target_stretch.915854356 Sep 24 08:15:33 AM UTC 24 Sep 24 08:16:33 AM UTC 24 4796561497 ps
T340 /workspaces/repo/scratch/os_regression_2024_09_23/i2c-sim-vcs/coverage/default/4.i2c_target_tx_stretch_ctrl.2559937391 Sep 24 08:16:23 AM UTC 24 Sep 24 08:16:33 AM UTC 24 372012626 ps
T33 /workspaces/repo/scratch/os_regression_2024_09_23/i2c-sim-vcs/coverage/default/4.i2c_host_may_nack.1331894421 Sep 24 08:16:22 AM UTC 24 Sep 24 08:16:35 AM UTC 24 447858640 ps
T20 /workspaces/repo/scratch/os_regression_2024_09_23/i2c-sim-vcs/coverage/default/5.i2c_host_error_intr.1473220919 Sep 24 08:16:34 AM UTC 24 Sep 24 08:16:36 AM UTC 24 129698596 ps
T175 /workspaces/repo/scratch/os_regression_2024_09_23/i2c-sim-vcs/coverage/default/5.i2c_host_fifo_reset_rx.3253461153 Sep 24 08:16:31 AM UTC 24 Sep 24 08:16:37 AM UTC 24 278558260 ps
T341 /workspaces/repo/scratch/os_regression_2024_09_23/i2c-sim-vcs/coverage/default/4.i2c_target_stretch.4094709616 Sep 24 08:16:05 AM UTC 24 Sep 24 08:16:38 AM UTC 24 4647098660 ps
T342 /workspaces/repo/scratch/os_regression_2024_09_23/i2c-sim-vcs/coverage/default/5.i2c_host_fifo_fmt_empty.2990347383 Sep 24 08:16:30 AM UTC 24 Sep 24 08:16:39 AM UTC 24 171402048 ps
T343 /workspaces/repo/scratch/os_regression_2024_09_23/i2c-sim-vcs/coverage/default/7.i2c_target_bad_addr.1337504550 Sep 24 08:17:42 AM UTC 24 Sep 24 08:17:51 AM UTC 24 737715299 ps
T344 /workspaces/repo/scratch/os_regression_2024_09_23/i2c-sim-vcs/coverage/default/5.i2c_host_stretch_timeout.2055944795 Sep 24 08:16:32 AM UTC 24 Sep 24 08:16:44 AM UTC 24 413110437 ps
T345 /workspaces/repo/scratch/os_regression_2024_09_23/i2c-sim-vcs/coverage/default/5.i2c_target_fifo_reset_tx.4238611075 Sep 24 08:16:41 AM UTC 24 Sep 24 08:16:45 AM UTC 24 269116481 ps
T346 /workspaces/repo/scratch/os_regression_2024_09_23/i2c-sim-vcs/coverage/default/5.i2c_target_stress_rd.2912918910 Sep 24 08:16:35 AM UTC 24 Sep 24 08:16:48 AM UTC 24 5344542650 ps
T83 /workspaces/repo/scratch/os_regression_2024_09_23/i2c-sim-vcs/coverage/default/5.i2c_target_smoke.3538056579 Sep 24 08:16:34 AM UTC 24 Sep 24 08:16:50 AM UTC 24 926863572 ps
T88 /workspaces/repo/scratch/os_regression_2024_09_23/i2c-sim-vcs/coverage/default/5.i2c_target_hrst.1605558370 Sep 24 08:16:45 AM UTC 24 Sep 24 08:16:50 AM UTC 24 1426967101 ps
T89 /workspaces/repo/scratch/os_regression_2024_09_23/i2c-sim-vcs/coverage/default/5.i2c_host_perf_precise.2429035072 Sep 24 08:16:31 AM UTC 24 Sep 24 08:16:50 AM UTC 24 1327514182 ps
T90 /workspaces/repo/scratch/os_regression_2024_09_23/i2c-sim-vcs/coverage/default/7.i2c_target_fifo_watermarks_acq.4201537146 Sep 24 08:17:47 AM UTC 24 Sep 24 08:17:53 AM UTC 24 1039818196 ps
T91 /workspaces/repo/scratch/os_regression_2024_09_23/i2c-sim-vcs/coverage/default/5.i2c_target_timeout.2680855621 Sep 24 08:16:39 AM UTC 24 Sep 24 08:16:51 AM UTC 24 1128555800 ps
T92 /workspaces/repo/scratch/os_regression_2024_09_23/i2c-sim-vcs/coverage/default/5.i2c_target_intr_smoke.1066001848 Sep 24 08:16:37 AM UTC 24 Sep 24 08:16:53 AM UTC 24 2517151302 ps
T93 /workspaces/repo/scratch/os_regression_2024_09_23/i2c-sim-vcs/coverage/default/5.i2c_host_may_nack.1847666048 Sep 24 08:16:46 AM UTC 24 Sep 24 08:16:53 AM UTC 24 391051648 ps
T94 /workspaces/repo/scratch/os_regression_2024_09_23/i2c-sim-vcs/coverage/default/5.i2c_target_fifo_watermarks_acq.4254123250 Sep 24 08:16:49 AM UTC 24 Sep 24 08:16:53 AM UTC 24 1019309048 ps
T95 /workspaces/repo/scratch/os_regression_2024_09_23/i2c-sim-vcs/coverage/default/5.i2c_alert_test.2032806133 Sep 24 08:16:52 AM UTC 24 Sep 24 08:16:54 AM UTC 24 19646085 ps
T96 /workspaces/repo/scratch/os_regression_2024_09_23/i2c-sim-vcs/coverage/default/5.i2c_target_nack_txstretch.654634171 Sep 24 08:16:51 AM UTC 24 Sep 24 08:16:54 AM UTC 24 521736762 ps
T347 /workspaces/repo/scratch/os_regression_2024_09_23/i2c-sim-vcs/coverage/default/5.i2c_target_nack_acqfull_addr.3075018316 Sep 24 08:16:51 AM UTC 24 Sep 24 08:16:55 AM UTC 24 678473325 ps
T348 /workspaces/repo/scratch/os_regression_2024_09_23/i2c-sim-vcs/coverage/default/5.i2c_target_smbus_maxlen.2360907484 Sep 24 08:16:50 AM UTC 24 Sep 24 08:16:55 AM UTC 24 2451344077 ps
T349 /workspaces/repo/scratch/os_regression_2024_09_23/i2c-sim-vcs/coverage/default/6.i2c_host_override.554764220 Sep 24 08:16:53 AM UTC 24 Sep 24 08:16:55 AM UTC 24 384165389 ps
T82 /workspaces/repo/scratch/os_regression_2024_09_23/i2c-sim-vcs/coverage/default/1.i2c_host_fifo_watermark.2365007578 Sep 24 08:14:49 AM UTC 24 Sep 24 08:16:56 AM UTC 24 5226158996 ps
T350 /workspaces/repo/scratch/os_regression_2024_09_23/i2c-sim-vcs/coverage/default/5.i2c_target_nack_acqfull.2669910348 Sep 24 08:16:51 AM UTC 24 Sep 24 08:16:56 AM UTC 24 1773116978 ps
T351 /workspaces/repo/scratch/os_regression_2024_09_23/i2c-sim-vcs/coverage/default/5.i2c_host_smoke.16572797 Sep 24 08:16:28 AM UTC 24 Sep 24 08:16:56 AM UTC 24 6693490947 ps
T352 /workspaces/repo/scratch/os_regression_2024_09_23/i2c-sim-vcs/coverage/default/6.i2c_host_fifo_reset_fmt.47586675 Sep 24 08:16:54 AM UTC 24 Sep 24 08:16:56 AM UTC 24 163130558 ps
T353 /workspaces/repo/scratch/os_regression_2024_09_23/i2c-sim-vcs/coverage/default/5.i2c_target_tx_stretch_ctrl.2170569077 Sep 24 08:16:50 AM UTC 24 Sep 24 08:16:57 AM UTC 24 281187884 ps
T354 /workspaces/repo/scratch/os_regression_2024_09_23/i2c-sim-vcs/coverage/default/5.i2c_target_bad_addr.3194292412 Sep 24 08:16:44 AM UTC 24 Sep 24 08:17:00 AM UTC 24 1614230108 ps
T355 /workspaces/repo/scratch/os_regression_2024_09_23/i2c-sim-vcs/coverage/default/8.i2c_target_hrst.2766365621 Sep 24 08:18:08 AM UTC 24 Sep 24 08:18:12 AM UTC 24 495276313 ps
T21 /workspaces/repo/scratch/os_regression_2024_09_23/i2c-sim-vcs/coverage/default/6.i2c_host_error_intr.3383727359 Sep 24 08:16:57 AM UTC 24 Sep 24 08:17:01 AM UTC 24 245145899 ps
T38 /workspaces/repo/scratch/os_regression_2024_09_23/i2c-sim-vcs/coverage/default/1.i2c_host_fifo_full.3852597485 Sep 24 08:14:51 AM UTC 24 Sep 24 08:17:02 AM UTC 24 5005998538 ps
T239 /workspaces/repo/scratch/os_regression_2024_09_23/i2c-sim-vcs/coverage/default/6.i2c_host_perf_precise.3777102478 Sep 24 08:16:57 AM UTC 24 Sep 24 08:17:05 AM UTC 24 315455089 ps
T356 /workspaces/repo/scratch/os_regression_2024_09_23/i2c-sim-vcs/coverage/default/6.i2c_target_stretch.31339669 Sep 24 08:17:01 AM UTC 24 Sep 24 08:17:07 AM UTC 24 2319100889 ps
T357 /workspaces/repo/scratch/os_regression_2024_09_23/i2c-sim-vcs/coverage/default/6.i2c_host_fifo_fmt_empty.3741875044 Sep 24 08:16:55 AM UTC 24 Sep 24 08:17:08 AM UTC 24 234871004 ps
T358 /workspaces/repo/scratch/os_regression_2024_09_23/i2c-sim-vcs/coverage/default/7.i2c_target_nack_acqfull.3660140836 Sep 24 08:17:50 AM UTC 24 Sep 24 08:17:57 AM UTC 24 560272337 ps
T359 /workspaces/repo/scratch/os_regression_2024_09_23/i2c-sim-vcs/coverage/default/6.i2c_target_fifo_reset_acq.2451986741 Sep 24 08:17:08 AM UTC 24 Sep 24 08:17:11 AM UTC 24 171893341 ps
T156 /workspaces/repo/scratch/os_regression_2024_09_23/i2c-sim-vcs/coverage/default/6.i2c_host_fifo_reset_rx.4124704312 Sep 24 08:16:56 AM UTC 24 Sep 24 08:17:12 AM UTC 24 434308473 ps
T360 /workspaces/repo/scratch/os_regression_2024_09_23/i2c-sim-vcs/coverage/default/6.i2c_target_fifo_reset_tx.335039965 Sep 24 08:17:10 AM UTC 24 Sep 24 08:17:12 AM UTC 24 184598775 ps
T361 /workspaces/repo/scratch/os_regression_2024_09_23/i2c-sim-vcs/coverage/default/6.i2c_target_stress_wr.320044244 Sep 24 08:16:58 AM UTC 24 Sep 24 08:17:12 AM UTC 24 15215520894 ps
T362 /workspaces/repo/scratch/os_regression_2024_09_23/i2c-sim-vcs/coverage/default/6.i2c_target_smoke.1055666045 Sep 24 08:16:57 AM UTC 24 Sep 24 08:17:14 AM UTC 24 7964677949 ps
T363 /workspaces/repo/scratch/os_regression_2024_09_23/i2c-sim-vcs/coverage/default/6.i2c_target_intr_smoke.3816306504 Sep 24 08:17:02 AM UTC 24 Sep 24 08:17:15 AM UTC 24 1179129632 ps
T157 /workspaces/repo/scratch/os_regression_2024_09_23/i2c-sim-vcs/coverage/default/0.i2c_host_fifo_full.4182252359 Sep 24 08:14:32 AM UTC 24 Sep 24 08:17:16 AM UTC 24 6116824799 ps
T364 /workspaces/repo/scratch/os_regression_2024_09_23/i2c-sim-vcs/coverage/default/6.i2c_target_perf.543025863 Sep 24 08:17:10 AM UTC 24 Sep 24 08:17:16 AM UTC 24 483487553 ps
T365 /workspaces/repo/scratch/os_regression_2024_09_23/i2c-sim-vcs/coverage/default/6.i2c_target_timeout.2595192039 Sep 24 08:17:05 AM UTC 24 Sep 24 08:17:17 AM UTC 24 9971484990 ps
T366 /workspaces/repo/scratch/os_regression_2024_09_23/i2c-sim-vcs/coverage/default/6.i2c_target_fifo_watermarks_tx.2350931420 Sep 24 08:17:17 AM UTC 24 Sep 24 08:17:20 AM UTC 24 324666668 ps
T367 /workspaces/repo/scratch/os_regression_2024_09_23/i2c-sim-vcs/coverage/default/6.i2c_target_stress_rd.3350381611 Sep 24 08:17:01 AM UTC 24 Sep 24 08:17:21 AM UTC 24 3917204466 ps
T25 /workspaces/repo/scratch/os_regression_2024_09_23/i2c-sim-vcs/coverage/default/6.i2c_host_mode_toggle.4026793808 Sep 24 08:17:14 AM UTC 24 Sep 24 08:17:21 AM UTC 24 150992670 ps
T368 /workspaces/repo/scratch/os_regression_2024_09_23/i2c-sim-vcs/coverage/default/6.i2c_host_stretch_timeout.2727700237 Sep 24 08:16:57 AM UTC 24 Sep 24 08:17:21 AM UTC 24 6358603129 ps
T261 /workspaces/repo/scratch/os_regression_2024_09_23/i2c-sim-vcs/coverage/default/7.i2c_host_may_nack.3144910994 Sep 24 08:17:47 AM UTC 24 Sep 24 08:17:55 AM UTC 24 2405272516 ps
T264 /workspaces/repo/scratch/os_regression_2024_09_23/i2c-sim-vcs/coverage/default/6.i2c_host_may_nack.43257890 Sep 24 08:17:16 AM UTC 24 Sep 24 08:17:22 AM UTC 24 1429615326 ps
T369 /workspaces/repo/scratch/os_regression_2024_09_23/i2c-sim-vcs/coverage/default/6.i2c_target_bad_addr.3688599195 Sep 24 08:17:12 AM UTC 24 Sep 24 08:17:23 AM UTC 24 934249346 ps
T370 /workspaces/repo/scratch/os_regression_2024_09_23/i2c-sim-vcs/coverage/default/7.i2c_alert_test.203598275 Sep 24 08:17:51 AM UTC 24 Sep 24 08:17:53 AM UTC 24 112731618 ps
T371 /workspaces/repo/scratch/os_regression_2024_09_23/i2c-sim-vcs/coverage/default/6.i2c_target_fifo_watermarks_acq.454387623 Sep 24 08:17:17 AM UTC 24 Sep 24 08:17:24 AM UTC 24 600763822 ps
T372 /workspaces/repo/scratch/os_regression_2024_09_23/i2c-sim-vcs/coverage/default/6.i2c_alert_test.3050761314 Sep 24 08:17:23 AM UTC 24 Sep 24 08:17:25 AM UTC 24 22974879 ps
T373 /workspaces/repo/scratch/os_regression_2024_09_23/i2c-sim-vcs/coverage/default/6.i2c_target_smbus_maxlen.2819443750 Sep 24 08:17:21 AM UTC 24 Sep 24 08:17:25 AM UTC 24 942729825 ps
T374 /workspaces/repo/scratch/os_regression_2024_09_23/i2c-sim-vcs/coverage/default/8.i2c_target_perf.2423932865 Sep 24 08:18:06 AM UTC 24 Sep 24 08:18:14 AM UTC 24 2335408217 ps
T48 /workspaces/repo/scratch/os_regression_2024_09_23/i2c-sim-vcs/coverage/default/6.i2c_target_nack_acqfull_addr.320635278 Sep 24 08:17:22 AM UTC 24 Sep 24 08:17:25 AM UTC 24 729887572 ps
T375 /workspaces/repo/scratch/os_regression_2024_09_23/i2c-sim-vcs/coverage/default/7.i2c_host_override.3139760815 Sep 24 08:17:24 AM UTC 24 Sep 24 08:17:26 AM UTC 24 82782452 ps
T376 /workspaces/repo/scratch/os_regression_2024_09_23/i2c-sim-vcs/coverage/default/6.i2c_target_tx_stretch_ctrl.2731951799 Sep 24 08:17:18 AM UTC 24 Sep 24 08:17:26 AM UTC 24 341504671 ps
T163 /workspaces/repo/scratch/os_regression_2024_09_23/i2c-sim-vcs/coverage/default/6.i2c_target_nack_txstretch.1075419773 Sep 24 08:17:23 AM UTC 24 Sep 24 08:17:26 AM UTC 24 1351554783 ps
T377 /workspaces/repo/scratch/os_regression_2024_09_23/i2c-sim-vcs/coverage/default/6.i2c_target_nack_acqfull.2969374334 Sep 24 08:17:21 AM UTC 24 Sep 24 08:17:27 AM UTC 24 573293058 ps
T378 /workspaces/repo/scratch/os_regression_2024_09_23/i2c-sim-vcs/coverage/default/7.i2c_host_fifo_reset_fmt.507549387 Sep 24 08:17:26 AM UTC 24 Sep 24 08:17:29 AM UTC 24 547786854 ps
T240 /workspaces/repo/scratch/os_regression_2024_09_23/i2c-sim-vcs/coverage/default/7.i2c_host_perf_precise.3041694373 Sep 24 08:17:27 AM UTC 24 Sep 24 08:17:33 AM UTC 24 235858664 ps
T176 /workspaces/repo/scratch/os_regression_2024_09_23/i2c-sim-vcs/coverage/default/7.i2c_host_fifo_reset_rx.3696300155 Sep 24 08:17:26 AM UTC 24 Sep 24 08:17:33 AM UTC 24 1041846088 ps
T177 /workspaces/repo/scratch/os_regression_2024_09_23/i2c-sim-vcs/coverage/default/2.i2c_host_fifo_watermark.3905201630 Sep 24 08:15:08 AM UTC 24 Sep 24 08:17:33 AM UTC 24 12743434207 ps
T379 /workspaces/repo/scratch/os_regression_2024_09_23/i2c-sim-vcs/coverage/default/7.i2c_host_stretch_timeout.1604585427 Sep 24 08:17:27 AM UTC 24 Sep 24 08:17:38 AM UTC 24 2540826649 ps
T380 /workspaces/repo/scratch/os_regression_2024_09_23/i2c-sim-vcs/coverage/default/7.i2c_host_fifo_fmt_empty.3762049687 Sep 24 08:17:26 AM UTC 24 Sep 24 08:17:38 AM UTC 24 485689420 ps
T59 /workspaces/repo/scratch/os_regression_2024_09_23/i2c-sim-vcs/coverage/default/3.i2c_target_stress_all.556215413 Sep 24 08:15:42 AM UTC 24 Sep 24 08:17:40 AM UTC 24 19527273546 ps
T381 /workspaces/repo/scratch/os_regression_2024_09_23/i2c-sim-vcs/coverage/default/7.i2c_target_fifo_reset_acq.609177352 Sep 24 08:17:39 AM UTC 24 Sep 24 08:17:41 AM UTC 24 335019594 ps
T112 /workspaces/repo/scratch/os_regression_2024_09_23/i2c-sim-vcs/coverage/default/4.i2c_host_fifo_watermark.1931491244 Sep 24 08:16:00 AM UTC 24 Sep 24 08:17:42 AM UTC 24 4782661510 ps
T382 /workspaces/repo/scratch/os_regression_2024_09_23/i2c-sim-vcs/coverage/default/6.i2c_host_smoke.4187954719 Sep 24 08:16:52 AM UTC 24 Sep 24 08:17:43 AM UTC 24 8806776163 ps
T383 /workspaces/repo/scratch/os_regression_2024_09_23/i2c-sim-vcs/coverage/default/7.i2c_target_fifo_reset_tx.2816511656 Sep 24 08:17:41 AM UTC 24 Sep 24 08:17:43 AM UTC 24 546144749 ps
T39 /workspaces/repo/scratch/os_regression_2024_09_23/i2c-sim-vcs/coverage/default/2.i2c_host_fifo_full.3630512621 Sep 24 08:15:10 AM UTC 24 Sep 24 08:17:44 AM UTC 24 33111282680 ps
T179 /workspaces/repo/scratch/os_regression_2024_09_23/i2c-sim-vcs/coverage/default/5.i2c_host_fifo_overflow.2805742075 Sep 24 08:16:29 AM UTC 24 Sep 24 08:17:45 AM UTC 24 4925632432 ps
T384 /workspaces/repo/scratch/os_regression_2024_09_23/i2c-sim-vcs/coverage/default/7.i2c_target_stretch.2864411863 Sep 24 08:17:34 AM UTC 24 Sep 24 08:17:46 AM UTC 24 1056498761 ps
T385 /workspaces/repo/scratch/os_regression_2024_09_23/i2c-sim-vcs/coverage/default/7.i2c_target_intr_smoke.151977465 Sep 24 08:17:34 AM UTC 24 Sep 24 08:17:46 AM UTC 24 1081440255 ps
T386 /workspaces/repo/scratch/os_regression_2024_09_23/i2c-sim-vcs/coverage/default/5.i2c_target_stress_all.3554485583 Sep 24 08:16:43 AM UTC 24 Sep 24 08:17:46 AM UTC 24 20482235537 ps
T387 /workspaces/repo/scratch/os_regression_2024_09_23/i2c-sim-vcs/coverage/default/7.i2c_target_timeout.2638199746 Sep 24 08:17:36 AM UTC 24 Sep 24 08:17:46 AM UTC 24 14877890391 ps
T180 /workspaces/repo/scratch/os_regression_2024_09_23/i2c-sim-vcs/coverage/default/4.i2c_host_fifo_overflow.2345550424 Sep 24 08:16:00 AM UTC 24 Sep 24 08:17:48 AM UTC 24 1665157701 ps
T276 /workspaces/repo/scratch/os_regression_2024_09_23/i2c-sim-vcs/coverage/default/7.i2c_target_smoke.2637809302 Sep 24 08:17:29 AM UTC 24 Sep 24 08:17:49 AM UTC 24 2364035656 ps
T388 /workspaces/repo/scratch/os_regression_2024_09_23/i2c-sim-vcs/coverage/default/7.i2c_target_nack_acqfull_addr.4221270400 Sep 24 08:17:50 AM UTC 24 Sep 24 08:17:55 AM UTC 24 2106837309 ps
T389 /workspaces/repo/scratch/os_regression_2024_09_23/i2c-sim-vcs/coverage/default/7.i2c_target_perf.4144811480 Sep 24 08:17:42 AM UTC 24 Sep 24 08:17:50 AM UTC 24 622315573 ps
T390 /workspaces/repo/scratch/os_regression_2024_09_23/i2c-sim-vcs/coverage/default/7.i2c_host_smoke.3866476776 Sep 24 08:17:24 AM UTC 24 Sep 24 08:17:50 AM UTC 24 4700552201 ps
T391 /workspaces/repo/scratch/os_regression_2024_09_23/i2c-sim-vcs/coverage/default/7.i2c_target_fifo_watermarks_tx.1534724256 Sep 24 08:17:47 AM UTC 24 Sep 24 08:17:50 AM UTC 24 259880710 ps
T140 /workspaces/repo/scratch/os_regression_2024_09_23/i2c-sim-vcs/coverage/default/8.i2c_host_override.2046122341 Sep 24 08:17:51 AM UTC 24 Sep 24 08:17:53 AM UTC 24 64123332 ps
T392 /workspaces/repo/scratch/os_regression_2024_09_23/i2c-sim-vcs/coverage/default/7.i2c_target_smbus_maxlen.3948889951 Sep 24 08:17:49 AM UTC 24 Sep 24 08:17:53 AM UTC 24 418604026 ps
T393 /workspaces/repo/scratch/os_regression_2024_09_23/i2c-sim-vcs/coverage/default/8.i2c_host_fifo_reset_fmt.196902683 Sep 24 08:17:52 AM UTC 24 Sep 24 08:17:55 AM UTC 24 350826210 ps
T394 /workspaces/repo/scratch/os_regression_2024_09_23/i2c-sim-vcs/coverage/default/3.i2c_host_fifo_overflow.3892654681 Sep 24 08:15:26 AM UTC 24 Sep 24 08:17:56 AM UTC 24 2779799873 ps
T395 /workspaces/repo/scratch/os_regression_2024_09_23/i2c-sim-vcs/coverage/default/1.i2c_target_stress_wr.486496172 Sep 24 08:14:53 AM UTC 24 Sep 24 08:19:19 AM UTC 24 40089202198 ps
T243 /workspaces/repo/scratch/os_regression_2024_09_23/i2c-sim-vcs/coverage/default/8.i2c_host_fifo_reset_rx.2677551870 Sep 24 08:17:54 AM UTC 24 Sep 24 08:17:59 AM UTC 24 267183052 ps
T396 /workspaces/repo/scratch/os_regression_2024_09_23/i2c-sim-vcs/coverage/default/7.i2c_target_intr_stress_wr.3989171971 Sep 24 08:17:35 AM UTC 24 Sep 24 08:17:59 AM UTC 24 12862077431 ps
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