Unified Coverage Report :: Group :: cip_base_pkg::intr_pins_cg::SHAPE{(num_interrupts - 1)=14}

Group : cip_base_pkg::intr_pins_cg::SHAPE{(num_interrupts - 1)=14}

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
100.00	1	100	1	64	64

Source File(s) :
/workspaces/repo/scratch/os_regression_2024_09_23/i2c-sim-vcs/default/sim-vcs/../src/lowrisc_dv_cip_lib_0/cip_base_env_cov.sv

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Summary for Group cip_base_pkg::intr_pins_cg::SHAPE{(num_interrupts - 1)=14}

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	19	0	19	100.00
Crosses	60	0	60	100.00

Variables for Group cip_base_pkg::intr_pins_cg::SHAPE{(num_interrupts - 1)=14}

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
cp_intr_pin	15	0	15	100.00	100	1	1	0
cp_intr_pin_value	4	0	4	100.00	100	1	1	0

Crosses for Group cip_base_pkg::intr_pins_cg::SHAPE{(num_interrupts - 1)=14}

CROSS	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	PRINT MISSING	COMMENT
cp_intr_pins_all_values	60	0	60	100.00	100	1	1	0

Summary for Variable cp_intr_pin

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	15	0	15	100.00

User Defined Bins for cp_intr_pin

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
all_pins[0]	627620	1			T1	1		T2	2		T3	8
all_pins[1]	627620	1			T1	1		T2	2		T3	8
all_pins[2]	627620	1			T1	1		T2	2		T3	8
all_pins[3]	627620	1			T1	1		T2	2		T3	8
all_pins[4]	627620	1			T1	1		T2	2		T3	8
all_pins[5]	627620	1			T1	1		T2	2		T3	8
all_pins[6]	627620	1			T1	1		T2	2		T3	8
all_pins[7]	627620	1			T1	1		T2	2		T3	8
all_pins[8]	627620	1			T1	1		T2	2		T3	8
all_pins[9]	627620	1			T1	1		T2	2		T3	8
all_pins[10]	627620	1			T1	1		T2	2		T3	8
all_pins[11]	627620	1			T1	1		T2	2		T3	8
all_pins[12]	627620	1			T1	1		T2	2		T3	8
all_pins[13]	627620	1			T1	1		T2	2		T3	8
all_pins[14]	627620	1			T1	1		T2	2		T3	8

---

Summary for Variable cp_intr_pin_value

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	4	0	4	100.00

User Defined Bins for cp_intr_pin_value

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
values[0x0]	7792785	1			T1	15		T2	30		T3	120
values[0x1]	1621515	1			T5	4		T6	4		T7	4
transitions[0x0=>0x1]	1620986	1			T5	4		T6	4		T7	4
transitions[0x1=>0x0]	1619676	1			T5	3		T6	3		T7	3

---

Summary for Cross cp_intr_pins_all_values

Samples crossed: cp_intr_pin cp_intr_pin_value

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	60	0	60	100.00

Automatically Generated Cross Bins for cp_intr_pins_all_values

Bins

cp_intr_pin	cp_intr_pin_value	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
all_pins[0]	values[0x0]	119843	1			T1	1		T2	2		T3	8
all_pins[0]	values[0x1]	507777	1			T5	2		T6	2		T7	2
all_pins[0]	transitions[0x0=>0x1]	507483	1			T5	2		T6	2		T7	2
all_pins[0]	transitions[0x1=>0x0]	55	1			T280	11		T281	2		T118	2
all_pins[1]	values[0x0]	627271	1			T1	1		T2	2		T3	8
all_pins[1]	values[0x1]	349	1			T30	66		T181	1		T272	9
all_pins[1]	transitions[0x0=>0x1]	342	1			T30	66		T181	1		T272	9
all_pins[1]	transitions[0x1=>0x0]	93	1			T72	1		T282	1		T283	1
all_pins[2]	values[0x0]	627520	1			T1	1		T2	2		T3	8
all_pins[2]	values[0x1]	100	1			T72	1		T282	1		T283	1
all_pins[2]	transitions[0x0=>0x1]	91	1			T72	1		T282	1		T283	1
all_pins[2]	transitions[0x1=>0x0]	82	1			T118	1		T128	6		T129	3
all_pins[3]	values[0x0]	627529	1			T1	1		T2	2		T3	8
all_pins[3]	values[0x1]	91	1			T118	2		T128	6		T129	3
all_pins[3]	transitions[0x0=>0x1]	74	1			T118	1		T128	5		T129	2
all_pins[3]	transitions[0x1=>0x0]	72	1			T12	1		T261	1		T255	1
all_pins[4]	values[0x0]	627531	1			T1	1		T2	2		T3	8
all_pins[4]	values[0x1]	89	1			T12	1		T261	1		T255	1
all_pins[4]	transitions[0x0=>0x1]	77	1			T12	1		T261	1		T255	1
all_pins[4]	transitions[0x1=>0x0]	46	1			T129	4		T238	3		T284	1
all_pins[5]	values[0x0]	627562	1			T1	1		T2	2		T3	8
all_pins[5]	values[0x1]	58	1			T118	1		T128	2		T129	4
all_pins[5]	transitions[0x0=>0x1]	43	1			T118	1		T128	1		T129	2
all_pins[5]	transitions[0x1=>0x0]	51	1			T118	1		T128	1		T129	1
all_pins[6]	values[0x0]	627554	1			T1	1		T2	2		T3	8
all_pins[6]	values[0x1]	66	1			T118	1		T128	2		T129	3
all_pins[6]	transitions[0x0=>0x1]	49	1			T128	2		T129	3		T238	3
all_pins[6]	transitions[0x1=>0x0]	28980	1			T9	2		T23	1		T42	1
all_pins[7]	values[0x0]	598623	1			T1	1		T2	2		T3	8
all_pins[7]	values[0x1]	28997	1			T9	2		T23	1		T42	1
all_pins[7]	transitions[0x0=>0x1]	28970	1			T9	2		T23	1		T42	1
all_pins[7]	transitions[0x1=>0x0]	74	1			T118	2		T128	5		T129	5
all_pins[8]	values[0x0]	627519	1			T1	1		T2	2		T3	8
all_pins[8]	values[0x1]	101	1			T118	4		T128	5		T129	6
all_pins[8]	transitions[0x0=>0x1]	78	1			T118	2		T128	5		T129	4
all_pins[8]	transitions[0x1=>0x0]	461904	1			T8	1		T9	2		T10	1
all_pins[9]	values[0x0]	165693	1			T1	1		T2	2		T3	8
all_pins[9]	values[0x1]	461927	1			T8	1		T9	2		T10	1
all_pins[9]	transitions[0x0=>0x1]	461917	1			T8	1		T9	2		T10	1
all_pins[9]	transitions[0x1=>0x0]	52	1			T118	1		T128	3		T129	2
all_pins[10]	values[0x0]	627558	1			T1	1		T2	2		T3	8
all_pins[10]	values[0x1]	62	1			T118	1		T128	3		T129	2
all_pins[10]	transitions[0x0=>0x1]	50	1			T118	1		T128	2		T129	1
all_pins[10]	transitions[0x1=>0x0]	621621	1			T5	2		T6	2		T7	2
all_pins[11]	values[0x0]	5987	1			T1	1		T2	2		T3	8
all_pins[11]	values[0x1]	621633	1			T5	2		T6	2		T7	2
all_pins[11]	transitions[0x0=>0x1]	621603	1			T5	2		T6	2		T7	2
all_pins[11]	transitions[0x1=>0x0]	96	1			T64	1		T68	1		T69	1
all_pins[12]	values[0x0]	627494	1			T1	1		T2	2		T3	8
all_pins[12]	values[0x1]	126	1			T64	1		T68	1		T69	1
all_pins[12]	transitions[0x0=>0x1]	112	1			T64	1		T68	1		T69	1
all_pins[12]	transitions[0x1=>0x0]	60	1			T118	4		T128	2		T129	1
all_pins[13]	values[0x0]	627546	1			T1	1		T2	2		T3	8
all_pins[13]	values[0x1]	74	1			T118	4		T128	2		T129	2
all_pins[13]	transitions[0x0=>0x1]	58	1			T118	1		T128	2		T129	1
all_pins[13]	transitions[0x1=>0x0]	49	1			T118	1		T128	2		T129	5
all_pins[14]	values[0x0]	627555	1			T1	1		T2	2		T3	8
all_pins[14]	values[0x1]	65	1			T118	4		T128	2		T129	6
all_pins[14]	transitions[0x0=>0x1]	39	1			T118	2		T128	1		T129	4
all_pins[14]	transitions[0x1=>0x0]	506441	1			T5	1		T6	1		T7	1