Unified Coverage Report :: Group :: cip_base_pkg::intr_test_cg::SHAPE{(num_interrupts - 1)=14}

Group : cip_base_pkg::intr_test_cg::SHAPE{(num_interrupts - 1)=14}

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
100.00	1	100	1	64	64

Source File(s) :
/workspaces/repo/scratch/os_regression_2024_09_23/i2c-sim-vcs/default/sim-vcs/../src/lowrisc_dv_cip_lib_0/cip_base_env_cov.sv

---

Summary for Group cip_base_pkg::intr_test_cg::SHAPE{(num_interrupts - 1)=14}

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	21	0	21	100.00
Crosses	90	0	90	100.00

Variables for Group cip_base_pkg::intr_test_cg::SHAPE{(num_interrupts - 1)=14}

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
cp_intr	15	0	15	100.00	100	1	1	0
cp_intr_en	2	0	2	100.00	100	1	1	2
cp_intr_state	2	0	2	100.00	100	1	1	2
cp_intr_test	2	0	2	100.00	100	1	1	2

Crosses for Group cip_base_pkg::intr_test_cg::SHAPE{(num_interrupts - 1)=14}

CROSS	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	PRINT MISSING	COMMENT
intr_test_cg_cc	90	0	90	100.00	100	1	1	0

Summary for Variable cp_intr

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	15	0	15	100.00

User Defined Bins for cp_intr

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
all_values[0]	309	1			T118	7		T128	11		T129	14
all_values[1]	309	1			T118	7		T128	11		T129	14
all_values[2]	309	1			T118	7		T128	11		T129	14
all_values[3]	309	1			T118	7		T128	11		T129	14
all_values[4]	309	1			T118	7		T128	11		T129	14
all_values[5]	309	1			T118	7		T128	11		T129	14
all_values[6]	309	1			T118	7		T128	11		T129	14
all_values[7]	309	1			T118	7		T128	11		T129	14
all_values[8]	309	1			T118	7		T128	11		T129	14
all_values[9]	309	1			T118	7		T128	11		T129	14
all_values[10]	309	1			T118	7		T128	11		T129	14
all_values[11]	309	1			T118	7		T128	11		T129	14
all_values[12]	309	1			T118	7		T128	11		T129	14
all_values[13]	309	1			T118	7		T128	11		T129	14
all_values[14]	309	1			T118	7		T128	11		T129	14

---

Summary for Variable cp_intr_en

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cp_intr_en

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

2567

1

T118

53

T128

88

T129

106

auto[1]

2068

1

T118

52

T128

77

T129

104

---

Summary for Variable cp_intr_state

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cp_intr_state

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

847

1

T118

11

T128

10

T129

8

auto[1]

3788

1

T118

94

T128

155

T129

202

---

Summary for Variable cp_intr_test

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cp_intr_test

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

2765

1

T118

55

T128

92

T129

115

auto[1]

1870

1

T118

50

T128

73

T129

95

---

Summary for Cross intr_test_cg_cc

Samples crossed: cp_intr cp_intr_test cp_intr_en cp_intr_state

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
TOTAL	90	0	90	100.00
Automatically Generated Cross Bins	90	0	90	100.00
User Defined Cross Bins	0	0	0

Automatically Generated Cross Bins for intr_test_cg_cc

Bins

cp_intr	cp_intr_test	cp_intr_en	cp_intr_state	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
all_values[0]	auto[0]	auto[0]	auto[0]	32	1			T129	1		T285	2		T286	1
all_values[0]	auto[0]	auto[0]	auto[1]	60	1			T118	2		T129	4		T238	4
all_values[0]	auto[0]	auto[1]	auto[0]	19	1			T128	1		T286	1		T287	3
all_values[0]	auto[0]	auto[1]	auto[1]	64	1			T118	1		T128	2		T129	3
all_values[0]	auto[1]	auto[0]	auto[1]	65	1			T118	2		T128	4		T129	2
all_values[0]	auto[1]	auto[1]	auto[1]	69	1			T118	2		T128	4		T129	4
all_values[1]	auto[0]	auto[0]	auto[0]	43	1			T129	1		T284	1		T285	1
all_values[1]	auto[0]	auto[0]	auto[1]	55	1			T128	5		T129	3		T238	2
all_values[1]	auto[0]	auto[1]	auto[0]	24	1			T238	1		T284	1		T288	1
all_values[1]	auto[0]	auto[1]	auto[1]	71	1			T118	2		T128	2		T129	5
all_values[1]	auto[1]	auto[0]	auto[1]	75	1			T118	2		T128	3		T129	2
all_values[1]	auto[1]	auto[1]	auto[1]	41	1			T118	3		T128	1		T129	3
all_values[2]	auto[0]	auto[0]	auto[0]	40	1			T118	1		T128	2		T129	2
all_values[2]	auto[0]	auto[0]	auto[1]	71	1			T118	2		T128	2		T129	1
all_values[2]	auto[0]	auto[1]	auto[0]	22	1			T128	1		T129	1		T238	3
all_values[2]	auto[0]	auto[1]	auto[1]	53	1			T128	2		T129	4		T238	1
all_values[2]	auto[1]	auto[0]	auto[1]	77	1			T118	2		T128	1		T129	3
all_values[2]	auto[1]	auto[1]	auto[1]	46	1			T118	2		T128	3		T129	3
all_values[3]	auto[0]	auto[0]	auto[0]	41	1			T285	1		T289	2		T288	1
all_values[3]	auto[0]	auto[0]	auto[1]	51	1			T118	3		T129	6		T238	1
all_values[3]	auto[0]	auto[1]	auto[0]	25	1			T238	1		T289	2		T290	2
all_values[3]	auto[0]	auto[1]	auto[1]	72	1			T128	4		T129	3		T238	6
all_values[3]	auto[1]	auto[0]	auto[1]	64	1			T118	3		T128	2		T129	3
all_values[3]	auto[1]	auto[1]	auto[1]	56	1			T118	1		T128	5		T129	2
all_values[4]	auto[0]	auto[0]	auto[0]	27	1			T118	1		T129	1		T284	1
all_values[4]	auto[0]	auto[0]	auto[1]	66	1			T118	2		T129	3		T238	4
all_values[4]	auto[0]	auto[1]	auto[0]	18	1			T118	1		T286	1		T291	1
all_values[4]	auto[0]	auto[1]	auto[1]	69	1			T118	1		T128	6		T129	5
all_values[4]	auto[1]	auto[0]	auto[1]	81	1			T128	1		T129	3		T238	4
all_values[4]	auto[1]	auto[1]	auto[1]	48	1			T118	2		T128	4		T129	2
all_values[5]	auto[0]	auto[0]	auto[0]	40	1			T286	2		T292	1		T289	1
all_values[5]	auto[0]	auto[0]	auto[1]	75	1			T118	3		T128	4		T129	2
all_values[5]	auto[0]	auto[1]	auto[0]	18	1			T128	1		T286	1		T293	1
all_values[5]	auto[0]	auto[1]	auto[1]	54	1			T118	2		T129	4		T238	1
all_values[5]	auto[1]	auto[0]	auto[1]	79	1			T118	2		T128	4		T129	6
all_values[5]	auto[1]	auto[1]	auto[1]	43	1			T128	2		T129	2		T238	2
all_values[6]	auto[0]	auto[0]	auto[0]	35	1			T286	2		T292	3		T289	1
all_values[6]	auto[0]	auto[0]	auto[1]	73	1			T118	2		T128	2		T129	3
all_values[6]	auto[0]	auto[1]	auto[0]	19	1			T284	2		T292	2		T293	2
all_values[6]	auto[0]	auto[1]	auto[1]	62	1			T118	3		T128	4		T129	6
all_values[6]	auto[1]	auto[0]	auto[1]	71	1			T118	1		T128	3		T129	2
all_values[6]	auto[1]	auto[1]	auto[1]	49	1			T118	1		T128	2		T129	3
all_values[7]	auto[0]	auto[0]	auto[0]	31	1			T129	1		T284	3		T285	1
all_values[7]	auto[0]	auto[0]	auto[1]	69	1			T128	4		T129	5		T238	4
all_values[7]	auto[0]	auto[1]	auto[0]	23	1			T284	1		T292	1		T290	2
all_values[7]	auto[0]	auto[1]	auto[1]	53	1			T118	2		T128	4		T129	2
all_values[7]	auto[1]	auto[0]	auto[1]	68	1			T118	3		T128	2		T129	5
all_values[7]	auto[1]	auto[1]	auto[1]	65	1			T118	2		T128	1		T129	1
all_values[8]	auto[0]	auto[0]	auto[0]	37	1			T285	1		T288	1		T293	1
all_values[8]	auto[0]	auto[0]	auto[1]	56	1			T128	3		T129	1		T238	4
all_values[8]	auto[0]	auto[1]	auto[0]	22	1			T128	1		T238	1		T291	2
all_values[8]	auto[0]	auto[1]	auto[1]	68	1			T118	4		T128	2		T129	4
all_values[8]	auto[1]	auto[0]	auto[1]	66	1			T118	1		T128	3		T129	4
all_values[8]	auto[1]	auto[1]	auto[1]	60	1			T118	2		T128	2		T129	5
all_values[9]	auto[0]	auto[0]	auto[0]	28	1			T118	3		T238	1		T285	1
all_values[9]	auto[0]	auto[0]	auto[1]	67	1			T118	1		T128	5		T129	2
all_values[9]	auto[0]	auto[1]	auto[0]	16	1			T285	1		T286	1		T287	1
all_values[9]	auto[0]	auto[1]	auto[1]	67	1			T118	1		T128	1		T129	7
all_values[9]	auto[1]	auto[0]	auto[1]	68	1			T128	3		T129	3		T238	3
all_values[9]	auto[1]	auto[1]	auto[1]	63	1			T118	2		T128	2		T129	2
all_values[10]	auto[0]	auto[0]	auto[0]	37	1			T118	2		T129	1		T286	1
all_values[10]	auto[0]	auto[0]	auto[1]	64	1			T118	2		T128	4		T129	3
all_values[10]	auto[0]	auto[1]	auto[0]	22	1			T118	1		T284	1		T290	1
all_values[10]	auto[0]	auto[1]	auto[1]	69	1			T128	3		T129	1		T238	6
all_values[10]	auto[1]	auto[0]	auto[1]	73	1			T118	1		T128	2		T129	7
all_values[10]	auto[1]	auto[1]	auto[1]	44	1			T118	1		T128	2		T129	2
all_values[11]	auto[0]	auto[0]	auto[0]	41	1			T284	3		T292	1		T290	3
all_values[11]	auto[0]	auto[0]	auto[1]	71	1			T128	6		T129	5		T238	1
all_values[11]	auto[0]	auto[1]	auto[0]	20	1			T128	1		T238	1		T284	4
all_values[11]	auto[0]	auto[1]	auto[1]	56	1			T118	3		T128	1		T129	2
all_values[11]	auto[1]	auto[0]	auto[1]	75	1			T118	2		T128	1		T129	4
all_values[11]	auto[1]	auto[1]	auto[1]	46	1			T118	2		T128	2		T129	3
all_values[12]	auto[0]	auto[0]	auto[0]	28	1			T284	1		T292	1		T289	2
all_values[12]	auto[0]	auto[0]	auto[1]	70	1			T118	1		T128	4		T129	3
all_values[12]	auto[0]	auto[1]	auto[0]	16	1			T294	1		T295	2		T293	1
all_values[12]	auto[0]	auto[1]	auto[1]	65	1			T118	3		T128	2		T129	6
all_values[12]	auto[1]	auto[0]	auto[1]	79	1			T118	3		T128	4		T129	1
all_values[12]	auto[1]	auto[1]	auto[1]	51	1			T128	1		T129	4		T238	4
all_values[13]	auto[0]	auto[0]	auto[0]	33	1			T118	1		T285	2		T292	1
all_values[13]	auto[0]	auto[0]	auto[1]	58	1			T128	2		T129	6		T238	3
all_values[13]	auto[0]	auto[1]	auto[0]	24	1			T128	1		T286	2		T294	4
all_values[13]	auto[0]	auto[1]	auto[1]	73	1			T118	1		T128	3		T129	1
all_values[13]	auto[1]	auto[0]	auto[1]	62	1			T118	1		T128	4		T129	4
all_values[13]	auto[1]	auto[1]	auto[1]	59	1			T118	4		T128	1		T129	3
all_values[14]	auto[0]	auto[0]	auto[0]	47	1			T118	1		T128	1		T238	1
all_values[14]	auto[0]	auto[0]	auto[1]	57	1			T118	2		T128	4		T129	2
all_values[14]	auto[0]	auto[1]	auto[0]	19	1			T128	1		T238	1		T284	4
all_values[14]	auto[0]	auto[1]	auto[1]	59	1			T118	1		T128	1		T129	5
all_values[14]	auto[1]	auto[0]	auto[1]	61	1			T118	1		T128	3		T129	1
all_values[14]	auto[1]	auto[1]	auto[1]	66	1			T118	2		T128	1		T129	6

User Defined Cross Bins for intr_test_cg_cc

Excluded/Illegal bins

NAME	COUNT	STATUS
test_1_state_0	0	Illegal