Unified Coverage Report :: Group :: cip_base_pkg::intr_cg::SHAPE{(num_interrupts - 1)=14}

Group : cip_base_pkg::intr_cg::SHAPE{(num_interrupts - 1)=14}

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
91.14	1	100	1	64	64

Source File(s) :
/workspaces/repo/scratch/os_regression_2024_10_02/i2c-sim-vcs/default/sim-vcs/../src/lowrisc_dv_cip_lib_0/cip_base_env_cov.sv

---

Summary for Group cip_base_pkg::intr_cg::SHAPE{(num_interrupts - 1)=14}

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	19	0	19	100.00
Crosses	60	7	53	88.33

Variables for Group cip_base_pkg::intr_cg::SHAPE{(num_interrupts - 1)=14}

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
cp_intr	15	0	15	100.00	100	1	1	0
cp_intr_en	2	0	2	100.00	100	1	1	2
cp_intr_state	2	0	2	100.00	100	1	1	2

Crosses for Group cip_base_pkg::intr_cg::SHAPE{(num_interrupts - 1)=14}

CROSS	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	PRINT MISSING	COMMENT
intr_cg_cc	60	7	53	88.33	100	1	1	0

Summary for Variable cp_intr

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	15	0	15	100.00

User Defined Bins for cp_intr

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
all_values[0]	806830	1			T1	1		T2	277		T3	2
all_values[1]	806830	1			T1	1		T2	277		T3	2
all_values[2]	806830	1			T1	1		T2	277		T3	2
all_values[3]	806830	1			T1	1		T2	277		T3	2
all_values[4]	806830	1			T1	1		T2	277		T3	2
all_values[5]	806830	1			T1	1		T2	277		T3	2
all_values[6]	806830	1			T1	1		T2	277		T3	2
all_values[7]	806830	1			T1	1		T2	277		T3	2
all_values[8]	806830	1			T1	1		T2	277		T3	2
all_values[9]	806830	1			T1	1		T2	277		T3	2
all_values[10]	806830	1			T1	1		T2	277		T3	2
all_values[11]	806830	1			T1	1		T2	277		T3	2
all_values[12]	806830	1			T1	1		T2	277		T3	2
all_values[13]	806830	1			T1	1		T2	277		T3	2
all_values[14]	806830	1			T1	1		T2	277		T3	2

---

Summary for Variable cp_intr_en

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cp_intr_en

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

9975933

1

T1

15

T2

3557

T3

30

auto[1]

2126517

1

T2

598

T4

6

T5

5

---

Summary for Variable cp_intr_state

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cp_intr_state

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

11394949

1

T1

15

T2

4155

T3

30

auto[1]

707501

1

T183

3195

T131

127

T132

64856

---

Summary for Cross intr_cg_cc

Samples crossed: cp_intr cp_intr_en cp_intr_state

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	60	7	53	88.33	7

Automatically Generated Cross Bins for intr_cg_cc

Uncovered bins

cp_intr	cp_intr_en	cp_intr_state	COUNT	AT LEAST	NUMBER	STATUS
[all_values[3]]	[auto[1]]	[auto[0]]	0	1	1
[all_values[5] , all_values[6]]	[auto[1]]	[auto[0]]	--	--	2
[all_values[8]]	[auto[1]]	[auto[0]]	0	1	1
[all_values[10]]	[auto[1]]	[auto[0]]	0	1	1
[all_values[13] , all_values[14]]	[auto[1]]	[auto[0]]	--	--	2

Covered bins

cp_intr	cp_intr_en	cp_intr_state	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
all_values[0]	auto[0]	auto[0]	123019	1			T1	1		T2	3		T3	2
all_values[0]	auto[0]	auto[1]	4417	1			T183	5		T132	602		T230	20
all_values[0]	auto[1]	auto[0]	636645	1			T2	274		T4	2		T5	2
all_values[0]	auto[1]	auto[1]	42749	1			T183	207		T131	9		T132	3722
all_values[1]	auto[0]	auto[0]	759550	1			T1	1		T2	277		T3	2
all_values[1]	auto[0]	auto[1]	46969	1			T183	210		T131	5		T132	4306
all_values[1]	auto[1]	auto[0]	140	1			T32	3		T271	2		T272	3
all_values[1]	auto[1]	auto[1]	171	1			T183	4		T131	2		T132	16
all_values[2]	auto[0]	auto[0]	759482	1			T1	1		T2	277		T3	2
all_values[2]	auto[0]	auto[1]	46996	1			T183	208		T131	4		T132	4321
all_values[2]	auto[1]	auto[0]	188	1			T169	1		T168	2		T62	1
all_values[2]	auto[1]	auto[1]	164	1			T183	5		T131	5		T132	4
all_values[3]	auto[0]	auto[0]	759652	1			T1	1		T2	277		T3	2
all_values[3]	auto[0]	auto[1]	46980	1			T183	208		T131	5		T132	4324
all_values[3]	auto[1]	auto[1]	198	1			T183	6		T131	4		T230	6
all_values[4]	auto[0]	auto[0]	759655	1			T1	1		T2	277		T3	2
all_values[4]	auto[0]	auto[1]	47008	1			T183	206		T131	6		T132	4320
all_values[4]	auto[1]	auto[0]	19	1			T12	1		T252	1		T259	1
all_values[4]	auto[1]	auto[1]	148	1			T183	3		T131	3		T132	2
all_values[5]	auto[0]	auto[0]	759658	1			T1	1		T2	277		T3	2
all_values[5]	auto[0]	auto[1]	46965	1			T183	207		T131	3		T132	4318
all_values[5]	auto[1]	auto[1]	207	1			T183	7		T131	6		T132	6
all_values[6]	auto[0]	auto[0]	759659	1			T1	1		T2	277		T3	2
all_values[6]	auto[0]	auto[1]	46984	1			T183	208		T131	2		T132	4319
all_values[6]	auto[1]	auto[1]	187	1			T183	6		T131	6		T132	5
all_values[7]	auto[0]	auto[0]	730659	1			T1	1		T2	243		T3	2
all_values[7]	auto[0]	auto[1]	45792	1			T183	187		T131	7		T132	4110
all_values[7]	auto[1]	auto[0]	28993	1			T2	34		T4	1		T6	3
all_values[7]	auto[1]	auto[1]	1386	1			T183	26		T131	2		T132	215
all_values[8]	auto[0]	auto[0]	759665	1			T1	1		T2	277		T3	2
all_values[8]	auto[0]	auto[1]	46978	1			T183	209		T131	2		T132	4320
all_values[8]	auto[1]	auto[1]	187	1			T183	4		T131	4		T132	3
all_values[9]	auto[0]	auto[0]	187419	1			T1	1		T2	262		T3	2
all_values[9]	auto[0]	auto[1]	9379	1			T183	195		T131	6		T132	849
all_values[9]	auto[1]	auto[0]	572237	1			T2	15		T4	1		T5	1
all_values[9]	auto[1]	auto[1]	37795	1			T183	19		T131	3		T132	3475
all_values[10]	auto[0]	auto[0]	759656	1			T1	1		T2	277		T3	2
all_values[10]	auto[0]	auto[1]	47010	1			T183	208		T131	5		T132	4319
all_values[10]	auto[1]	auto[1]	164	1			T183	5		T131	4		T132	1
all_values[11]	auto[0]	auto[0]	2157	1			T1	1		T2	2		T3	2
all_values[11]	auto[0]	auto[1]	288	1			T183	6		T132	18		T230	27
all_values[11]	auto[1]	auto[0]	757496	1			T2	275		T4	2		T5	2
all_values[11]	auto[1]	auto[1]	46889	1			T183	208		T131	9		T132	4307
all_values[12]	auto[0]	auto[0]	759597	1			T1	1		T2	277		T3	2
all_values[12]	auto[0]	auto[1]	47019	1			T183	209		T131	5		T132	4321
all_values[12]	auto[1]	auto[0]	63	1			T62	1		T273	1		T63	1
all_values[12]	auto[1]	auto[1]	151	1			T183	5		T131	2		T132	3
all_values[13]	auto[0]	auto[0]	759672	1			T1	1		T2	277		T3	2
all_values[13]	auto[0]	auto[1]	46977	1			T183	210		T131	6		T132	4321
all_values[13]	auto[1]	auto[1]	181	1			T183	1		T131	3		T132	4
all_values[14]	auto[0]	auto[0]	759668	1			T1	1		T2	277		T3	2
all_values[14]	auto[0]	auto[1]	47003	1			T183	213		T131	7		T132	4325
all_values[14]	auto[1]	auto[1]	159	1			T131	2		T230	7		T36	6