Tests
dashboard | hierarchy | modlist | groups | tests | asserts
Total Coverage Summary 
SCORELINECONDTOGGLEFSMBRANCHASSERTGROUP
91.19 97.14 89.39 97.22 72.02 94.08 98.47 90.00


Total tests in report: 1821
Tests are in graded order

Scores are accumulated (Total) and incremental (Incr) for each test.

SCORE LINE COND TOGGLE FSM BRANCH ASSERT GROUP  
TOTAL INCRTOTALINCRTOTALINCRTOTALINCRTOTALINCRTOTALINCRTOTALINCRTOTALINCRNAME
65.56 65.56 84.18 84.18 64.25 64.25 89.10 89.10 17.86 17.86 76.05 76.05 87.77 87.77 39.68 39.68 /workspaces/repo/scratch/os_regression_2024_10_02/i2c-sim-vcs/coverage/default/0.i2c_host_smoke.1470424066
76.66 11.11 91.35 7.17 72.79 8.54 90.72 1.62 58.33 40.48 85.67 9.62 90.61 2.84 47.16 7.47 /workspaces/repo/scratch/os_regression_2024_10_02/i2c-sim-vcs/coverage/default/0.i2c_target_glitch.2661990416
79.84 3.17 92.52 1.17 75.46 2.67 91.65 0.93 58.33 0.00 86.17 0.50 90.61 0.00 64.11 16.95 /workspaces/repo/scratch/os_regression_2024_10_02/i2c-sim-vcs/coverage/default/3.i2c_host_stress_all.3316821969
81.91 2.07 93.75 1.23 78.06 2.60 91.88 0.23 63.10 4.76 87.81 1.64 91.27 0.66 67.47 3.37 /workspaces/repo/scratch/os_regression_2024_10_02/i2c-sim-vcs/coverage/default/0.i2c_target_bad_addr.1924473719
83.18 1.28 93.78 0.03 79.22 1.17 92.81 0.93 63.10 0.00 87.88 0.07 94.76 3.49 70.74 3.26 /workspaces/repo/scratch/os_regression_2024_10_02/i2c-sim-vcs/coverage/cover_reg_top/2.i2c_tl_errors.2368721856
84.42 1.23 94.58 0.80 81.63 2.41 92.81 0.00 64.29 1.19 89.02 1.14 95.41 0.66 73.16 2.42 /workspaces/repo/scratch/os_regression_2024_10_02/i2c-sim-vcs/coverage/default/0.i2c_host_fifo_watermark.1175611294
85.32 0.91 94.89 0.31 83.25 1.62 93.39 0.58 66.67 2.38 89.74 0.71 95.63 0.22 73.68 0.53 /workspaces/repo/scratch/os_regression_2024_10_02/i2c-sim-vcs/coverage/default/4.i2c_host_error_intr.2967281546
86.03 0.71 95.29 0.40 84.91 1.66 93.97 0.58 67.26 0.60 91.02 1.28 95.85 0.22 73.89 0.21 /workspaces/repo/scratch/os_regression_2024_10_02/i2c-sim-vcs/coverage/default/0.i2c_target_nack_txstretch.450601019
86.54 0.51 95.57 0.28 85.51 0.60 94.20 0.23 67.26 0.00 91.80 0.78 96.07 0.22 75.37 1.47 /workspaces/repo/scratch/os_regression_2024_10_02/i2c-sim-vcs/coverage/default/1.i2c_host_override.4238579233
87.04 0.50 95.91 0.34 86.34 0.83 94.43 0.23 67.26 0.00 92.44 0.64 96.07 0.00 76.84 1.47 /workspaces/repo/scratch/os_regression_2024_10_02/i2c-sim-vcs/coverage/default/3.i2c_host_may_nack.2362844651
87.54 0.50 96.03 0.12 87.13 0.79 94.66 0.23 67.86 0.60 92.80 0.36 96.07 0.00 78.21 1.37 /workspaces/repo/scratch/os_regression_2024_10_02/i2c-sim-vcs/coverage/default/0.i2c_target_stress_all.4112821389
87.97 0.44 96.06 0.03 87.24 0.11 96.75 2.09 67.86 0.00 92.87 0.07 96.29 0.22 78.74 0.53 /workspaces/repo/scratch/os_regression_2024_10_02/i2c-sim-vcs/coverage/default/0.i2c_sec_cm.1488989341
88.37 0.39 96.06 0.00 87.28 0.04 96.75 0.00 67.86 0.00 92.94 0.07 96.51 0.22 81.16 2.42 /workspaces/repo/scratch/os_regression_2024_10_02/i2c-sim-vcs/coverage/default/30.i2c_host_stress_all.1219208528
88.73 0.37 96.49 0.43 87.28 0.00 96.75 0.00 69.05 1.19 93.37 0.43 96.51 0.00 81.68 0.53 /workspaces/repo/scratch/os_regression_2024_10_02/i2c-sim-vcs/coverage/default/6.i2c_target_nack_acqfull_addr.2657574135
88.98 0.25 96.49 0.00 87.35 0.08 96.75 0.00 69.05 0.00 93.37 0.00 96.51 0.00 83.37 1.68 /workspaces/repo/scratch/os_regression_2024_10_02/i2c-sim-vcs/coverage/default/0.i2c_host_fifo_reset_fmt.3986780437
89.23 0.24 96.52 0.03 87.39 0.04 96.75 0.00 69.05 0.00 93.37 0.00 98.03 1.53 83.47 0.11 /workspaces/repo/scratch/os_regression_2024_10_02/i2c-sim-vcs/coverage/cover_reg_top/2.i2c_csr_rw.2545443972
89.47 0.24 96.58 0.06 87.47 0.08 96.75 0.00 70.24 1.19 93.51 0.14 98.03 0.00 83.68 0.21 /workspaces/repo/scratch/os_regression_2024_10_02/i2c-sim-vcs/coverage/default/10.i2c_host_error_intr.3838884243
89.65 0.18 96.58 0.00 87.77 0.30 96.75 0.00 70.24 0.00 93.51 0.00 98.03 0.00 84.63 0.95 /workspaces/repo/scratch/os_regression_2024_10_02/i2c-sim-vcs/coverage/cover_reg_top/6.i2c_tl_intg_err.1403677673
89.82 0.17 96.74 0.15 87.81 0.04 96.75 0.00 70.83 0.60 93.73 0.21 98.03 0.00 84.84 0.21 /workspaces/repo/scratch/os_regression_2024_10_02/i2c-sim-vcs/coverage/default/2.i2c_target_stress_all.3307156113
89.97 0.15 96.86 0.12 87.92 0.11 96.75 0.00 71.43 0.60 93.87 0.14 98.03 0.00 84.95 0.11 /workspaces/repo/scratch/os_regression_2024_10_02/i2c-sim-vcs/coverage/default/0.i2c_target_nack_acqfull_addr.2946687529
90.10 0.12 96.98 0.12 87.92 0.00 96.75 0.00 72.02 0.60 94.01 0.14 98.03 0.00 84.95 0.00 /workspaces/repo/scratch/os_regression_2024_10_02/i2c-sim-vcs/coverage/default/18.i2c_target_nack_acqfull.2174915421
90.21 0.11 96.98 0.00 88.37 0.45 96.98 0.23 72.02 0.00 94.01 0.00 98.03 0.00 85.05 0.11 /workspaces/repo/scratch/os_regression_2024_10_02/i2c-sim-vcs/coverage/default/0.i2c_host_fifo_overflow.3458799685
90.30 0.09 96.98 0.00 88.37 0.00 96.98 0.00 72.02 0.00 94.01 0.00 98.03 0.00 85.68 0.63 /workspaces/repo/scratch/os_regression_2024_10_02/i2c-sim-vcs/coverage/cover_reg_top/0.i2c_intr_test.1253358329
90.37 0.08 96.98 0.00 88.37 0.00 96.98 0.00 72.02 0.00 94.01 0.00 98.03 0.00 86.21 0.53 /workspaces/repo/scratch/os_regression_2024_10_02/i2c-sim-vcs/coverage/cover_reg_top/3.i2c_intr_test.2816008737
90.45 0.08 96.98 0.00 88.37 0.00 96.98 0.00 72.02 0.00 94.01 0.00 98.03 0.00 86.74 0.53 /workspaces/repo/scratch/os_regression_2024_10_02/i2c-sim-vcs/coverage/default/3.i2c_host_fifo_reset_rx.55740023
90.52 0.07 96.98 0.00 88.45 0.08 96.98 0.00 72.02 0.00 94.01 0.00 98.03 0.00 87.16 0.42 /workspaces/repo/scratch/os_regression_2024_10_02/i2c-sim-vcs/coverage/default/9.i2c_host_stress_all.1898501225
90.59 0.07 97.11 0.12 88.56 0.11 97.22 0.23 72.02 0.00 94.01 0.00 98.03 0.00 87.16 0.00 /workspaces/repo/scratch/os_regression_2024_10_02/i2c-sim-vcs/coverage/default/0.i2c_alert_test.3187394098
90.65 0.06 97.11 0.00 88.56 0.00 97.22 0.00 72.02 0.00 94.01 0.00 98.03 0.00 87.58 0.42 /workspaces/repo/scratch/os_regression_2024_10_02/i2c-sim-vcs/coverage/default/0.i2c_target_fifo_watermarks_acq.3594626323
90.71 0.06 97.11 0.00 88.56 0.00 97.22 0.00 72.02 0.00 94.01 0.00 98.03 0.00 88.00 0.42 /workspaces/repo/scratch/os_regression_2024_10_02/i2c-sim-vcs/coverage/default/16.i2c_host_may_nack.1446059509
90.77 0.06 97.11 0.00 88.56 0.00 97.22 0.00 72.02 0.00 94.01 0.00 98.03 0.00 88.42 0.42 /workspaces/repo/scratch/os_regression_2024_10_02/i2c-sim-vcs/coverage/default/17.i2c_host_fifo_reset_fmt.3298981934
90.82 0.05 97.14 0.03 88.60 0.04 97.22 0.00 72.02 0.00 94.08 0.07 98.03 0.00 88.63 0.21 /workspaces/repo/scratch/os_regression_2024_10_02/i2c-sim-vcs/coverage/default/8.i2c_host_perf.1540529846
90.85 0.04 97.14 0.00 88.75 0.15 97.22 0.00 72.02 0.00 94.08 0.00 98.03 0.00 88.74 0.11 /workspaces/repo/scratch/os_regression_2024_10_02/i2c-sim-vcs/coverage/default/23.i2c_host_mode_toggle.2956638452
90.89 0.03 97.14 0.00 88.75 0.00 97.22 0.00 72.02 0.00 94.08 0.00 98.25 0.22 88.74 0.00 /workspaces/repo/scratch/os_regression_2024_10_02/i2c-sim-vcs/coverage/default/10.i2c_host_fifo_watermark.3122188159
90.92 0.03 97.14 0.00 88.75 0.00 97.22 0.00 72.02 0.00 94.08 0.00 98.47 0.22 88.74 0.00 /workspaces/repo/scratch/os_regression_2024_10_02/i2c-sim-vcs/coverage/default/17.i2c_target_smoke.2807245417
90.95 0.03 97.14 0.00 88.75 0.00 97.22 0.00 72.02 0.00 94.08 0.00 98.47 0.00 88.95 0.21 /workspaces/repo/scratch/os_regression_2024_10_02/i2c-sim-vcs/coverage/default/22.i2c_target_nack_acqfull_addr.567454786
90.98 0.03 97.14 0.00 88.75 0.00 97.22 0.00 72.02 0.00 94.08 0.00 98.47 0.00 89.16 0.21 /workspaces/repo/scratch/os_regression_2024_10_02/i2c-sim-vcs/coverage/default/33.i2c_target_fifo_reset_acq.3204441239
91.01 0.03 97.14 0.00 88.75 0.00 97.22 0.00 72.02 0.00 94.08 0.00 98.47 0.00 89.37 0.21 /workspaces/repo/scratch/os_regression_2024_10_02/i2c-sim-vcs/coverage/default/47.i2c_host_stress_all.501673374
91.03 0.03 97.14 0.00 88.93 0.19 97.22 0.00 72.02 0.00 94.08 0.00 98.47 0.00 89.37 0.00 /workspaces/repo/scratch/os_regression_2024_10_02/i2c-sim-vcs/coverage/cover_reg_top/2.i2c_tl_intg_err.4697543
91.06 0.02 97.14 0.00 89.09 0.15 97.22 0.00 72.02 0.00 94.08 0.00 98.47 0.00 89.37 0.00 /workspaces/repo/scratch/os_regression_2024_10_02/i2c-sim-vcs/coverage/cover_reg_top/11.i2c_tl_intg_err.296744018
91.08 0.02 97.14 0.00 89.12 0.04 97.22 0.00 72.02 0.00 94.08 0.00 98.47 0.00 89.47 0.11 /workspaces/repo/scratch/os_regression_2024_10_02/i2c-sim-vcs/coverage/default/21.i2c_target_hrst.755062630
91.09 0.02 97.14 0.00 89.12 0.00 97.22 0.00 72.02 0.00 94.08 0.00 98.47 0.00 89.58 0.11 /workspaces/repo/scratch/os_regression_2024_10_02/i2c-sim-vcs/coverage/default/1.i2c_target_tx_stretch_ctrl.396070951
91.11 0.02 97.14 0.00 89.12 0.00 97.22 0.00 72.02 0.00 94.08 0.00 98.47 0.00 89.68 0.11 /workspaces/repo/scratch/os_regression_2024_10_02/i2c-sim-vcs/coverage/default/10.i2c_target_stress_rd.1400274713
91.12 0.02 97.14 0.00 89.12 0.00 97.22 0.00 72.02 0.00 94.08 0.00 98.47 0.00 89.79 0.11 /workspaces/repo/scratch/os_regression_2024_10_02/i2c-sim-vcs/coverage/default/13.i2c_target_fifo_reset_tx.3079851380
91.14 0.02 97.14 0.00 89.12 0.00 97.22 0.00 72.02 0.00 94.08 0.00 98.47 0.00 89.89 0.11 /workspaces/repo/scratch/os_regression_2024_10_02/i2c-sim-vcs/coverage/default/20.i2c_host_may_nack.1615343735
91.15 0.02 97.14 0.00 89.12 0.00 97.22 0.00 72.02 0.00 94.08 0.00 98.47 0.00 90.00 0.11 /workspaces/repo/scratch/os_regression_2024_10_02/i2c-sim-vcs/coverage/default/31.i2c_host_may_nack.1519444658
91.16 0.01 97.14 0.00 89.20 0.08 97.22 0.00 72.02 0.00 94.08 0.00 98.47 0.00 90.00 0.00 /workspaces/repo/scratch/os_regression_2024_10_02/i2c-sim-vcs/coverage/cover_reg_top/10.i2c_tl_errors.634024593
91.17 0.01 97.14 0.00 89.24 0.04 97.22 0.00 72.02 0.00 94.08 0.00 98.47 0.00 90.00 0.00 /workspaces/repo/scratch/os_regression_2024_10_02/i2c-sim-vcs/coverage/cover_reg_top/10.i2c_tl_intg_err.1474943334
91.17 0.01 97.14 0.00 89.27 0.04 97.22 0.00 72.02 0.00 94.08 0.00 98.47 0.00 90.00 0.00 /workspaces/repo/scratch/os_regression_2024_10_02/i2c-sim-vcs/coverage/cover_reg_top/16.i2c_tl_intg_err.3872411698
91.18 0.01 97.14 0.00 89.31 0.04 97.22 0.00 72.02 0.00 94.08 0.00 98.47 0.00 90.00 0.00 /workspaces/repo/scratch/os_regression_2024_10_02/i2c-sim-vcs/coverage/cover_reg_top/2.i2c_same_csr_outstanding.3781617860
91.18 0.01 97.14 0.00 89.35 0.04 97.22 0.00 72.02 0.00 94.08 0.00 98.47 0.00 90.00 0.00 /workspaces/repo/scratch/os_regression_2024_10_02/i2c-sim-vcs/coverage/default/10.i2c_host_may_nack.424587006
91.19 0.01 97.14 0.00 89.39 0.04 97.22 0.00 72.02 0.00 94.08 0.00 98.47 0.00 90.00 0.00 /workspaces/repo/scratch/os_regression_2024_10_02/i2c-sim-vcs/coverage/default/11.i2c_host_mode_toggle.4057370116

Tests that do not contribute to grading

Name   
/workspaces/repo/scratch/os_regression_2024_10_02/i2c-sim-vcs/coverage/cover_reg_top/0.i2c_csr_aliasing.3870760111
/workspaces/repo/scratch/os_regression_2024_10_02/i2c-sim-vcs/coverage/cover_reg_top/0.i2c_csr_bit_bash.1765839021
/workspaces/repo/scratch/os_regression_2024_10_02/i2c-sim-vcs/coverage/cover_reg_top/0.i2c_csr_hw_reset.2377274278
/workspaces/repo/scratch/os_regression_2024_10_02/i2c-sim-vcs/coverage/cover_reg_top/0.i2c_csr_mem_rw_with_rand_reset.1087579812
/workspaces/repo/scratch/os_regression_2024_10_02/i2c-sim-vcs/coverage/cover_reg_top/0.i2c_csr_rw.1540494330
/workspaces/repo/scratch/os_regression_2024_10_02/i2c-sim-vcs/coverage/cover_reg_top/0.i2c_same_csr_outstanding.2336427053
/workspaces/repo/scratch/os_regression_2024_10_02/i2c-sim-vcs/coverage/cover_reg_top/0.i2c_tl_errors.2263865334
/workspaces/repo/scratch/os_regression_2024_10_02/i2c-sim-vcs/coverage/cover_reg_top/0.i2c_tl_intg_err.1744747202
/workspaces/repo/scratch/os_regression_2024_10_02/i2c-sim-vcs/coverage/cover_reg_top/1.i2c_csr_aliasing.504506391
/workspaces/repo/scratch/os_regression_2024_10_02/i2c-sim-vcs/coverage/cover_reg_top/1.i2c_csr_bit_bash.4266492341
/workspaces/repo/scratch/os_regression_2024_10_02/i2c-sim-vcs/coverage/cover_reg_top/1.i2c_csr_hw_reset.257010341
/workspaces/repo/scratch/os_regression_2024_10_02/i2c-sim-vcs/coverage/cover_reg_top/1.i2c_csr_mem_rw_with_rand_reset.802363346
/workspaces/repo/scratch/os_regression_2024_10_02/i2c-sim-vcs/coverage/cover_reg_top/1.i2c_csr_rw.105212896
/workspaces/repo/scratch/os_regression_2024_10_02/i2c-sim-vcs/coverage/cover_reg_top/1.i2c_intr_test.3232720634
/workspaces/repo/scratch/os_regression_2024_10_02/i2c-sim-vcs/coverage/cover_reg_top/1.i2c_same_csr_outstanding.763177896
/workspaces/repo/scratch/os_regression_2024_10_02/i2c-sim-vcs/coverage/cover_reg_top/1.i2c_tl_errors.163899074
/workspaces/repo/scratch/os_regression_2024_10_02/i2c-sim-vcs/coverage/cover_reg_top/1.i2c_tl_intg_err.532263346
/workspaces/repo/scratch/os_regression_2024_10_02/i2c-sim-vcs/coverage/cover_reg_top/10.i2c_csr_mem_rw_with_rand_reset.895337953
/workspaces/repo/scratch/os_regression_2024_10_02/i2c-sim-vcs/coverage/cover_reg_top/10.i2c_csr_rw.2335437637
/workspaces/repo/scratch/os_regression_2024_10_02/i2c-sim-vcs/coverage/cover_reg_top/10.i2c_intr_test.4163894990
/workspaces/repo/scratch/os_regression_2024_10_02/i2c-sim-vcs/coverage/cover_reg_top/11.i2c_csr_mem_rw_with_rand_reset.3748414608
/workspaces/repo/scratch/os_regression_2024_10_02/i2c-sim-vcs/coverage/cover_reg_top/11.i2c_csr_rw.3025092805
/workspaces/repo/scratch/os_regression_2024_10_02/i2c-sim-vcs/coverage/cover_reg_top/11.i2c_intr_test.3233465483
/workspaces/repo/scratch/os_regression_2024_10_02/i2c-sim-vcs/coverage/cover_reg_top/11.i2c_same_csr_outstanding.873834493
/workspaces/repo/scratch/os_regression_2024_10_02/i2c-sim-vcs/coverage/cover_reg_top/11.i2c_tl_errors.378812752
/workspaces/repo/scratch/os_regression_2024_10_02/i2c-sim-vcs/coverage/cover_reg_top/12.i2c_csr_mem_rw_with_rand_reset.2034961630
/workspaces/repo/scratch/os_regression_2024_10_02/i2c-sim-vcs/coverage/cover_reg_top/12.i2c_csr_rw.2263438337
/workspaces/repo/scratch/os_regression_2024_10_02/i2c-sim-vcs/coverage/cover_reg_top/12.i2c_intr_test.1932306584
/workspaces/repo/scratch/os_regression_2024_10_02/i2c-sim-vcs/coverage/cover_reg_top/12.i2c_same_csr_outstanding.3734887039
/workspaces/repo/scratch/os_regression_2024_10_02/i2c-sim-vcs/coverage/cover_reg_top/12.i2c_tl_errors.472417960
/workspaces/repo/scratch/os_regression_2024_10_02/i2c-sim-vcs/coverage/cover_reg_top/12.i2c_tl_intg_err.4223360529
/workspaces/repo/scratch/os_regression_2024_10_02/i2c-sim-vcs/coverage/cover_reg_top/13.i2c_csr_mem_rw_with_rand_reset.563168017
/workspaces/repo/scratch/os_regression_2024_10_02/i2c-sim-vcs/coverage/cover_reg_top/13.i2c_csr_rw.1481536744
/workspaces/repo/scratch/os_regression_2024_10_02/i2c-sim-vcs/coverage/cover_reg_top/13.i2c_intr_test.1041033410
/workspaces/repo/scratch/os_regression_2024_10_02/i2c-sim-vcs/coverage/cover_reg_top/13.i2c_same_csr_outstanding.386155414
/workspaces/repo/scratch/os_regression_2024_10_02/i2c-sim-vcs/coverage/cover_reg_top/13.i2c_tl_errors.3804060628
/workspaces/repo/scratch/os_regression_2024_10_02/i2c-sim-vcs/coverage/cover_reg_top/13.i2c_tl_intg_err.3413051982
/workspaces/repo/scratch/os_regression_2024_10_02/i2c-sim-vcs/coverage/cover_reg_top/14.i2c_csr_mem_rw_with_rand_reset.3132705036
/workspaces/repo/scratch/os_regression_2024_10_02/i2c-sim-vcs/coverage/cover_reg_top/14.i2c_csr_rw.4151903631
/workspaces/repo/scratch/os_regression_2024_10_02/i2c-sim-vcs/coverage/cover_reg_top/14.i2c_intr_test.839176167
/workspaces/repo/scratch/os_regression_2024_10_02/i2c-sim-vcs/coverage/cover_reg_top/14.i2c_same_csr_outstanding.1316663451
/workspaces/repo/scratch/os_regression_2024_10_02/i2c-sim-vcs/coverage/cover_reg_top/14.i2c_tl_errors.1385621519
/workspaces/repo/scratch/os_regression_2024_10_02/i2c-sim-vcs/coverage/cover_reg_top/14.i2c_tl_intg_err.1282131220
/workspaces/repo/scratch/os_regression_2024_10_02/i2c-sim-vcs/coverage/cover_reg_top/15.i2c_csr_mem_rw_with_rand_reset.740438234
/workspaces/repo/scratch/os_regression_2024_10_02/i2c-sim-vcs/coverage/cover_reg_top/15.i2c_csr_rw.1901743333
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/workspaces/repo/scratch/os_regression_2024_10_02/i2c-sim-vcs/coverage/default/7.i2c_target_intr_stress_wr.1176244147
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/workspaces/repo/scratch/os_regression_2024_10_02/i2c-sim-vcs/coverage/default/8.i2c_alert_test.2590713021
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/workspaces/repo/scratch/os_regression_2024_10_02/i2c-sim-vcs/coverage/default/8.i2c_host_fifo_full.2123023522
/workspaces/repo/scratch/os_regression_2024_10_02/i2c-sim-vcs/coverage/default/8.i2c_host_fifo_overflow.1377366038
/workspaces/repo/scratch/os_regression_2024_10_02/i2c-sim-vcs/coverage/default/8.i2c_host_fifo_reset_fmt.3293619811
/workspaces/repo/scratch/os_regression_2024_10_02/i2c-sim-vcs/coverage/default/8.i2c_host_fifo_reset_rx.1351186727
/workspaces/repo/scratch/os_regression_2024_10_02/i2c-sim-vcs/coverage/default/8.i2c_host_fifo_watermark.3339351673
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/workspaces/repo/scratch/os_regression_2024_10_02/i2c-sim-vcs/coverage/default/8.i2c_host_mode_toggle.2543719084
/workspaces/repo/scratch/os_regression_2024_10_02/i2c-sim-vcs/coverage/default/8.i2c_host_override.649863349
/workspaces/repo/scratch/os_regression_2024_10_02/i2c-sim-vcs/coverage/default/8.i2c_host_perf_precise.2498166530
/workspaces/repo/scratch/os_regression_2024_10_02/i2c-sim-vcs/coverage/default/8.i2c_host_smoke.1938533349
/workspaces/repo/scratch/os_regression_2024_10_02/i2c-sim-vcs/coverage/default/8.i2c_host_stretch_timeout.3144875
/workspaces/repo/scratch/os_regression_2024_10_02/i2c-sim-vcs/coverage/default/8.i2c_target_bad_addr.1605126006
/workspaces/repo/scratch/os_regression_2024_10_02/i2c-sim-vcs/coverage/default/8.i2c_target_fifo_reset_acq.1459226428
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/workspaces/repo/scratch/os_regression_2024_10_02/i2c-sim-vcs/coverage/default/8.i2c_target_fifo_watermarks_acq.4233828074
/workspaces/repo/scratch/os_regression_2024_10_02/i2c-sim-vcs/coverage/default/8.i2c_target_fifo_watermarks_tx.3724287706
/workspaces/repo/scratch/os_regression_2024_10_02/i2c-sim-vcs/coverage/default/8.i2c_target_intr_smoke.4143595249
/workspaces/repo/scratch/os_regression_2024_10_02/i2c-sim-vcs/coverage/default/8.i2c_target_intr_stress_wr.3375104411
/workspaces/repo/scratch/os_regression_2024_10_02/i2c-sim-vcs/coverage/default/8.i2c_target_nack_acqfull.3797941192
/workspaces/repo/scratch/os_regression_2024_10_02/i2c-sim-vcs/coverage/default/8.i2c_target_nack_acqfull_addr.3270774058
/workspaces/repo/scratch/os_regression_2024_10_02/i2c-sim-vcs/coverage/default/8.i2c_target_perf.2191764187
/workspaces/repo/scratch/os_regression_2024_10_02/i2c-sim-vcs/coverage/default/8.i2c_target_smbus_maxlen.49378649
/workspaces/repo/scratch/os_regression_2024_10_02/i2c-sim-vcs/coverage/default/8.i2c_target_smoke.3677130948
/workspaces/repo/scratch/os_regression_2024_10_02/i2c-sim-vcs/coverage/default/8.i2c_target_stress_all.3284470540
/workspaces/repo/scratch/os_regression_2024_10_02/i2c-sim-vcs/coverage/default/8.i2c_target_stress_rd.1823394833
/workspaces/repo/scratch/os_regression_2024_10_02/i2c-sim-vcs/coverage/default/8.i2c_target_stress_wr.1519286711
/workspaces/repo/scratch/os_regression_2024_10_02/i2c-sim-vcs/coverage/default/8.i2c_target_stretch.2806945470
/workspaces/repo/scratch/os_regression_2024_10_02/i2c-sim-vcs/coverage/default/8.i2c_target_timeout.1541139350
/workspaces/repo/scratch/os_regression_2024_10_02/i2c-sim-vcs/coverage/default/8.i2c_target_tx_stretch_ctrl.4227440670
/workspaces/repo/scratch/os_regression_2024_10_02/i2c-sim-vcs/coverage/default/9.i2c_alert_test.3755788364
/workspaces/repo/scratch/os_regression_2024_10_02/i2c-sim-vcs/coverage/default/9.i2c_host_error_intr.221821792
/workspaces/repo/scratch/os_regression_2024_10_02/i2c-sim-vcs/coverage/default/9.i2c_host_fifo_fmt_empty.2243470355
/workspaces/repo/scratch/os_regression_2024_10_02/i2c-sim-vcs/coverage/default/9.i2c_host_fifo_full.3953946911
/workspaces/repo/scratch/os_regression_2024_10_02/i2c-sim-vcs/coverage/default/9.i2c_host_fifo_overflow.2605373145
/workspaces/repo/scratch/os_regression_2024_10_02/i2c-sim-vcs/coverage/default/9.i2c_host_fifo_reset_fmt.1466823558
/workspaces/repo/scratch/os_regression_2024_10_02/i2c-sim-vcs/coverage/default/9.i2c_host_fifo_reset_rx.2624590844
/workspaces/repo/scratch/os_regression_2024_10_02/i2c-sim-vcs/coverage/default/9.i2c_host_fifo_watermark.3736269457
/workspaces/repo/scratch/os_regression_2024_10_02/i2c-sim-vcs/coverage/default/9.i2c_host_may_nack.2730292575
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/workspaces/repo/scratch/os_regression_2024_10_02/i2c-sim-vcs/coverage/default/9.i2c_host_perf_precise.1161324184
/workspaces/repo/scratch/os_regression_2024_10_02/i2c-sim-vcs/coverage/default/9.i2c_host_smoke.4060669467
/workspaces/repo/scratch/os_regression_2024_10_02/i2c-sim-vcs/coverage/default/9.i2c_host_stretch_timeout.1072082719
/workspaces/repo/scratch/os_regression_2024_10_02/i2c-sim-vcs/coverage/default/9.i2c_target_bad_addr.1148847089
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/workspaces/repo/scratch/os_regression_2024_10_02/i2c-sim-vcs/coverage/default/9.i2c_target_fifo_watermarks_tx.3320343666
/workspaces/repo/scratch/os_regression_2024_10_02/i2c-sim-vcs/coverage/default/9.i2c_target_intr_smoke.662146585
/workspaces/repo/scratch/os_regression_2024_10_02/i2c-sim-vcs/coverage/default/9.i2c_target_intr_stress_wr.1283696838
/workspaces/repo/scratch/os_regression_2024_10_02/i2c-sim-vcs/coverage/default/9.i2c_target_nack_acqfull.2575254338
/workspaces/repo/scratch/os_regression_2024_10_02/i2c-sim-vcs/coverage/default/9.i2c_target_nack_acqfull_addr.2607570454
/workspaces/repo/scratch/os_regression_2024_10_02/i2c-sim-vcs/coverage/default/9.i2c_target_nack_txstretch.3679627249
/workspaces/repo/scratch/os_regression_2024_10_02/i2c-sim-vcs/coverage/default/9.i2c_target_perf.2937200158
/workspaces/repo/scratch/os_regression_2024_10_02/i2c-sim-vcs/coverage/default/9.i2c_target_smbus_maxlen.4268663055
/workspaces/repo/scratch/os_regression_2024_10_02/i2c-sim-vcs/coverage/default/9.i2c_target_smoke.2986211387
/workspaces/repo/scratch/os_regression_2024_10_02/i2c-sim-vcs/coverage/default/9.i2c_target_stress_all.3516693865
/workspaces/repo/scratch/os_regression_2024_10_02/i2c-sim-vcs/coverage/default/9.i2c_target_stress_rd.3254181003
/workspaces/repo/scratch/os_regression_2024_10_02/i2c-sim-vcs/coverage/default/9.i2c_target_stress_wr.4250373275
/workspaces/repo/scratch/os_regression_2024_10_02/i2c-sim-vcs/coverage/default/9.i2c_target_stretch.426456844
/workspaces/repo/scratch/os_regression_2024_10_02/i2c-sim-vcs/coverage/default/9.i2c_target_timeout.1481223520
/workspaces/repo/scratch/os_regression_2024_10_02/i2c-sim-vcs/coverage/default/9.i2c_target_tx_stretch_ctrl.2382368619



Total test records in report: 1821
tests.html | tests1.html | tests2.html | tests3.html | tests4.html | tests5.html | tests6.html | tests7.html | tests8.html | tests9.html | tests10.html | tests11.html | tests12.html | tests13.html | tests14.html | tests15.html | tests16.html | tests17.html | tests18.html | tests19.html | tests20.html | tests21.html | tests22.html | tests23.html | tests24.html | tests25.html | tests26.html | tests27.html | tests28.html | tests29.html | tests30.html | tests31.html | tests32.html | tests33.html | tests34.html | tests35.html | tests36.html | tests37.html | tests38.html
TEST NOTEST LOCATIONTEST NAMESTATUSSTARTEDFINISHEDSIMULATION TIME
T1 /workspaces/repo/scratch/os_regression_2024_10_02/i2c-sim-vcs/coverage/default/0.i2c_host_override.3859210543 Oct 02 08:18:31 PM UTC 24 Oct 02 08:18:33 PM UTC 24 93270668 ps
T2 /workspaces/repo/scratch/os_regression_2024_10_02/i2c-sim-vcs/coverage/default/0.i2c_host_smoke.1470424066 Oct 02 08:18:02 PM UTC 24 Oct 02 08:18:34 PM UTC 24 8827799646 ps
T3 /workspaces/repo/scratch/os_regression_2024_10_02/i2c-sim-vcs/coverage/default/0.i2c_host_fifo_reset_fmt.3986780437 Oct 02 08:18:36 PM UTC 24 Oct 02 08:18:39 PM UTC 24 653377150 ps
T4 /workspaces/repo/scratch/os_regression_2024_10_02/i2c-sim-vcs/coverage/default/0.i2c_host_fifo_fmt_empty.1091979822 Oct 02 08:18:36 PM UTC 24 Oct 02 08:18:42 PM UTC 24 251697373 ps
T5 /workspaces/repo/scratch/os_regression_2024_10_02/i2c-sim-vcs/coverage/default/0.i2c_host_fifo_reset_rx.2142313328 Oct 02 08:18:40 PM UTC 24 Oct 02 08:18:49 PM UTC 24 1499244504 ps
T6 /workspaces/repo/scratch/os_regression_2024_10_02/i2c-sim-vcs/coverage/default/0.i2c_host_perf_precise.3114096106 Oct 02 08:18:57 PM UTC 24 Oct 02 08:19:03 PM UTC 24 248525913 ps
T7 /workspaces/repo/scratch/os_regression_2024_10_02/i2c-sim-vcs/coverage/default/0.i2c_host_perf.3120454559 Oct 02 08:18:49 PM UTC 24 Oct 02 08:19:11 PM UTC 24 6474696082 ps
T8 /workspaces/repo/scratch/os_regression_2024_10_02/i2c-sim-vcs/coverage/default/0.i2c_host_error_intr.4183636140 Oct 02 08:19:12 PM UTC 24 Oct 02 08:19:15 PM UTC 24 134718253 ps
T9 /workspaces/repo/scratch/os_regression_2024_10_02/i2c-sim-vcs/coverage/default/0.i2c_host_stretch_timeout.2580313826 Oct 02 08:19:04 PM UTC 24 Oct 02 08:19:20 PM UTC 24 9638131140 ps
T10 /workspaces/repo/scratch/os_regression_2024_10_02/i2c-sim-vcs/coverage/default/0.i2c_target_smoke.3347217829 Oct 02 08:19:22 PM UTC 24 Oct 02 08:19:35 PM UTC 24 741582713 ps
T42 /workspaces/repo/scratch/os_regression_2024_10_02/i2c-sim-vcs/coverage/default/0.i2c_target_glitch.2661990416 Oct 02 08:19:15 PM UTC 24 Oct 02 08:19:36 PM UTC 24 8713106328 ps
T43 /workspaces/repo/scratch/os_regression_2024_10_02/i2c-sim-vcs/coverage/default/0.i2c_target_stress_rd.2795925134 Oct 02 08:19:36 PM UTC 24 Oct 02 08:19:48 PM UTC 24 1248426163 ps
T30 /workspaces/repo/scratch/os_regression_2024_10_02/i2c-sim-vcs/coverage/default/0.i2c_host_fifo_watermark.1175611294 Oct 02 08:18:33 PM UTC 24 Oct 02 08:19:50 PM UTC 24 5428754241 ps
T44 /workspaces/repo/scratch/os_regression_2024_10_02/i2c-sim-vcs/coverage/default/0.i2c_target_intr_smoke.1493540130 Oct 02 08:19:37 PM UTC 24 Oct 02 08:19:50 PM UTC 24 2260836048 ps
T71 /workspaces/repo/scratch/os_regression_2024_10_02/i2c-sim-vcs/coverage/default/2.i2c_target_smoke.1142271052 Oct 02 08:22:11 PM UTC 24 Oct 02 08:22:20 PM UTC 24 829327498 ps
T68 /workspaces/repo/scratch/os_regression_2024_10_02/i2c-sim-vcs/coverage/default/0.i2c_target_fifo_reset_acq.2787648562 Oct 02 08:19:50 PM UTC 24 Oct 02 08:19:52 PM UTC 24 162252049 ps
T45 /workspaces/repo/scratch/os_regression_2024_10_02/i2c-sim-vcs/coverage/default/0.i2c_target_fifo_reset_tx.3597568931 Oct 02 08:19:51 PM UTC 24 Oct 02 08:19:54 PM UTC 24 590816692 ps
T46 /workspaces/repo/scratch/os_regression_2024_10_02/i2c-sim-vcs/coverage/default/0.i2c_target_perf.1695452100 Oct 02 08:19:51 PM UTC 24 Oct 02 08:19:57 PM UTC 24 410713002 ps
T72 /workspaces/repo/scratch/os_regression_2024_10_02/i2c-sim-vcs/coverage/default/0.i2c_target_timeout.1407455215 Oct 02 08:19:46 PM UTC 24 Oct 02 08:19:58 PM UTC 24 1063362192 ps
T73 /workspaces/repo/scratch/os_regression_2024_10_02/i2c-sim-vcs/coverage/default/0.i2c_target_hrst.2897150654 Oct 02 08:19:55 PM UTC 24 Oct 02 08:20:00 PM UTC 24 780967399 ps
T64 /workspaces/repo/scratch/os_regression_2024_10_02/i2c-sim-vcs/coverage/default/0.i2c_target_bad_addr.1924473719 Oct 02 08:19:53 PM UTC 24 Oct 02 08:20:02 PM UTC 24 2352188067 ps
T74 /workspaces/repo/scratch/os_regression_2024_10_02/i2c-sim-vcs/coverage/default/0.i2c_target_fifo_watermarks_tx.3493264647 Oct 02 08:20:01 PM UTC 24 Oct 02 08:20:04 PM UTC 24 451024804 ps
T41 /workspaces/repo/scratch/os_regression_2024_10_02/i2c-sim-vcs/coverage/default/2.i2c_host_fifo_fmt_empty.1017338295 Oct 02 08:21:44 PM UTC 24 Oct 02 08:22:19 PM UTC 24 1882847985 ps
T169 /workspaces/repo/scratch/os_regression_2024_10_02/i2c-sim-vcs/coverage/default/0.i2c_target_fifo_watermarks_acq.3594626323 Oct 02 08:20:00 PM UTC 24 Oct 02 08:20:05 PM UTC 24 689039015 ps
T11 /workspaces/repo/scratch/os_regression_2024_10_02/i2c-sim-vcs/coverage/default/0.i2c_host_may_nack.1627304903 Oct 02 08:19:59 PM UTC 24 Oct 02 08:20:06 PM UTC 24 610369583 ps
T58 /workspaces/repo/scratch/os_regression_2024_10_02/i2c-sim-vcs/coverage/default/0.i2c_target_nack_txstretch.450601019 Oct 02 08:20:07 PM UTC 24 Oct 02 08:20:10 PM UTC 24 138239982 ps
T168 /workspaces/repo/scratch/os_regression_2024_10_02/i2c-sim-vcs/coverage/default/0.i2c_target_smbus_maxlen.3106794640 Oct 02 08:20:05 PM UTC 24 Oct 02 08:20:11 PM UTC 24 912080534 ps
T61 /workspaces/repo/scratch/os_regression_2024_10_02/i2c-sim-vcs/coverage/default/0.i2c_target_nack_acqfull.2054006824 Oct 02 08:20:06 PM UTC 24 Oct 02 08:20:11 PM UTC 24 1352762876 ps
T174 /workspaces/repo/scratch/os_regression_2024_10_02/i2c-sim-vcs/coverage/default/0.i2c_sec_cm.1488989341 Oct 02 08:20:10 PM UTC 24 Oct 02 08:20:12 PM UTC 24 40820567 ps
T62 /workspaces/repo/scratch/os_regression_2024_10_02/i2c-sim-vcs/coverage/default/0.i2c_target_nack_acqfull_addr.2946687529 Oct 02 08:20:06 PM UTC 24 Oct 02 08:20:12 PM UTC 24 979087561 ps
T98 /workspaces/repo/scratch/os_regression_2024_10_02/i2c-sim-vcs/coverage/default/0.i2c_alert_test.3187394098 Oct 02 08:20:11 PM UTC 24 Oct 02 08:20:13 PM UTC 24 15617047 ps
T77 /workspaces/repo/scratch/os_regression_2024_10_02/i2c-sim-vcs/coverage/default/1.i2c_host_override.4238579233 Oct 02 08:20:12 PM UTC 24 Oct 02 08:20:14 PM UTC 24 166722122 ps
T34 /workspaces/repo/scratch/os_regression_2024_10_02/i2c-sim-vcs/coverage/default/1.i2c_host_fifo_reset_fmt.332581459 Oct 02 08:20:13 PM UTC 24 Oct 02 08:20:15 PM UTC 24 83136558 ps
T154 /workspaces/repo/scratch/os_regression_2024_10_02/i2c-sim-vcs/coverage/default/1.i2c_host_fifo_reset_rx.2658606450 Oct 02 08:20:16 PM UTC 24 Oct 02 08:20:23 PM UTC 24 172579964 ps
T155 /workspaces/repo/scratch/os_regression_2024_10_02/i2c-sim-vcs/coverage/default/0.i2c_target_intr_stress_wr.3833390283 Oct 02 08:19:43 PM UTC 24 Oct 02 08:20:25 PM UTC 24 8267848626 ps
T156 /workspaces/repo/scratch/os_regression_2024_10_02/i2c-sim-vcs/coverage/default/1.i2c_host_fifo_fmt_empty.206640321 Oct 02 08:20:15 PM UTC 24 Oct 02 08:20:40 PM UTC 24 970360818 ps
T157 /workspaces/repo/scratch/os_regression_2024_10_02/i2c-sim-vcs/coverage/default/1.i2c_target_smoke.1039185150 Oct 02 08:20:34 PM UTC 24 Oct 02 08:20:50 PM UTC 24 812200581 ps
T50 /workspaces/repo/scratch/os_regression_2024_10_02/i2c-sim-vcs/coverage/default/1.i2c_target_glitch.3635757911 Oct 02 08:20:34 PM UTC 24 Oct 02 08:20:55 PM UTC 24 2107207931 ps
T75 /workspaces/repo/scratch/os_regression_2024_10_02/i2c-sim-vcs/coverage/default/0.i2c_target_stress_all.4112821389 Oct 02 08:19:53 PM UTC 24 Oct 02 08:20:56 PM UTC 24 43298189256 ps
T31 /workspaces/repo/scratch/os_regression_2024_10_02/i2c-sim-vcs/coverage/default/1.i2c_host_fifo_overflow.1917415271 Oct 02 08:20:13 PM UTC 24 Oct 02 08:21:01 PM UTC 24 1782372660 ps
T158 /workspaces/repo/scratch/os_regression_2024_10_02/i2c-sim-vcs/coverage/default/1.i2c_target_stretch.2247383360 Oct 02 08:20:54 PM UTC 24 Oct 02 08:21:03 PM UTC 24 547134210 ps
T299 /workspaces/repo/scratch/os_regression_2024_10_02/i2c-sim-vcs/coverage/default/1.i2c_target_intr_smoke.1556064920 Oct 02 08:20:55 PM UTC 24 Oct 02 08:21:05 PM UTC 24 1799084097 ps
T27 /workspaces/repo/scratch/os_regression_2024_10_02/i2c-sim-vcs/coverage/default/1.i2c_host_stretch_timeout.3356387833 Oct 02 08:20:25 PM UTC 24 Oct 02 08:21:05 PM UTC 24 3072889682 ps
T239 /workspaces/repo/scratch/os_regression_2024_10_02/i2c-sim-vcs/coverage/default/1.i2c_target_fifo_reset_tx.1131563616 Oct 02 08:21:06 PM UTC 24 Oct 02 08:21:09 PM UTC 24 151947847 ps
T241 /workspaces/repo/scratch/os_regression_2024_10_02/i2c-sim-vcs/coverage/default/1.i2c_target_fifo_reset_acq.2702653911 Oct 02 08:21:06 PM UTC 24 Oct 02 08:21:10 PM UTC 24 233774376 ps
T76 /workspaces/repo/scratch/os_regression_2024_10_02/i2c-sim-vcs/coverage/default/1.i2c_target_timeout.3851787890 Oct 02 08:21:02 PM UTC 24 Oct 02 08:21:14 PM UTC 24 4387696926 ps
T208 /workspaces/repo/scratch/os_regression_2024_10_02/i2c-sim-vcs/coverage/default/1.i2c_target_perf.568463531 Oct 02 08:21:07 PM UTC 24 Oct 02 08:21:15 PM UTC 24 1089620519 ps
T300 /workspaces/repo/scratch/os_regression_2024_10_02/i2c-sim-vcs/coverage/default/1.i2c_target_hrst.1017880887 Oct 02 08:21:14 PM UTC 24 Oct 02 08:21:19 PM UTC 24 643777932 ps
T65 /workspaces/repo/scratch/os_regression_2024_10_02/i2c-sim-vcs/coverage/default/1.i2c_target_bad_addr.2866156872 Oct 02 08:21:10 PM UTC 24 Oct 02 08:21:20 PM UTC 24 17118911895 ps
T301 /workspaces/repo/scratch/os_regression_2024_10_02/i2c-sim-vcs/coverage/default/1.i2c_target_fifo_watermarks_tx.2222934752 Oct 02 08:21:24 PM UTC 24 Oct 02 08:21:26 PM UTC 24 443408074 ps
T273 /workspaces/repo/scratch/os_regression_2024_10_02/i2c-sim-vcs/coverage/default/1.i2c_target_fifo_watermarks_acq.4176014834 Oct 02 08:21:24 PM UTC 24 Oct 02 08:21:30 PM UTC 24 855947130 ps
T302 /workspaces/repo/scratch/os_regression_2024_10_02/i2c-sim-vcs/coverage/default/1.i2c_target_smbus_maxlen.1378968796 Oct 02 08:21:27 PM UTC 24 Oct 02 08:21:32 PM UTC 24 7934588816 ps
T213 /workspaces/repo/scratch/os_regression_2024_10_02/i2c-sim-vcs/coverage/default/1.i2c_target_stress_rd.2493538935 Oct 02 08:20:51 PM UTC 24 Oct 02 08:21:35 PM UTC 24 3433726148 ps
T69 /workspaces/repo/scratch/os_regression_2024_10_02/i2c-sim-vcs/coverage/default/1.i2c_target_tx_stretch_ctrl.396070951 Oct 02 08:21:26 PM UTC 24 Oct 02 08:21:37 PM UTC 24 468173480 ps
T63 /workspaces/repo/scratch/os_regression_2024_10_02/i2c-sim-vcs/coverage/default/1.i2c_target_nack_acqfull_addr.2516193114 Oct 02 08:21:33 PM UTC 24 Oct 02 08:21:38 PM UTC 24 2250163361 ps
T160 /workspaces/repo/scratch/os_regression_2024_10_02/i2c-sim-vcs/coverage/default/1.i2c_target_nack_acqfull.2339295110 Oct 02 08:21:31 PM UTC 24 Oct 02 08:21:38 PM UTC 24 885274263 ps
T303 /workspaces/repo/scratch/os_regression_2024_10_02/i2c-sim-vcs/coverage/default/2.i2c_target_stretch.3456328318 Oct 02 08:22:14 PM UTC 24 Oct 02 08:22:19 PM UTC 24 273374830 ps
T99 /workspaces/repo/scratch/os_regression_2024_10_02/i2c-sim-vcs/coverage/default/1.i2c_alert_test.3002373751 Oct 02 08:21:38 PM UTC 24 Oct 02 08:21:40 PM UTC 24 19520551 ps
T19 /workspaces/repo/scratch/os_regression_2024_10_02/i2c-sim-vcs/coverage/default/0.i2c_host_fifo_full.2839522041 Oct 02 08:18:43 PM UTC 24 Oct 02 08:21:41 PM UTC 24 3908309254 ps
T184 /workspaces/repo/scratch/os_regression_2024_10_02/i2c-sim-vcs/coverage/default/1.i2c_sec_cm.2565424453 Oct 02 08:21:38 PM UTC 24 Oct 02 08:21:41 PM UTC 24 190173134 ps
T101 /workspaces/repo/scratch/os_regression_2024_10_02/i2c-sim-vcs/coverage/default/2.i2c_host_override.283531392 Oct 02 08:21:40 PM UTC 24 Oct 02 08:21:43 PM UTC 24 87265259 ps
T35 /workspaces/repo/scratch/os_regression_2024_10_02/i2c-sim-vcs/coverage/default/2.i2c_host_fifo_reset_fmt.1342323438 Oct 02 08:21:42 PM UTC 24 Oct 02 08:21:44 PM UTC 24 411960484 ps
T14 /workspaces/repo/scratch/os_regression_2024_10_02/i2c-sim-vcs/coverage/default/1.i2c_host_perf.3523674614 Oct 02 08:20:22 PM UTC 24 Oct 02 08:21:45 PM UTC 24 27057571302 ps
T12 /workspaces/repo/scratch/os_regression_2024_10_02/i2c-sim-vcs/coverage/default/1.i2c_host_may_nack.4002570119 Oct 02 08:21:20 PM UTC 24 Oct 02 08:21:48 PM UTC 24 656371032 ps
T161 /workspaces/repo/scratch/os_regression_2024_10_02/i2c-sim-vcs/coverage/default/2.i2c_host_fifo_reset_rx.1938270010 Oct 02 08:21:46 PM UTC 24 Oct 02 08:22:04 PM UTC 24 224583087 ps
T17 /workspaces/repo/scratch/os_regression_2024_10_02/i2c-sim-vcs/coverage/default/2.i2c_host_error_intr.1781283797 Oct 02 08:22:06 PM UTC 24 Oct 02 08:22:09 PM UTC 24 111594163 ps
T304 /workspaces/repo/scratch/os_regression_2024_10_02/i2c-sim-vcs/coverage/default/2.i2c_host_perf_precise.4200497597 Oct 02 08:21:49 PM UTC 24 Oct 02 08:22:10 PM UTC 24 779854688 ps
T25 /workspaces/repo/scratch/os_regression_2024_10_02/i2c-sim-vcs/coverage/default/1.i2c_host_fifo_full.1087734404 Oct 02 08:20:19 PM UTC 24 Oct 02 08:22:10 PM UTC 24 11591894632 ps
T32 /workspaces/repo/scratch/os_regression_2024_10_02/i2c-sim-vcs/coverage/default/1.i2c_host_smoke.2856510188 Oct 02 08:20:12 PM UTC 24 Oct 02 08:22:11 PM UTC 24 2021285714 ps
T305 /workspaces/repo/scratch/os_regression_2024_10_02/i2c-sim-vcs/coverage/default/2.i2c_host_smoke.2836654921 Oct 02 08:21:38 PM UTC 24 Oct 02 08:22:13 PM UTC 24 1275665037 ps
T306 /workspaces/repo/scratch/os_regression_2024_10_02/i2c-sim-vcs/coverage/default/2.i2c_target_stress_rd.708725884 Oct 02 08:22:12 PM UTC 24 Oct 02 08:22:23 PM UTC 24 819572473 ps
T13 /workspaces/repo/scratch/os_regression_2024_10_02/i2c-sim-vcs/coverage/default/2.i2c_host_may_nack.2010407564 Oct 02 08:22:53 PM UTC 24 Oct 02 08:23:06 PM UTC 24 1225791847 ps
T307 /workspaces/repo/scratch/os_regression_2024_10_02/i2c-sim-vcs/coverage/default/2.i2c_target_intr_smoke.916017890 Oct 02 08:22:20 PM UTC 24 Oct 02 08:22:28 PM UTC 24 2754018793 ps
T308 /workspaces/repo/scratch/os_regression_2024_10_02/i2c-sim-vcs/coverage/default/2.i2c_host_stretch_timeout.2280037116 Oct 02 08:22:05 PM UTC 24 Oct 02 08:22:29 PM UTC 24 1923385020 ps
T242 /workspaces/repo/scratch/os_regression_2024_10_02/i2c-sim-vcs/coverage/default/2.i2c_target_fifo_reset_acq.3418367922 Oct 02 08:22:28 PM UTC 24 Oct 02 08:22:32 PM UTC 24 807998074 ps
T309 /workspaces/repo/scratch/os_regression_2024_10_02/i2c-sim-vcs/coverage/default/2.i2c_target_fifo_reset_tx.26081129 Oct 02 08:22:29 PM UTC 24 Oct 02 08:22:32 PM UTC 24 461246034 ps
T310 /workspaces/repo/scratch/os_regression_2024_10_02/i2c-sim-vcs/coverage/default/2.i2c_target_timeout.2289770139 Oct 02 08:22:21 PM UTC 24 Oct 02 08:22:34 PM UTC 24 3382313322 ps
T311 /workspaces/repo/scratch/os_regression_2024_10_02/i2c-sim-vcs/coverage/default/2.i2c_target_perf.912710887 Oct 02 08:22:30 PM UTC 24 Oct 02 08:22:41 PM UTC 24 1833140922 ps
T66 /workspaces/repo/scratch/os_regression_2024_10_02/i2c-sim-vcs/coverage/default/2.i2c_target_bad_addr.1754113450 Oct 02 08:22:33 PM UTC 24 Oct 02 08:22:46 PM UTC 24 5887579989 ps
T312 /workspaces/repo/scratch/os_regression_2024_10_02/i2c-sim-vcs/coverage/default/2.i2c_target_stress_wr.1015272703 Oct 02 08:22:11 PM UTC 24 Oct 02 08:22:48 PM UTC 24 15356704633 ps
T33 /workspaces/repo/scratch/os_regression_2024_10_02/i2c-sim-vcs/coverage/default/2.i2c_host_fifo_overflow.812882014 Oct 02 08:21:42 PM UTC 24 Oct 02 08:22:56 PM UTC 24 14475544395 ps
T102 /workspaces/repo/scratch/os_regression_2024_10_02/i2c-sim-vcs/coverage/default/0.i2c_host_fifo_overflow.3458799685 Oct 02 08:18:34 PM UTC 24 Oct 02 08:22:56 PM UTC 24 5196504450 ps
T313 /workspaces/repo/scratch/os_regression_2024_10_02/i2c-sim-vcs/coverage/default/2.i2c_target_fifo_watermarks_tx.4209726761 Oct 02 08:22:56 PM UTC 24 Oct 02 08:22:59 PM UTC 24 128319423 ps
T280 /workspaces/repo/scratch/os_regression_2024_10_02/i2c-sim-vcs/coverage/default/2.i2c_target_fifo_watermarks_acq.3834707162 Oct 02 08:22:54 PM UTC 24 Oct 02 08:23:00 PM UTC 24 458882068 ps
T70 /workspaces/repo/scratch/os_regression_2024_10_02/i2c-sim-vcs/coverage/default/2.i2c_target_tx_stretch_ctrl.3264227273 Oct 02 08:22:56 PM UTC 24 Oct 02 08:23:03 PM UTC 24 209449384 ps
T100 /workspaces/repo/scratch/os_regression_2024_10_02/i2c-sim-vcs/coverage/default/2.i2c_alert_test.3504555158 Oct 02 08:23:04 PM UTC 24 Oct 02 08:23:06 PM UTC 24 20364170 ps
T187 /workspaces/repo/scratch/os_regression_2024_10_02/i2c-sim-vcs/coverage/default/2.i2c_sec_cm.3500818632 Oct 02 08:23:04 PM UTC 24 Oct 02 08:23:07 PM UTC 24 164304176 ps
T59 /workspaces/repo/scratch/os_regression_2024_10_02/i2c-sim-vcs/coverage/default/2.i2c_target_nack_txstretch.4080271757 Oct 02 08:23:04 PM UTC 24 Oct 02 08:23:07 PM UTC 24 490200577 ps
T67 /workspaces/repo/scratch/os_regression_2024_10_02/i2c-sim-vcs/coverage/default/2.i2c_target_nack_acqfull_addr.350716524 Oct 02 08:23:04 PM UTC 24 Oct 02 08:23:09 PM UTC 24 1576486222 ps
T314 /workspaces/repo/scratch/os_regression_2024_10_02/i2c-sim-vcs/coverage/default/2.i2c_target_smbus_maxlen.3361341754 Oct 02 08:23:04 PM UTC 24 Oct 02 08:23:09 PM UTC 24 756583005 ps
T146 /workspaces/repo/scratch/os_regression_2024_10_02/i2c-sim-vcs/coverage/default/3.i2c_host_override.3876369623 Oct 02 08:23:07 PM UTC 24 Oct 02 08:23:09 PM UTC 24 33706383 ps
T162 /workspaces/repo/scratch/os_regression_2024_10_02/i2c-sim-vcs/coverage/default/2.i2c_target_nack_acqfull.2399513549 Oct 02 08:23:04 PM UTC 24 Oct 02 08:23:10 PM UTC 24 2054100875 ps
T315 /workspaces/repo/scratch/os_regression_2024_10_02/i2c-sim-vcs/coverage/default/3.i2c_host_fifo_reset_fmt.21993750 Oct 02 08:23:10 PM UTC 24 Oct 02 08:23:13 PM UTC 24 416602955 ps
T240 /workspaces/repo/scratch/os_regression_2024_10_02/i2c-sim-vcs/coverage/default/1.i2c_target_stress_all.2175964361 Oct 02 08:21:10 PM UTC 24 Oct 02 08:23:15 PM UTC 24 52896452408 ps
T316 /workspaces/repo/scratch/os_regression_2024_10_02/i2c-sim-vcs/coverage/default/5.i2c_host_fifo_reset_fmt.1941577099 Oct 02 08:26:30 PM UTC 24 Oct 02 08:26:33 PM UTC 24 105208138 ps
T175 /workspaces/repo/scratch/os_regression_2024_10_02/i2c-sim-vcs/coverage/default/3.i2c_host_fifo_reset_rx.55740023 Oct 02 08:23:11 PM UTC 24 Oct 02 08:23:16 PM UTC 24 404105012 ps
T317 /workspaces/repo/scratch/os_regression_2024_10_02/i2c-sim-vcs/coverage/default/3.i2c_host_perf_precise.2377218486 Oct 02 08:23:16 PM UTC 24 Oct 02 08:23:20 PM UTC 24 438897728 ps
T18 /workspaces/repo/scratch/os_regression_2024_10_02/i2c-sim-vcs/coverage/default/3.i2c_host_error_intr.3911264437 Oct 02 08:23:17 PM UTC 24 Oct 02 08:23:20 PM UTC 24 371902403 ps
T318 /workspaces/repo/scratch/os_regression_2024_10_02/i2c-sim-vcs/coverage/default/3.i2c_host_fifo_fmt_empty.3620901134 Oct 02 08:23:10 PM UTC 24 Oct 02 08:23:25 PM UTC 24 789453665 ps
T289 /workspaces/repo/scratch/os_regression_2024_10_02/i2c-sim-vcs/coverage/default/3.i2c_host_stretch_timeout.1323683292 Oct 02 08:23:17 PM UTC 24 Oct 02 08:23:31 PM UTC 24 615378443 ps
T319 /workspaces/repo/scratch/os_regression_2024_10_02/i2c-sim-vcs/coverage/default/3.i2c_target_smoke.2256256044 Oct 02 08:23:21 PM UTC 24 Oct 02 08:23:39 PM UTC 24 884023557 ps
T176 /workspaces/repo/scratch/os_regression_2024_10_02/i2c-sim-vcs/coverage/default/3.i2c_host_fifo_overflow.1071868577 Oct 02 08:23:08 PM UTC 24 Oct 02 08:23:47 PM UTC 24 2840214316 ps
T288 /workspaces/repo/scratch/os_regression_2024_10_02/i2c-sim-vcs/coverage/default/3.i2c_host_smoke.123078400 Oct 02 08:23:07 PM UTC 24 Oct 02 08:23:47 PM UTC 24 1607615923 ps
T320 /workspaces/repo/scratch/os_regression_2024_10_02/i2c-sim-vcs/coverage/default/3.i2c_target_stretch.3528969430 Oct 02 08:23:41 PM UTC 24 Oct 02 08:23:51 PM UTC 24 2225796654 ps
T266 /workspaces/repo/scratch/os_regression_2024_10_02/i2c-sim-vcs/coverage/default/3.i2c_target_stress_rd.427307903 Oct 02 08:23:32 PM UTC 24 Oct 02 08:23:57 PM UTC 24 1055433265 ps
T321 /workspaces/repo/scratch/os_regression_2024_10_02/i2c-sim-vcs/coverage/default/3.i2c_target_intr_smoke.1668715850 Oct 02 08:23:48 PM UTC 24 Oct 02 08:24:00 PM UTC 24 4028851139 ps
T322 /workspaces/repo/scratch/os_regression_2024_10_02/i2c-sim-vcs/coverage/default/3.i2c_target_fifo_reset_acq.838323611 Oct 02 08:24:01 PM UTC 24 Oct 02 08:24:04 PM UTC 24 284554804 ps
T323 /workspaces/repo/scratch/os_regression_2024_10_02/i2c-sim-vcs/coverage/default/3.i2c_target_timeout.22074008 Oct 02 08:23:52 PM UTC 24 Oct 02 08:24:05 PM UTC 24 1398366625 ps
T324 /workspaces/repo/scratch/os_regression_2024_10_02/i2c-sim-vcs/coverage/default/3.i2c_target_fifo_reset_tx.946077862 Oct 02 08:24:01 PM UTC 24 Oct 02 08:24:05 PM UTC 24 239211950 ps
T325 /workspaces/repo/scratch/os_regression_2024_10_02/i2c-sim-vcs/coverage/default/1.i2c_target_intr_stress_wr.3384049637 Oct 02 08:20:57 PM UTC 24 Oct 02 08:24:08 PM UTC 24 27221868712 ps
T326 /workspaces/repo/scratch/os_regression_2024_10_02/i2c-sim-vcs/coverage/default/3.i2c_target_perf.2551832434 Oct 02 08:24:04 PM UTC 24 Oct 02 08:24:11 PM UTC 24 380030622 ps
T327 /workspaces/repo/scratch/os_regression_2024_10_02/i2c-sim-vcs/coverage/default/3.i2c_target_bad_addr.1053822108 Oct 02 08:24:05 PM UTC 24 Oct 02 08:24:15 PM UTC 24 1142213001 ps
T328 /workspaces/repo/scratch/os_regression_2024_10_02/i2c-sim-vcs/coverage/default/5.i2c_host_perf_precise.3418207641 Oct 02 08:26:34 PM UTC 24 Oct 02 08:26:38 PM UTC 24 180546388 ps
T78 /workspaces/repo/scratch/os_regression_2024_10_02/i2c-sim-vcs/coverage/default/2.i2c_host_fifo_watermark.2352151692 Oct 02 08:21:42 PM UTC 24 Oct 02 08:24:34 PM UTC 24 2957267660 ps
T329 /workspaces/repo/scratch/os_regression_2024_10_02/i2c-sim-vcs/coverage/default/3.i2c_target_fifo_watermarks_acq.2715300583 Oct 02 08:24:36 PM UTC 24 Oct 02 08:24:40 PM UTC 24 670029600 ps
T330 /workspaces/repo/scratch/os_regression_2024_10_02/i2c-sim-vcs/coverage/default/3.i2c_target_fifo_watermarks_tx.2041528927 Oct 02 08:24:38 PM UTC 24 Oct 02 08:24:41 PM UTC 24 786770264 ps
T331 /workspaces/repo/scratch/os_regression_2024_10_02/i2c-sim-vcs/coverage/default/3.i2c_target_smbus_maxlen.919742279 Oct 02 08:24:41 PM UTC 24 Oct 02 08:24:48 PM UTC 24 2230239571 ps
T252 /workspaces/repo/scratch/os_regression_2024_10_02/i2c-sim-vcs/coverage/default/3.i2c_host_may_nack.2362844651 Oct 02 08:24:35 PM UTC 24 Oct 02 08:24:49 PM UTC 24 976650767 ps
T60 /workspaces/repo/scratch/os_regression_2024_10_02/i2c-sim-vcs/coverage/default/3.i2c_target_nack_txstretch.4137314162 Oct 02 08:24:51 PM UTC 24 Oct 02 08:24:55 PM UTC 24 275627271 ps
T163 /workspaces/repo/scratch/os_regression_2024_10_02/i2c-sim-vcs/coverage/default/2.i2c_host_fifo_full.799196740 Oct 02 08:21:46 PM UTC 24 Oct 02 08:24:55 PM UTC 24 22634326009 ps
T164 /workspaces/repo/scratch/os_regression_2024_10_02/i2c-sim-vcs/coverage/default/3.i2c_target_nack_acqfull.143284675 Oct 02 08:24:48 PM UTC 24 Oct 02 08:24:55 PM UTC 24 1069209818 ps
T165 /workspaces/repo/scratch/os_regression_2024_10_02/i2c-sim-vcs/coverage/default/3.i2c_target_nack_acqfull_addr.231658982 Oct 02 08:24:51 PM UTC 24 Oct 02 08:24:56 PM UTC 24 515290922 ps
T332 /workspaces/repo/scratch/os_regression_2024_10_02/i2c-sim-vcs/coverage/default/3.i2c_alert_test.2216041869 Oct 02 08:24:56 PM UTC 24 Oct 02 08:24:57 PM UTC 24 17152708 ps
T295 /workspaces/repo/scratch/os_regression_2024_10_02/i2c-sim-vcs/coverage/default/3.i2c_target_tx_stretch_ctrl.63579306 Oct 02 08:24:40 PM UTC 24 Oct 02 08:24:58 PM UTC 24 828812324 ps
T188 /workspaces/repo/scratch/os_regression_2024_10_02/i2c-sim-vcs/coverage/default/3.i2c_sec_cm.406918418 Oct 02 08:24:56 PM UTC 24 Oct 02 08:24:58 PM UTC 24 141181308 ps
T333 /workspaces/repo/scratch/os_regression_2024_10_02/i2c-sim-vcs/coverage/default/4.i2c_host_override.1978974371 Oct 02 08:24:57 PM UTC 24 Oct 02 08:24:59 PM UTC 24 43609666 ps
T245 /workspaces/repo/scratch/os_regression_2024_10_02/i2c-sim-vcs/coverage/default/4.i2c_host_fifo_reset_fmt.2464629885 Oct 02 08:24:59 PM UTC 24 Oct 02 08:25:02 PM UTC 24 979172859 ps
T15 /workspaces/repo/scratch/os_regression_2024_10_02/i2c-sim-vcs/coverage/default/3.i2c_host_perf.2200634496 Oct 02 08:23:14 PM UTC 24 Oct 02 08:25:12 PM UTC 24 7515410717 ps
T166 /workspaces/repo/scratch/os_regression_2024_10_02/i2c-sim-vcs/coverage/default/4.i2c_host_fifo_reset_rx.532571759 Oct 02 08:25:02 PM UTC 24 Oct 02 08:25:15 PM UTC 24 823473582 ps
T334 /workspaces/repo/scratch/os_regression_2024_10_02/i2c-sim-vcs/coverage/default/4.i2c_host_perf_precise.3885451428 Oct 02 08:25:13 PM UTC 24 Oct 02 08:25:16 PM UTC 24 101247516 ps
T335 /workspaces/repo/scratch/os_regression_2024_10_02/i2c-sim-vcs/coverage/default/4.i2c_host_fifo_fmt_empty.1277598612 Oct 02 08:25:00 PM UTC 24 Oct 02 08:25:16 PM UTC 24 1023708246 ps
T51 /workspaces/repo/scratch/os_regression_2024_10_02/i2c-sim-vcs/coverage/default/2.i2c_target_intr_stress_wr.36159571 Oct 02 08:22:21 PM UTC 24 Oct 02 08:25:25 PM UTC 24 20493784192 ps
T79 /workspaces/repo/scratch/os_regression_2024_10_02/i2c-sim-vcs/coverage/default/1.i2c_host_fifo_watermark.554741435 Oct 02 08:20:13 PM UTC 24 Oct 02 08:25:33 PM UTC 24 5103766565 ps
T167 /workspaces/repo/scratch/os_regression_2024_10_02/i2c-sim-vcs/coverage/default/3.i2c_host_fifo_full.4078195329 Oct 02 08:23:11 PM UTC 24 Oct 02 08:25:37 PM UTC 24 2343162168 ps
T20 /workspaces/repo/scratch/os_regression_2024_10_02/i2c-sim-vcs/coverage/default/4.i2c_host_error_intr.2967281546 Oct 02 08:25:16 PM UTC 24 Oct 02 08:25:42 PM UTC 24 6740065377 ps
T336 /workspaces/repo/scratch/os_regression_2024_10_02/i2c-sim-vcs/coverage/default/4.i2c_target_stretch.3758580800 Oct 02 08:25:43 PM UTC 24 Oct 02 08:25:55 PM UTC 24 2365460826 ps
T177 /workspaces/repo/scratch/os_regression_2024_10_02/i2c-sim-vcs/coverage/default/3.i2c_host_fifo_watermark.4112581293 Oct 02 08:23:08 PM UTC 24 Oct 02 08:25:58 PM UTC 24 22137791479 ps
T55 /workspaces/repo/scratch/os_regression_2024_10_02/i2c-sim-vcs/coverage/default/2.i2c_target_stress_all.3307156113 Oct 02 08:22:33 PM UTC 24 Oct 02 08:26:00 PM UTC 24 21874864682 ps
T337 /workspaces/repo/scratch/os_regression_2024_10_02/i2c-sim-vcs/coverage/default/4.i2c_host_stretch_timeout.1668077617 Oct 02 08:25:16 PM UTC 24 Oct 02 08:26:00 PM UTC 24 2767515287 ps
T338 /workspaces/repo/scratch/os_regression_2024_10_02/i2c-sim-vcs/coverage/default/4.i2c_target_smoke.1472422864 Oct 02 08:25:26 PM UTC 24 Oct 02 08:26:03 PM UTC 24 854622930 ps
T339 /workspaces/repo/scratch/os_regression_2024_10_02/i2c-sim-vcs/coverage/default/4.i2c_target_intr_smoke.2310950401 Oct 02 08:25:56 PM UTC 24 Oct 02 08:26:06 PM UTC 24 4013282583 ps
T340 /workspaces/repo/scratch/os_regression_2024_10_02/i2c-sim-vcs/coverage/default/4.i2c_target_fifo_reset_acq.1021706876 Oct 02 08:26:03 PM UTC 24 Oct 02 08:26:06 PM UTC 24 126795590 ps
T341 /workspaces/repo/scratch/os_regression_2024_10_02/i2c-sim-vcs/coverage/default/4.i2c_target_fifo_reset_tx.4231233588 Oct 02 08:26:05 PM UTC 24 Oct 02 08:26:09 PM UTC 24 283127188 ps
T178 /workspaces/repo/scratch/os_regression_2024_10_02/i2c-sim-vcs/coverage/default/4.i2c_host_fifo_overflow.3920151323 Oct 02 08:24:59 PM UTC 24 Oct 02 08:26:11 PM UTC 24 2371684993 ps
T342 /workspaces/repo/scratch/os_regression_2024_10_02/i2c-sim-vcs/coverage/default/4.i2c_target_timeout.1131541297 Oct 02 08:26:00 PM UTC 24 Oct 02 08:26:14 PM UTC 24 1248389790 ps
T16 /workspaces/repo/scratch/os_regression_2024_10_02/i2c-sim-vcs/coverage/default/4.i2c_host_perf.2252659013 Oct 02 08:25:08 PM UTC 24 Oct 02 08:26:14 PM UTC 24 12285381296 ps
T343 /workspaces/repo/scratch/os_regression_2024_10_02/i2c-sim-vcs/coverage/default/4.i2c_target_perf.1791437085 Oct 02 08:26:07 PM UTC 24 Oct 02 08:26:15 PM UTC 24 2839154446 ps
T344 /workspaces/repo/scratch/os_regression_2024_10_02/i2c-sim-vcs/coverage/default/4.i2c_host_smoke.3611520758 Oct 02 08:24:56 PM UTC 24 Oct 02 08:26:17 PM UTC 24 8761029714 ps
T345 /workspaces/repo/scratch/os_regression_2024_10_02/i2c-sim-vcs/coverage/default/4.i2c_target_bad_addr.861054845 Oct 02 08:26:10 PM UTC 24 Oct 02 08:26:18 PM UTC 24 14269453632 ps
T346 /workspaces/repo/scratch/os_regression_2024_10_02/i2c-sim-vcs/coverage/default/4.i2c_target_fifo_watermarks_tx.2308291882 Oct 02 08:26:19 PM UTC 24 Oct 02 08:26:22 PM UTC 24 376041636 ps
T347 /workspaces/repo/scratch/os_regression_2024_10_02/i2c-sim-vcs/coverage/default/4.i2c_target_fifo_watermarks_acq.3779993386 Oct 02 08:26:18 PM UTC 24 Oct 02 08:26:22 PM UTC 24 3210185984 ps
T348 /workspaces/repo/scratch/os_regression_2024_10_02/i2c-sim-vcs/coverage/default/4.i2c_host_may_nack.2818972393 Oct 02 08:26:17 PM UTC 24 Oct 02 08:26:24 PM UTC 24 283103079 ps
T231 /workspaces/repo/scratch/os_regression_2024_10_02/i2c-sim-vcs/coverage/default/2.i2c_host_perf.3179686356 Oct 02 08:21:49 PM UTC 24 Oct 02 08:26:26 PM UTC 24 49061173200 ps
T349 /workspaces/repo/scratch/os_regression_2024_10_02/i2c-sim-vcs/coverage/default/4.i2c_target_tx_stretch_ctrl.1801316654 Oct 02 08:26:21 PM UTC 24 Oct 02 08:26:27 PM UTC 24 197502902 ps
T113 /workspaces/repo/scratch/os_regression_2024_10_02/i2c-sim-vcs/coverage/default/4.i2c_host_fifo_watermark.3141705269 Oct 02 08:24:58 PM UTC 24 Oct 02 08:26:27 PM UTC 24 17354929358 ps
T123 /workspaces/repo/scratch/os_regression_2024_10_02/i2c-sim-vcs/coverage/default/4.i2c_target_smbus_maxlen.3775079984 Oct 02 08:26:22 PM UTC 24 Oct 02 08:26:27 PM UTC 24 2155653066 ps
T124 /workspaces/repo/scratch/os_regression_2024_10_02/i2c-sim-vcs/coverage/default/4.i2c_target_nack_txstretch.1033419616 Oct 02 08:26:25 PM UTC 24 Oct 02 08:26:28 PM UTC 24 312718094 ps
T125 /workspaces/repo/scratch/os_regression_2024_10_02/i2c-sim-vcs/coverage/default/4.i2c_sec_cm.4042606707 Oct 02 08:26:27 PM UTC 24 Oct 02 08:26:29 PM UTC 24 416441222 ps
T126 /workspaces/repo/scratch/os_regression_2024_10_02/i2c-sim-vcs/coverage/default/4.i2c_target_nack_acqfull_addr.2252873223 Oct 02 08:26:25 PM UTC 24 Oct 02 08:26:29 PM UTC 24 1068673487 ps
T127 /workspaces/repo/scratch/os_regression_2024_10_02/i2c-sim-vcs/coverage/default/4.i2c_alert_test.3013451796 Oct 02 08:26:28 PM UTC 24 Oct 02 08:26:31 PM UTC 24 37378241 ps
T128 /workspaces/repo/scratch/os_regression_2024_10_02/i2c-sim-vcs/coverage/default/4.i2c_target_nack_acqfull.2025115069 Oct 02 08:26:25 PM UTC 24 Oct 02 08:26:31 PM UTC 24 560826852 ps
T129 /workspaces/repo/scratch/os_regression_2024_10_02/i2c-sim-vcs/coverage/default/5.i2c_host_override.810440703 Oct 02 08:26:28 PM UTC 24 Oct 02 08:26:31 PM UTC 24 20472926 ps
T56 /workspaces/repo/scratch/os_regression_2024_10_02/i2c-sim-vcs/coverage/default/4.i2c_target_stress_wr.1700081164 Oct 02 08:25:34 PM UTC 24 Oct 02 08:26:34 PM UTC 24 35781899739 ps
T130 /workspaces/repo/scratch/os_regression_2024_10_02/i2c-sim-vcs/coverage/default/5.i2c_host_fifo_fmt_empty.1416816164 Oct 02 08:26:31 PM UTC 24 Oct 02 08:26:39 PM UTC 24 839511160 ps
T21 /workspaces/repo/scratch/os_regression_2024_10_02/i2c-sim-vcs/coverage/default/5.i2c_host_error_intr.4151578496 Oct 02 08:26:38 PM UTC 24 Oct 02 08:26:42 PM UTC 24 457903332 ps
T350 /workspaces/repo/scratch/os_regression_2024_10_02/i2c-sim-vcs/coverage/default/5.i2c_host_fifo_reset_rx.2059523922 Oct 02 08:26:32 PM UTC 24 Oct 02 08:26:44 PM UTC 24 178385471 ps
T351 /workspaces/repo/scratch/os_regression_2024_10_02/i2c-sim-vcs/coverage/default/5.i2c_host_smoke.3896120023 Oct 02 08:26:28 PM UTC 24 Oct 02 08:26:57 PM UTC 24 1457650273 ps
T267 /workspaces/repo/scratch/os_regression_2024_10_02/i2c-sim-vcs/coverage/default/4.i2c_target_stress_rd.2521794824 Oct 02 08:25:38 PM UTC 24 Oct 02 08:27:06 PM UTC 24 1708405115 ps
T38 /workspaces/repo/scratch/os_regression_2024_10_02/i2c-sim-vcs/coverage/default/5.i2c_host_perf.1798587591 Oct 02 08:26:34 PM UTC 24 Oct 02 08:27:07 PM UTC 24 2813968099 ps
T352 /workspaces/repo/scratch/os_regression_2024_10_02/i2c-sim-vcs/coverage/default/5.i2c_host_fifo_overflow.4043261753 Oct 02 08:26:30 PM UTC 24 Oct 02 08:27:07 PM UTC 24 2640838232 ps
T57 /workspaces/repo/scratch/os_regression_2024_10_02/i2c-sim-vcs/coverage/default/3.i2c_target_intr_stress_wr.2165631268 Oct 02 08:23:48 PM UTC 24 Oct 02 08:27:08 PM UTC 24 17488027164 ps
T353 /workspaces/repo/scratch/os_regression_2024_10_02/i2c-sim-vcs/coverage/default/5.i2c_target_intr_smoke.3518366833 Oct 02 08:27:07 PM UTC 24 Oct 02 08:27:14 PM UTC 24 4988880735 ps
T354 /workspaces/repo/scratch/os_regression_2024_10_02/i2c-sim-vcs/coverage/default/5.i2c_target_fifo_reset_tx.60177271 Oct 02 08:27:13 PM UTC 24 Oct 02 08:27:15 PM UTC 24 1158693008 ps
T170 /workspaces/repo/scratch/os_regression_2024_10_02/i2c-sim-vcs/coverage/default/5.i2c_target_fifo_reset_acq.2704919564 Oct 02 08:27:12 PM UTC 24 Oct 02 08:27:15 PM UTC 24 684164485 ps
T355 /workspaces/repo/scratch/os_regression_2024_10_02/i2c-sim-vcs/coverage/default/5.i2c_target_smoke.3611144921 Oct 02 08:26:43 PM UTC 24 Oct 02 08:27:19 PM UTC 24 1093022296 ps
T356 /workspaces/repo/scratch/os_regression_2024_10_02/i2c-sim-vcs/coverage/default/5.i2c_target_stress_wr.265938875 Oct 02 08:26:44 PM UTC 24 Oct 02 08:27:20 PM UTC 24 31143615972 ps
T357 /workspaces/repo/scratch/os_regression_2024_10_02/i2c-sim-vcs/coverage/default/5.i2c_target_timeout.4261932604 Oct 02 08:27:08 PM UTC 24 Oct 02 08:27:20 PM UTC 24 1143310672 ps
T358 /workspaces/repo/scratch/os_regression_2024_10_02/i2c-sim-vcs/coverage/default/5.i2c_target_perf.626174107 Oct 02 08:27:14 PM UTC 24 Oct 02 08:27:22 PM UTC 24 565838628 ps
T359 /workspaces/repo/scratch/os_regression_2024_10_02/i2c-sim-vcs/coverage/default/5.i2c_target_intr_stress_wr.3591308679 Oct 02 08:27:08 PM UTC 24 Oct 02 08:27:24 PM UTC 24 6910619002 ps
T360 /workspaces/repo/scratch/os_regression_2024_10_02/i2c-sim-vcs/coverage/default/5.i2c_host_stretch_timeout.1792891156 Oct 02 08:26:35 PM UTC 24 Oct 02 08:27:25 PM UTC 24 3312067681 ps
T361 /workspaces/repo/scratch/os_regression_2024_10_02/i2c-sim-vcs/coverage/default/6.i2c_host_fifo_watermark.3432620897 Oct 02 08:27:32 PM UTC 24 Oct 02 08:29:05 PM UTC 24 13348202367 ps
T181 /workspaces/repo/scratch/os_regression_2024_10_02/i2c-sim-vcs/coverage/default/5.i2c_target_hrst.2847044018 Oct 02 08:27:20 PM UTC 24 Oct 02 08:27:25 PM UTC 24 242371772 ps
T362 /workspaces/repo/scratch/os_regression_2024_10_02/i2c-sim-vcs/coverage/default/5.i2c_target_bad_addr.2711260772 Oct 02 08:27:16 PM UTC 24 Oct 02 08:27:25 PM UTC 24 953555513 ps
T363 /workspaces/repo/scratch/os_regression_2024_10_02/i2c-sim-vcs/coverage/default/1.i2c_target_stress_wr.3202883554 Oct 02 08:20:41 PM UTC 24 Oct 02 08:27:26 PM UTC 24 41367296537 ps
T22 /workspaces/repo/scratch/os_regression_2024_10_02/i2c-sim-vcs/coverage/default/5.i2c_host_mode_toggle.890169618 Oct 02 08:27:23 PM UTC 24 Oct 02 08:27:27 PM UTC 24 374004918 ps
T364 /workspaces/repo/scratch/os_regression_2024_10_02/i2c-sim-vcs/coverage/default/5.i2c_target_fifo_watermarks_tx.226771298 Oct 02 08:27:26 PM UTC 24 Oct 02 08:27:29 PM UTC 24 96479818 ps
T365 /workspaces/repo/scratch/os_regression_2024_10_02/i2c-sim-vcs/coverage/default/5.i2c_target_fifo_watermarks_acq.1846278750 Oct 02 08:27:26 PM UTC 24 Oct 02 08:27:29 PM UTC 24 1505321225 ps
T366 /workspaces/repo/scratch/os_regression_2024_10_02/i2c-sim-vcs/coverage/default/5.i2c_target_tx_stretch_ctrl.1640851338 Oct 02 08:27:26 PM UTC 24 Oct 02 08:27:30 PM UTC 24 131858266 ps
T367 /workspaces/repo/scratch/os_regression_2024_10_02/i2c-sim-vcs/coverage/default/5.i2c_target_smbus_maxlen.2131276311 Oct 02 08:27:27 PM UTC 24 Oct 02 08:27:31 PM UTC 24 1819708160 ps
T368 /workspaces/repo/scratch/os_regression_2024_10_02/i2c-sim-vcs/coverage/default/5.i2c_target_nack_acqfull.1864995419 Oct 02 08:27:27 PM UTC 24 Oct 02 08:27:31 PM UTC 24 439068843 ps
T369 /workspaces/repo/scratch/os_regression_2024_10_02/i2c-sim-vcs/coverage/default/5.i2c_target_nack_acqfull_addr.1700152188 Oct 02 08:27:28 PM UTC 24 Oct 02 08:27:32 PM UTC 24 3678303547 ps
T114 /workspaces/repo/scratch/os_regression_2024_10_02/i2c-sim-vcs/coverage/default/5.i2c_host_fifo_watermark.4012752091 Oct 02 08:26:29 PM UTC 24 Oct 02 08:27:32 PM UTC 24 9976914110 ps
T370 /workspaces/repo/scratch/os_regression_2024_10_02/i2c-sim-vcs/coverage/default/5.i2c_alert_test.1114625614 Oct 02 08:27:30 PM UTC 24 Oct 02 08:27:32 PM UTC 24 106169154 ps
T371 /workspaces/repo/scratch/os_regression_2024_10_02/i2c-sim-vcs/coverage/default/6.i2c_host_override.3133907677 Oct 02 08:27:31 PM UTC 24 Oct 02 08:27:33 PM UTC 24 32434030 ps
T26 /workspaces/repo/scratch/os_regression_2024_10_02/i2c-sim-vcs/coverage/default/4.i2c_host_fifo_full.194159888 Oct 02 08:25:06 PM UTC 24 Oct 02 08:27:34 PM UTC 24 7956428488 ps
T259 /workspaces/repo/scratch/os_regression_2024_10_02/i2c-sim-vcs/coverage/default/5.i2c_host_may_nack.1036132449 Oct 02 08:27:26 PM UTC 24 Oct 02 08:27:35 PM UTC 24 348143776 ps
T246 /workspaces/repo/scratch/os_regression_2024_10_02/i2c-sim-vcs/coverage/default/6.i2c_host_fifo_reset_fmt.4184381597 Oct 02 08:27:34 PM UTC 24 Oct 02 08:27:36 PM UTC 24 98344739 ps
T372 /workspaces/repo/scratch/os_regression_2024_10_02/i2c-sim-vcs/coverage/default/6.i2c_host_perf_precise.1019489810 Oct 02 08:27:36 PM UTC 24 Oct 02 08:27:39 PM UTC 24 71714504 ps
T28 /workspaces/repo/scratch/os_regression_2024_10_02/i2c-sim-vcs/coverage/default/6.i2c_host_error_intr.2707895835 Oct 02 08:27:39 PM UTC 24 Oct 02 08:27:42 PM UTC 24 102108525 ps
T237 /workspaces/repo/scratch/os_regression_2024_10_02/i2c-sim-vcs/coverage/default/6.i2c_host_fifo_reset_rx.1802950738 Oct 02 08:27:34 PM UTC 24 Oct 02 08:27:43 PM UTC 24 138763093 ps
T268 /workspaces/repo/scratch/os_regression_2024_10_02/i2c-sim-vcs/coverage/default/5.i2c_target_stress_rd.1217161514 Oct 02 08:26:45 PM UTC 24 Oct 02 08:27:51 PM UTC 24 5240044856 ps
T290 /workspaces/repo/scratch/os_regression_2024_10_02/i2c-sim-vcs/coverage/default/5.i2c_target_stress_all.378178701 Oct 02 08:27:16 PM UTC 24 Oct 02 08:27:57 PM UTC 24 4384755782 ps
T373 /workspaces/repo/scratch/os_regression_2024_10_02/i2c-sim-vcs/coverage/default/6.i2c_host_fifo_fmt_empty.1735310078 Oct 02 08:27:34 PM UTC 24 Oct 02 08:27:58 PM UTC 24 351459013 ps
T374 /workspaces/repo/scratch/os_regression_2024_10_02/i2c-sim-vcs/coverage/default/6.i2c_target_stress_rd.4072663577 Oct 02 08:27:51 PM UTC 24 Oct 02 08:27:59 PM UTC 24 809328977 ps
T375 /workspaces/repo/scratch/os_regression_2024_10_02/i2c-sim-vcs/coverage/default/7.i2c_target_perf.857220109 Oct 02 08:28:51 PM UTC 24 Oct 02 08:29:01 PM UTC 24 3594087684 ps
T376 /workspaces/repo/scratch/os_regression_2024_10_02/i2c-sim-vcs/coverage/default/6.i2c_host_stretch_timeout.4207281649 Oct 02 08:27:37 PM UTC 24 Oct 02 08:28:03 PM UTC 24 4389576554 ps
T377 /workspaces/repo/scratch/os_regression_2024_10_02/i2c-sim-vcs/coverage/default/6.i2c_target_intr_smoke.3558624462 Oct 02 08:27:53 PM UTC 24 Oct 02 08:28:03 PM UTC 24 4274000666 ps
T378 /workspaces/repo/scratch/os_regression_2024_10_02/i2c-sim-vcs/coverage/default/6.i2c_target_stretch.489690196 Oct 02 08:27:52 PM UTC 24 Oct 02 08:28:05 PM UTC 24 3092686673 ps
T379 /workspaces/repo/scratch/os_regression_2024_10_02/i2c-sim-vcs/coverage/default/6.i2c_target_fifo_reset_acq.1517187567 Oct 02 08:28:04 PM UTC 24 Oct 02 08:28:07 PM UTC 24 609872458 ps
T380 /workspaces/repo/scratch/os_regression_2024_10_02/i2c-sim-vcs/coverage/default/6.i2c_target_fifo_reset_tx.1552743402 Oct 02 08:28:04 PM UTC 24 Oct 02 08:28:08 PM UTC 24 447069493 ps
T381 /workspaces/repo/scratch/os_regression_2024_10_02/i2c-sim-vcs/coverage/default/6.i2c_target_timeout.1498524666 Oct 02 08:27:59 PM UTC 24 Oct 02 08:28:09 PM UTC 24 2285485708 ps
T382 /workspaces/repo/scratch/os_regression_2024_10_02/i2c-sim-vcs/coverage/default/6.i2c_target_smoke.1101089238 Oct 02 08:27:51 PM UTC 24 Oct 02 08:28:10 PM UTC 24 8155612210 ps
T383 /workspaces/repo/scratch/os_regression_2024_10_02/i2c-sim-vcs/coverage/default/5.i2c_host_fifo_full.363390530 Oct 02 08:26:32 PM UTC 24 Oct 02 08:28:12 PM UTC 24 3317979324 ps
T384 /workspaces/repo/scratch/os_regression_2024_10_02/i2c-sim-vcs/coverage/default/6.i2c_target_bad_addr.1882786519 Oct 02 08:28:06 PM UTC 24 Oct 02 08:28:13 PM UTC 24 2708362470 ps
T385 /workspaces/repo/scratch/os_regression_2024_10_02/i2c-sim-vcs/coverage/default/6.i2c_target_perf.1687459932 Oct 02 08:28:04 PM UTC 24 Oct 02 08:28:14 PM UTC 24 3121754921 ps
T386 /workspaces/repo/scratch/os_regression_2024_10_02/i2c-sim-vcs/coverage/default/5.i2c_target_stretch.2549424972 Oct 02 08:26:58 PM UTC 24 Oct 02 08:28:15 PM UTC 24 4809194095 ps
T23 /workspaces/repo/scratch/os_regression_2024_10_02/i2c-sim-vcs/coverage/default/6.i2c_host_mode_toggle.2417139027 Oct 02 08:28:10 PM UTC 24 Oct 02 08:28:15 PM UTC 24 580906038 ps
T171 /workspaces/repo/scratch/os_regression_2024_10_02/i2c-sim-vcs/coverage/default/6.i2c_target_fifo_watermarks_tx.1386550242 Oct 02 08:28:15 PM UTC 24 Oct 02 08:28:18 PM UTC 24 334824685 ps
T387 /workspaces/repo/scratch/os_regression_2024_10_02/i2c-sim-vcs/coverage/default/7.i2c_alert_test.3714613244 Oct 02 08:29:05 PM UTC 24 Oct 02 08:29:07 PM UTC 24 34997381 ps
T388 /workspaces/repo/scratch/os_regression_2024_10_02/i2c-sim-vcs/coverage/default/6.i2c_target_fifo_watermarks_acq.1171559902 Oct 02 08:28:15 PM UTC 24 Oct 02 08:28:19 PM UTC 24 1313478190 ps
T389 /workspaces/repo/scratch/os_regression_2024_10_02/i2c-sim-vcs/coverage/default/6.i2c_target_smbus_maxlen.3728321941 Oct 02 08:28:16 PM UTC 24 Oct 02 08:28:21 PM UTC 24 457957386 ps
T390 /workspaces/repo/scratch/os_regression_2024_10_02/i2c-sim-vcs/coverage/default/6.i2c_host_fifo_overflow.4243793048 Oct 02 08:27:32 PM UTC 24 Oct 02 08:28:21 PM UTC 24 7034204689 ps
T391 /workspaces/repo/scratch/os_regression_2024_10_02/i2c-sim-vcs/coverage/default/6.i2c_host_smoke.2026808596 Oct 02 08:27:30 PM UTC 24 Oct 02 08:28:24 PM UTC 24 1076440011 ps
T392 /workspaces/repo/scratch/os_regression_2024_10_02/i2c-sim-vcs/coverage/default/6.i2c_host_may_nack.2434389515 Oct 02 08:28:13 PM UTC 24 Oct 02 08:28:25 PM UTC 24 471382247 ps
T393 /workspaces/repo/scratch/os_regression_2024_10_02/i2c-sim-vcs/coverage/default/6.i2c_target_tx_stretch_ctrl.2285900544 Oct 02 08:28:16 PM UTC 24 Oct 02 08:28:28 PM UTC 24 539722916 ps
T394 /workspaces/repo/scratch/os_regression_2024_10_02/i2c-sim-vcs/coverage/default/6.i2c_target_nack_acqfull.2234813943 Oct 02 08:28:25 PM UTC 24 Oct 02 08:28:29 PM UTC 24 2176964694 ps
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