Group : cip_base_pkg::intr_pins_cg::SHAPE{(num_interrupts - 1)=14}
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Group : cip_base_pkg::intr_pins_cg::SHAPE{(num_interrupts - 1)=14}
SCOREWEIGHTGOALAT LEASTAUTO BIN MAXPRINT MISSING
100.00 1 100 1 64 64


Source File(s) :
/workspaces/repo/scratch/os_regression_2024_10_02/i2c-sim-vcs/default/sim-vcs/../src/lowrisc_dv_cip_lib_0/cip_base_env_cov.sv


Summary for Group cip_base_pkg::intr_pins_cg::SHAPE{(num_interrupts - 1)=14}

CATEGORYEXPECTEDUNCOVEREDCOVEREDPERCENT
Variables 19 0 19 100.00
Crosses 60 0 60 100.00


Variables for Group cip_base_pkg::intr_pins_cg::SHAPE{(num_interrupts - 1)=14}
VARIABLEEXPECTEDUNCOVEREDCOVEREDPERCENTGOALWEIGHTAT LEASTAUTO BIN MAXCOMMENT
cp_intr_pin 15 0 15 100.00 100 1 1 0
cp_intr_pin_value 4 0 4 100.00 100 1 1 0


Crosses for Group cip_base_pkg::intr_pins_cg::SHAPE{(num_interrupts - 1)=14}
CROSSEXPECTEDUNCOVEREDCOVEREDPERCENTGOALWEIGHTAT LEASTPRINT MISSINGCOMMENT
cp_intr_pins_all_values 60 0 60 100.00 100 1 1 0


Summary for Variable cp_intr_pin

CATEGORYEXPECTEDUNCOVEREDCOVEREDPERCENT
User Defined Bins 15 0 15 100.00


User Defined Bins for cp_intr_pin

Bins
NAMECOUNTAT LEASTSTATUSTESTCOUNTTESTCOUNTTESTCOUNT
all_pins[0] 806830 1 T1 1 T2 277 T3 2
all_pins[1] 806830 1 T1 1 T2 277 T3 2
all_pins[2] 806830 1 T1 1 T2 277 T3 2
all_pins[3] 806830 1 T1 1 T2 277 T3 2
all_pins[4] 806830 1 T1 1 T2 277 T3 2
all_pins[5] 806830 1 T1 1 T2 277 T3 2
all_pins[6] 806830 1 T1 1 T2 277 T3 2
all_pins[7] 806830 1 T1 1 T2 277 T3 2
all_pins[8] 806830 1 T1 1 T2 277 T3 2
all_pins[9] 806830 1 T1 1 T2 277 T3 2
all_pins[10] 806830 1 T1 1 T2 277 T3 2
all_pins[11] 806830 1 T1 1 T2 277 T3 2
all_pins[12] 806830 1 T1 1 T2 277 T3 2
all_pins[13] 806830 1 T1 1 T2 277 T3 2
all_pins[14] 806830 1 T1 1 T2 277 T3 2


Summary for Variable cp_intr_pin_value

CATEGORYEXPECTEDUNCOVEREDCOVEREDPERCENT
User Defined Bins 4 0 4 100.00


User Defined Bins for cp_intr_pin_value

Bins
NAMECOUNTAT LEASTSTATUSTESTCOUNTTESTCOUNTTESTCOUNT
values[0x0] 9982292 1 T1 15 T2 3550 T3 30
values[0x1] 2120158 1 T2 605 T4 6 T5 5
transitions[0x0=>0x1] 2119664 1 T2 605 T4 6 T5 5
transitions[0x1=>0x0] 2118365 1 T2 604 T4 5 T5 4


Summary for Cross cp_intr_pins_all_values

Samples crossed: cp_intr_pin cp_intr_pin_value
CATEGORYEXPECTEDUNCOVEREDCOVEREDPERCENTMISSING
Automatically Generated Cross Bins 60 0 60 100.00


Automatically Generated Cross Bins for cp_intr_pins_all_values

Bins
cp_intr_pincp_intr_pin_valueCOUNTAT LEASTSTATUSTESTCOUNTTESTCOUNTTESTCOUNT
all_pins[0] values[0x0] 131156 1 T1 1 T2 3 T3 2
all_pins[0] values[0x1] 675674 1 T2 274 T4 2 T5 2
all_pins[0] transitions[0x0=>0x1] 675477 1 T2 274 T4 2 T5 2
all_pins[0] transitions[0x1=>0x0] 56 1 T272 4 T278 2 T230 1
all_pins[1] values[0x0] 806577 1 T1 1 T2 277 T3 2
all_pins[1] values[0x1] 253 1 T32 3 T279 1 T271 2
all_pins[1] transitions[0x0=>0x1] 234 1 T32 3 T279 1 T271 2
all_pins[1] transitions[0x1=>0x0] 118 1 T169 1 T273 1 T280 1
all_pins[2] values[0x0] 806693 1 T1 1 T2 277 T3 2
all_pins[2] values[0x1] 137 1 T169 1 T273 1 T280 1
all_pins[2] transitions[0x0=>0x1] 120 1 T169 1 T273 1 T280 1
all_pins[2] transitions[0x1=>0x0] 71 1 T131 3 T36 2 T133 1
all_pins[3] values[0x0] 806742 1 T1 1 T2 277 T3 2
all_pins[3] values[0x1] 88 1 T131 3 T36 3 T133 2
all_pins[3] transitions[0x0=>0x1] 73 1 T131 3 T36 2 T133 1
all_pins[3] transitions[0x1=>0x0] 81 1 T12 1 T252 1 T259 1
all_pins[4] values[0x0] 806734 1 T1 1 T2 277 T3 2
all_pins[4] values[0x1] 96 1 T12 1 T252 1 T259 1
all_pins[4] transitions[0x0=>0x1] 74 1 T12 1 T252 1 T259 1
all_pins[4] transitions[0x1=>0x0] 75 1 T132 3 T36 3 T281 1
all_pins[5] values[0x0] 806733 1 T1 1 T2 277 T3 2
all_pins[5] values[0x1] 97 1 T131 1 T132 5 T36 4
all_pins[5] transitions[0x0=>0x1] 72 1 T131 1 T132 2 T36 3
all_pins[5] transitions[0x1=>0x0] 55 1 T183 4 T131 3 T132 1
all_pins[6] values[0x0] 806750 1 T1 1 T2 277 T3 2
all_pins[6] values[0x1] 80 1 T183 4 T131 3 T132 4
all_pins[6] transitions[0x0=>0x1] 60 1 T183 2 T131 3 T132 4
all_pins[6] transitions[0x1=>0x0] 33092 1 T2 41 T4 1 T6 3
all_pins[7] values[0x0] 773718 1 T1 1 T2 236 T3 2
all_pins[7] values[0x1] 33112 1 T2 41 T4 1 T6 3
all_pins[7] transitions[0x0=>0x1] 33085 1 T2 41 T4 1 T6 3
all_pins[7] transitions[0x1=>0x0] 58 1 T131 3 T132 2 T230 1
all_pins[8] values[0x0] 806745 1 T1 1 T2 277 T3 2
all_pins[8] values[0x1] 85 1 T183 3 T131 3 T132 2
all_pins[8] transitions[0x0=>0x1] 65 1 T183 3 T131 3 T132 2
all_pins[8] transitions[0x1=>0x0] 609975 1 T2 15 T4 1 T5 1
all_pins[9] values[0x0] 196835 1 T1 1 T2 262 T3 2
all_pins[9] values[0x1] 609995 1 T2 15 T4 1 T5 1
all_pins[9] transitions[0x0=>0x1] 609974 1 T2 15 T4 1 T5 1
all_pins[9] transitions[0x1=>0x0] 65 1 T183 2 T131 1 T132 1
all_pins[10] values[0x0] 806744 1 T1 1 T2 277 T3 2
all_pins[10] values[0x1] 86 1 T183 2 T131 1 T132 1
all_pins[10] transitions[0x0=>0x1] 68 1 T183 2 T131 1 T132 1
all_pins[10] transitions[0x1=>0x0] 800139 1 T2 275 T4 2 T5 2
all_pins[11] values[0x0] 6673 1 T1 1 T2 2 T3 2
all_pins[11] values[0x1] 800157 1 T2 275 T4 2 T5 2
all_pins[11] transitions[0x0=>0x1] 800124 1 T2 275 T4 2 T5 2
all_pins[11] transitions[0x1=>0x0] 108 1 T62 1 T63 1 T67 1
all_pins[12] values[0x0] 806689 1 T1 1 T2 277 T3 2
all_pins[12] values[0x1] 141 1 T62 1 T273 1 T63 1
all_pins[12] transitions[0x0=>0x1] 126 1 T62 1 T273 1 T63 1
all_pins[12] transitions[0x1=>0x0] 67 1 T131 1 T230 1 T36 2
all_pins[13] values[0x0] 806748 1 T1 1 T2 277 T3 2
all_pins[13] values[0x1] 82 1 T183 1 T131 1 T132 1
all_pins[13] transitions[0x0=>0x1] 65 1 T183 1 T131 1 T132 1
all_pins[13] transitions[0x1=>0x0] 58 1 T131 2 T230 1 T36 5
all_pins[14] values[0x0] 806755 1 T1 1 T2 277 T3 2
all_pins[14] values[0x1] 75 1 T131 2 T230 1 T36 5
all_pins[14] transitions[0x0=>0x1] 47 1 T131 2 T36 2 T133 1
all_pins[14] transitions[0x1=>0x0] 674347 1 T2 273 T4 1 T5 1

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