Unified Coverage Report :: Group :: cip_base_pkg::intr_test_cg::SHAPE{(num_interrupts - 1)=14}

Group : cip_base_pkg::intr_test_cg::SHAPE{(num_interrupts - 1)=14}

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
100.00	1	100	1	64	64

Source File(s) :
/workspaces/repo/scratch/os_regression_2024_10_02/i2c-sim-vcs/default/sim-vcs/../src/lowrisc_dv_cip_lib_0/cip_base_env_cov.sv

---

Summary for Group cip_base_pkg::intr_test_cg::SHAPE{(num_interrupts - 1)=14}

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	21	0	21	100.00
Crosses	90	0	90	100.00

Variables for Group cip_base_pkg::intr_test_cg::SHAPE{(num_interrupts - 1)=14}

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
cp_intr	15	0	15	100.00	100	1	1	0
cp_intr_en	2	0	2	100.00	100	1	1	2
cp_intr_state	2	0	2	100.00	100	1	1	2
cp_intr_test	2	0	2	100.00	100	1	1	2

Crosses for Group cip_base_pkg::intr_test_cg::SHAPE{(num_interrupts - 1)=14}

CROSS	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	PRINT MISSING	COMMENT
intr_test_cg_cc	90	0	90	100.00	100	1	1	0

Summary for Variable cp_intr

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	15	0	15	100.00

User Defined Bins for cp_intr

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
all_values[0]	392	1			T183	11		T131	7		T132	7
all_values[1]	392	1			T183	11		T131	7		T132	7
all_values[2]	392	1			T183	11		T131	7		T132	7
all_values[3]	392	1			T183	11		T131	7		T132	7
all_values[4]	392	1			T183	11		T131	7		T132	7
all_values[5]	392	1			T183	11		T131	7		T132	7
all_values[6]	392	1			T183	11		T131	7		T132	7
all_values[7]	392	1			T183	11		T131	7		T132	7
all_values[8]	392	1			T183	11		T131	7		T132	7
all_values[9]	392	1			T183	11		T131	7		T132	7
all_values[10]	392	1			T183	11		T131	7		T132	7
all_values[11]	392	1			T183	11		T131	7		T132	7
all_values[12]	392	1			T183	11		T131	7		T132	7
all_values[13]	392	1			T183	11		T131	7		T132	7
all_values[14]	392	1			T183	11		T131	7		T132	7

---

Summary for Variable cp_intr_en

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cp_intr_en

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

3292

1

T183

88

T131

51

T132

41

auto[1]

2588

1

T183

77

T131

54

T132

64

---

Summary for Variable cp_intr_state

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cp_intr_state

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

874

1

T183

15

T131

8

T132

19

auto[1]

5006

1

T183

150

T131

97

T132

86

---

Summary for Variable cp_intr_test

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cp_intr_test

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

3461

1

T183

98

T131

47

T132

58

auto[1]

2419

1

T183

67

T131

58

T132

47

---

Summary for Cross intr_test_cg_cc

Samples crossed: cp_intr cp_intr_test cp_intr_en cp_intr_state

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
TOTAL	90	0	90	100.00
Automatically Generated Cross Bins	90	0	90	100.00
User Defined Cross Bins	0	0	0

Automatically Generated Cross Bins for intr_test_cg_cc

Bins

cp_intr	cp_intr_test	cp_intr_en	cp_intr_state	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
all_values[0]	auto[0]	auto[0]	auto[0]	37	1			T36	1		T137	3		T282	1
all_values[0]	auto[0]	auto[0]	auto[1]	86	1			T183	3		T131	1		T230	2
all_values[0]	auto[0]	auto[1]	auto[0]	22	1			T183	2		T132	1		T281	1
all_values[0]	auto[0]	auto[1]	auto[1]	80	1			T183	2		T131	1		T132	3
all_values[0]	auto[1]	auto[0]	auto[1]	98	1			T183	3		T131	3		T132	1
all_values[0]	auto[1]	auto[1]	auto[1]	69	1			T183	1		T131	2		T132	2
all_values[1]	auto[0]	auto[0]	auto[0]	50	1			T132	1		T230	4		T36	1
all_values[1]	auto[0]	auto[0]	auto[1]	94	1			T183	5		T131	3		T230	5
all_values[1]	auto[0]	auto[1]	auto[0]	33	1			T131	2		T132	2		T281	1
all_values[1]	auto[0]	auto[1]	auto[1]	63	1			T183	2		T132	1		T36	4
all_values[1]	auto[1]	auto[0]	auto[1]	89	1			T183	2		T131	2		T132	2
all_values[1]	auto[1]	auto[1]	auto[1]	63	1			T183	2		T132	1		T230	3
all_values[2]	auto[0]	auto[0]	auto[0]	38	1			T134	3		T283	2		T136	2
all_values[2]	auto[0]	auto[0]	auto[1]	76	1			T183	1		T131	2		T230	3
all_values[2]	auto[0]	auto[1]	auto[0]	23	1			T183	1		T134	1		T283	2
all_values[2]	auto[0]	auto[1]	auto[1]	91	1			T183	4		T132	3		T230	2
all_values[2]	auto[1]	auto[0]	auto[1]	93	1			T183	3		T131	3		T230	7
all_values[2]	auto[1]	auto[1]	auto[1]	71	1			T183	2		T131	2		T132	4
all_values[3]	auto[0]	auto[0]	auto[0]	30	1			T230	1		T135	1		T283	4
all_values[3]	auto[0]	auto[0]	auto[1]	87	1			T183	5		T132	1		T230	6
all_values[3]	auto[0]	auto[1]	auto[0]	19	1			T132	1		T134	1		T283	1
all_values[3]	auto[0]	auto[1]	auto[1]	92	1			T131	1		T132	4		T230	3
all_values[3]	auto[1]	auto[0]	auto[1]	98	1			T183	3		T132	1		T230	4
all_values[3]	auto[1]	auto[1]	auto[1]	66	1			T183	3		T131	6		T36	4
all_values[4]	auto[0]	auto[0]	auto[0]	46	1			T183	3		T132	2		T133	1
all_values[4]	auto[0]	auto[0]	auto[1]	91	1			T183	1		T131	1		T230	6
all_values[4]	auto[0]	auto[1]	auto[0]	22	1			T183	2		T132	1		T36	1
all_values[4]	auto[0]	auto[1]	auto[1]	85	1			T183	2		T131	3		T132	2
all_values[4]	auto[1]	auto[0]	auto[1]	78	1			T183	2		T230	5		T36	2
all_values[4]	auto[1]	auto[1]	auto[1]	70	1			T183	1		T131	3		T132	2
all_values[5]	auto[0]	auto[0]	auto[0]	34	1			T281	1		T284	3		T136	1
all_values[5]	auto[0]	auto[0]	auto[1]	89	1			T183	5		T131	1		T230	6
all_values[5]	auto[0]	auto[1]	auto[0]	20	1			T132	1		T36	1		T133	1
all_values[5]	auto[0]	auto[1]	auto[1]	69	1			T183	2		T131	1		T132	3
all_values[5]	auto[1]	auto[0]	auto[1]	99	1			T183	3		T131	2		T132	1
all_values[5]	auto[1]	auto[1]	auto[1]	81	1			T183	1		T131	3		T132	2
all_values[6]	auto[0]	auto[0]	auto[0]	34	1			T230	1		T285	1		T282	1
all_values[6]	auto[0]	auto[0]	auto[1]	90	1			T183	1		T132	1		T230	4
all_values[6]	auto[0]	auto[1]	auto[0]	24	1			T131	1		T132	1		T133	1
all_values[6]	auto[0]	auto[1]	auto[1]	82	1			T183	6		T131	2		T132	2
all_values[6]	auto[1]	auto[0]	auto[1]	102	1			T183	1		T131	4		T132	2
all_values[6]	auto[1]	auto[1]	auto[1]	60	1			T183	3		T132	1		T36	2
all_values[7]	auto[0]	auto[0]	auto[0]	27	1			T281	2		T284	1		T285	4
all_values[7]	auto[0]	auto[0]	auto[1]	96	1			T183	4		T131	3		T132	2
all_values[7]	auto[0]	auto[1]	auto[0]	20	1			T183	1		T230	1		T283	2
all_values[7]	auto[0]	auto[1]	auto[1]	83	1			T183	2		T230	3		T36	2
all_values[7]	auto[1]	auto[0]	auto[1]	84	1			T183	2		T131	1		T132	4
all_values[7]	auto[1]	auto[1]	auto[1]	82	1			T183	2		T131	3		T132	1
all_values[8]	auto[0]	auto[0]	auto[0]	45	1			T131	1		T230	2		T36	1
all_values[8]	auto[0]	auto[0]	auto[1]	91	1			T183	2		T132	1		T230	4
all_values[8]	auto[0]	auto[1]	auto[0]	14	1			T183	1		T131	2		T132	2
all_values[8]	auto[0]	auto[1]	auto[1]	83	1			T183	3		T131	1		T132	1
all_values[8]	auto[1]	auto[0]	auto[1]	93	1			T183	2		T131	2		T132	1
all_values[8]	auto[1]	auto[1]	auto[1]	66	1			T183	3		T131	1		T132	2
all_values[9]	auto[0]	auto[0]	auto[0]	32	1			T282	2		T286	2		T287	3
all_values[9]	auto[0]	auto[0]	auto[1]	100	1			T183	4		T131	3		T132	2
all_values[9]	auto[0]	auto[1]	auto[0]	17	1			T132	1		T230	1		T282	2
all_values[9]	auto[0]	auto[1]	auto[1]	85	1			T183	1		T131	1		T132	1
all_values[9]	auto[1]	auto[0]	auto[1]	95	1			T183	4		T131	1		T132	3
all_values[9]	auto[1]	auto[1]	auto[1]	63	1			T183	2		T131	2		T230	2
all_values[10]	auto[0]	auto[0]	auto[0]	36	1			T132	3		T230	1		T36	2
all_values[10]	auto[0]	auto[0]	auto[1]	76	1			T183	3		T131	1		T230	4
all_values[10]	auto[0]	auto[1]	auto[0]	17	1			T183	1		T132	2		T134	1
all_values[10]	auto[0]	auto[1]	auto[1]	99	1			T183	2		T131	2		T132	1
all_values[10]	auto[1]	auto[0]	auto[1]	92	1			T183	5		T131	2		T230	4
all_values[10]	auto[1]	auto[1]	auto[1]	72	1			T131	2		T132	1		T230	3
all_values[11]	auto[0]	auto[0]	auto[0]	35	1			T230	1		T285	1		T286	4
all_values[11]	auto[0]	auto[0]	auto[1]	87	1			T183	2		T131	2		T132	2
all_values[11]	auto[0]	auto[1]	auto[0]	15	1			T281	4		T135	1		T284	2
all_values[11]	auto[0]	auto[1]	auto[1]	86	1			T183	5		T230	6		T36	4
all_values[11]	auto[1]	auto[0]	auto[1]	100	1			T183	3		T131	2		T132	3
all_values[11]	auto[1]	auto[1]	auto[1]	69	1			T183	1		T131	3		T132	2
all_values[12]	auto[0]	auto[0]	auto[0]	31	1			T230	1		T36	2		T135	1
all_values[12]	auto[0]	auto[0]	auto[1]	97	1			T183	2		T131	3		T132	2
all_values[12]	auto[0]	auto[1]	auto[0]	26	1			T131	2		T132	1		T230	3
all_values[12]	auto[0]	auto[1]	auto[1]	87	1			T183	4		T132	1		T230	1
all_values[12]	auto[1]	auto[0]	auto[1]	80	1			T183	3		T131	2		T132	1
all_values[12]	auto[1]	auto[1]	auto[1]	71	1			T183	2		T132	2		T230	2
all_values[13]	auto[0]	auto[0]	auto[0]	46	1			T183	2		T134	1		T135	6
all_values[13]	auto[0]	auto[0]	auto[1]	99	1			T183	2		T131	4		T230	7
all_values[13]	auto[0]	auto[1]	auto[0]	19	1			T183	1		T134	1		T135	1
all_values[13]	auto[0]	auto[1]	auto[1]	69	1			T183	2		T132	2		T36	2
all_values[13]	auto[1]	auto[0]	auto[1]	89	1			T183	1		T131	1		T132	1
all_values[13]	auto[1]	auto[1]	auto[1]	70	1			T183	3		T131	2		T132	4
all_values[14]	auto[0]	auto[0]	auto[0]	36	1			T281	1		T136	1		T285	2
all_values[14]	auto[0]	auto[0]	auto[1]	92	1			T183	2		T131	1		T132	2
all_values[14]	auto[0]	auto[1]	auto[0]	26	1			T183	1		T281	2		T134	1
all_values[14]	auto[0]	auto[1]	auto[1]	82	1			T183	4		T131	2		T132	2
all_values[14]	auto[1]	auto[0]	auto[1]	94	1			T183	4		T132	2		T230	6
all_values[14]	auto[1]	auto[1]	auto[1]	62	1			T131	4		T132	1		T230	2

User Defined Cross Bins for intr_test_cg_cc

Excluded/Illegal bins

NAME	COUNT	STATUS
test_1_state_0	0	Illegal